Semiconductor chip comprising a cover protection layer covering a portion of a passivation layer

Abstract

A semiconductor chip capable of withstanding damage such as cracks generated in a manufacturing process is provided. The semiconductor chip according to the inventive concept includes a semiconductor substrate including a residual scribe groove surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, the cover protection layer being integrally formed with a buffer protection layer covering a portion of the residual scribe groove, wherein the buffer protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extension protection layer extending from the corner protection layer along the residual scribe groove and in contact with the cover protection layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0081059, filed on July 12, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor chip, and more specifically, to a semiconductor chip having a protective overlay layer covering a passivation layer. Background Technology

[0004] Semiconductor chips can be formed by dividing the semiconductor substrate after forming a semiconductor device on the semiconductor substrate.

[0005] As a method for dividing a semiconductor substrate into multiple semiconductor chips, a sawing method can be performed using a blade. Alternatively, after forming a modified layer inside the semiconductor substrate, a method can be performed to thin the semiconductor substrate to divide the modified layer along a breaking point. Summary of the Invention

[0006] The present invention provides a semiconductor chip that can withstand damage such as cracks that may occur during the separation of the semiconductor chip from the semiconductor substrate.

[0007] According to an exemplary embodiment of the present invention, a semiconductor chip includes a semiconductor substrate having residual scribe lines around a die region and the periphery of the die edge of the die region. A passivation layer covers a portion above the semiconductor substrate. A protective cover layer is disposed on a portion of the passivation layer and the die region. The protective cover layer is integrally formed with a buffer protective layer covering a portion of the residual scribe lines. The buffer protective layer has a corner protective layer that contacts a portion of an edge adjacent to a corner of the semiconductor substrate, and an extended protective layer that extends along the residual scribe lines extending from the surface of the corner protective layer and contacts the protective cover layer.

[0008] According to an exemplary embodiment of the present invention, a semiconductor chip is provided, comprising a semiconductor substrate and a die region therein in which a plurality of chip pads are disposed. The semiconductor chip further has a periphery surrounding the edge of the die region and a residual scribe groove therein in which a plurality of residual test pads are disposed. A passivation layer at least partially covers the semiconductor substrate and exposes the plurality of chip pads and the plurality of residual test pads. A protective overlay layer at least partially covers a portion of the passivation layer and is integrated with a portion of the passivation layer. The protective overlay layer includes a first portion covering an inner region of the die edge, a second portion contacting a portion of the edge adjacent to a corner of the semiconductor substrate in the residual scribe groove, and a third portion extending from the second portion along the residual scribe groove to be spaced apart from the plurality of residual test pads. A portion of the end of the third portion opposite to the second portion is spaced apart from the edge of the semiconductor substrate.

[0009] According to an exemplary embodiment of the present invention, a semiconductor chip including a semiconductor substrate and a die region is provided. A plurality of chip pads are arranged in the die region, and a residual scribe line at least partially surrounds the periphery of the die edge of the die region. A passivation layer at least partially covers a portion above the semiconductor substrate. A protective overlay layer at least partially covers a portion of the passivation layer. The residual scribe line includes a plurality of intersecting regions, which are portions adjacent to each corner of the semiconductor substrate. The residual scribe line also has a test region, which is a portion in which a plurality of residual test pads are disposed between the plurality of intersecting regions. The protective overlay layer includes: a central covering portion that at least partially covers a region inside the chip edge; a peripheral covering portion having a constant width from the chip edge and surrounding the central covering portion and covering a portion of the residual scribe line; a corner protective layer that contacts a portion of the edge of the semiconductor substrate in the intersecting regions; and an extending protective layer that extends from the corner protective layer along the residual scribe line and contacts the peripheral covering portion in the intersecting regions. Attached Figure Description

[0010] The foregoing and other aspects of the inventive concept will be more clearly understood by referring to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A This is a plan view illustrating a semiconductor substrate for manufacturing a semiconductor chip according to an exemplary embodiment of the present invention;

[0012] Figure 1B Is it like this? Figure 1A A magnified planar view of region Ib of the semiconductor substrate shown;

[0013] Figure 1C Is it like this? Figure 1B A magnified planar view of region Ic of the semiconductor substrate shown;

[0014] Figure 1DIs along such Figure 1B The cross-sectional view of the semiconductor substrate shown is taken from line Id.

[0015] Figure 1E Is along as Figure 1B The cross-sectional view of the semiconductor substrate shown is taken from line Ie.

[0016] Figures 2 to 4B This is a perspective view illustrating a method for manufacturing a semiconductor chip according to an exemplary embodiment of the concept of the present invention. Figure 2 , Figure 3A and Figure 4A ) and floor plan ( Figure 3B and Figure 4B );

[0017] Figure 5A This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention;

[0018] Figure 5B yes Figure 5A A magnified plan view of region Vb of the semiconductor chip shown;

[0019] Figure 6 This is a plan view illustrating an exemplary embodiment of a semiconductor substrate for manufacturing a semiconductor chip according to a concept of the present invention;

[0020] Figure 7 This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention;

[0021] Figure 8A This is a plan view illustrating an exemplary embodiment of a semiconductor substrate for manufacturing a semiconductor chip according to a concept of the present invention;

[0022] Figure 8B It is shown Figure 8A Enlarged plan view of region VIIIb;

[0023] Figure 9 This is a plan view illustrating a method for manufacturing a semiconductor chip from a semiconductor substrate according to an exemplary embodiment of the present invention;

[0024] Figure 10 This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention;

[0025] Figure 11 This is a plan view illustrating an exemplary embodiment of a semiconductor substrate for manufacturing a semiconductor chip according to a concept of the present invention;

[0026] Figure 12 This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention;

[0027] Figure 13A This is a plan view illustrating an exemplary embodiment of a semiconductor substrate for manufacturing a semiconductor chip according to a concept of the present invention;

[0028] Figure 13B yes Figure 13A A magnified plan view of region XIIIb;

[0029] Figure 14 This is a plan view illustrating a method for manufacturing a semiconductor chip according to an exemplary embodiment of the concept of the present invention;

[0030] Figure 15 This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention;

[0031] Figure 16 This is a plan view illustrating an exemplary embodiment of a semiconductor substrate for manufacturing a semiconductor chip according to the concept of the present invention; and

[0032] Figure 17 This is a plan view illustrating an exemplary embodiment of a semiconductor chip according to the concept of the present invention. Detailed Implementation

[0033] Exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of elements may be exaggerated for clarity, but this is not a limitation. It should be understood that the same reference numerals may refer to the same elements throughout the drawings. When the term "set on..." is used to indicate a relationship between elements, it should be understood that this does not necessarily mean that one element is directly set on another element, but rather that an intervening layer may exist between them.

[0034] Figures 1A to 1E These include perspective views, plan views, and cross-sectional views of a semiconductor substrate 100 for manufacturing a semiconductor chip, respectively, according to exemplary embodiments of the present invention. Specifically, Figure 1A This is a three-dimensional view of a semiconductor substrate used to manufacture semiconductor chips. Figure 1B yes Figure 1A The plan view of region Ib shown. Figure 1C yes Figure 1B An enlarged view of the area Ic depicted in the image. Figure 1D It is along Figure 1B The cross-sectional view shown is taken from line Id. Figure 1E It is along Figure 1B The cross-sectional view taken from line Id in the diagram.

[0035] See Figures 1A to 1EThe semiconductor substrate 100 may have a first side 102 and a second side 104 opposite to each other, and may be a semiconductor wafer in which a notch 106 is formed. The semiconductor substrate 100 may include, for example, silicon (Si) or germanium (Ge). Optionally, the semiconductor substrate 100 may include compounds including silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). The semiconductor substrate 100 may include a semiconductor wafer, a conductive material, an insulating material, and a semiconductor material disposed on the semiconductor wafer. The semiconductor substrate 100 may have a semiconductor device 118 formed thereon, the semiconductor device 118 including a plurality of individual devices of various kinds disposed on the first side 102.

[0036] In an exemplary embodiment of the present invention, the semiconductor substrate 100 may have a (100) surface-oriented main surface. In other embodiments, the semiconductor substrate 100 may have a (110) surface-oriented main surface. The surface orientation of the main surface of the semiconductor substrate 100 may be determined according to SEMI (Semiconductor Equipment and Materials Association) standards. Figure 1A The direction in which the notch 106 is formed.

[0037] The semiconductor substrate 100 may have a plurality of die regions 110 disposed on a first side 102 and divided into rows and columns by a dicing groove 120. For example, the dicing groove 120 may define the plurality of die regions 110 by extending orthogonally in the direction of the die regions 110 of the semiconductor substrate 100.

[0038] Multiple chip pads 112 may be arranged on a first side 102 of a semiconductor substrate 100, located in each of a plurality of die regions 110. According to an exemplary embodiment of the present invention, the multiple chip pads 112 may be edge pads arranged adjacent to the die edge 110B (the edge of each of the plurality of die regions 110).

[0039] According to an exemplary embodiment of the present invention, the plurality of chip pads 112 may be central pads arranged in the central portion of each of the plurality of die regions 110.

[0040] The scribe line 120 may include a test region TER in which a test element group (TEG) is formed, and a cross region CVR in which no TEG is formed. The cross region CVR may be a portion of the scribe line 120 that extends orthogonally thereto and a portion adjacent thereto. The test region TER may be a portion of the scribe line 120 that extends in a direction other than through the cross region CVR.

[0041] In the test area TER of the dicing groove 120, multiple test pads 122 can be arranged on the first side 102 of the semiconductor substrate 100. The multiple test pads 122 can be used to test the TEG formed in the test area TER.

[0042] Multiple chip pads 112 and multiple test pads 122 may include conductive materials. For example, the multiple chip pads 112 and multiple test pads 122 may include nickel (Ni), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), and / or tungsten (W). The multiple chip pads 112 and multiple test pads 122 are shown as buried in... Figure 1D and Figure 1E The semiconductor substrate 100 is located within the semiconductor substrate 100. However, the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, a plurality of chip pads 112 and a plurality of test pads 122 may protrude from a first side 102 of the semiconductor substrate 100.

[0043] A passivation layer 140 and a protective cover layer 130 covering a portion of the passivation layer 140 are disposed on a first side 102 of the semiconductor substrate 100. According to an exemplary embodiment of the present invention, the protective cover layer 130 may be integrated with a portion of the passivation layer 140. The passivation layer 140 may comprise an inorganic material, such as an oxide or a nitride. For example, the passivation layer 140 may comprise silicon oxide and / or silicon nitride. The protective cover layer 130 may be formed of, for example, photosensitive polyimide (PSPI).

[0044] Passivation layer 140 may expose a plurality of chip pads 112 and a plurality of test pads 122 disposed on a first side 102 of semiconductor substrate 100. For example, passivation layer 140 may cover the entire first side 102 of semiconductor substrate 100 except for the plurality of chip pads 112 and the plurality of test pads 122, but is not limited thereto. According to an exemplary embodiment of the present invention, passivation layer 140 may expose the plurality of chip pads 112 and the plurality of test pads 122, as well as some regions of the first side 102 of semiconductor substrate 100 adjacent to the plurality of test pads 122. According to an exemplary embodiment of the present invention, passivation layer 140 may cover portions adjacent to each edge of the plurality of chip pads 112 and the plurality of test pads 122. The remaining portions of the plurality of chip pads 112 and the plurality of test pads 122 may be exposed. Passivation layer 140 may substantially cover the entire first side 102 of semiconductor substrate 100 in the intersection region CVR of dicing groove 120.

[0045] The protective overlay 130 may cover a portion of the upper surface of the passivation layer 140. The protective overlay 130 may cover all upper surfaces of the passivation layer 140 in the die region 110. According to an exemplary embodiment of the present invention, the protective overlay 130 may expose a portion of the upper surface of the passivation layer 140 adjacent to a plurality of chip pads 112 in the die region 110.

[0046] The protective cover 130 may include a first protective cover 132 covering the die region 110, and a second protective cover 134 covering a portion of the scribe line groove 120 in the cross region CVR. The second protective cover 134 may be integrally formed with the first protective cover 132. Figure 1C In the diagram, for clarity, the dashed line extends along the boundary between the first protective layer 132 and the second protective layer 134. However, the boundary between the first protective layer 132 and the second protective layer 134 may not actually exist, as they can be integrally formed.

[0047] The protective layer 130 may include a first protective layer 132. The protective layer 132 may include a portion covering the portion of the dicing groove 120 adjacent to the edge 110B of the die. For example, the first protective layer 132 may include a central portion 132X covering the die region 110 and a peripheral portion 132Y covering a first width W1 constant from the edge 110B and surrounding the perimeter of the die region 110. The central portion 132X and the peripheral portion 132Y may be integrally formed. According to an exemplary embodiment of the present invention, the first protective layer 132 may not include the peripheral portion 132Y, but may only include the central portion 132X.

[0048] The second protective cover 134 may include intersecting portions disposed on orthogonally extending scribe grooves 120. For example, the intersecting portion 134X covers the central portion between the edges of four adjacent bare film regions 110, and the extended portion 134Y extends from the intersecting portion 134X along the scribe grooves 120. The intersecting portion 134X and the extended portion 134Y may be integrally formed.

[0049] The cover extension 134Y may have a second width W2 extending from the cover intersection 134X in the direction of the scribe line 120 and may contact the corner portion of the first cover layer 132. The cover extension 134Y may not cover the test area TER where multiple test pads 122 are arranged. The cover extension 134Y may have a split induction groove 134G disposed at the end opposite to the cover intersection 134X. For example, the split induction groove 134G may be disposed at the end of the cover extension 134Y adjacent to the test area TER. The width of the split induction groove 134G may gradually narrow in the direction toward the cover intersection 134X. The width at one end of the cover extension 134Y may be greater than the maximum width of the split induction groove 134G in the same direction. Therefore, the end of the cover extension 134Y can be bifurcated by the separation guide groove 134G formed therebetween, and can include two blunt portions that narrow as they extend along the scribe groove 120 in a direction away from the cover intersection 134X.

[0050] The end of the cover extension 134Y opposite to the cover intersection 134X can be spaced apart from the test pad 122 by a first length D1. The first length D1 can be less than a second length D2, which is the length from the corner of the die edge 110B to one end of the cover extension 134Y.

[0051] The covering cross portion 134X and the covering extension portion 134Y of the covering protective layer 130 can be integrally formed, and are shown as different elements for ease of description and illustration.

[0052] Chip wiring 114 and chip via 116 electrically connected to multiple chip pads 112, and test wiring 124 and test via 126 electrically connected to multiple test pads 122 can be arranged inside the semiconductor substrate 100.

[0053] According to an exemplary embodiment of the present invention, the chip wiring 114, chip via 116, test wiring 124 and test via 126 may include, for example, aluminum (Al), copper (Cu), or tungsten (W).

[0054] Semiconductor device 118 may be disposed in die region 110 and inside semiconductor substrate 100. Semiconductor device 118 may be electrically connected to multiple chip pads 112 via chip wiring 114 and chip vias 116.

[0055] Semiconductor device 118 may be, for example, a memory cell device. According to an exemplary embodiment of the present invention, semiconductor device 118 may be: flash memory, phase-change RAM (PRAM), resistive RAM (PRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), or a similar device. However, semiconductor device 118 is not limited thereto. According to an exemplary embodiment of the present invention, flash memory may be, for example, a NAND flash memory device or a V-NAND flash memory device. According to an exemplary embodiment of the present invention, semiconductor device 118 may be a DRAM device, an SRAM device, an SDRAM device, an SGRAM device, or an RDRAM device. However, semiconductor device 118 is not limited thereto. According to an exemplary embodiment of the present invention, semiconductor device 118 may be a logic device.

[0056] The multiple die regions 110 of the semiconductor substrate 100 can be divided into multiple individual semiconductor chips 110C (see...). Figure 5A Each of the plurality of semiconductor chips 110C may include a die region 110 and a residual dicing groove 120R (see [reference]). Figure 5A The residual dicing groove 120R is the portion of the dicing groove 120 surrounding the periphery of the bare wafer region 110.

[0057] The first protective layer 132 may cover the die region 110 of each semiconductor chip 110C, and a portion of the residual dicing groove 120R surrounds the periphery of the die region 110 adjacent to the die edge 110B. The second protective layer 134 may cover a portion of the residual dicing groove 120R adjacent to the corner of each semiconductor chip 110C.

[0058] The first protective layer 132 can protect each of the plurality of semiconductor chips 110C, and the second protective layer 134 can be used as a buffer area to prevent damage such as cracks from occurring when the corners of the plurality of semiconductor chips 110C collide with each other during the process of separating the plurality of semiconductor chips 110C from the semiconductor substrate 100.

[0059] Figures 2 to 4B This is a perspective view illustrating a method for manufacturing a semiconductor chip 110C according to an exemplary embodiment of the present invention. Figure 2 , Figure 3A and Figure 4A ) and floor plan ( Figure 4B and Figure 3B In particular, Figure 3B and Figure 4B It corresponds to Figure 1A A magnified planar view of the Ib region.

[0060] See Figure 2The protective strip 10 is adhered to the first side 102 of the semiconductor substrate 100.

[0061] See you together Figure 3A and Figure 3B The semiconductor substrate 100 is inverted so that side 104 faces upward, and then the focusing point of the laser beam 22 is positioned within the semiconductor substrate 100 by a concentrator 20. The laser beam 22 irradiates the second side 104 of the semiconductor substrate 100 to form a modified layer 150 based on multiphoton absorption within the semiconductor substrate 100. The laser beam 22 irradiates along a scribe line 120, thereby forming the modified layer 150 within the scribe line 120 inside the semiconductor substrate 100. According to an exemplary embodiment of the present invention, the laser beam 22 can irradiate the semiconductor substrate 100 using a YAG (yttrium aluminum garnet) pulsed laser with a wavelength of approximately 1342 nm.

[0062] The modified layer 150 may extend orthogonally along the dicing groove 120 inside the semiconductor substrate 100. A plurality of modified layers 150 may extend perpendicularly to each other below the second cover layer 134 and along the portion of the dicing groove 120 between the first cover layer 132 covering two adjacent die regions 110.

[0063] The modified layer 150 can be formed in the dicing groove 120 to overlap with the separation induction groove 134G. The modified layer 150 can be formed to extend along the gap between two separation induction grooves 134G facing each other in the dicing groove 120.

[0064] Apart from the second protective cover layer 134, the protective cover layer 130 may not be formed in the portion of the dicing groove 120 where the modified layer 150 is formed. For example, the protective cover layer 130 may only be formed in a relatively small portion of the dicing groove 120 where the modified layer 150 is not formed. Therefore, interference encountered during the division of the semiconductor substrate 100 into multiple semiconductor chips 110C using the modified layer 150 as a break point can be minimized.

[0065] A modified layer 150 extending across a plurality of test pads 122 within a semiconductor substrate 100 is shown, but the inventive concept is not limited thereto. For example, the modified layer 150 may extend across all of the plurality of test pads 122 within the semiconductor substrate 100, extend only across some portions of the plurality of test pads 122, or extend along portions adjacent to the plurality of test pads 122 without overlapping the plurality of test pads 122.

[0066] See Figure 4A and Figure 4B The second side 104 of the semiconductor substrate 100 can be ground to thin the semiconductor substrate 100. Then, a modified layer 150 (see...) is used... Figure 4BThe semiconductor substrate 100 is divided into a plurality of semiconductor chips 110C as a break point. Each of the plurality of semiconductor chips 110C may include a die region 110 and a residual scribe groove 120R, the residual scribe groove 120R being the portion of the scribe groove 120 surrounding the periphery of the die region 110 along the die edge 110B (see [link to documentation]). Figure 3B A portion of multiple test pads 122 or multiple test pads 122 retained on the residual scribe groove 120R (see...) Figure 4B This can be referred to as residual test pad 122R.

[0067] The semiconductor substrate 100 and the polishing apparatus 30 can rotate independently to polish the second side 104 of the semiconductor substrate 100. According to an exemplary embodiment of the present invention, the rotation direction of the semiconductor substrate 100 and the rotation direction of the polishing apparatus 30 can be substantially the same. According to an exemplary embodiment of the present invention, the rotational speed of the polishing apparatus 30 can be greater than the rotational speed of the semiconductor substrate 100.

[0068] Because pressure can be applied to the semiconductor substrate 100 by the polishing equipment 30 during the polishing process on the second side 104 of the semiconductor substrate 100, cracks may be generated in the modified layer 150, which serves as the breakage starting point, in the semiconductor substrate 100. Therefore, each part of the semiconductor substrate 100 can be individually divided into multiple semiconductor chips 110C.

[0069] According to an exemplary embodiment of the present invention, when the dicing groove 120 (see Figure 3B When extending in the bare die region 110 of the semiconductor substrate 100, the following can be performed in the bare die region 110: creating a crack in the modified layer 150, which serves as the breakage initiation point (see...). Figure 3B ). Covering protective layer 130 (see) Figure 1C It may have a second protective layer 134 (see Figure 1C The coverage extension 134Y (see) Figure 1C The separation induction groove 134G is located at the end of the semiconductor chip 110C. Therefore, it can be performed not in the bare die region 110, but towards the corners of the multiple semiconductor chips 110C: at the modified layer 150 (see [link to original text]) which serves as the break-off starting point. Figure 3B Cracks were generated in the process.

[0070] During the process of dividing the semiconductor substrate 100 into a plurality of semiconductor chips 110C, the plurality of semiconductor chips 110C may not be divided simultaneously. During the grinding of the semiconductor substrate 100 in which some portions of the plurality of semiconductor chips 110C are divided, the corners of the plurality of semiconductor chips 110C (which are divided first) may collide with the corners of other adjacent semiconductor chips 110C. However, as a second protective covering layer 134 (see...) Figure 3B A portion of the buffer protective layer 134R can cover the surfaces of adjacent portions of the corners of multiple semiconductor chips 110C, thus preventing damage such as cracks even when the corners of multiple adjacent semiconductor chips 110C collide with each other. The first cover protective layer 132 may include a die protective layer, and therefore, the die protective layer and the buffer protective layer 134R can be integrally formed. The cover protective layer 132 and the buffer protective layer 134R together can be collectively referred to as the chip protective layer 130R.

[0071] Figure 5A and Figure 5B This is a plan view of a semiconductor chip 110C according to an exemplary embodiment of the present invention. Specifically, Figure 5B yes Figure 5A An illustration of a magnified view of region Vb in the diagram.

[0072] See Figure 5A and Figure 5B The semiconductor chip 110C may include a portion of the semiconductor substrate 100 (see [reference]). Figure 1D and 1E It includes a bare die region 110 and a residual dicing groove 120R surrounding the periphery of the bare die region 110.

[0073] When the dicing groove 120 extends orthogonally in the direction of the die region 110 of the semiconductor substrate 100 of the semiconductor chip 110C, the residual dicing groove 120R, which is part of the dicing groove 120, can also extend in the direction of the die region 110 of the semiconductor substrate 100.

[0074] Semiconductor chip 110C includes a passivation layer 140 and a chip protective layer 130R covering a portion of the passivation layer 140.

[0075] The residual dicing groove 120R may include a cross region CVR and a test region TER, wherein the cross region CVR is a portion adjacent to each corner of the die region 110 of the semiconductor chip 110C, and the test region TER is adjacent to the side of the cross region CVR, in which residual test pads 122R are arranged between adjacent corners of the die region 110.

[0076] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R; instead, it may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0077] Chip protection layer 130R may cover a portion of the upper surface of passivation layer 140. Chip protection layer 130R may cover all, but is not limited to, the upper surface of passivation layer 140 in die region 110. In an exemplary embodiment of the present invention, chip protection layer 130R may not cover a portion of the upper surface of passivation layer 140 adjacent to the plurality of chip pads 112 in die region 110; instead, it may expose a portion of the upper surface of passivation layer 140 adjacent to the plurality of chip pads 112 in die region 110.

[0078] The chip protection layer 130R may include a cover protection layer 132 covering the bare die region 110 and a buffer protection layer 134R covering a portion of the residual dicing groove 120R. The cover protection layer 132 and the buffer protection layer 134R may be integrally formed.

[0079] The protective layer 132 may also cover a portion of the residual scribe groove 120R adjacent to the die edge 110B. For example, the protective layer 132 may include a central covering portion 132X covering the die region 110 and a peripheral covering portion 132Y having a constant first width W1 at a distance from the die edge 110B. The peripheral covering portion 132Y may contact the central covering portion 132X to substantially surround the entire perimeter of the central covering portion 132X (except for the corners covered by 134R) and cover a portion of the residual scribe groove 120R. According to an exemplary embodiment of the present invention, the peripheral covering portion 132Y may have a constant first width W1 extending from the die edge 110B toward the scribe groove 120. The residual scribe groove 120R may surround the periphery of the die region 110, and the width of the residual scribe groove 120R may be greater than the constant first width W1 of the peripheral covering portion 132Y. The central portion 132X and the peripheral portion 132Y of the protective layer 132 can be formed integrally.

[0080] The buffer protection layer 134R may include: a corner protection layer 134XR, which covers a portion of the residual scribe groove 120R and is disposed at the corner of the semiconductor chip 110C; and an extended protection layer 134YR, which contacts the covering protection layer 132 and extends from the surface of the corner protection layer 134XR along a portion of the residual scribe groove 120R. The corner protection layer 134XR and the extended protection layer 134YR may be integrally formed.

[0081] The extended protective layer 134YR of the buffer protective layer 134R covers a portion of the dicing groove 120 in the cross region CVR and is part of the buffer cover protective layer 134R disposed on the passivation layer 140. Since the passivation layer 140 substantially covers the entire first side 102 of the semiconductor substrate 100, the lower surface of the buffer protective layer 134R can contact the upper surface of the passivation layer 140 in the cross region CVR.

[0082] The corner protective layer 134XR can contact a portion of the edge adjacent to the corner of the semiconductor chip 110C.

[0083] The extended protective layer 134YR may not cover the test area TER arranged together with the residual test pads 122R. The peripheral coverage portion 132Y may cover the portion of the test area TER adjacent to the die edge 110B where the residual test pads 122R are not arranged. The extended protective layer 134YR may have a separation groove 134GR at one end opposite to the corner protective layer 134XR (e.g., the end facing the test area TER). A portion of one end of the extended protective layer 134YR may be separated from the edge of one side of the semiconductor chip 110C by the separation groove 134GR. According to an exemplary embodiment of the present invention, the width of the separation groove 134GR may decrease as the separation groove 134GR extends toward the corner protective layer 134XR. The residual dicing groove 120R extends in the direction of the die area 110 of the semiconductor substrate 100, and the separation groove 134GR may extend in the direction of the die area 110 of the semiconductor substrate 100 and narrow in width toward the corner protective layer 134XR.

[0084] The residual dicing groove 120R, which is the remaining part of the dicing groove 120, may have an end corresponding to the separation groove 134GR.

[0085] According to an exemplary embodiment of the present invention, one end of the extended protective layer 134YR may have a blunt shape. A portion of the extended protective layer 134YR adjacent to the separation groove 134GR may extend toward the corner protective layer 134XR and may have a gradually decreasing width.

[0086] One end of the extended protective layer 134YR opposite to the corner protective layer 134XR can be spaced apart from the adjacent residual test pad 122R. The first length D1, which is the distance between the end of the extended protective layer 134YR and the residual test pad 122R, can be less than the second length D2, which is the length from the end of the extended protective layer 134YR to the end of the corner protective layer 134XR.

[0087] Because the corner protection layer 134XR covers the corner portion of the semiconductor chip 110C, damage to the corners of the semiconductor chip 110C, such as cracks, can be prevented. Since the chip protection layer 130R does not cover the edge of the semiconductor chip 110C (excluding the portion covered by the corner protection layer 134XR), therefore, when... Figure 1A When dividing multiple semiconductor chips 110C from a semiconductor substrate 100, the division can occur without interference, and cracks in the die region 110 can be prevented due to the separation trench 134GR.

[0088] For ease of explanation, the central portion 132X, the peripheral portion 132Y, the corner protective layer 134XR, and the extended protective layer 134YR integrally formed with the chip protective layer 130R can be named the first part 132X, the second part 132Y, the third part 134XR, and the fourth part 134YR, respectively.

[0089] Figure 6 This is a plan view of a semiconductor substrate 100 for manufacturing a semiconductor chip, according to an exemplary embodiment of the present invention. Specifically, Figure 6 Is with Figure 1A A plan view of the portion corresponding to region Ib in the diagram.

[0090] See Figure 6 The semiconductor substrate 100 may have a plurality of die regions 110 defined by scribe lines 120 on a first side 102. A plurality of chip pads 112 may be arranged in each of the plurality of die regions 110 on the first side 102 of the semiconductor substrate 100. A plurality of test pads 122 may be arranged in the scribe lines 120 on the first side 102 of the semiconductor substrate 100.

[0091] A passivation layer 140 and a protective cover layer 130a covering a portion of the passivation layer are disposed on a first side 102 of the semiconductor substrate 100. The protective cover layer 130a may cover a portion of the upper surface of the passivation layer 140.

[0092] The protective layer 130a may include a first protective layer 132a covering the bare die region 110 and a second protective layer 134a covering a portion of the dicing groove 120. The first protective layer 132a and the second protective layer 134a may be integrally formed.

[0093] The first protective layer 132a may cover a portion of the die region 110 inside the die edge 110B. The first protective layer 132a may not cover the dicing groove 120.

[0094] The second protective layer 134a may overlap with the intersection of the orthogonally extending scribe grooves 120. For example, the second protective layer 134a may overlap with portions disposed between the edges of four adjacent bare film regions 110 and portions extending along the scribe grooves 120.

[0095] The second protective cover 134a may have a separation induction groove 134Ga disposed at the end of a portion extending along the scribe line 120. The separation induction groove 134Ga may extend toward the interior of the second protective cover 134a and gradually narrow. The width of the end of the second protective cover 134a extending along the scribe line 120 may be greater than the maximum width of the separation induction groove 134Ga in the same direction. The end of the portion of the second protective cover 134a extending along the scribe line 120 may bifurcate through the separation induction groove 134Ga disposed therebetween, and may include two blunt portions, the width of which narrows as it extends along the scribe line 120.

[0096] The end of the portion of the second protective layer 134a extending along the scribe groove 120 may be spaced apart from the plurality of test pads 122.

[0097] Figure 7 This is a plan view of a semiconductor chip 110Ca according to an exemplary embodiment of the present invention.

[0098] See Figure 7 The semiconductor chip 110Ca may include a die region 110 and residual dicing grooves 120R surrounding the periphery of the die region 110.

[0099] The semiconductor chip 110Ca may include a passivation layer 140 and a chip protective layer 130Ra covering a portion of the passivation layer 140.

[0100] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R; instead, it may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0101] The chip protective layer 130Ra may cover a portion of the upper surface of the passivation layer 140. The chip protective layer 130Ra may cover all, but is not limited to, the upper surface of the passivation layer 140 in the die region 110. According to an exemplary embodiment of the present invention, the chip protective layer 130Ra may not cover a portion of the upper surface of the passivation layer 140 adjacent to the plurality of chip pads 112 in the die region 110; instead, it may expose a portion of the upper surface of the passivation layer 140 adjacent to the plurality of chip pads 112 in the die region 110.

[0102] The chip protection layer 130Ra may include a cover protection layer 132a that covers only the area of ​​the die region 110 inside the die edge 110B, and a buffer protection layer 134Ra that covers a portion of the plurality of residual dicing grooves 120R. The cover protection layer 132a and the buffer protection layer 134Ra may be integrally formed.

[0103] The buffer protection layer 134Ra may include: a corner protection layer 134XRa that covers portions of the plurality of residual scribe lines 120R at the corners of the semiconductor chip 110Ca; and an extended protection layer 134YRa that is a portion of the residual scribe lines 120R that contacts the overlay protection layer 132a and extends along the die edge 110B. The corner protection layer 134XRa and the extended protection layer 134YRa may be integrally formed.

[0104] The end of the extended protective layer 134YRa opposite to the corner protective layer 134XRa can be spaced apart from the residual test pad 122R. The end of the extended protective layer 134YRa opposite to the corner protective layer 134XRa can have a separation groove 134GRa. A portion of the end of the extended protective layer 134YRa can be separated from the edge of the semiconductor chip 110Ca through the separation groove 134GRa. The end of the extended protective layer 134YRa can have a blunt shape. The portion of the extended protective layer 134YRa adjacent to the separation groove 134GRa can extend towards the end of the extended protective layer 134YRa, and its width can gradually decrease.

[0105] Because the corner protection layer 134XRa covers the portion of the semiconductor chip 110Ca adjacent to its corner, damage to the corner of the semiconductor chip 110Ca, such as cracks, can be prevented. Since the chip protection layer 130Ra does not cover the edge of the semiconductor chip 110Ca (excluding the portion covered by the corner protection layer 134XRa), it can be protected from interference. Figure 1A The semiconductor substrate 100 is divided into multiple semiconductor chips 110Ca, and cracks in the die region 110 can be prevented due to the separation trench 134GRa.

[0106] For ease of explanation, the overlay protective layer 132a, corner protective layer 134XRa, and extended protective layer 134YRa of the integrally formed chip protective layer 130Ra can be named the first part 132a, the second part 134XRa, and the third part 134YRa, respectively.

[0107] Figure 8A and Figure 8B This is a plan view of a semiconductor substrate 100 for manufacturing a semiconductor chip, according to an exemplary embodiment of the present invention. Specifically, Figure 8A It corresponds to Figure 1AA plan view of part of region Ib in the diagram. Figure 8B yes Figure 8A An enlarged view of region VIIIb shown.

[0108] See you together Figure 8A and Figure 8B The semiconductor substrate 100 may have a plurality of die regions 110 defined by scribe lines 120 on a first side 102. A plurality of chip pads 112 may be arranged in each of the plurality of die regions 110 on the first side 102 of the semiconductor substrate 100. A plurality of test pads 122 may be arranged in the scribe lines 120 on the first side 102 of the semiconductor substrate 100.

[0109] A passivation layer 140 and a protective cover layer 130b covering a portion of the passivation layer are disposed on a first side 102 of the semiconductor substrate 100. The protective cover layer 130b may cover a portion of the upper surface of the passivation layer 140.

[0110] The protective layer 130b may include a first protective layer 132 covering the bare die region 110 and a second protective layer 134b covering a portion of the dicing groove 120. The first protective layer 132 and the second protective layer 134b may be integrally formed.

[0111] The first protective layer 132 may include a portion of the protective layer 130b covering a portion of the dicing groove 120 adjacent to the edge 110B of the die. For example, the first protective layer 132 may include a central covering portion 132X covering the die region 110, and a peripheral covering portion 132Y having a constant first width W1 at a distance from the edge 110B and surrounding the die region 110. The central covering portion 132X and the peripheral covering portion 132Y may be integrally formed.

[0112] The second protective cover 134b may include the intersections of orthogonally extending scribe grooves 120. For example, an intersection 134Xb may cover the portion between the edges of four adjacent bare film regions 110, and an extension 134Yb may extend along the scribe grooves 120 from the intersection 134Xb. The intersection 134Xb and the extension 134Yb may be integrally formed.

[0113] The second protective cover 134b may have a separation induction groove 134Gb disposed at the end of the portion extending along the scribe line 120. The separation induction groove 134Gb may extend with a constant width toward the cover intersection portion 134Xb. The width of the end of the cover extension portion 134Yb may be greater than the width of the separation induction groove 134Gb in the same direction. Therefore, the end of the second protective cover 134b may be divided into two blunt portions having substantially the same width and extension length by the separation induction groove 134Gb.

[0114] The end of the portion of the second protective layer 134b extending along the scribe groove 120 may be spaced apart from the plurality of test pads 122.

[0115] Figure 9 This is a plan view illustrating a method for manufacturing a semiconductor chip from a semiconductor substrate according to an exemplary embodiment of the present invention.

[0116] See Figure 9 Modified layer 150 and above Figure 3A and Figure 3B It is formed using the same method described in [the text].

[0117] The modified layer 150 may extend orthogonally to overlap with the dicing groove 120. The modified layers 150 may be perpendicular to each other and extend below the second cover layer 134b and extend along a portion of the dicing groove 120 between the first cover layer 132 covering two adjacent die regions 110.

[0118] A modified layer 150 can be formed in the dicing groove 120 to overlap with the separation induction groove 134Gb. The modified layer 150 can be formed to extend along the gap between two separation induction grooves 134Gb facing each other in the dicing groove 120.

[0119] Figure 10 This is a plan view of a semiconductor chip 110Cb according to an exemplary embodiment of the present invention.

[0120] See Figure 10 The semiconductor chip 110Cb may include a die region 110 and residual dicing grooves 120R surrounding the periphery of the die region 110.

[0121] The semiconductor chip 110Cb may include a passivation layer 140 and a chip protective layer 130Rb covering a portion of the passivation layer 140.

[0122] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R; instead, it may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0123] The chip protection layer 130Rb may cover a portion of the upper surface of the passivation layer 140. The chip protection layer 130Rb may include a cover protection layer 132 covering the bare die region 110 and a buffer protection layer 134Rb covering a portion of the residual dicing groove 120R. The cover protection layer 132 and the buffer protection layer 134Rb may be integrally formed.

[0124] The protective layer 132 may also include a portion covering a portion of the residual scribe lines 120R adjacent to the die edge 110B. For example, the protective layer 132 may include: a central portion 132X covering the die region 110; and a peripheral portion 132Y covering a portion of the residual scribe lines 120R at a constant width from the die edge 110B and covering a portion of the residual scribe lines 120R to surround the die region 110. The central portion 132X and the peripheral portion 132Y may be integrally formed.

[0125] The buffer protection layer 134Rb may include: a corner protection layer 134XRb, which covers a portion of the residual dicing groove 120R at the corner of the semiconductor chip 110Cb; and an extension protection layer 134YRb, which is a portion of the residual dicing groove 120R that extends from the corner protection layer 134XRb to the die edge 110B. The corner protection layer 134XRb and the extension protection layer 134YRb may be integrally formed.

[0126] The end of the extended protective layer 134YRb opposite the corner protective layer 134XRb may have a separation groove 134GRb. A portion of the end of the extended protective layer 134YRb can be separated from the edge of the semiconductor chip 110Cb by the separation groove 134GRb. The separation groove 134GRb may have a substantially constant width as it extends toward the corner protective layer 134XR. A residual dicing groove 120R is present on the semiconductor chip 110Cb. Figures 1A to 1E The semiconductor substrate 100 shown extends in the direction of the die region 110. However, the separation trench 134GRb may have a substantially constant width in the direction extending toward the die region 110 of the semiconductor substrate 100.

[0127] The end of the extended protective layer 134YRb may have a blunt shape. A portion of the extended protective layer 134YRb adjacent to the separation groove 134GRb may have a substantially constant width and extend toward the end of the extended protective layer 134YRb.

[0128] Figure 11 This is a plan view of a semiconductor substrate 100 for manufacturing a semiconductor chip, according to an exemplary embodiment of the present invention. Specifically, Figure 11 Is with Figure 1A The plan view of the portion corresponding to region Ib shown.

[0129] See Figure 11 The semiconductor substrate 100 may have a plurality of die regions 110 defined by scribe lines 120 on a first side 102 of the semiconductor substrate 100. A plurality of chip pads 112 may be arranged in each of the plurality of die regions 110 on the first side 102 of the semiconductor substrate 100. A plurality of test pads 122 may be arranged in the scribe lines 120 on the first side 102 of the semiconductor substrate 100.

[0130] A passivation layer 140 and a protective cover layer 130c covering a portion of the passivation layer are disposed on a first side 102 of the semiconductor substrate 100. The protective cover layer 130c may cover a portion of the upper surface of the passivation layer 140.

[0131] The protective layer 130c may include a first protective layer 132a covering the bare die region 110 and a second protective layer 134c covering a portion of the dicing groove 120. The first protective layer 132a and the second protective layer 134c may be integrally formed.

[0132] The first protective layer 132a may cover a portion of the die region 110 inside the die edge 110B. The first protective layer 132a may not cover the dicing groove 120.

[0133] The second protective layer 134c may include the intersections of orthogonally extending scribe grooves 120. For example, the second protective layer 134c may include portions disposed between the edges of four adjacent bare film regions 110, and portions extending along the scribe grooves 120.

[0134] The second protective cover 134c may have a separation induction groove 134Gc disposed at an end extending along the scribe line 120. The separation induction groove 134Gc may have a substantially constant width and extend toward the interior of the second protective cover 134c. The width of the end of the second protective cover 134c extending along the scribe line 120 may be greater than the width of the separation induction groove 134Gc in the same direction. The end of the portion of the second protective cover 134c extending along the scribe line 120 may bifurcate through the separation induction groove 134Gc disposed therebetween, and may include two blunt portions having a substantially constant width and extending along the scribe line 120.

[0135] The end of the second protective layer 134c extending along the scribe groove 120 may be spaced apart from a plurality of test pads 122.

[0136] Figure 12 This is a plan view of a semiconductor chip 110Cc according to an exemplary embodiment of the present invention.

[0137] See Figure 12 The semiconductor chip 110Cc may include a die region 110 and residual dicing grooves 120R surrounding the periphery of the die region 110.

[0138] The semiconductor chip 110Cc may include a passivation layer 140 and a chip protection layer 130Rc covering a portion of the passivation layer 140.

[0139] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R, but may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0140] The chip protection layer 130Rc may cover a portion of the upper surface of the passivation layer 140. The chip protection layer 130Rc may include a cover protection layer 132a that covers only the die region 110 within the die edge 110B, and a buffer protection layer 134Rc that covers a portion of the plurality of residual dicing grooves 120R. The cover protection layer 132a and the buffer protection layer 134Rc may be integrally formed.

[0141] The buffer protection layer 134Rc may include: a corner protection layer 134XRc, which covers a portion of a plurality of residual scribe lines 120R disposed on the corner of the semiconductor chip 110Cc; and an extended protection layer 134YRc, which is a portion in the residual scribe lines 120R that contacts the overlay protection layer 132a and extends along a portion of the die edge 110B. The corner protection layer 134XRc and the extended protection layer 134YRc may be integrally formed.

[0142] The end of the extended protective layer 134YRc opposite to the corner protective layer 134XRc can be separated from the residual test pad 122R. The end of the extended protective layer 134YRc opposite to the corner protective layer 134XRc can have a separation groove 134GRc. The separation groove 134GRc can have a substantially constant width extending toward the corner protective layer 134XRc. A portion of the end of the extended protective layer 134YRc can be separated from the edge of the semiconductor chip 110Cc through the separation groove 134GRc. The end of the extended protective layer 134YRc can have a blunt shape. A portion of the extended protective layer 134YRc adjacent to the separation groove 134GRc can have a substantially constant width and extend toward the end of the extended protective layer 134YRc.

[0143] Figure 13A and 13B This is a plan view of a semiconductor substrate 100 for manufacturing a semiconductor chip, according to an exemplary embodiment of the present invention. Specifically, Figure 13A It corresponds to Figure 1AA plan view of part of region Ib in the diagram. Figure 13B yes Figure 13A A magnified view of region XIIIb in the image.

[0144] See you together Figure 13A and Figure 13B The semiconductor substrate 100 may have a plurality of die regions 110 defined by scribe lines 120 on a first side 102. A plurality of chip pads 112 may be arranged in each of the plurality of die regions 110 on the first side 102 of the semiconductor substrate 100. A plurality of test pads 122 may be arranged in the scribe lines 120 on the first side 102 of the semiconductor substrate 100.

[0145] A passivation layer 140 and a protective cover layer 130d covering a portion of the passivation layer are disposed on a first side 102 of the semiconductor substrate 100. The protective cover layer 130d may cover a portion of the upper surface of the passivation layer 140.

[0146] The protective cover 130 may include a first protective cover 132 covering the bare die region 110 and a second protective cover 134d covering a portion of the dicing groove 120. The first protective cover 132 and the second protective cover 134d may be integrally formed.

[0147] The first protective layer 132 may include a portion of the protective layer 130 covering a portion of the scribe groove 120 adjacent to the edge 110B of the die. For example, the first protective layer 132 may include a central covering portion 132X covering the die region 110, and a peripheral covering portion 132Y surrounding the die region 110 and having a constant first width W1 at a distance of 1 from the edge 110B. The central covering portion 132X and the peripheral covering portion 132Y may be integrally formed.

[0148] The second protective cover 134d may include the intersections of orthogonally extending scribe grooves 120. For example, the second protective cover 134d may include: a covering intersection 134Xd covering portions disposed between the edges of four adjacent bare die regions 110; and a covering extension 134Yd extending from the covering intersection 134Xd along the scribe grooves 120. The covering intersection 134Xd and the covering extension 134Yd may be integrally formed.

[0149] The second protective cover 134d may have a separation guiding groove 134Gd disposed at an end extending along the scribe line 120. The separation guiding groove 134Gd may extend toward the cover intersection portion 134Xd and have a width that gradually decreases in the extending direction. The width of the end of the cover extension portion 134Yd may be the same as the maximum width of the separation guiding groove 134Gd in the same direction. Therefore, the end of the second protective cover 134d may bifurcate through the separation guiding groove 134Gd disposed therebetween, and may include two sharp portions extending along the scribe line 120 and narrowing in the extending direction.

[0150] The end of the second cover layer 134d extending along the scribe groove 120 of the second cover layer 134d may be spaced apart from a plurality of test pads 122.

[0151] Figure 14 This is a plan view illustrating a method for manufacturing a semiconductor chip according to an exemplary embodiment of the present invention.

[0152] See Figure 14 Modified layer 150 is as described above. Figure 3A and Figure 3B It is formed using the same method described in [the text].

[0153] The modified layer 150 may extend orthogonally within the dicing groove 120. The modified layer 150 may be perpendicular to each other below the second cover layer 134d and extend along a portion of the dicing groove 120 between the first cover layers 132 covering two adjacent die regions 110.

[0154] A modified layer 150 can be formed in the dicing groove 120 to overlap with the separation induction groove 134Gd. The modified layer 150 can be formed to extend along the gap between two separation induction grooves 134Gd facing each other in the dicing groove 120.

[0155] Figure 15 This is a plan view of a semiconductor chip 110Cd according to an embodiment of the present invention.

[0156] See Figure 15 The semiconductor chip 110Cd may include a die region 110 and residual dicing grooves 120R surrounding the periphery of the die region 110.

[0157] The semiconductor chip 110Cd may include a passivation layer 140 and a chip protective layer 130Rd covering a portion of the passivation layer 140.

[0158] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R; instead, it may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0159] The chip protection layer 130Rd may cover a portion of the upper surface of the passivation layer 140. The chip protection layer 130Rd may include a cover protection layer 132 covering the bare die region 110 and a buffer protection layer 134Rd covering a portion of the residual dicing groove 120R. The cover protection layer 132 and the buffer protection layer 134Rd may be integrally formed.

[0160] The protective layer 132 may also include a portion covering a portion of the residual scribe lines 120R adjacent to the die edge 110B. For example, the protective layer 132 may include: a central covering portion 132X covering the die region 110; and a peripheral covering portion 132Y of constant width extending from the die edge 110B toward the residual scribe lines 120R and covering a portion of the residual scribe lines 120R to surround the die region 110. The central covering portion 132X and the peripheral covering portion 132Y may be integrally formed.

[0161] The buffer protection layer 134Rd may include: a corner protection layer 134XRd, which covers a portion of the residual dicing groove 120R at the corner of the semiconductor chip 110Cd; and an extended protection layer 134YRd, which is a portion of the residual dicing groove 120R extending from the corner protection layer 134XRd to the die edge 110B. The corner protection layer 134XRd and the extended protection layer 134YRd may be integrally formed.

[0162] The end of the extended protective layer 134YRd opposite to the corner protective layer 134XRd may have a separation groove 134GRd. A portion of the extended protective layer 134YRd can be separated from the edge of the semiconductor chip 110Cd through the separation groove 134GRd. The separation groove 134GRd may extend toward the corner protective layer 134XRd and narrow in width in the extending direction. One end of the extended protective layer 134YRd may have a sharp shape. A portion of the extended protective layer 134YRd adjacent to the separation groove 134GRd may extend toward the end of the extended protective layer 134YRd and may narrow in width in the extending direction.

[0163] Figure 16 This is a plan view of a semiconductor substrate 100 for manufacturing a semiconductor chip, according to an exemplary embodiment of the present invention. Specifically, Figure 16 It corresponds to Figure 1A A plan view of part of region Ib in the diagram.

[0164] See Figure 16The semiconductor substrate 100 may have a plurality of die regions 110 defined by scribe lines 120 on a first side 102 of the semiconductor substrate 100. A plurality of chip pads 112 may be arranged in each of the plurality of die regions 110 on the first side 102 of the semiconductor substrate 100. A plurality of test pads 122 may be arranged in the scribe lines 120 on the first side 102 of the semiconductor substrate 100.

[0165] A passivation layer 140 and a protective cover layer 130e covering a portion of the passivation layer are disposed on a first side 102 of the semiconductor substrate 100. The protective cover layer 130e may cover a portion of the upper surface of the passivation layer 140.

[0166] The protective layer 130e may include a first protective layer 132a covering the bare die region 110 and a second protective layer 134e covering a portion of the dicing groove 120. The first protective layer 132a and the second protective layer 134e may be integrally formed.

[0167] The first protective layer 132a may cover a portion of the die region 110 inside the die edge 110B. The first protective layer 132a may not cover the dicing groove 120.

[0168] The second protective layer 134e may include the intersections of orthogonally extending scribe grooves 120. For example, the second protective layer 134e includes portions disposed between the edges of four adjacent bare film regions 110 and portions extending along the scribe grooves 120.

[0169] The second protective cover 134e may have a separation induction groove 134Ge at the end of the portion extending along the scribe line 120. The separation induction groove 134Ge may extend toward the interior of the second protective cover 134e and its width may gradually narrow. The width of the end of the portion of the second protective cover 134e extending along the scribe line 120 may be the same as the maximum width of the separation induction groove 134Ge in the same direction. The end of the second protective cover 134e extending along the scribe line 120 may fork through the separation induction groove 134Ge disposed therebetween, and may include two sharp portions extending along the scribe line 120 and narrowing in width.

[0170] The end of the portion of the second protective layer 134e extending along the scribe groove 120 may be spaced apart from the plurality of test pads 122.

[0171] Figure 17 This is a plan view of a semiconductor chip 110Ce according to an exemplary embodiment of the present invention.

[0172] See Figure 17The semiconductor chip 110Ce may include a die region 110 and residual dicing grooves 120R surrounding the periphery of the die region 110.

[0173] The semiconductor chip 110Ce may include a passivation layer 140 and a chip protection layer 130Re covering a portion of the passivation layer 140.

[0174] The passivation layer 140 may not cover the multiple chip pads 112 and the multiple residual test pads 122R; instead, it may expose the multiple chip pads 112 and the multiple residual test pads 122R.

[0175] The chip protection layer 130Re may cover a portion of the upper surface of the passivation layer 140. The chip protection layer 130Re may include a cover protection layer 132a that covers only the die region 110 within the die edge 110B, and a buffer protection layer 134Re that covers a portion of the plurality of residual dicing grooves 120R. The cover protection layer 132a and the buffer protection layer 134Re may be integrally formed.

[0176] The buffer protection layer 134Re may include: a corner protection layer 134XRe, which covers portions of the plurality of residual scribe lines 120R at the corners of the semiconductor chip 110Ce; and an extended protection layer 134YRe, which is a portion of the residual scribe lines 120R that contacts the overlay protection layer 132a and extends along a portion of the die edge 110B. The corner protection layer 134XRe and the extended protection layer 134YRe may be integrally formed.

[0177] The end of the extended protective layer 134YRe opposite to the corner protective layer 134XRe may be spaced apart from the residual test pad 122R. The end of the extended protective layer 134YRe opposite to the corner protective layer 134XRe may have a separation groove 134GRe. The separation groove 134GRe may extend toward the corner protective layer 134XRe and narrow in width in the extension direction. A portion of the end of the extended protective layer 134YRe may be separated from the edge of the semiconductor chip 110Ce through the separation groove 134GRe. The end of the extended protective layer 134YRe may have a sharp shape. A portion of the extended protective layer 134YRe adjacent to the separation groove 134GRe may extend toward the end of the extended protective layer 134YRe and may narrow in width in the extension direction.

[0178] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor chip, comprising: A semiconductor substrate, comprising at least partially residual dicing grooves surrounding a die region having a die edge; A passivation layer that at least partially covers the semiconductor substrate; as well as A protective overlay is disposed on a portion of the passivation layer and the bare die region, wherein the protective overlay is integrally formed with a buffer protective layer covering a portion of the residual dicing groove. The buffer protection layer includes: a corner protection layer that contacts a portion of an edge adjacent to a corner of the semiconductor substrate; and an extended protection layer that extends along the residual scribe groove extending from the surface of the corner protection layer and contacts the cover protection layer.

2. The semiconductor chip of claim 1, wherein a portion of the end of the extended protective layer opposite to the corner protective layer is spaced apart from the corner of the semiconductor substrate by a separation groove.

3. The semiconductor chip according to claim 2, wherein the width of the separation groove decreases in the direction toward the corner protection layer.

4. The semiconductor chip of claim 2, wherein the separation groove has a constant width in the direction extending toward the corner protection layer.

5. The semiconductor chip of claim 2, wherein the width of the portion of the extended protective layer that contacts the separation trench decreases in the direction away from the corner protective layer.

6. The semiconductor chip of claim 2, wherein the portion of the extended protective layer that contacts the separation trench has a constant width extending away from the corner protective layer.

7. The semiconductor chip of claim 1, wherein the end of the extended protective layer opposite to the corner protective layer has a sharp shape.

8. The semiconductor chip according to claim 1, wherein the end of the extended protective layer opposite to the corner protective layer has a blunt shape.

9. The semiconductor chip according to claim 1, further comprising: Residual test pads are located in the residual scribe grooves not covered by the passivation layer or the buffer protection layer. The end of the extended protective layer opposite to the corner protective layer is spaced apart from the residual test pad.

10. The semiconductor chip of claim 9, wherein the distance between the end of the extended protective layer and the residual test pad is less than the extension length from the edge of the die to the end of the extended protective layer.

11. The semiconductor chip of claim 1, wherein the lower surface of the buffer protective layer is in contact with the upper surface of all of the plurality of passivation layers.

12. The semiconductor chip of claim 1, wherein the protective layer comprises a central covering portion and a peripheral covering portion, wherein the central covering portion covers the interior of the die edge, the peripheral covering portion has a constant width from the die edge to surround the central covering portion and cover a portion of the residual dicing groove, wherein the extended protective layer contacts the peripheral covering portion.

13. The semiconductor chip of claim 12, wherein the width of the residual dicing groove is greater than the width of the peripheral coverage portion.

14. A semiconductor chip, comprising: A semiconductor substrate comprising a die region in which a plurality of chip pads are disposed and a peripheral area surrounding the edge of the die region and a residual dicing groove in which a plurality of residual test pads are disposed. A passivation layer that at least partially covers the semiconductor substrate and exposes the plurality of chip pads and the plurality of residual test pads; as well as A protective layer is provided that at least partially covers a portion of the passivation layer and is integrated with that portion of the passivation layer. The protective layer includes a first portion that at least partially covers the inner region of the die edge of the die area, a second portion that contacts a portion of the edge adjacent to the corner of the semiconductor substrate in the residual scribe groove, and a third portion that extends from the second portion along the residual scribe groove and is spaced apart from the plurality of residual test pads, wherein a portion of the end of the third portion opposite to the second portion is spaced apart from the edge of the semiconductor substrate.

15. The semiconductor chip of claim 14, wherein the residual dicing groove extends in the direction of the die region of the semiconductor substrate and extends along the die edge.

16. The semiconductor chip of claim 15, wherein the separation groove between the edge of the semiconductor substrate and the third portion extends in the direction of the bare die region of the semiconductor substrate.

17. The semiconductor chip of claim 14, wherein the protective overlay further comprises a fourth portion having a constant width at a distance from the edge of the die to surround the first portion and cover a portion of the residual scribe groove, and the third portion contacts the fourth portion and extends along the residual scribe groove.

18. A semiconductor chip, comprising: A semiconductor substrate, comprising a die region in which a plurality of chip pads are disposed and a residual dicing groove surrounding at least part of the periphery of the die edge of the die region; A passivation layer that at least partially covers the portion above the semiconductor substrate; and A protective layer is provided that at least partially covers a portion of the passivation layer; The residual dicing groove includes multiple intersecting regions and a test region. The multiple intersecting regions are portions adjacent to each corner of the semiconductor substrate, and the test region is a portion in which multiple residual test pads are disposed between the multiple intersecting regions. The protective covering layer includes: The central portion is covered, which at least partially covers the area inside the edge of the bare sheet. The coverage area has a constant width from the edge of the bare die and surrounds the central coverage area, covering a portion of the remaining dicing groove. A corner protective layer that contacts a portion of the edge of the semiconductor substrate in the intersection region, and An extended protective layer extends from the corner protective layer along the residual scribbling groove and contacts the periphery of the cover in the intersection area.

19. The semiconductor chip of claim 18, wherein the extended protective layer is spaced apart from the plurality of residual test pads, and a portion of the end of the extended protective layer opposite to the corner protective layer is spaced apart from the edge of the semiconductor substrate.

20. The semiconductor chip of claim 18, wherein the passivation layer substantially covers the entire semiconductor substrate in the cross region.

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