Semiconductor Devices

Abstract

A semiconductor device may include: active fins, which are spaced apart from each other by recesses between the active fins, each of the active fins protruding from the upper surface of a substrate; an isolation structure, which includes a liner on the lower surface and on the sidewalls of the lower portion of the recess, and a barrier pattern on the liner, the barrier pattern filling the remaining portion of the lower portion of the recess and including nitride, carbide or polysilicon; a gate electrode structure on the active fins and the isolation structure; and a source / drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0081124 filed on July 12, 2018 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments relate to semiconductor devices and more particularly to fin field effect transistors (finFETs). Background Art

[0004] As the thickness of the gate spacer on the sidewall of the gate structure gradually decreases, the source / drain layer insulated from the gate structure by the gate spacer may be electrically shorted with the gate structure. Therefore, a method for preventing electrical shorting is provided. Summary of the invention

[0005] Example embodiments provide semiconductor devices having improved features.

[0006] According to some aspects, the present disclosure relates to a semiconductor device, comprising: active fins, which are spaced apart from each other by recesses between the active fins, each of the active fins protruding from an upper surface of a substrate; an isolation structure, which is formed in the recess, comprising: a liner, which is on a lower surface and sidewalls of a lower portion of the recess; and a blocking pattern, which is on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and comprising nitride, carbide or polysilicon; a gate electrode structure, which is located on the active fins and the isolation structure; and a source / drain layer, which is located on a portion of each of the active fins adjacent to the gate electrode structure.

[0007] According to some aspects, the present disclosure relates to a semiconductor device, comprising: an active fin protruding from an upper surface of a substrate and comprising a lower active pattern and an upper active pattern stacked on the lower active pattern; an isolation structure comprising: a pad located on a sidewall of the lower active pattern and on the upper surface of the substrate; and a blocking pattern on the pad, the blocking pattern surrounding the sidewall of the lower active pattern and comprising nitride, carbide or polysilicon; a gate electrode structure located on the upper active pattern and the isolation structure; and a source / drain layer located on a portion of the active fin adjacent to the gate electrode structure, wherein the entire lower surface of the gate electrode structure is covered by the upper active pattern, the pad and the blocking pattern.

[0008] According to some aspects, the present disclosure relates to a semiconductor device, comprising: first active fins, the first active fins being spaced apart from each other by first recesses between the first active fins, the first recesses comprising a central portion, the central portion having a lower surface lower than a lower surface of an edge portion of the first recess, each of the first active fins protruding from a first region of a substrate, the substrate comprising the first region and a second region; second active fins, the second active fins being spaced apart from each other by second recesses between the second active fins, the second recesses comprising a central portion, the central portion having a lower surface lower than a lower surface of an edge portion of the second recess, each of the second active fins protruding from the second region of the substrate; a first isolation structure, comprising: a first insulating pattern filling the edge portion of the first recess a lower portion; and a stress structure filling the lower portion of the central portion of the first recess, the stress structure comprising a third insulating pattern and a liner, the liner covering the lower surface and sidewalls of the third insulating pattern; a second isolation structure comprising: a second insulating pattern filling the lower portion of the edge portion of the second recess; and a fourth insulating pattern filling the lower portion of the central portion of the second recess; a first gate electrode structure located on the first active fin and the first isolation structure; a second gate electrode structure located on the second active fin and the second isolation structure; a first source / drain layer located on a portion of each of the first active fins adjacent to the first gate electrode structure; and a second source / drain layer located on a portion of each of the second active fins adjacent to the second gate electrode structure.

[0009] In a semiconductor device according to example embodiments, a gate electrode structure and a source / gate layer adjacent to the gate electrode structure may not contact each other but may be spaced apart from each other by an isolation structure and a gate spacer so that an electrical short circuit may not occur between the gate electrode structure and the source / drain layer.

[0010] However, the effects of the present invention may not be limited to the above-described effects, and may be variously extended without departing from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 22 are plan views and cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to example embodiments.

[0012] Figure 23 to Figure 29 are plan views and cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to example embodiments.

[0013] Figure 30 to Figure 35 are cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to example embodiments.

[0014] Fig.36 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0015] Fig.37 and Fig.38 are cross-sectional views of stages of a method of fabricating a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0016] Semiconductor devices according to example embodiments will be described more fully hereinafter with reference to the accompanying drawings.

[0017] Figures 1 to 22 1 is a plan view and a cross-sectional view showing various stages of a method for manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 1 , Figure 6 , Fig. 9 , Fig.12 , Fig.15 and Fig.18 is a plan view, and Figures 2 to 5 , Figures 7 and 8 , Figure 10 to Figure 11 , Figure 13 to Figure 14 , Figure 16 to Figure 17 ,as well as Figures 19 to 22 It is a cross-sectional view.

[0018] Figures 2 to 5 , Fig.10 , Fig.13 and Fig.19 are sectional views taken along the line AA' of the corresponding plan view, Figure 7 , Fig.16 and Fig. 20 are sectional views taken along line BB' of the corresponding plan view, and Figure 8 , Fig.11 , Fig.14 , Fig.17 , Fig.21 and Fig. 22 Included are cross-sectional views respectively taken along line CC' and line DD' of the corresponding plan view.

[0019] refer to Figure 1 and Figure 2 , the upper portion of the substrate 100 may be partially etched to form the first active fin 105. Therefore, the first active fin 105 may protrude in a vertical direction substantially perpendicular to the upper surface of the substrate 100, and may include the same material as that of the substrate 100. The vertical direction may be a third direction substantially orthogonal to both the first direction and the second direction.

[0020] The substrate 100 may include semiconductor materials such as silicon, germanium, silicon germanium, etc., or III-V compounds such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] In example embodiments, after forming a first mask 110 on the substrate 100, an upper portion of the substrate 100 may be etched using the first mask 110 as an etching mask to form first active fins 105. The first active fins 105 may extend longitudinally in a first direction substantially parallel to the upper surface of the substrate 100, and a plurality of first active fins 105 may be formed in a second direction substantially parallel to the upper surface of the substrate 100 and intersecting the first direction. In example embodiments, the first direction and the second direction may be orthogonal to each other.

[0022] The first recesses 120 may be formed between the first active fins 105 and extend longitudinally in the first direction. For example, the first active fins 105 may be spaced apart from each other in the second direction by the first recesses 120 .

[0023] refer to Figure 3 , a first liner layer 130 may be formed on the first active fin 105, the first mask 110, and the substrate 100. After forming the first liner layer 130, a barrier layer 140 may be formed on the first liner layer 130 to partially or completely fill the first recess 120. The first liner layer 130 may be conformally formed on the surface on which it is deposited.

[0024] In example embodiments, the first liner layer 130 may include an oxide, such as silicon oxide, and may be conformally formed on the first active fin 105, the first mask 110, and the substrate 100. In some embodiments, the first liner layer 130 may have a substantially uniform thickness on the first active fin 105, the first mask 110, and the substrate 100. The first liner layer 130 may increase adhesion between the barrier layer 140 and the first active fin 105, and thus may be formed to have a small thickness.

[0025] In example embodiments, the barrier layer 140 may include a material having a high etch selectivity relative to oxide, for example, a nitride such as silicon nitride, a carbide such as silicon carbide, polysilicon, etc. The barrier layer 140 may be formed to fill at least a lower portion of the first recess 120. For example, the barrier layer 140 may completely fill a portion of more than half of the first recess 120 between adjacent first active fins 105.

[0026] refer to Figure 4 , an upper portion of the barrier layer 140 may be removed to form a barrier pattern 145 filling a lower portion of the first recess 120 .

[0027] When the blocking pattern 145 is formed, the upper portion of the first liner layer 130 may be exposed. For example, the first liner layer 130 may be exposed along the side surface of the upper portion of the first active fin 105 and the top and side surfaces of the first mask 110. The upper portion of the blocking layer 140 may be removed by, for example, an etch-back process.

[0028] refer to Figure 5 , after forming a sacrificial layer (not shown) on the first liner layer 130 to fill an upper portion of the first recess 120 , the sacrificial layer may be planarized until an upper surface of the first active fin 105 may be exposed.

[0029] The sacrificial layer may include an oxide, such as silicon oxide. In example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process. In the planarization process, portions of the first mask 110 and the first liner layer 130 on the surface of the first mask 110 may be completely removed.

[0030] The sacrificial layer may be removed to expose the upper surface of the barrier pattern 145 thereunder. In example embodiments, the sacrificial layer may be removed by an etch-back process, and a portion of the first liner layer 130 covering the upper sidewall of the first active fin 105 may also be removed together with the sacrificial layer to form a first liner 135 covering the lower sidewall of the first active fin 105 and the upper surface of the substrate 100. The first liner 135 and the barrier pattern 145 sequentially stacked and filling the lower portion of the first recess 120 may form a first isolation structure 155.

[0031] The first active fin 105 may include a first lower active pattern 105 b , a sidewall of which may be surrounded by the first isolation structure 155 , and a first upper active pattern 105 a protruding from an upper surface of the first isolation structure 155 in a vertical direction.

[0032] refer to Figures 6 to 8 , a dummy gate structure 190 may be formed on the first active fin 105 and the first isolation structure 155 .

[0033] A dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer may be sequentially formed on the first active fin 105 and the first isolation structure 155, the dummy gate mask layer may be patterned to form a dummy gate mask 180, and the dummy gate electrode layer and the dummy gate insulating layer may be sequentially etched using the dummy gate mask 180 as an etching mask to form a dummy gate structure 190.

[0034] Thus, a dummy gate structure 190 including a dummy gate insulating pattern 160 , a dummy gate electrode 170 , and a dummy gate mask 180 , which are sequentially stacked, may be formed on the substrate 100 .

[0035] The dummy gate insulating layer may include an oxide such as silicon oxide, the dummy gate electrode layer may include, for example, polysilicon, and the dummy gate mask layer may include a nitride such as silicon nitride.

[0036] The dummy gate insulating layer may be formed by, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. Alternatively, the dummy gate insulating layer may be formed by performing a thermal oxidation process on the first upper active pattern 105a of the first active fin 105, and in this case, the dummy gate insulating layer may be formed only on the upper surface of the first upper active pattern 105a. The dummy gate electrode layer and the dummy gate mask layer may also be formed by, for example, a CVD process, an ALD process, etc.

[0037] In example embodiments, the dummy gate structure 190 may lengthwise extend in the second direction, and a plurality of dummy gate structures 190 may be formed in the first direction.

[0038] refer to Figures 9 to 11 , a spacer layer covering the dummy gate structure 190 may be formed on the first active fin 105 and the first isolation structure 155, and the spacer layer may be anisotropically etched to form a gate spacer 200 on each pair of opposite sidewalls of the dummy gate structure 190 along the first direction. In this case, a fin spacer 210 may be formed on each pair of opposite sidewalls of the first active pattern 105a along the second direction.

[0039] The spacer layer may include a nitride, such as silicon nitride. In one embodiment, the spacer layer may have a stack structure including a nitride layer and an oxide layer.

[0040] An upper portion of the first active fin 105 adjacent to the gate spacer 200 may be etched to form a second recess 220 .

[0041] Fig.10 and Fig.11 It is shown that only a portion of the first upper active pattern 105a of the first active fin 105 is etched to form the second recess 220, so that the lower surface of the second recess 220 is higher than the upper surface of the first lower active pattern 105b, however, the embodiment may not be limited thereto. For example, not only the first upper active pattern 105a but also a portion of the first lower active pattern 105b may be etched to form the second recess 220, and thus the lower surface of the second recess 220 may be lower than the height of the upper surface of the portion of the first lower active pattern 105b where the second recess 220 is not formed.

[0042] When forming the second recess 220 , the fin spacer 210 on each pair of opposite sidewalls of the first upper active pattern 105 a may also be partially removed so that a portion of the fin spacer 210 may remain, or the fin spacer 210 may be completely removed.

[0043] In example embodiments, an etching process for forming the second recess 220 and an etching process for forming the gate spacer 200 and the fin spacer 210 may be performed in-situ.

[0044] refer to Figure 12 to Figure 14 , a first source / drain layer 230 filling the second recess 220 may be formed.

[0045] In example embodiments, the first source / drain layer 230 may be formed by performing a selective epitaxial growth (SEG) process using the upper surface of the first active fin 105 exposed by the second recess 220 as a seed.

[0046] In example embodiments, the SEG process may be performed using a silicon source gas, a germanium source gas, an etching gas, and a carrier gas, and thus a single crystal silicon germanium layer may be formed as the first source / drain layer 230. The SEG process may also be performed using a P-type impurity source gas, and thus a single crystal silicon germanium layer doped with a P-type impurity may be formed as the first source / drain layer 230.

[0047] Alternatively, the SEG process may be performed using a silicon source gas, a carbon source gas, an etching gas, and a carrier gas, and thus a single crystal silicon carbide layer may be formed as the first source / drain layer 230. The SEG process may also be performed using an N-type impurity source gas, and thus a single crystal silicon carbide layer doped with N-type impurities may be formed as the first source / drain layer 230. In some embodiments, the SEG process may be performed using a silicon source gas, an etching gas, and a carrier gas, and thus a single crystal silicon layer may be formed as the first source / drain layer 230. The SEG process may also be performed using an N-type impurity source gas, and thus a single crystal silicon layer doped with N-type impurities may be formed as the first source / drain layer 230.

[0048] The first source / drain layer 230 may be grown not only in the vertical direction (e.g., the third direction) but also in the horizontal direction (e.g., the first and / or second direction) to fill the second recess 220, and the upper portion of the first source / drain layer 230 may contact the sidewall of the gate spacer 200. In example embodiments, the first source / drain layer 230 may have a shape in which a cross section taken along the second direction may be similar to a pentagon. The term "contact" as used herein refers to a connection contact (i.e., touching), unless the context indicates otherwise.

[0049] In example embodiments, when first active fins 105 disposed adjacent in the second direction are close to each other, first source / drain layers 230 respectively grown on adjacent ones of the first active fins 105 may merge with each other at positions between the adjacent first active fins 105 . Fig.13 It is shown that two first source / drain layers 230 respectively grown on two adjacent first active fins 105 are merged with each other, however, the embodiment may not be limited thereto. Therefore, for example, more than two first source / drain layers 230 may be merged with each other.

[0050] After the insulating interlayer 240 covering the dummy gate structure 190, the gate spacer 200, the fin spacer 210, and the first source / drain layer 230 is formed to a sufficient height on the first active fin 105 and the first isolation structure 155, the insulating interlayer 240 may be planarized until the upper surface of the dummy gate electrode 170 may be exposed. After planarization, the top surface of the insulating interlayer 240 may be coplanar with the upper surface of the dummy electrode 170. During the planarization process, the dummy gate mask 180 may also be removed together with the insulating interlayer 240.

[0051] The space between the merged first source / drain layer 230 and the first isolation structure 155 may not be completely filled with the insulating interlayer 240, and thus an air gap 245 may be formed therein. The air gap 245 may be formed below the merged portion of the first source / drain layer 230 and above the first isolation structure 155. The air gap 245 may be defined by the first source / drain layer 230 and the first isolation structure 155.

[0052] The insulating interlayer 240 may include silicon oxide such as toner silazene (TOSZ). The planarization process may be performed through a CMP process and / or an etch-back process.

[0053] refer to Figures 15 to 17 The exposed dummy gate electrode 170 and the dummy gate insulating pattern 160 thereunder may be removed to form a first opening 250 exposing the inner sidewall of the gate spacer 200 and the upper surface of the first active fin 105 .

[0054] In example embodiments, the dummy gate electrode 170 and the dummy gate insulating pattern 160 thereunder may be removed through a dry etching process and a wet etching process.

[0055] The wet etching process may be performed using hydrofluoric acid (HF), and an upper portion of the first liner 135 included in the first isolation structure 155 below the dummy gate insulating pattern 160 may be partially removed. For example, a relatively small portion of the first liner 135 may be removed from between the barrier pattern 145 and the first lower active pattern 105 b near the upper surface of the barrier pattern 145. However, since the first liner 135 may have a relatively very small thickness, most of the lower surface of the first isolation structure 155 contacting the dummy gate insulating pattern 160 may be occupied by the barrier pattern 145.

[0056] In a wet etching process using hydrofluoric acid (HF), the barrier pattern 145 may include a material having a high etching selectivity with respect to an oxide included in the dummy gate insulating pattern 160, and thus may be hardly etched. Therefore, the first opening 250 may substantially expose only the first active pattern 105 a of the first active fin 105 and the barrier pattern 145 adjacent thereto in the second direction, and may not expose the first source / drain layer 230.

[0057] However, as described above, the upper portion of the first liner 135 may be partially removed, and thus the uppermost surface of the portion of the first liner 135 below the dummy gate insulating pattern 160 may be lower than the uppermost surface of the portion of the first liner 135 spaced apart therefrom in the first direction. In addition, the uppermost surface of the portion of the first liner 135 below the dummy gate insulating pattern 160 may be lower than the upper surface of the blocking pattern 145.

[0058] refer to Figures 18 to 21 , a first gate electrode structure 300 filling the first opening 250 may be formed.

[0059] Specifically, after performing a thermal oxidation process on the upper surface of the first active fin 105 exposed by the first opening 250 to form a first interface pattern 260, a gate insulation layer and a work function control layer can be sequentially formed on the first interface pattern 260, the first isolation structure 155, the gate spacer 200 and the insulating interlayer 240, and a gate electrode layer filling the remaining portion of the first opening can be formed on the work function control layer.

[0060] The work function control layer and the gate electrode layer may be formed by, for example, a CVD process, an ALD process, a physical vapor deposition (PVD) process, etc. A thermal treatment process may be further performed on the gate electrode layer, such as a rapid thermal annealing (RTA) process, a spike RTA process, a flash RTA process, or a laser annealing process, etc.

[0061] Similar to the gate insulating layer or the gate electrode layer, the first interface pattern 260 may be formed by a CVD process or an ALD process instead of a thermal oxidation process, and in this case, the first interface pattern 260 may be formed not only on the upper surface of the first active fin 105 but also on the upper surface of the first isolation structure 155 and the inner sidewall of the gate spacer 200. In some embodiments, the first interface pattern 260 may be formed in a space between the barrier pattern 145 and the first lower active pattern 105b near the upper surface of the barrier pattern 145, and a portion of the first liner 135 in the space is removed by a wet etching process performed using hydrofluoric acid (HF). Alternatively, the first interface pattern 260 may not be formed.

[0062] The gate electrode layer, the work function layer, and the gate insulation layer can be planarized until the upper surface of the insulating interlayer 240 is exposed to form a first gate insulation pattern 270 and a first work function control pattern 280 sequentially stacked on the upper surface of the first interface pattern 260, the upper surface of the first isolation structure 155, and the inner side wall of the gate insulator 200, and a first gate electrode 290 filling the remaining portion of the first opening 250 can be formed on the first work function control pattern 280.

[0063] The first interface pattern 260, the first gate insulating pattern 270, the first work function control pattern 280, and the first gate electrode 290, which are sequentially stacked, may form a first gate electrode structure 300, and may form a transistor together with the first source / drain layer 230. The transistor may form a PMOS transistor or an NMOS transistor according to the conductivity type of the first source / drain layer 230.

[0064] As described above, since the first opening 250 may not expose the first source / drain layer 230 , the first gate electrode structure 300 filling the first opening 250 and the first source / drain layer 230 may not contact each other, and an electrical short may not occur therebetween.

[0065] refer to Fig. 22 After removing the upper portions of the first gate electrode structure 300 and the gate spacer 200 to form the third recess, a capping pattern 310 filling the third recess may be formed.

[0066] The capping pattern 310 may be formed by forming a capping layer filling the third recess on the first gate electrode structure 300 , the gate spacer 200 , and the insulating interlayer 240 , and planarizing the capping layer until an upper surface of the insulating interlayer 240 is exposed.

[0067] In example embodiments, the capping pattern 310 may include nitride, eg, silicon nitride.

[0068] The first gate electrode structure 300 , the gate spacer 200 covering the sidewalls of the first gate electrode structure 300 , and the capping pattern 310 covering the upper surfaces of the first gate electrode structure 300 and the gate spacer 200 may be collectively referred to as a first gate structure.

[0069] Wirings, vias, and contact plugs electrically connected to the first source / drain layer 230 and / or the first gate electrode structure 300 may be formed to complete the manufacture of the semiconductor device.

[0070] The semiconductor device may include a first active fin 105, a first isolation structure 155, a first gate electrode structure 300, and a first source / drain layer 230, wherein the first active fins 105 protrude from the upper surface of the substrate 100 and are spaced apart from each other by a first recess 120 therebetween, the first isolation structure 155 including a first liner 135 on the lower sidewall and lower surface of the first recess 120 and a blocking pattern 145 on the first liner 135 filling the remaining portion of the lower portion of the first recess 120, the first gate electrode structure 300 on the first active fin 105 and the first isolation structure 155, and the first source / drain layer 230 on a portion of each of the first active fins 105 adjacent to the first gate electrode structure 300.

[0071] The semiconductor device may further include a gate spacer 200 covering a sidewall of the first gate electrode structure 300 , and the first gate electrode structure 300 and the first source / drain layer 230 may be electrically insulated from each other by the gate spacer 200 and a first isolation structure 155 including a barrier pattern 145 .

[0072] Figure 23 to Figure 29 1 is a plan view and a cross-sectional view showing various stages of a method for manufacturing a semiconductor device according to a comparative example embodiment. Specifically, Fig.24 and Fig. 27 is a plan view, and Fig.23 , Fig.25 , Fig.26 , Fig.28 , Fig.29 It is a cross-sectional view.

[0073] Respectively, Fig.23 is a sectional view taken along the line AA' of the corresponding plan view, Fig.25 and 28 is a cross-sectional view taken along line BB' of the corresponding plan view, and Fig.26 and Fig.29 Included are cross-sectional views respectively taken along line CC' and line DD' of the corresponding plan view.

[0074] The exemplary method of manufacturing a semiconductor device includes Figures 1 to 22 The processes included in the method shown in are substantially the same or similar processes, and thus a detailed description thereof is omitted here.

[0075] refer to Fig.23 , in execution with Figure 1 and Figure 2 After a process substantially the same as or similar to the illustrated process, an isolation pattern 150 filling a lower portion of the first recess 120 may be formed.

[0076] The isolation pattern 150 may be formed by forming an isolation layer on the first active fin 105 , the first mask 110 , and the substrate 100 , planarizing the isolation layer until an upper surface of the first active fin 105 is exposed, and removing an upper portion of the isolation layer.

[0077] The isolation pattern 150 may include oxide, for example, silicon oxide.

[0078] refer to Figure 24 to Figure 26 , can be executed with Figures 6 to 17 The processes shown in are substantially the same or similar processes.

[0079] However, when the dummy gate insulating pattern 160 is removed by a wet etching process using hydrofluoric acid (HF), a portion of the isolation pattern 150 in contact with the lower surface of the dummy gate insulating pattern 160 and a portion of the isolation pattern 150 adjacent thereto in the first direction may be completely removed. Therefore, a fourth recess 255 connected to the lower portion of the first opening 250 and extending longitudinally by a given length in the first direction may be formed on the isolation pattern 150. The fourth recess 255 may extend below the upper surface of the barrier pattern 145 and be formed in an upper portion of the first isolation structure 155. A portion of the fourth recess 255 may be formed below a portion of the gate spacer 200 and the first source / drain layer 230. Therefore, a portion of the lower surface of the first source / drain layer 230 adjacent to the gate spacer 200 may be exposed through the fourth recess 255.

[0080] refer to Figure 27 to Figure 29 , can be executed with Figures 18 to 21 The processes shown in are substantially the same or similar processes.

[0081] Thus, a second gate electrode structure 305 including a second interface pattern 265, a second gate insulating pattern 275, a second work function control pattern 285, and a second gate electrode 295 stacked sequentially may be formed to fill the first opening 250 and the fourth recess 255. The second gate electrode structure 305 may contact a portion of the lower surface of the first source / drain layer 230 through the fourth recess 255, so that an electrical short circuit may occur between the second gate electrode structure 305 and the first source / drain layer 230.

[0082] In accordance with Figures 1 to 22 In the method of manufacturing a semiconductor device in the illustrated example embodiment, the first opening 250 formed by a wet etching process using hydrofluoric acid (HF) may not expose the first source / drain layer 230 , and thus an electrical short may not occur between the first gate electrode structure 300 and the first source / drain layer 230 .

[0083] Figure 30 to Figure 35 are cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to example embodiments.

[0084] The method for manufacturing a semiconductor device comprises: Figures 1 to 22 The processes included in the method shown in are substantially the same or similar processes, and thus a detailed description thereof is omitted here.

[0085] refer to Fig.30 , an upper portion of the substrate 400 may be partially etched to form the second active fin 402 and the third active fin 404 .

[0086] The substrate 400 may include a first region I and a second region II. In example embodiments, the first region I may be an NMOS region, and the second region II may be a PMOS region.

[0087] In example embodiments, after forming a second mask 412 and a third mask 414 on the first region I and the second region II of the substrate 400, respectively, an upper portion of the substrate 400 may be etched by using the second mask 412 and the third mask 414 as etching masks to form second active fins 402 and third active fins 404 on the first region I and the second region II, respectively. Each of the second active fins 402 and the third active fins 404 may extend longitudinally in a first direction substantially parallel to the upper surface of the substrate 400, and a plurality of second active fins 402 and a plurality of third active fins 404 may be formed in a second direction substantially parallel to the upper surface of the substrate 400 and intersecting the first direction.

[0088] The second active fins 402 may be spaced apart from each other in the second direction by the fifth recesses 403 , and the third active fins 404 may be spaced apart from each other in the second direction by the sixth recesses 405 .

[0089] refer to Fig.31 After forming the first insulating layer 420 covering the second active fins 402, the third active fins 404, the second mask 412, and the third mask 414 on the substrate 400 to fill the fifth recess 403 and the sixth recess 405, one or more of the second active fins 402, the second mask 412 thereon, the portion of the first insulating layer 420 covering the one or more of the second active fins 402, and the upper portion of the substrate 400 thereunder can be removed to form a second opening 432 on the first region I of the substrate 400, and one or more of the third active fins 404, the third mask 414 thereon, the portion of the first insulating layer 420 covering the one or more of the third active fins 404, and the upper portion of the substrate 400 thereunder can be removed to form a third opening 434 on the second region II of the substrate 400.

[0090] Therefore, the second opening 432 may be formed in the fifth recess 403 to have a lower surface lower than the lower surface of the fifth recess 403, and may be considered as a part of the fifth recess 403. In this case, the lower surface of the central portion of the fifth recess 403 may be lower than the lower surface of the edge portion of the fifth recess 403. For example, the lower surface of the edge portion of the fifth recess 403 may be the lower surface of the portion below the first insulating layer 420 covering the sidewall of the second active fin 402, and the lower surface of the central portion of the fifth recess 403 may be the lower surface of the portion between the adjacent edge portions. In addition, the third opening 434 may be formed in the sixth recess 405 to have a lower surface lower than the lower surface of the sixth recess 405, and may be considered as a part of the sixth recess 405. In this case, the lower surface of the central portion of the sixth recess 405 may be lower than the lower surface of the edge portion of the sixth recess 405. For example, the lower surface of the edge portion of the sixth recess 405 may be the lower surface of the portion below the first insulating layer 420 covering the sidewall of the third active fin 404 , and the lower surface of the central portion of the sixth recess 405 may be the lower surface of the portion between adjacent edge portions.

[0091] In example embodiments, the first insulating layer 420 may include oxide, eg, silicon oxide.

[0092] In example embodiments, each of the second opening 432 and the third opening 434 may longitudinally extend in the first direction, and thus each portion of the first insulation layer 420 longitudinally extending in the first direction may include the second active fin 402 or the third active fin 404 therein.

[0093] Fig.31 It is shown that the first insulating layer 420 covers only one second active fin 402 between the second openings 432 on the first region I of the substrate 400, and covers only one third active fin 404 between the third openings 432 on the second region II of the substrate 400, however, the embodiment may not be limited thereto. For example, the first insulating layer 420 may include one or more second active fins 402, or one or more third active fins 404 therein.

[0094] refer to Fig.32 After forming a second insulating pattern 442 and a third insulating pattern 444 filling the second opening 432 and the third opening 434 on the first region I and the second region II of the substrate 400, respectively, a fourth mask 450 can be formed on the first insulating layer 420 and the third insulating pattern 444 on the second region II of the substrate 400.

[0095] The second insulating pattern 442 and the third insulating pattern 444 may include substantially the same material and may include nitride, such as silicon nitride. The fourth mask 450 may include, for example, a spin-on-hard mask (SOH), an amorphous carbon layer (ACL), or the like.

[0096] refer to Fig.33 , after removing the second insulating pattern 442 to form the second opening 432 again, a second liner 460 may be formed on an inner wall of the second opening 432 , and a fourth insulating pattern 470 may be formed to fill a remaining portion of the second opening 432 .

[0097] In example embodiments, the second liner 460 may include an oxide, eg, silicon oxide, and the fourth insulating pattern 470 may include a nitride, eg, silicon nitride. The second liner 460 and the fourth insulating pattern 470 may form a first stress structure 480 .

[0098] The first stress structure 480 may apply compressive stress to each of the second active fins 402 in the second direction, and thus may apply tensile stress to each of the second active fins 402 in the first direction. Therefore, mobility of charges in a channel in each of the second active fins 402 may be increased.

[0099] Then, the fourth mask 450 may be removed. The fourth mask 450 may be removed by, for example, an ashing process and / or a stripping process.

[0100] refer to Fig.34 , the first insulating layer 420, the first stress structure 480 and the upper portion of the third insulating pattern 444 can be removed to expose the second upper active pattern 402a of the second active fin 402 on the first region I of the substrate 400, and expose the third upper active pattern 404a of the third active fin 404 on the second region II of the substrate 400.

[0101] A fifth insulating pattern 422 may be formed by removing a remaining portion of the upper first insulating layer 420 on the first region I of the substrate 400 , and a sixth insulating pattern 424 may be formed by removing a remaining portion of the upper first insulating layer 420 on the second region II of the substrate 400 .

[0102] The first stress structure 480 in the lower portion of the second opening 432 may surround the sidewalls of the second lower active pattern 402b of the second active fin 402, and may form a second isolation structure together with the fifth insulation pattern 422 contacting the sidewalls of the second lower active pattern 402b. Also, the third insulation pattern 444 in the lower portion of the third opening 434 may surround the sidewalls of the third lower active pattern 404b of the third active fin 404, and may form a third isolation structure together with the sixth insulation pattern 424 contacting the sidewalls of the third lower active pattern 404b. As used herein, the term "contact" refers to direct contact (i.e., touching), unless the context indicates otherwise.

[0103] In some embodiments, the fifth insulating pattern 422 and the stress structure 480 may form a second isolation structure, wherein the second insulating pattern 422 fills a lower portion of an edge portion of the fifth recess 403, and the stress structure 480 fills a lower portion of a central portion of the fifth recess 403. The sixth insulating pattern 424 and the third insulating pattern 444 may form a third isolation structure, wherein the sixth insulating pattern 424 fills a lower portion of an edge portion of the sixth recess 405, and the third insulating pattern 444 fills a lower portion of a central portion of the sixth recess 405.

[0104] refer to Fig.35 , can be executed with Figures 6 to 21 The processes included in the process are substantially the same or similar to the process, so that a third gate electrode structure 532 and a third source / drain layer (not shown) on the second active fin 402 adjacent to the third gate electrode structure 532 can be formed on the first region I of the substrate 400, and a fourth gate electrode structure 534 and a fourth source / drain layer (not shown) on the third active fin 404 adjacent to the fourth gate electrode structure 534 can be formed on the second region II of the substrate 400.

[0105] The third gate electrode structure 532 may include a third interface pattern 492, a third gate insulation pattern 502, a third work function control pattern 512, and a third gate electrode 522 stacked sequentially, and the fourth gate electrode structure 534 may include a fourth interface pattern 494, a fourth gate insulation pattern 504, a fourth work function control pattern 514, and a fourth gate electrode 524.

[0106] The semiconductor device according to the example embodiment may include an NMOS transistor on a first region I and a PMOS transistor on a second region II of a substrate 400, respectively, and since a second active fin 402 that may form a channel of the NMOS transistor may be subjected to tensile stress in a first direction through a first stress structure 480 including a second liner 460 and a fourth insulating pattern 470, the mobility of carriers (i.e., charges) in the channel may be increased, so that the semiconductor device may have improved performance.

[0107] When the fifth insulating pattern 422 and the sixth insulating pattern 424 are formed to have a thinner thickness, similar to Figures 1 to 22 In the semiconductor device manufactured by the process shown in , the second isolation structure and the third isolation structure can be hardly removed in the wet etching process used to form the third gate electrode structure 532 and the fourth gate electrode structure 534, respectively, and thus electrical short circuits between the third gate electrode structure 532 and the third source / drain layer and between the fourth gate electrode structure 534 and the fourth source / drain layer can be prevented.

[0108] Fig.36 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0109] Except for the second pad, the semiconductor device is substantially the same as Figure 30 to Figure 35 Therefore, the same reference numerals refer to the same elements, and detailed descriptions thereof are omitted here.

[0110] refer to Fig.36 The second isolation structure covering the sidewalls of the second lower active pattern 402b of the second active fin 402 (on which the NMOS transistor may be formed on the first region I of the substrate 400) may include a fifth insulating pattern 422 and a fourth insulating pattern 470, but may not include a second liner 460.

[0111] This can be done by Fig.33 In the illustrated process, only the fourth insulating pattern 470 is formed in the second opening 432 without forming the second liner 460. In this case, only the fourth insulating pattern 470 can form the first stress structure 480, and in order to apply a desired degree of stress to the second active fin 402, the composition of the material included in the fourth insulating pattern 470 can be adjusted.

[0112] Fig.37 and Fig.38 are cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to example embodiments.

[0113] The method for manufacturing a semiconductor device comprises: Figure 30 to Figure 35 The processes in the method shown in are substantially the same or similar processes, and thus a detailed description thereof is omitted here.

[0114] refer to Fig.37 , in execution with Figure 30 to Figure 32 A thermal treatment process may be performed on the first region I of the substrate 400 after a process substantially the same as or similar to the process shown in FIG.

[0115] In example embodiments, the heat treatment process may be performed under an oxygen atmosphere or a hydrogen atmosphere. Thus, physical properties of the second insulating pattern 442 may be changed, and the second insulating pattern 442 may be converted into the seventh insulating pattern 446.

[0116] In example embodiments, the seventh insulating pattern 446 may apply compressive stress to the second active fin 402 in the second direction, and thus may apply tensile stress to the channel in the second active fin 402 in the first direction. Therefore, mobility of carriers in the channel, that is, charges in the channel may increase.

[0117] refer to Fig.38 After removing the fourth mask 450, the Figure 34 to Figure 35 The processes shown in the drawings are substantially the same or similar processes to complete the manufacture of the semiconductor device.

[0118] In each of the NMOS transistor and the PMOS transistor included in the semiconductor device, electrical short circuit between the third gate electrode structure 532 and the third source / drain layer (not shown) adjacent thereto and between the fourth gate electrode structure 534 and the fourth source / drain layer (not shown) adjacent thereto can be prevented.

[0119] The semiconductor device described above can be applied to various types of memory devices and systems including finFETs. For example, the semiconductor device can be applied to logic devices such as a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP) including finFETs. In addition, the semiconductor device can be applied to volatile memory devices such as DRAM devices or SRAM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, RRAM devices, etc., which can include finFETs in a peripheral circuit region or a cell region.

[0120] As noted above, although the invention has been described with reference to exemplary embodiments, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept.

Claims

1. A semiconductor device, comprising: active fins, the active fins being spaced apart from each other by recesses between the active fins, each of the active fins protruding from an upper surface of a substrate; An isolation structure, formed in the recess, comprising: a gasket on a lower surface and side walls of a lower portion of the recess; and a barrier pattern on the liner, the barrier pattern filling a remaining portion of the lower portion of the recess and comprising nitride, carbide, or polysilicon; a gate electrode structure located on the active fin and the isolation structure; and a source / drain layer located on a portion of each of the active fins adjacent to the gate electrode structure, wherein each of the active fins extends longitudinally in a first direction substantially parallel to the upper surface of the substrate, wherein the gate electrode structure extends longitudinally in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction, and The uppermost surface of a first portion of the pad below the gate electrode structure is lower than the uppermost surface of a second portion of the pad spaced apart from the first portion of the pad in the first direction.

2. The semiconductor device according to claim 1, in, The liner comprises an oxide, and wherein the barrier pattern contacts the pad.

3. The semiconductor device according to claim 1, further comprising: a gate spacer covering a sidewall of the gate electrode structure, Wherein, the source / drain layer is electrically insulated from the gate electrode structure by the gate spacer and the isolation structure. 4 . The semiconductor device according to claim 1 , wherein the source / drain layer is formed on a portion of each of the active fins adjacent to the gate electrode structure along the first direction. 5 . The semiconductor device according to claim 1 , wherein an uppermost surface of a portion of the liner under the gate electrode structure is lower than an upper surface of the barrier pattern.

6. The semiconductor device according to claim 1, wherein each of the active fins includes a lower active pattern and an upper active pattern stacked on the lower active pattern, and The isolation structure covers the sidewalls of the lower active pattern. 7 . The semiconductor device according to claim 6 , wherein the gate electrode structure is formed on an upper surface and sidewalls of the upper active pattern and on an upper surface of the isolation structure.

8. The semiconductor device according to claim 1, wherein the gate electrode structure comprises an interface pattern on an upper surface of each of the active fins, and a gate insulation pattern, a work function control pattern, and a gate electrode sequentially stacked on the interface pattern and the isolation structure.

9. A semiconductor device comprising: an active fin protruding from an upper surface of the substrate and including a lower active pattern and an upper active pattern stacked on the lower active pattern; An isolation structure comprising: a spacer located on a sidewall of the lower active pattern and the upper surface of the substrate; and a blocking pattern on the liner, the blocking pattern surrounding the sidewall of the lower active pattern and including nitride, carbide or polysilicon; a gate electrode structure located on the upper active pattern and the isolation structure; and a source / drain layer located on a portion of the active fin adjacent to the gate electrode structure, wherein the entire lower surface of the gate electrode structure is covered by the upper active pattern, the pad and the barrier pattern, and The uppermost surface of the first portion of the pad below the gate electrode structure is lower than the uppermost surface of the second portion of the pad, and the second portion of the pad is spaced apart from the first portion of the pad in a first direction substantially parallel to the upper surface of the substrate. 10 . The semiconductor device according to claim 9 , wherein the liner comprises a material different from a material of the barrier pattern.

11. The semiconductor device according to claim 9, further comprising: a gate spacer covering a sidewall of the gate electrode structure, The source / drain layer is electrically insulated from the gate electrode structure by the gate spacer and the isolation structure.

12. The semiconductor device according to claim 9, wherein the active fins extend longitudinally in the first direction, and The gate electrode structure extends longitudinally in a second direction that is substantially parallel to the upper surface of the substrate and intersects the first direction. 13 . The semiconductor device according to claim 12 , wherein the source / drain layer is formed on a portion of the active fin adjacent to the gate electrode structure along the first direction. 14 . The semiconductor device according to claim 11 , wherein an uppermost surface of a portion of the liner under the gate electrode structure is lower than an upper surface of the barrier pattern.

Images