Switching power converter and method and circuit for controlling the switching power converter

Abstract

The present invention is entitled "Switching power converter and method and circuit for controlling the switching power converter". The present invention provides a switching power converter and a method and circuit for controlling the switching power converter. In a power converter having a primary side and a secondary side separated by a main transformer, an exemplary method may include: driving a primary current through a primary winding of the main transformer; generating a signal indicating a current through the primary winding of the main transformer on the secondary side of the main transformer; and stopping driving the primary current through the primary winding when the signal indicating the primary current reaches a predetermined value.

Description

Technical Field

[0001] The present patent application relates to the technical field of power converters, in particular to a switching power converter and a method and circuit for controlling the switching power converter. Background Art

[0002] The switching power converter implements a primary side controller that controls the duty cycle of a pulse width modulation (PWM) signal applied to the gate of a primary field effect transistor (FET). In many cases, the feedback parameter for the control loop is a signal indicative of an output voltage provided from the secondary side via an optocoupler having its light emitting diode (LED) operatively coupled to the output voltage of the power converter and its optically driven transistor coupled to provide a signal indicative of the output voltage to the primary side controller. Summary of the invention

[0003] An exemplary method may include: driving a primary current through a primary winding of a main transformer of a power converter; generating a signal indicative of the primary current on a secondary side of the main transformer; and stopping driving the primary current through the primary winding when the signal indicative of the primary current reaches a predetermined value.

[0004] In the exemplary method, driving the primary current may further include: sending an effective control signal from the secondary side to the primary side; and turning on a main switch on the primary side in response to the effective control signal. Stopping driving the primary current may further include: sending a de-effective control signal from the secondary side to the primary side; and turning off the main switch on the primary side in response to the de-effective control signal. Sending the effective signal may further include sending through a system that provides galvanic isolation between the primary side and the secondary side. Sending through a system that provides galvanic isolation may further include at least one selected from the group consisting of: sending through a gate drive transformer different from the main transformer; sending through an optocoupler; and sending through the main transformer.

[0005] In the exemplary method, generating a signal indicating the primary current on the secondary side of the main transformer may further include: sensing the output voltage of the power converter; sensing the voltage at the node between the secondary winding of the main transformer and the rectifier on the secondary side; and charging a capacitor in response to a voltage difference between a voltage at a switch node and the output voltage, the voltage on the capacitor being a signal indicating the primary current. After charging the capacitor, the method may include: sensing the output voltage of the power converter; sensing the voltage at the node between the secondary winding of the main transformer and the rectifier on the secondary side; and discharging the capacitor in response to a voltage difference between a voltage at the switch node and the output voltage, the voltage on the capacitor being a signal indicating the primary current.

[0006] In the exemplary method, generating a signal indicative of the primary current on the secondary side of the main transformer may also include: sensing a voltage at a node between the secondary winding of the transformer and a rectifier on the secondary side; and charging a capacitor in response to a voltage at a switching node, the voltage on the capacitor being a signal indicative of the primary current.

[0007] In the exemplary method, driving the primary current may further include driving the primary current through a primary winding of the power converter arranged for a flyback operation.

[0008] In the exemplary method, driving the primary current may further include driving the primary current through a primary winding of the power converter arranged for forward operation.

[0009] Another exemplary embodiment is a circuit for controlling a switching power converter, the circuit comprising: a gate terminal, a winding sensing terminal, an output voltage terminal, a primary pulse width modulation (PWM) terminal, and an external capacitor terminal; a first substrate; a PWM controller, the PWM controller being defined on the first substrate and electrically coupled to the output voltage terminal and the PWM terminal, the PWM controller being configured to generate a primary PWM signal driven to the primary PWM terminal; an emulation controller, the emulation controller being defined on the first substrate, the emulation controller being electrically coupled to the winding sensing terminal, the output voltage terminal, and the external capacitor terminal, the emulation controller being configured to generate a signal indicating a primary current by driving the current to the external capacitor terminal; and wherein the PWM controller is also coupled to the signal indicating the primary current, and the PWM controller is configured to control a duty cycle of the primary PWM signal based on the signal indicating the primary current.

[0010] In this exemplary circuit: the PWM controller may be configured to assert a primary PWM signal to cause a main field effect transistor (FET) on a primary side of a switching power converter to become conductive; the emulation controller may generate a signal indicative of a primary current in response to assertion of the primary PWM signal; the PWM controller may be configured to deassert the primary PWM signal when the signal indicative of the primary current reaches a predetermined threshold. The emulation controller may reset the signal indicative of the primary current when the PWM controller deasserts the primary PWM signal. The PWM controller may set the predetermined threshold at least in part in response to a voltage on an output voltage terminal.

[0011] In the exemplary circuit, the simulation controller may also include: a differential amplifier defining a first differential input, a second differential input, and an amplifier output, the first differential input being coupled to the winding sensing terminal, the second differential input being coupled to the output voltage terminal, and the amplifier output being coupled to the external capacitor terminal; and an electrically controlled switch being coupled between the external capacitor terminal and ground, the electrically controlled switch having a control input coupled to a gate terminal.

[0012] In the exemplary circuit, the simulation controller may also include: an amplifier defining a first input and an amplifier output, the first input being coupled to the winding sensing terminal and the amplifier output being coupled to the external capacitor terminal; and an electrically controlled switch coupled between the external capacitor terminal and ground, the electrically controlled switch having a control input coupled to the gate terminal.

[0013] The exemplary circuit may also include: a second substrate different from the first substrate; and a primary side controller defined on the second substrate, the primary side controller configured to drive the gate output terminal in response to a signal from the secondary side controller.

[0014] The exemplary circuit may also include: a second substrate, which is different from the first substrate; a primary side controller, which is defined on the second substrate, and the primary side controller is configured to drive the gate output terminal in response to a signal from the secondary side controller; and a galvanic isolation circuit, which is disposed within the packaged circuit and is communicatively coupled between the secondary side controller and the primary side controller.

[0015] Another exemplary embodiment is a power converter. The power converter includes a primary side and a secondary side. The primary side may include: a primary winding of a main transformer; a primary field effect transistor (FET) coupled to the primary winding, the primary FET having a gate; a primary side controller defining a pulse input and a gate output, the gate output coupled to the gate of the FET, the primary side controller being configured to drive the gate output in response to a PWM signal received on the pulse input. The secondary side may include: a secondary winding of the main transformer; a secondary FET coupled to the secondary winding and defining a gate; a secondary side controller defining a gate terminal, a winding sensing terminal, an output voltage terminal, a primary pulse width modulation (PWM) terminal, and a capacitor terminal, the gate terminal being coupled to the gate of the secondary FET, the winding sensing terminal being coupled to a node between the secondary winding and the secondary FET; a capacitor coupled between the capacitor terminal of the secondary side controller and ground; an isolation circuit providing galvanic isolation, the isolation circuit being coupled between the PWM terminal of the secondary side controller and a pulse input of the primary side controller. The secondary side controller is configured to: command the primary side controller to turn on the primary FET to induce a primary current through the primary winding, the command being passed through the isolation circuit via the primary PWM terminal; generate a signal indicative of the primary current; and command the primary side controller to turn off the primary FET when the signal indicative of the primary current reaches a predetermined value, the command being passed through the isolation circuit via the primary PWM terminal.

[0016] In an exemplary power converter, the secondary side controller may also include: a substrate; a PWM controller defined on the substrate and electrically coupled to the output voltage terminal and the PWM terminal, the PWM controller being configured to generate a primary PWM signal driven to the primary PWM terminal; a simulation controller defined on the substrate, the simulation controller being electrically coupled to the winding sensing terminal, the output voltage terminal and the capacitor terminal, the simulation controller being configured to generate a signal indicating the primary current by driving the current to the capacitor terminal; and wherein the PWM controller is also coupled to the signal indicating the primary current, and the PWM controller is configured to control the duty cycle of the primary PWM signal based on the signal indicating the primary current.

[0017] In an exemplary power converter, the secondary winding and the secondary FET may be arranged for flyback operation. In an exemplary power converter, the secondary winding and the secondary FET may be arranged for forward operation. The primary winding and the primary FET may be arranged for at least one selected from the group consisting of: a half-bridge topology; and a full-bridge topology.

[0018] In the exemplary power converter, the isolation circuit may be at least one selected from the group consisting of: a communication transformer that is different from the main transformer; and an optocoupler. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To describe in detail the exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0020] Figure 1 shows a schematic diagram of a switching power converter according to at least some embodiments;

[0021] Figure 2 shows a simulation circuit according to at least some embodiments;

[0022] Figure 3 A switching power converter according to at least some embodiments is shown;

[0023] Figure 4 shows a block diagram of a secondary side controller according to at least some embodiments;

[0024] Figure 5 shows a circuit diagram of a power converter according to at least some embodiments;

[0025] Figure 6 shows a block diagram of a simulation controller according to at least some embodiments; and

[0026] Figure 7 Methods according to at least some embodiments are shown.

[0027] definition

[0028] Various terms are used to refer to specific system components. Different companies may refer to a component by different names - this document is not intended to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "include" and "comprising" are used in an open-ended manner, and therefore, these terms should be interpreted to mean "including but not limited to...". In addition, the terms "couple" or "coupled" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0029] "Controller" shall mean a separate circuit component configured to read signals and take action in response to such signals, a separate circuit component on a substrate, an application-specific integrated circuit (ASIC) constructed on a substrate, a microcontroller constructed on a substrate (with control software stored on or off the substrate), or a combination thereof.

[0030] With respect to an electrical device (eg, on a substrate), the terms "input" and "output" refer to electrical connections to the electrical device and should not be considered verbs requiring action. For example, a controller may have a gate output and one or more sense inputs.

[0031] Reference to actions occurring on the "secondary side" of a transformer should mean the generation or modification of electrical signals with energy derived from the secondary winding of the main transformer. Thus, "on the secondary side" is in some cases a spatial constraint (because in many cases the actions occurring "on the secondary side" will be physically on the secondary side), and "on the secondary side" is an electrical constraint. DETAILED DESCRIPTION

[0032] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it should be understood by those skilled in the art that the following description has a wide range of applications, and the discussion of any embodiment is only intended to be an example of that embodiment, and is not intended to indicate that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0033] The duty cycle of the pulse width modulation (PWM) signal applied to the gate of the main FET controls the peak current generated through the primary winding in each switching cycle. In critical conduction mode (CrM) and discontinuous conduction mode (DCM), the peak current through the primary winding is the controlled variable in the control loop (i.e., peak current control). That is, the control loop modulates the set point of the peak current in each switching cycle, where a lower set point of the peak current results in a shorter duty cycle of the PWM signal, and a higher set point of the peak current results in a longer duty cycle.

[0034] For transient load and adjustable load scenarios (Universal Serial Bus (USB) Power Delivery (PD) operation mode), the reaction time of the primary side controller may be too slow to ensure that the output voltage remains within acceptable limits. In addition, controlling the secondary side switch (synchronous rectifier (SR)) from the secondary without any information about the duty cycle and frequency of the main power switch is unreliable. This usually results in breakdown or premature disconnection of the SR switch.

[0035] Various exemplary embodiments relate to a switching power converter that implements peak primary current control on a secondary-side switching power converter. More specifically, in an exemplary embodiment, when the main field effect transistor (FET) is turned on, the secondary-side controller implements peak current mode control of the current through the primary winding. However, because the peak current mode control is implemented on the secondary side, the secondary-side controller emulates the primary current. Still more specifically, in an exemplary embodiment, a pulse width modulation (PWM) signal driven to the gate of the main FET is initially generated by the secondary-side controller and transmitted to the primary side via a system that provides galvanic isolation. The secondary-side controller commands the primary-side controller to turn on the primary FET, which causes a current through the primary winding of the main transformer. The secondary-side controller also generates a signal indicating the primary current, and when the signal indicating the primary current reaches a predetermined value, the secondary-side controller commands the primary-side controller to turn off the primary FET. The secondary-side controller is responsible for generating a primary PWM signal to make the entire switching power converter better respond to load transients and changes in output voltage (e.g., caused by implementing multiple power transmission modes). The description now turns to an exemplary switching power converter to familiarize the reader, as well as to provide a mathematical basis for emulating primary current on the secondary side of the power converter.

[0036] Figure 1 1 shows a schematic diagram of a switching power converter 100 (hereinafter referred to only as "power converter 100") according to at least some embodiments. In particular, power converter 100 includes a primary side 102 galvanically isolated from a secondary side 104 via a main transformer 106. A direct current (DC) supply voltage V DC is supplied to the power converter 100. The power converter generates a DC output voltage V OUT (The load is exemplarily shown as a load resistor R L ). The primary side 102 includes a primary winding 108 of a main transformer 106. A first lead or a first connection of the primary winding 108 is coupled to a supply voltage V DC The second lead or second connection of the primary winding 108 is coupled to the main FET 110. In particular, the main FET 110 defines a drain 112, a gate 114, and a source 116. The drain 112 is coupled to the second connection of the primary winding 108. The source 116 is coupled to an exemplary sense resistor 118, and the second side of the sense resistor is coupled to ground. The gate 114 is coupled to the primary side controller (at Figure 1 not shown).

[0037] On the secondary side 104, the exemplary power converter 100 includes a secondary winding 120 of the main transformer 106. A first lead or first connection of the secondary winding 120 is coupled to the output voltage V OUTThe positive terminal of the secondary winding 120 is connected to the positive terminal of the secondary winding 120, and the second lead or second connection is coupled to the secondary FET 122. The secondary FET 122 defines a drain 124, a gate 126, and a source 128. The drain 124 is coupled to the second connection of the secondary winding 120. The source is coupled to the ground or common terminal on the secondary side 104. The gate is coupled to the secondary side controller (at Figure 1 The secondary FET 122 may include a body diode 136 between the drain 124 and the source 128. The secondary side 104 also includes a smoothing filter capacitor 130, which is coupled to the output voltage V OUT The positive terminal and output voltage V OUT In some embodiments, it may also include a post-LC filter capacitor 130 to further reduce ripple or in some cases create a secondary resonant circuit for waveform formation.

[0038] In operation, the exemplary power converter 100 operates by transferring energy across the main transformer 106 by turning the main FET 110 on and then off. That is, when the main FET 110 is on, current builds up through the primary winding 108, from the voltage source V DC The peak current flows through the primary winding 108, through the main FET 110, and through the sense resistor 118 to ground. Once the current reaches a predetermined value (hereinafter referred to as the "peak current"), the main FET 110 is rendered non-conductive. Additional clamping circuitry may be implemented on the primary side 102, but is not shown to avoid overly complicating the drawing. The peak current value is based on various factors, such as the desired output voltage V OUT and the current supplied to the load).

[0039] During the time period when the main FET is conducting, a voltage is induced on the secondary winding 120 having a polarity such as Figure 1 124 side, but during the time period when the main FET 110 is conducting, the secondary FET 122 is in a non-conducting state and no current flows through the secondary winding 120. Therefore, during the time period when the main FET 110 is conducting, energy is stored in the field of the main transformer 106. Likewise, once the current through the primary winding 108 reaches the peak current, the main FET 110 is rendered non-conductive. Once the main FET 110 is rendered non-conductive, the voltage induced on the secondary winding is reversed, turning the secondary FET 122 on, and the collapsed field is directed to the load R L Current is generated in the secondary winding 120 which supplies power and stores charge in the capacitor 130. Thus, the exemplary power converter 100 shown is arranged for flyback operation.

[0040] In a related art power converter implementing peak current control, the current through the primary winding 108 may be sensed by sensing the voltage at the current sensing node 134 between the source 116 of the main FET 110 and the sensing resistor 118. More specifically, in a related art power converter, the primary side controller (in Figure 1 1 (not shown) senses the primary current (via sense resistor 118) and renders the main FET non-conductive in each cycle when the set point for the peak current is reached. For steady state operation, having the primary side controller implement peak current control works well. However, for transient loads and adjustable load scenarios (Universal Serial Bus (USB) Power Delivery (PD) operating mode), the reaction time of the primary side controller may be too slow to ensure that the output voltage remains within acceptable limits. In an exemplary embodiment, the exemplary embodiment simulates or emulates the primary current on the secondary side 104 to generate a signal indicative of the primary current, rather than measuring the primary current on the primary side 102. The secondary side controller (in Figure 1 The exemplary system implements primary current control, but the implementation is provided on the secondary side 104, where the primary PWM signal is generated on the secondary side 104 and sent to the primary side 102. The description now turns to an exemplary mathematical basis for emulating the primary current on the secondary side 104.

[0041] Still reference Figure 1 , on the primary side 102, during the time period when the main FET 110 is conducting, the peak voltage at the current sensing node 134 can be calculated based on the following equation:

[0042]

[0043] Where V CS is the voltage at the current sensing node 134, V DC is the supply voltage, T 导通 is the on-time of the main FET 110 in the switching cycle, L is the magnetizing inductance of the primary winding 108, and R CS is the resistance of the sense resistor 118. On the secondary side 104, during the time period when the secondary FET 122 is not conducting (e.g., when the primary FET 110 is conducting), the voltage at the node 132 between the secondary winding 120 and the secondary FET 122 can be calculated by the following equation:

[0044]

[0045] Where V S is the voltage at node 132, N is the turns ratio of the main transformer, and the remaining parameters are defined as above.

[0046] In an exemplary embodiment, a signal indicative of the primary current is generated on the secondary side of the main transformer. Available parameters for simulating the primary current are the output voltage V OUT and the voltage V at node 132 S . Figure 2 A simulation circuit according to at least some embodiments is shown. In particular, Figure 2 A transconductance amplifier 200 (hereinafter referred to only as "amplifier 200") is shown, which defines a non-inverting input 202, an inverting input 204, and a current output 206. The non-inverting input 202 is coupled to a voltage V at node 132. S , and the inverting input 204 is coupled to the output voltage V OUT The amplifier has a gain G and generates a ramp current I based on the differential voltage at the input and the gain G. 斜坡 In the exemplary system shown, the current output 206 (driving I 斜坡 ) feeds capacitor 208. 斜坡 The current can be expressed as follows:

[0047] I 斜坡 =(V S -V oUT )·G (3)

[0048] Among them I 斜坡 is the ramp current, G is the gain of amplifier 200, and the remaining parameters are as described above. Substituting V from equation (2) S Substituting into equation (3) we obtain:

[0049]

[0050] Assuming that the voltage on capacitor 208 starts from zero in each cycle (caused by switch 210 being at least temporarily closed), the voltage on the capacitor can be shown by the following equation:

[0051]

[0052] Where V C is the voltage on capacitor C 208. Substituting I from equation (4) 斜坡 Substituting into equation (5) we obtain:

[0053]

[0054] Now, if the voltage on capacitor C 208 is selected to emulate the voltage V at current sense node 134 CS (i.e., V S Equal to V CS ), then we then set equation (1) equal to equation (6) and solve for C to obtain:

[0055]

[0056] In other words, the capacitor can be selected to simulate or emulate the magnetizing inductance, and the choice of capacitor is related to the supply voltage V DC , output voltage V OUT and the on-time T 导通 In other words, it is possible to calculate and choose Figure 2 The single capacitor value in the exemplary circuit and regardless of the supply voltage V DC , output voltage V OUT and the on-time T 导通 The operation remains valid regardless of changes in the duty cycle of the primary PWM signal.

[0057] Figure 3 A power converter according to at least some embodiments is shown. In particular, Figure 3 It shows that Figure 1 1 and 12. The power converter 100 shown in FIG. 1 includes all of the components of the power converter 100, and also includes a primary side controller 300, a galvanic isolation circuit 302 (hereinafter referred to only as "isolation circuit 302"), and a secondary side controller 304. The secondary side controller 304 defines a gate terminal 306, a winding sense terminal 308, an output voltage terminal 310, a primary PWM terminal 312, and an external capacitor terminal 314. There will also be additional terminals (e.g., a ground terminal), but those additional terminals are not shown to avoid overly complicating the drawing. The gate terminal 306 is coupled to the gate of the secondary FET 122, and thus the secondary side controller 304 turns the secondary FET 122 on and off by appropriately driving the gate signal to the gate 126 of the secondary FET 122. The winding sense terminal 308 is coupled to the node 132 (and therefore to the V discussed above). S The output voltage terminal 310 is coupled to the output voltage V OUT As shown, the secondary side controller 304 is directly coupled to the output voltage V OUT302 for sensing purposes, but it is also contemplated that the voltage may be reduced by a voltage divider circuit. The primary PWM terminal 312 is coupled to the primary side controller 300 via the isolation circuit 302, wherein the isolation circuit 302 provides galvanic isolation between the primary side 102 and the secondary side 104. The secondary side controller 304 sends the primary PWM signal to the primary side controller 300 via the isolation circuit 302. The external capacitor terminal 314 is coupled to the capacitor 208 selected to emulate the primary current, as discussed above (and as discussed in more detail below).

[0058] The primary side controller 300 defines a pulse input 316, a gate output 318, and a voltage sense input 320. The pulse input 316 is coupled to the isolation circuit 302 to receive the primary PWM signal from the secondary side controller 304. The gate output 318 is coupled to the gate 114 of the main FET 110. The voltage sense input 320 is coupled to the supply voltage V DC There will also be additional terminals (eg, ground terminals), but those additional terminals are not shown so as not to overcomplicate the drawing. The description now turns to a description of an exemplary startup condition for power converter 100, followed by a description of non-startup operation.

[0059] Initially, the power converter 100 is considered to be powered off (ie, no power supply voltage V is provided). DC ). When the initial power supply voltage V DC However, in the case of any previous switching cycles of the main FET 110, no power has been transmitted to the secondary side 104 to operate the secondary side controller 304, and thus the secondary side controller 304 remains powered off. Assuming that the secondary side controller 304 is powered off, the secondary side controller 304 will not be able to generate and provide the primary PWM signal to the primary side controller 300. Therefore, during the initial startup of the power converter 100 (i.e., when the power supply voltage V DC 316 ), the primary side controller 300 generates and drives the gate signal on the gate output 318 in the absence of the primary PWM signal supplied to the pulse input 316. Driving the gate signal by the primary side controller 300 may be performed at a predetermined frequency and duty cycle to charge the capacitor 130 on the secondary side 104 (or the peak charging capacitor on the secondary auxiliary winding) to power the secondary side controller 304. Once the secondary side controller 304 is powered on (i.e., non-startup operation), the secondary side controller 304 sends the primary PWM signal across the isolation circuit 302 to the pulse input 316, and the primary side controller 300 asserts and deasserts the gate output 318 in response to the assertion and deassertion of the primary PWM signal on the gate input 316, respectively.

[0060] During non-startup operation, and from the perspective of the secondary side controller 304, the secondary side controller 304 is configured to command the primary side controller 300 to turn on the main FET 110 to induce a primary current through the primary winding 108. In an exemplary embodiment, the command is issued through the isolation circuit 302 via the primary PWM terminal 312. In response to the command, the primary side controller 300 asserts the gate output 318 to the gate 114 of the main FET 110. Concurrently with the command to turn on the main FET 110, the secondary side controller 304 generates a signal indicative of the primary current. In an exemplary system, the signal indicative of the primary current is a voltage at the external capacitor terminal 314, which is caused by the current driven to the capacitor 208 (where the capacitor 208 is selected as described above) to simulate or emulate the primary current. When the signal indicative of the primary current reaches or exceeds a predetermined value (peak current), the secondary side controller 304 then commands the primary side controller 300 to render the main FET 110 non-conductive, the command passing through the isolation circuit 302 and to the pulse input 316 via the primary PWM terminal 312. In response to the command to render the main FET 110 non-conductive, the primary side controller 300 deasserts the gate output 318 to the gate 114 of the main FET 110. Thus, the secondary side controller 304 effectively generates and controls each switching cycle of the main FET 110 by selectively asserting and deasserting the primary PWM signal applied to the primary PWM terminal 312. In other words, for each switching cycle of each FET 110, the secondary side controller 304 commands the main FET 110 to become conductive, generates a signal indicative of the primary current on the secondary side, and commands the main FET 110 to become non-conductive when the signal indicative of the primary current reaches a predetermined value.

[0061] Still reference Figure 3 , the isolation circuit 302 can take any suitable form. In some cases, the isolation circuit is a gate drive transformer that is different from the main transformer 106, where the communication transformer has a primary winding (on the secondary side 104) and a secondary winding (on the primary side 102). Thus, the secondary side controller 304 can drive the primary PWM signal to the primary winding, and the secondary winding can provide the PWM signal to the pulse input 316 of the primary side controller 300. In other embodiments, the isolation circuit 302 can take the form of an optocoupler or a galvanic isolator built on silicon using inductive or capacitive coupling. That is, the optocoupler can define an optical diode coupled to the primary PWM terminal 312. The optocoupler can define a transistor whose base region is optically driven by light from the diode, where the transistor is coupled to the pulse input 316 of the primary side controller 300.

[0062] Figure 4A block diagram of a secondary side controller according to at least some embodiments is shown. In particular, Figure 4 An exemplary secondary side controller 304 is shown in the form of a packaged integrated circuit 400. The packaged integrated circuit 400 may take any suitable form (e.g., dual in-line package (DIP), surface mount, etc.). Regardless of the package form, a plurality of terminals of the packaged integrated circuit 400 are electrically accessible, such as a gate terminal 306, a winding sense terminal 308, an output voltage terminal 310, a primary PWM terminal 312, an external capacitor terminal 314, and a ground or common terminal 402. Other terminals are also present, but are not shown to avoid overly complicating the drawing. The terminals are electrically coupled in any suitable form to various electronic devices monolithically constructed on a substrate 404 (the substrate is shown in dashed lines) of a semiconductor material (e.g., silicon).

[0063] In particular, the exemplary secondary side controller 304 may include a PWM controller 406 defined on the substrate 404. The PWM controller 406 is electrically coupled to the output voltage (via the output voltage terminal 310) and to the primary PWM terminal 312. The exemplary secondary side controller 304 may also include an emulation controller 408 defined on the substrate 404. The emulation controller 408 is electrically coupled to the winding sense terminal 308, the output voltage terminal 310, and the external capacitor terminal 314. Finally, the exemplary secondary side controller 304 may include a gate driver 410 coupled to the gate terminal 306. The secondary side controller 304 may generate a voltage from the output voltage V via the output voltage terminal 310 (or a separate power terminal). OUT The example secondary side controller 304 uses an internal ground or common terminal via a common terminal 402 (shown as coupled to a common connection), but the distribution of the ground or common terminal throughout the secondary side controller 304 is not shown to avoid over-complication of the drawing.

[0064] As the name implies, the gate driver 410 is designed and constructed to drive the secondary FET 122 ( Figure 3 ) of the gate 126 ( Figure 3 ) so that the secondary FET 122 ( Figure 3 ) as the power converter 100 ( Figure 3 ) of the secondary side 104 ( Figure 3 ) is turned on and off as part of the synchronous operation. When the main FET 110 is not conducting and the secondary winding 120 ( Figure 3 ) provides current to capacitor 130, the gate signal at gate terminal 306 is asserted, and thus secondary FET 122 is turned on ( Figure 3). In contrast, the main FET 110 acts as the primary side 102 ( Figure 3 ), the gate signal at the gate terminal 306 is deasserted, and thus the secondary FET 122 is not conducting, during a time period when the secondary side controller 304 is conducting as part of a switching cycle on the secondary side controller 304. In at least some embodiments, the secondary side controller 304 asserts the gate signal on the gate terminal 306 when the secondary side controller 304 senses that the body diode 136 is forward biased.

[0065] The exemplary PWM controller 406 is designed and configured to generate a primary PWM signal that is driven to the primary PWM terminal 312. In particular, the PWM controller 406 is coupled to a signal indicative of the primary current (i.e., the voltage at the external capacitor terminal 314), and the PWM controller 406 is configured to control the duty cycle of the primary PWM signal based on the signal indicative of the primary current and the sensed output voltage.

[0066] Still reference Figure 4 , the simulation controller 408 is designed and configured to generate a signal indicative of the primary current by driving a current into the external capacitor terminal 314 (and capacitor 208 as shown), where the external capacitor 208 can be selected as described above. Although the simulation controller 408 can take many suitable forms, Figure 4 In the exemplary system of Figure 2 The amplifier 200 (eg, a differential input current amplifier) ​​and the switch 210 (eg, an electronically controlled switch) are discussed. In particular, the non-inverting input 202 is coupled to the winding sense terminal 308 (and thus to the node 132 ( Figure 2 ), the winding sense terminal supplies the V discussed above S The inverting input 204 is coupled to the output voltage terminal 310 (and thus to the output voltage V OUT ( Figure 2)). The current output 206 of the amplifier 200 is coupled to the external capacitor terminal 314 (and therefore to the external capacitor 208). The current output 206 is also coupled to the switch 210. In particular, the switch 210 defines a first connection 414, a second connection 416, and a control input 418. The first connection 414 is coupled to the current output 206, and the control input 418 is coupled to the PWM signal driven to the primary PWM terminal 312. The second connection 416 of the switch 210 is coupled to the common terminal. Then, in operation, when the primary PWM signal is deasserted, the switch 210 is closed, thereby discharging the voltage on the capacitor 208. When the PWM signal is asserted, the switch 210 is opened, so that the current generated by the amplifier 200 can charge the capacitor 208 over time and thus generate a signal indicative of the primary current. When the signal indicative of the primary current reaches a predetermined value (set and monitored by the PWM controller 406), the primary PWM signal is deasserted again, and in an exemplary embodiment, the process restarts.

[0067] Various embodiments implementing simulated or emulated primary current on the secondary side 104 of the power converter can operate in many operating modes with respect to the current through the primary winding 108. For example, the secondary side controller 304 can implement a discontinuous conduction mode of the primary winding 108. That is, in each switching cycle, the field associated with the transformer can collapse completely, and thus the current through the primary winding can drop to zero within a non-zero time period before the next charging cycle in which the main FET 110 becomes conductive. In other cases, the secondary side controller 304 can implement a continuous conduction mode of the primary winding 108. That is, in each switching cycle, the field associated with the transformer may only partially collapse, and thus the current through the primary winding 108 is still flowing when the next charging cycle (in which the main FET 110 becomes conductive) begins. In yet other cases, the secondary side controller 304 can implement a critical conduction mode of the primary winding 108. That is, in each switching cycle, the next charging cycle (in which the main FET 110 becomes conductive) begins or is triggered by the current in the primary winding 108 reaching zero.

[0068] Although the various exemplary embodiments shown and discussed thus far relate to a power converter 100 arranged for flyback operation, the simulation or emulation of the primary current on the secondary side 104 may occur in other topologies. Figure 5 is a circuit diagram of a power converter 500 according to at least some embodiments. In particular, Figure 55. A power converter 500 is shown arranged for forward operation. In forward operation, the main transformer 502 is designed and constructed so that the polarity of the voltage on the secondary winding 504 caused by the current in the primary winding 508 (as shown by the same name terminals in the figure) is the same as the polarity of the main transformer 106 ( Figure 1 ) is opposite in polarity. The primary side 102 is similar to the setup for flyback operation. On the secondary side 104, the inductor 510 resides between the first lead of the secondary winding 504 and V OUT An isolation FET 512 resides between the second lead of the secondary winding 504 and the common terminal on the secondary side 104, and the gate of the isolation FET is coupled to the secondary controller 304. A grounding FET 514 selectively couples the inductor 510 to the common terminal on the secondary side 104, and the gate of the grounding FET is coupled to the secondary side controller 304. The exemplary secondary side 104 also includes a V OUT A voltage divider is formed between the MOSFET and the common terminal, and the secondary side controller 304 is coupled across one of the resistors (the lower sense resistor in the figure) so that the voltage drop across the sense resistor can be measured. Although there are subtle differences, in

[0069] Figure 5 In an exemplary embodiment of , the secondary side controller 304 simulates the primary current by generating a signal indicative of the primary current (eg, during a time period when the main FET 110 is conducting). More specifically, the secondary side controller 304 can charge the external capacitor 208 .

[0070] For the exemplary power converter arranged for forward operation, the voltage at the current sense node 134 is given by equation (1) above. On the secondary side 104, when the main FET 110 is on and the isolation FET 512 is simultaneously conducting, the voltage at the node 506 between the secondary winding 504 and the inductor 510 simplifies to:

[0071]

[0072] A power converter arranged for forward conduction may use a single input amplifier (or the second input may be grounded) rather than using a differential amplifier 200 ( Figure 2 ), and therefore I 斜坡 The current can be as follows:

[0073] I 斜坡 =V S ·G (9)

[0074] V from equation (8) S Substituting into equation (9) we obtain:

[0075]

[0076] Assuming again that the voltage on capacitor 208 starts at zero in each cycle (due to switch 210 being at least temporarily closed), the voltage on the capacitor can be shown by the following equation:

[0077]

[0078] Same as before. Substituting I from equation (10) 斜坡 Substituting into equation (11) we obtain:

[0079]

[0080] Likewise, if the voltage on capacitor C 208 is selected to emulate the voltage V at node 134 CS (i.e., V S Equal to V CS ), then setting equation (1) equal to equation (12) and solving for C again yields:

[0081]

[0082] In other words, even for a power converter arranged for forward operation, the capacitor can be selected to emulate the magnetizing inductance, and the choice of capacitor is related to the supply voltage V DC , output voltage V OUT and the on-time T 导通 Not relevant.

[0083] As before, the secondary side controller 304 in the exemplary power converter 500 generates a primary PWM signal supplied to the primary side controller 300 via the isolation circuit 302. Thus, the above description of a power converter arranged for flyback operation is equally valid except for the timing of turning on the isolation FET 512 and the ground FET 514. The isolation FET 512 is turned on simultaneously with the main FET 110, and the ground FET 514 is turned on opposite to the isolation FET 512, as will be understood by those of ordinary skill in the art having the benefit of this disclosure.

[0084] Furthermore, generating the primary PWM signal on the secondary side, but still using peak current control of the primary winding (e.g., by emulating current on the secondary side) can occur in other topologies such as full-bridge topologies and half-bridge topologies driving the main transformer. Furthermore, while the discussion has also assumed synchronous rectification on the secondary side, a secondary side controller can also be placed and used on the secondary side, even when the rectifier on the secondary side is only a diode.

[0085] Back to Figure 3The various exemplary embodiments discussed so far have assumed that the primary side controller 300, the galvanic isolation circuit 302, and the secondary side controller 304 are separate and distinct circuits, and may even be separately packaged. However, in other exemplary embodiments, the controllers 300 and 304 and the galvanic isolation circuit 302 may be combined and packaged in any convenient form. For example, Figure 3 Various controllers and circuits are shown combined into a packaged circuit 322. More specifically, the exemplary packaged circuit 322 includes a secondary side controller 304 (in some cases on its own substrate (e.g., Figure 4 304), the primary side controller 300 (in some cases on a separate and different substrate from the secondary side controller 304), and the galvanic isolation circuit 302 (possibly also on its own substrate), which are packaged together in a packaged circuit 322. In the case where the primary side controller 300 and the secondary side controller 304 are packaged together, the various terminals of the secondary side controller discussed previously (e.g., the gate terminal 306, the voltage sense terminal 308, the output voltage terminal 310, and the external capacitor terminal 314) are terminals of the entire packaged device 322. Similarly, some of the inputs to the primary side controller 300 also become terminals of the packaged circuit 322 (e.g., the gate output 318 becomes the gate output terminal, and the voltage sense input 320 becomes the voltage sense terminal). As previously discussed, there will be additional terminals, but these additional terminals are not included in the figure to avoid making the figure more complicated.

[0086] If a packaged circuit 322 is used in place of separate and distinct components, the inputs and terminals coupled to the galvanic isolation circuit do not necessarily need to be externally accessible terminals of the packaged circuit 322. For example, if the galvanic isolation circuit 302 is packaged with the packaged circuit 322, then the pulse input 316 does not necessarily need to be externally accessible. Similarly, if the galvanic isolation circuit 302 is packaged with the packaged circuit 322, then the primary PWM signal (driven to the primary PWM signal terminal of the independent secondary side controller) does not need to be externally accessible. In the case where the galvanic isolation circuit 302 is packaged together with the controllers 300 and 304, the galvanic isolation circuit 302 may take the form of an isolator built on silicon using inductive or capacitive coupling or an optocoupler embedded in the package. In still other cases, the packaged circuit 322 may exclude the galvanic isolation circuit 302 and instead have terminal connections for achieving galvanic isolation outside the packaged circuit 322 (e.g., via a communications transformer or optocoupler disposed outside the package of the packaged circuit 322).

[0087] Other variations on packaging are also contemplated. For example, the primary side controller 300 and the galvanic isolation circuit 302 may be co-packaged and used with a separate, distinct, and separately packaged secondary side controller 304. Additionally, the primary side controller 300 may be separately packaged and the galvanic isolation circuit 302 may be a co-packaged secondary side controller 304.

[0088] The various embodiments discussed so far arranged for flyback operation have implicitly assumed that the primary winding 108 operates in a mode (eg, CrM mode or DCM mode) in which the current reaches zero before the next charging cycle. Figure 2 In the embodiment of FIG. 4 , the implicit assumption is that the switch 210 is closed every cycle to consume the current stored on the capacitor before each simulation. However, in further embodiments, the secondary side controller 304 and in particular the simulation controller 408 may be implemented in a switching power supply operating in a continuous current mode (CCM), in which the current through the primary winding 108 rises and falls, but does not reach zero in normal operation. Figure 6 A simulation controller according to at least some embodiments operable in a CCM system is shown. In particular,

[0089] Figure 6 Shows Figure 2 The components of the simulated controller (e.g., amplifier 200, non-inverting input 202, inverting input 204, current output 206, capacitor 208, and switch 210) are all related to Figure 2 are similarly coupled. Figure 6 The exemplary emulation controller of EM also includes another transconductance amplifier 600 (hereinafter referred to only as "amplifier 600"), which defines an inverting input 602, a non-inverting input 604, a current output 606, and a current input 608. The inverting input 602 is coupled to V S , and the non-inverting input 604 is coupled to V OUT The current output 606 is coupled to the common terminal on the secondary side, and the current input 608 is coupled to the capacitor 208 .

[0090] Figure 6 The operation of the simulation controller amplifier 200 is similar to Figure 2 operation. In the main FET110( Figure 3 ) is conducting, the emulation controller generates a (rising) voltage on capacitor 208 that emulates the voltage at current sense node 134 ( Figure 3 However, once the peak current is reached and the main FET 110 is turned off, the voltage at the current sense node 134 is simulated by causing the voltage to be between V S With VOUT Instead of resetting the circuit by closing switch 210, the circuit continues by ramping down proportionally to the difference between the primary current and the secondary current. Once the signal indicative of the primary current (here, the voltage on capacitor 208) reaches a predetermined non-zero value on the downward direction, secondary side controller 304 commands primary side controller 300 to turn main FET 110 on again, and the simulation cycle continues. Switch 210 may be closed only in a complete reset situation (such as at initial startup).

[0091] Figure 7 A method according to at least some embodiments is shown. In particular, the method starts (block 700) and includes: driving a primary current through a primary winding of a main transformer of a power converter (block 702); generating a signal indicative of the primary current on a secondary side of the main transformer (block 704); and stopping driving the primary current through the primary winding when the signal indicative of the primary current reaches a predetermined value (block 706). The method then ends (block 708).

[0092] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are interpreted as being intended to include all such variations and modifications.

Claims

1. A method for controlling a power converter, comprising: driving a primary current through a primary winding of a main transformer of a power converter; when a signal indicative of the primary current reaches a predetermined value, stopping said driving of said primary current through said primary winding; The signal indicative of the primary current is generated on the secondary side of the main transformer by: sensing a voltage at a node between a secondary winding of the main transformer and a rectifier on the secondary side; as well as charging a capacitor in response to the voltage at the node, The voltage across the capacitor is the signal indicative of the primary current.

2. The method of claim 1 , wherein driving the primary current further comprises: sending a valid control signal from the secondary side to the primary side; as well as A main switch on the primary side is turned on in response to the asserted control signal.

3. The method of claim 2, wherein stopping the driving of the primary current further comprises: sending a de-assertion control signal from the secondary side to the primary side; as well as The main switch on the primary side is rendered non-conductive in response to the deasserted control signal.

4. The method according to claim 1, wherein generating the signal indicative of the primary current further comprises sensing an output voltage of the power converter; and Wherein charging the capacitor further comprises charging the capacitor in response to a voltage difference between a voltage at the node and the output voltage.

5. A circuit for controlling a switching power converter, comprising: a gate terminal, a winding sense terminal, an output voltage terminal, a primary pulse width modulation terminal, and an external capacitor terminal; a first substrate; a pulse width modulation controller defined on the first substrate and electrically coupled to the output voltage terminal and the primary pulse width modulation terminal, the pulse width modulation controller configured to generate a primary pulse width modulation signal driven to the primary pulse width modulation terminal; an emulation controller defined on the first substrate, the emulation controller electrically coupled to the winding sense terminal, the output voltage terminal, and the external capacitor terminal, the emulation controller configured to generate a signal indicative of a primary current by driving a current into the external capacitor terminal; and The PWM controller is further coupled to the signal indicative of the primary current, and is configured to control a duty cycle of the primary PWM signal based on the signal indicative of the primary current.

6. The circuit according to claim 5: wherein the pulse width modulation controller is configured to assert the primary pulse width modulation signal to cause a primary field effect transistor on a primary side of the switching power converter to become conductive; wherein the emulation controller generates the signal indicative of the primary current in response to the assertion of the primary pulse width modulation signal; The PWM controller is configured to de-assert the primary PWM signal when the signal indicative of the primary current reaches a predetermined threshold.

7. The circuit of claim 5, wherein the simulation controller further comprises: a differential amplifier defining a first differential input coupled to the winding sense terminal, a second differential input coupled to the output voltage terminal, and an amplifier output coupled to the external capacitor terminal; and An electronically controlled switch is coupled between the external capacitor terminal and ground, the electronically controlled switch having a control input coupled to the gate terminal.

8. The circuit of claim 5, wherein the simulation controller further comprises: an amplifier defining a first input and an amplifier output, the first input being coupled to the winding sense terminal and the amplifier output being coupled to the external capacitor terminal; and An electronically controlled switch is coupled between the external capacitor terminal and ground, the electronically controlled switch having a control input coupled to the gate terminal.

9. A power converter, comprising: A primary side, the primary side comprising: Primary winding of main transformer; a primary field effect transistor coupled to the primary winding, the primary field effect transistor having a gate; a primary side controller defining a pulse input and a gate output, the gate output coupled to the gate of the primary field effect transistor, the primary side controller configured to drive the gate output in response to a pulse width modulated signal received on the pulse input; A secondary side, the secondary side comprising: The secondary winding of the main transformer; a secondary field effect transistor coupled to the secondary winding and defining a gate; a secondary side controller defining a gate terminal coupled to the gate of the secondary field effect transistor, a winding sense terminal coupled to a node between the secondary winding and the secondary field effect transistor, an output voltage terminal, a primary pulse width modulation terminal, and a capacitor terminal; a capacitor coupled between the capacitor terminal of the secondary side controller and ground; an isolation circuit providing galvanic isolation, the isolation circuit being coupled between the primary pulse width modulation terminal of the secondary side controller and the pulse input of the primary side controller; wherein the secondary side controller is configured to, during each switching cycle of the primary field effect transistor: commanding the primary side controller to turn on the primary field effect transistor to induce a primary current through the primary winding, the command passing through the isolation circuit via the primary pulse width modulation terminal; generating a signal indicative of the primary current; and commanding the primary side controller to render the primary field effect transistor non-conductive when the signal indicative of the primary current reaches a predetermined value, the command being passed through the isolation circuit via the primary pulse width modulation terminal, The secondary side controller further comprises: substrate; a pulse width modulation controller defined on the substrate and electrically coupled to the output voltage terminal and the pulse width modulation terminal, the pulse width modulation controller configured to generate a primary pulse width modulation signal driven to the primary pulse width modulation terminal; an emulation controller defined on the substrate, the emulation controller electrically coupled to the winding sense terminal, the output voltage terminal, and the capacitor terminal, the emulation controller configured to generate a signal indicative of a primary current by driving a current into the capacitor terminal; and The PWM controller is further coupled to the signal indicative of the primary current, and is configured to control a duty cycle of the primary PWM signal based on the signal indicative of the primary current.

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