A control circuit for bit line voltage and Nand Flash

Abstract

The present invention provides a bit line voltage control circuit and a Nand Flash. The circuit includes a first to a third switching transistor; a second power supply; a first switching module, the first end of which is connected to the second switching transistor or the ground. When the first end is connected to the second switching transistor, the second end is connected to the first switching transistor and the third switching transistor. When the first end is connected to the ground, the second end is connected to the second switching transistor. When the control end receives a high-level first data signal, the first switching module is turned on; a second switching module, the first end of which is connected to the second power supply. When the control end receives a high-level second data signal, the second switching module is turned on; a third switching module, the first end of which is connected to the second end of the second switching module, the control end receives a third data signal, and the second end is respectively connected to the first switching transistor and the third switching transistor. When the third data signal is high, the third switching module is turned on. The present invention improves the control accuracy of the bit line voltage during slow programming and effectively shortens the slow programming time.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a bit line voltage control circuit and a Nand Flash. Background Art

[0002] Nand Flash (flash memory) is a non-volatile memory. Nand Flash has advantages such as fast rewrite speed and large storage capacity, and is widely used in electronic products. With the extensive use of Nand Flash, the requirements for the programming performance of Nand Flash are also continuously increasing.

[0003] As Figure 1 shown, when programming Nand Flash, as the program (programming) pulse progresses, more and more electrons are injected into the FG (Floating Gate, floating gate) of the cell, and the potential VFG of the FG will gradually become lower. Therefore, before the end of the program or the success of the program, the program voltage VPGM must be continuously increased to keep the difference between the potential VFG of the FG and the channel potential Vchannel, that is, VFG - Vchannel, large enough to write more electrons into the FG of the corresponding cell. Since the program voltage difference DVPGM between two program pulses is positively correlated with the threshold distribution width of the cell after final programming, in order to reduce the threshold distribution width of the cell after final programming, the VFG - Vchannel of the cell that needs to be fast programmed can be reduced to achieve reducing DVPGM without loss of programming performance, thereby reducing the threshold distribution width of the cell after final programming.

[0004] The prior art reduces VFG - Vchannel through Figure 2 the bit line voltage control circuit shown. Since whether to program or inhibit (shield) the cell is determined by the voltage magnitude of the BL corresponding to the cell, the prior art controls the BL_clamp voltage V_BL_clamp' through Figure 2 the bit line voltage control circuit shown to reduce the VFG - Vchannel of the cell corresponding to the bit line during slow programming. At this time, Vchannel can be the bit line voltage V_BL_Slow_Program' during slow programming.

[0005] However, Figure 2 the bit line voltage control circuit shown also has the following defects:

[0006] First, since the bit line is a relatively large capacitive load, Figure 2The control accuracy of the shown bit line voltage control circuit is greatly affected by the surrounding environment of the selected bit line, and the charging speeds vary greatly, making it difficult to achieve precise control of the bit line voltage during slow programming.

[0007] Second, the bit line voltage is used to distinguish three states (programming state, slow programming state, and shielding state), and Figure 2 in the shown bit line voltage control circuit, there is only one control signal Data_B’ for directly controlling the bit line voltage. As Figure 3 shown, Figure 2 it is necessary to control the BL voltage V_BL_Slow_Program’ during slow programming in two stages (i.e., T1’ stage and T2’ stage), and the slow programming takes a long time. Summary of the Invention

[0008] In view of the above problems, the purpose of the embodiments of the present invention is to provide a bit line voltage control circuit and a NandFlash to solve the problems of low control accuracy and long time consumption of the bit line voltage control circuit in the prior art during slow programming.

[0009] To solve the above problems, the embodiments of the present invention disclose a bit line voltage control circuit. The bit line voltage control circuit includes a first switching transistor connected to the bit line, a second switching transistor connected to the ground, and a third switching transistor connected to a first power supply. The bit line voltage control circuit further includes: a second power supply; a first switching module, a first end of the first switching module is connected to the second switching transistor or the ground. When the first end of the first switching module is connected to the second switching transistor, a second end of the first switching module is respectively connected to the first switching transistor and the third switching transistor. When the first end of the first switching module is connected to the ground, the second end of the first switching module is connected to the second switching transistor, and a control end of the first switching module receives a first data signal. When the first data signal is at a high level, the first switching module conducts; a second switching module, a first end of the second switching module is connected to the second power supply, and a control end of the second switching module receives a second data signal. When the second data signal is at a high level, the second switching module conducts; a third switching module, a first end of the third switching module is connected to a second end of the second switching module, a control end of the third switching module receives a third data signal, and a second end of the third switching module is respectively connected to the first switching transistor and the third switching transistor. When the third data signal is at a high level, the third switching module conducts; wherein, when the second data signal is the same as the control signal of the third switching transistor, the first data signal is the inverted signal of the third data signal; when the third data signal is the same as the control signal of the third switching transistor, the first data signal is the inverted signal of the second data signal.

[0010] Optionally, the magnitude and rate of change of the voltage of the second power supply are adjustable.

[0011] Optionally, when the bit line voltage control circuit is operating, the first switching transistor is always in the on state.

[0012] Optionally, the first switching module is a first NMOS transistor, or the first switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

[0013] Optionally, the second switching module is a second NMOS transistor, or the second switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

[0014] Optionally, the third switching module is a third NMOS transistor, or the third switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

[0015] Optionally, when the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a low-level signal, the bit line voltage is a shielding voltage.

[0016] Optionally, when the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a high-level signal and the third data signal is a low-level signal, the bit line voltage is a programming voltage.

[0017] Optionally, when the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a high-level signal and the third data signal is a high-level signal, the bit line voltage is a slow programming voltage.

[0018] The bit line voltage control circuit according to an embodiment of the present invention has the following advantages: By adding a second power supply, a first switch module, a second switch module, and a third switch module to the bit line voltage control circuit. Among them, the first end of the first switch module is connected to the second switch transistor or ground. When the first end of the first switch module is connected to the second switch transistor, the second end of the first switch module is respectively connected to the first switch transistor and the third switch transistor. When the first end of the first switch module is connected to ground, the second end of the first switch module is connected to the second switch transistor, and the control end of the first switch module receives a first data signal; when the first data signal is at a high level, the first switch module is turned on; the first end of the second switch module is connected to the second power supply, and the control end of the second switch module receives a second data signal; when the second data signal is at a high level, the second switch module is turned on; the first end of the third switch module is connected to the second end of the second switch module, the control end of the third switch module receives a third data signal, and the second end of the third switch module is respectively connected to the first switch transistor and the third switch transistor; when the third data signal is at a high level, the third switch module is turned on; when the second data signal is the same as the control signal of the third switch transistor, the first data signal is the inverse signal of the third data signal; when the third data signal is the same as the control signal of the third switch transistor, the first data signal is the inverse signal of the second data signal. In this way, not only can the bit line voltage during slow programming be accurately controlled by setting the voltage magnitude of the second power supply, and the threshold distribution width of the cell after final programming is reduced without sacrificing programming performance, but also since the first data signal and the inverse signal of the first data signal are added to control the corresponding switch modules, the charging of the BL during slow programming can be completed faster, effectively reducing the slow programming time.

[0019] To solve the above problems, an embodiment of the present invention also discloses a Nand Flash, which includes at least one of the above-mentioned bit line voltage control circuits, and the bit line voltage control circuit is connected to a bit line in the Nand Flash.

[0020] The Nand Flash according to an embodiment of the present invention has the following advantages: By adopting the above-mentioned bit line voltage control circuit, not only can the bit line voltage during slow programming be accurately controlled by setting the voltage magnitude of the second power supply, and the threshold distribution width of the cell after final programming is reduced without sacrificing programming performance, but also since the first data signal and the inverse signal of the first data signal are added to control the corresponding switch modules, the charging of the BL during slow programming can be completed faster, effectively reducing the slow programming time. Description of the Drawings

[0021] Figure 1 is a schematic diagram of each voltage during programming of Nand Flash in the prior art;

[0022] Figure 2 It is a schematic structural diagram of a bit line voltage control circuit in the prior art;

[0023] Figure 3 It is a schematic waveform diagram of each signal in the bit line voltage control circuit in the prior art;

[0024] Figure 4 It is a structural block diagram of an embodiment of a bit line voltage control circuit of the present invention;

[0025] Figure 5 It is a structural block diagram of another embodiment of a bit line voltage control circuit of the present invention;

[0026] Figure 6 It is a schematic structural diagram of an embodiment of a bit line voltage control circuit of the present invention;

[0027] Figure 7 It is a schematic waveform diagram of each signal in an embodiment of a bit line voltage control circuit of the present invention. Detailed implementation manners

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0029] Refer to Figure 4 , which shows a structural block diagram of an embodiment of a bit line voltage control circuit of the present invention. The bit line voltage control circuit includes a first switch transistor 10 connected to a bit line BLn, a second switch transistor 20 connected to a ground VSS, and a third switch transistor 30 connected to a first power supply VDD. The bit line voltage control circuit may further include: a second power supply VSRC; a first switch module 40, a first end of the first switch module 40 is connected to the second switch transistor 20 or the ground. Refer to Figure 4 , when the first end of the first switch module 40 is connected to the second switch transistor 20, a second end of the first switch module 40 is respectively connected to the first switch transistor 10 and the third switch transistor 30. Refer to Figure 5, when the first end of the first switch module 40 is connected to the ground, the second end of the first switch module 40 is connected to the second switching transistor 20, and the control end of the first switch module 40 receives the first data signal Data_1; when the first data signal Data_1 is at a high level, the first switch module 40 is turned on; a second switch module 50, the first end of the second switch module 50 is connected to the second power supply VSRC, and the control end of the second switch module 50 receives the second data signal Data_2; when the second data signal Data_2 is at a high level, the second switch module 50 is turned on; a third switch module 60, the first end of the third switch module 60 is connected to the second end of the second switch module 50, the control end of the third switch module 60 receives the third data signal Data_3, and the second end of the third switch module 60 is respectively connected to the first switching transistor 10 and the third switching transistor 30 (that is, when the second end of the first switch module 40 is respectively connected to the first switching transistor 10 and the third switching transistor 30, the second end of the third switch module 60 is connected to the second end of the first switch module 40; when the second end of the first switch module 40 is connected to the second switching transistor 20, the second end of the third switch module 60 is connected to the second switching transistor 20); when the third data signal Data_3 is at a high level, the third switch module 60 is turned on; wherein, when the second data signal Data_2 is the same as the control signal of the third switching transistor, the first data signal Data_1 is the inverse signal of the third data signal Data_3; when the third data signal Data_3 is the same as the control signal of the third switching transistor, the first data signal Data_1 is the inverse signal of the second data signal Data_2.

[0030] In this way, by setting the voltage magnitude of the second power supply VSRC, precise control of the bit line voltage during slow programming can be achieved. Without sacrificing programming performance, the threshold distribution width of the cell after final programming is reduced. Moreover, since the first data signal Data_1 and the inverse signal of the first data signal Data_1 are added to control the corresponding switch modules, the charging of the BL during slow programming can be completed faster, effectively reducing the slow programming time.

[0031] Optionally, the voltage magnitude and the voltage change rate of the second power supply VSRC are adjustable. Specifically, by adjusting the voltage magnitude and / or the voltage change rate of the second power supply VSRC, the threshold distribution width of the cell after final programming can be made less than a preset value.

[0032] Optionally, when the bit line voltage control circuit is working, the first switching transistor 10 is always in an on state, so as to complete the charging of the BL during slow programming at the fastest speed and reduce the slow programming time.

[0033] Optionally, the first switching module 40 may be a module composed of at least one switching transistor. For example, the first switching module 40 may be the first NMOS transistor N1, or the first switching module 40 may be composed of at least one PMOS transistor and at least one NMOS transistor. Wherein, when the first switching module 40 is the first NMOS transistor N1, the structure of the bit line voltage control circuit may be as Figure 6 shown.

[0034] Optionally, the second switching module 50 may be a module composed of at least one switching transistor. For example, the second switching module 50 may be the second NMOS transistor N2, or the second switching module 50 may be composed of at least one PMOS transistor and at least one NMOS transistor. Wherein, when the second switching module 50 is the second NMOS transistor N2, the structure of the bit line voltage control circuit may be as Figure 6 shown.

[0035] Optionally, the third switching module 60 may be a module composed of at least one switching transistor. For example, the third switching module 60 may be the third NMOS transistor N3, or the third switching module 60 may be composed of at least one PMOS transistor and at least one NMOS transistor. Wherein, when the third switching module 60 is the third NMOS transistor N3, the structure of the bit line voltage control circuit may be as Figure 6 shown.

[0036] Figure 6 In, the second data signal Data_2 is the same as the control signal Data_B of the third switching transistor, and the first data signal Data_1 ( Figure 6 Data_S_B in) is the inverse signal of the third data signal Data_3 ( Figure 6 Data_S in). The first switching transistor 10 may be the fourth NMOS transistor N4, the second switching transistor 20 may be the fifth NMOS transistor N5, the third switching transistor 30 may be the first PMOS transistor P1. The gate of the fourth NMOS transistor N4 receives the fourth data signal BL_clamp, the gate of the fifth NMOS transistor N5 receives the second data signal Data_B, and the gate of the first PMOS transistor P1 receives the second data signal Data_B.

[0037] At this time, the first end of the second NMOS transistor N2 is connected to the second power supply VSRC, and the gate of the second NMOS transistor N2 receives the second data signal Data_B. The first end of the third NMOS transistor N3 is connected to the second end of the second NMOS transistor N2, the gate of the third NMOS transistor N3 receives the third data signal Data_S, and the second end of the third NMOS transistor N3 is respectively connected to the first end of the fourth NMOS transistor N4 and the first end of the first PMOS transistor. The first end of the first NMOS transistor N1 is connected to the first end of the fifth NMOS transistor N5, the gate of the first NMOS transistor N1 receives the inverted signal Data_S_B of the third data signal, and the second end of the first NMOS transistor N1 is connected to the second end of the third NMOS transistor N3.

[0038] Wherein, the first end of the first NMOS transistor N1 can be the source or the drain of the first NMOS transistor N1, and the second end of the first NMOS transistor N1 can be the drain or the source of the first NMOS transistor N1. The second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are similar to the first NMOS transistor N1 and will not be elaborated here.

[0039] Optionally, referring to Figure 7 , when the second data signal Data_2 is the same as the control signal Data_B of the third switch transistor, if the second data signal Data_B is a low-level signal, the bit line voltage is the shielding voltage V_BL_Inhibit. At this time, the shielding operation can be performed on the cell string corresponding to the bit line BLn.

[0040] Optionally, referring to Figure 7 , when the second data signal Data_2 is the same as the control signal Data_B of the third switch transistor, if the second data signal Data_B is a high-level signal and the third data signal Data_S is a low-level signal, the bit line voltage is the programming voltage V_BL_Program. At this time, the programming operation can be performed on the cell string corresponding to the bit line BLn.

[0041] Optionally, referring to Figure 7 , when the second data signal Data_2 is the same as the control signal Data_B of the third switch transistor, if the second data signal Data_B is a high-level signal and the third data signal Data_S is a high-level signal, the bit line voltage is the slow programming voltage V_BL_Slow_Program. At this time, the slow programming operation can be performed on the cell string corresponding to the bit line BLn.

[0042] Figure 7Among them, V_BL_clamp is the voltage of the fourth data signal BL_clamp. Among them, V_BL_clamp needs to be large enough to turn on the fourth NMOS transistor N4, so that the first power supply VDD is transmitted to the bit line BLn. Figure 6 Among them, VSRC is the Vchannel of the cell in the middle, VFG is the potential of FG, and Vchannel is the channel potential. Figure 6 Among them, the time required for the voltage of the bit line BLn to be charged to a voltage at which slow programming operations can be performed, the time required for the voltage of the bit line BLn to be charged to a voltage at which masking operations can be performed, and the time required for the voltage of the bit line BLn to be discharged to a voltage at which programming operations can be performed. The longest of these three times is T.

[0043] Optionally, when the third data signal Data_3 is the same as the control signal Data_B of the third switching transistor, if the third data signal Data_B is a low-level signal, the bit line voltage is the masking voltage. At this time, masking operations can be performed on the cell string corresponding to the bit line BLn.

[0044] Optionally, when the third data signal Data_3 is the same as the control signal Data_B of the third switching transistor, if the third data signal Data_B is a high-level signal and the second data signal Data_2 is a low-level signal, the bit line voltage is the programming voltage. At this time, programming operations can be performed on the cell string corresponding to the bit line BLn.

[0045] Optionally, when the third data signal Data_3 is the same as the control signal Data_B of the third switching transistor, if the third data signal Data_B is a high-level signal and the second data signal Data_2 is a high-level signal, the bit line voltage is the slow programming voltage. At this time, slow programming operations can be performed on the cell string corresponding to the bit line BLn.

[0046] In specific implementation, the charging and discharging of the BL voltage can be performed in parallel with the charging part of the WL line or all in parallel, so as to further reduce the overall programming time required.

[0047] The bit line voltage control circuit according to the embodiment of the present invention has the following advantages: By adding a second power supply, a first switch module, a second switch module, and a third switch module to the bit line voltage control circuit, wherein, the first end of the first switch module is connected to the second switch transistor or ground. When the first end of the first switch module is connected to the second switch transistor, the second end of the first switch module is respectively connected to the first switch transistor and the third switch transistor. When the first end of the first switch module is connected to ground, the second end of the first switch module is connected to the second switch transistor, and the control end of the first switch module receives a first data signal; when the first data signal is at a high level, the first switch module is turned on; the first end of the second switch module is connected to the second power supply, and the control end of the second switch module receives a second data signal; when the second data signal is at a high level, the second switch module is turned on; the first end of the third switch module is connected to the second end of the second switch module, the control end of the third switch module receives a third data signal, and the second end of the third switch module is respectively connected to the first switch transistor and the third switch transistor; when the third data signal is at a high level, the third switch module is turned on; when the second data signal is the same as the control signal of the third switch transistor, the first data signal is the inverse signal of the third data signal; when the third data signal is the same as the control signal of the third switch transistor, the first data signal is the inverse signal of the second data signal. In this way, not only can the bit line voltage during slow programming be accurately controlled by setting the voltage magnitude and / or voltage change speed of the second power supply, and the threshold distribution width of the cell after final programming is reduced without sacrificing programming performance, but also because the first data signal and the inverse signal of the first data signal are added to control the corresponding switch modules, the charging of the BL during slow programming can be completed faster, effectively reducing the slow programming time.

[0048] The embodiment of the present invention also discloses a Nand Flash, which includes at least one of the above-mentioned bit line voltage control circuits, and the bit line voltage control circuit is connected to a bit line in the Nand Flash.

[0049] The Nand Flash according to the embodiment of the present invention has the following advantages: By adopting the above-mentioned bit line voltage control circuit, not only can the bit line voltage during slow programming be accurately controlled by setting the voltage magnitude and / or voltage change speed of the second power supply, and the threshold distribution width of the cell after final programming is reduced without sacrificing programming performance, but also because the second data signal is added to control the second switch module and the third switch module, the charging of the BL during slow programming can be completed faster, effectively reducing the slow programming time.

[0050] For the embodiment of the Nand Flash, since it includes a bit line voltage control circuit, the description is relatively simple, and the relevant parts can be referred to the partial description of the bit line voltage control circuit embodiment.

[0051] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0052] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0053] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0054] The above has introduced in detail a bit line voltage control circuit and a Nand Flash provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A bit line voltage control circuit, characterized in that, the bit line voltage control circuit includes a first switching transistor connected to the bit line, a second switching transistor connected to the ground, and a third switching transistor connected to a first power supply, and the bit line voltage control circuit further includes: a second power supply; the voltage magnitude and voltage change rate of the second power supply are adjustable; a first switching module, a first end of the first switching module is connected to the second switching transistor or the ground. When the first end of the first switching module is connected to the second switching transistor, a second end of the first switching module is respectively connected to the first switching transistor and the third switching transistor. When the first end of the first switching module is connected to the ground, the second end of the first switching module is connected to the second switching transistor, and a control end of the first switching module receives a first data signal; when the first data signal is at a high level, the first switching module is turned on; a second switching module, a first end of the second switching module is connected to the second power supply, and a control end of the second switching module receives a second data signal; when the second data signal is at a high level, the second switching module is turned on; a third switching module, a first end of the third switching module is connected to a second end of the second switching module, a control end of the third switching module receives a third data signal, and a second end of the third switching module is respectively connected to the first switching transistor and the third switching transistor; when the third data signal is at a high level, the third switching module is turned on; wherein, when the second data signal is the same as the control signal of the third switching transistor, the first data signal is the inverse signal of the third data signal; when the third data signal is the same as the control signal of the third switching transistor, the first data signal is the inverse signal of the second data signal.

2. The bit line voltage control circuit according to claim 1, characterized in that, when the bit line voltage control circuit is working, the first switching transistor is always in an on state.

3. The bit line voltage control circuit according to claim 1, characterized in that, the first switching module is a first NMOS transistor, or the first switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

4. The bit line voltage control circuit according to claim 1, characterized in that, the second switching module is a second NMOS transistor, or the second switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

5. The bit line voltage control circuit according to claim 1, characterized in that, the third switching module is a third NMOS transistor, or the third switching module is composed of at least one PMOS transistor and at least one NMOS transistor.

6. The bit line voltage control circuit according to claim 1, characterized in that, when the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a low level signal, the bit line voltage is a shielding voltage.

7. The bit line voltage control circuit according to claim 1, characterized in that, When the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a high-level signal and the third data signal is a low-level signal, the bit line voltage is a programming voltage.

8. The bit line voltage control circuit according to claim 1, wherein, when the second data signal is the same as the control signal of the third switching transistor, if the second data signal is a high-level signal and the third data signal is a high-level signal, the bit line voltage is a slow programming voltage.

9. A Nand Flash, wherein, it includes the bit line voltage control circuit according to any one of claims 1-8, and the bit line voltage control circuit is connected to a bit line in the Nand Flash.

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