Vertical field effect transistor (VFET) device and method of forming the same

Abstract

A vertical field effect transistor (VFET) device and a method for forming the device are provided. The method may include: forming a channel region including a first channel region and a second channel region; forming a first cavity in a substrate; forming a first bottom source / drain in the first cavity; forming a second cavity in the substrate; and forming a second bottom source / drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include: after forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 698,568, filed in the U.S. Patent and Trademark Office (USPTO) on July 16, 2018, entitled “VTFET (CMOS) BOTTOM S / D FORMATION METHOD WITH INDEPENDENT CONTROL OF CHANNEL TO S / DPROXIMITY BETWEEN NMOS AND PMOS,” and U.S. Application No. 16 / 434,211, filed in the U.S. Patent and Trademark Office (USPTO) on June 7, 2019, entitled “VERTICAL FIELD-EFFECT TRANSISTOR (VFET) DEVICES AND METHODS OF FORMING THE SAME,” the disclosures of which are incorporated herein by reference in their entireties. Technical Field

[0003] The present disclosure relates generally to the field of electronics, and more particularly, to vertical field effect transistor (VFET) devices. Background Art

[0004] Due to the high scalability of vertical field-effect transistor (VFET) devices, various structures and manufacturing processes of VFET devices have been studied. In particular, structures and manufacturing processes that allow for controlling the overlap of the bottom source / drain side junctions and forming abrupt junctions near the bottom source / drain have been studied to improve the performance of VFET devices. Summary of the Invention

[0005] According to some embodiments of the present inventive concept, a method of forming a vertical field effect transistor (VFET) device may include forming a channel region that protrudes from an upper surface of a substrate and extends longitudinally along a first horizontal direction. The channel region may include a first channel region and a second channel region aligned in the first horizontal direction, and the first channel region and the second channel region may overlap with a first portion and a second portion of the substrate, respectively. The method may also include forming a first cavity in the substrate by removing a first portion of the substrate; forming a first bottom source / drain in the first cavity of the substrate; forming a second cavity in the substrate by removing a second portion of the substrate; and forming a second bottom source / drain in the second cavity of the substrate. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include, after forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and forming a first gate structure on one side of the first channel region and a second gate structure on one side of the second channel region.

[0006] According to some embodiments of the present invention, a method of forming a vertical field effect transistor (VFET) device may include forming a channel region on a substrate. The channel region may extend longitudinally along a first horizontal direction and may include a first channel region and a second channel region aligned in the first horizontal direction. The method may also include forming a first bottom source / drain in the substrate; forming a second bottom source / drain in the substrate; after forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and forming a first gate structure on one side of the first channel region and forming a second gate structure on one side of the second channel region. The first channel region may overlap with the first bottom source / drain, and the second channel region may overlap with the second bottom source / drain.

[0007] According to some embodiments of the present invention, a method of forming a vertical field effect transistor (VFET) device may include: forming an N-type field effect transistor on a substrate and forming a P-type field effect transistor on the substrate. The N-type field effect transistor may include a first channel region, a first bottom source / drain between the first channel region and the substrate, and a first gate structure on one side of the first channel region. The first channel region may include a lower surface facing the substrate, and the first bottom source / drain may separate the entire lower surface of the first channel region from the substrate in a vertical direction perpendicular to the upper surface of the substrate. The P-type field effect transistor may include a second channel region, a second bottom source / drain between the second channel region and the substrate, and a second gate structure on one side of the second channel region. The second channel region may include a lower surface facing the substrate, and the second bottom source / drain may separate the entire lower surface of the second channel region from the substrate in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 15C is a diagram illustrating a method of forming a vertical field effect transistor (VFET) device according to some embodiments of the inventive concept. Figure 1 、 Figure 2 、 Figure 3 、 Figure 6 、 Figure 9 and Figure 12 It's a perspective drawing. Figure 4A 、 Figure 5A 、 Figure 7A 、 Figure 8A 、 Figure 10A 、 Figure 11A 、 Figure 13A 、 Figure 14A and Figure 15A Each of them is a cross-sectional view taken along line II' of its corresponding perspective view, Figure 4B 、 Figure 5B 、 Figure 7B 、 Figure 8B 、 Figure 10B 、 Figure 11B 、 Figure 13B 、 Figure 14B and Figure 15B Each of them is a cross-sectional view taken along line II-II' of its corresponding perspective view, and Figure 4C 、 Figure 5C 、 Figure 7C 、 Figure 8C 、 Figure 10C 、 Figure 11C 、 Figure 13C 、 Figure 14C and Figure 15C Each of them is a cross-sectional view taken along line III-III' of its corresponding perspective view.

[0009] Figure 16 and Figure 17 is a flow chart illustrating a method of forming a VFET device according to some embodiments of the present inventive concept. DETAILED DESCRIPTION

[0010] Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the present disclosure, and therefore the present disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided to make this disclosure thorough and complete and to convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals represent like elements throughout.

[0011] Example embodiments of the present inventive concepts are described herein with reference to cross-sectional and plan views that are schematic illustrations of idealized embodiments and intermediate structures of the example embodiments. Thus, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments of the present inventive concepts should not be construed as limited to the specific shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0012] Figures 1 to 15C 1 is a diagram illustrating a method of forming a VEFT device according to some embodiments of the present invention. Specifically, Figure 1 、 Figure 2 、 Figure 3 、 Figure 6 、 Figure 9 and Figure 12 It's a perspective drawing. Figure 4A 、 Figure 5A 、 Figure 7A 、 Figure 8A 、 Figure 10A 、 Figure 11A 、 Figure 13A 、 Figure 14A and Figure 15A Each of them is a cross-sectional view taken along line II' of its corresponding perspective view, Figure 4B 、 Figure 5B 、 Figure 7B 、 Figure 8B 、 Figure 10B 、 Figure 11B 、 Figure 13B 、 Figure 14B and Figure 15B Each of them is a cross-sectional view taken along line II-II' of its corresponding perspective view, and Figure 4C 、 Figure 5C 、 Figure 7C 、 Figure 8C 、 Figure 10C 、 Figure 11C 、 Figure 13C 、 Figure 14C and Figure 15C Each of them is a cross-sectional view taken along line III-III' of its corresponding perspective view.

[0013] refer to Figure 1 , the method may include forming a channel region 12 protruding from the upper surface 10_S of the substrate 10. The substrate 10 may include a first region A and a second region B. Each channel region 12 may extend longitudinally along a first direction D1 (i.e., a first horizontal direction) parallel to the upper surface 10_S of the substrate 10, and the channel regions 12 may be spaced apart from each other along a second direction D2 (i.e., a second horizontal direction) parallel to the upper surface 10_S of the substrate 10. Each channel region 12 may include a first channel region 12A and a second channel region 12B aligned in the first direction D1. The first channel region 12A may be located on the first region A of the substrate 10 and may vertically overlap with a portion of the substrate 10. The second channel region 12B may be located on the second region B of the substrate 10 and may vertically overlap with a portion of the substrate 10. In some embodiments, the first direction D1 is perpendicular to the second direction D2.

[0014] In some embodiments, forming the channel regions 12 may include forming a mask layer 14 on the substrate 10 and etching the substrate 10 using the mask layer 14 as an etching mask to form the channel regions 12. Thus, each channel region 12 is a portion of the substrate 10. In some embodiments, as shown in FIG. Figure 1 As shown, each mask layer 14 may have a line shape extending along the first direction D1, and thus each channel region 12 may also have a line shape extending along the first direction D1. Figure 1 Two channel regions 12 are shown, but it should be understood that any number (eg, one, two, three, four, or more) of channel regions 12 may be formed on the substrate 10 .

[0015] The substrate 10 may include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 may be a bulk substrate (eg, a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate.

[0016] refer to Figure 2, a protective layer 16 may be formed on the channel region 12 and the substrate 10. In some embodiments, the protective layer 16 may have a uniform thickness along the surface of the channel region 12 and the upper surface 10_S of the substrate 10, but the present inventive concept is not limited thereto. In some embodiments, the protective layer 16 may have a first thickness on one side of the channel region 12 that is thicker than a second thickness of the protective layer 16 on the upper surface 10_S of the substrate 10. The protective layer 16 may include a material different from that of the substrate 10 and may have an etch selectivity relative to the substrate 10. For example, the protective layer 16 may include a silicon nitride layer and / or a silicon oxynitride layer.

[0017] refer to Figure 3 , a mask film 20 may be formed on the second region B of the substrate 10 and may expose the first region A of the substrate 10. A portion of the protective layer 16 is located on the exposed first region A of the substrate 10, and a portion of the substrate 10 may be removed (e.g., etched) using the mask film 20 as a mask to form a first cavity 21A in the substrate 10.

[0018] Figure 4A 、 Figure 4B and Figure 4C According to some embodiments of the present invention, Figure 3 The line II' and the line II-II' are parallel to the second direction D2, and the line III-III' is parallel to the first direction D1.

[0019] refer to Figures 4A to 4C , the first cavity 21A may be formed between the lower surface 12A_S of the first channel region 12A and the substrate 10, and thus the lower surface 12A_S of the first channel region 12A may be spaced apart from the substrate 10 along the third direction D3 (eg, vertical direction) by the first cavity 21A. Figure 4A and Figure 4C As shown, the first cavity 21A may expose the lower surface 12A_S of the first channel region 12A. In some embodiments, the lower surface 12A_S of the first channel region 12A and the upper surface 10_S of the substrate 10 may be at the same level, as shown in FIG. Figure 4C shown.

[0020] In some embodiments, the first cavity 21A may be formed in the first region A of the substrate 10 and may not extend into the second region B of the substrate 10. Figure 4CAs shown. Therefore, the entire lower surface 12A_S of the first channel region 12A can be exposed to the first cavity 21A without causing the first channel region 12A to collapse because the first channel region 12A is connected to the second channel region 12B while forming the first cavity 21A. In other words, the first channel region 12A can completely float on the substrate 10 (i.e., the entire lower surface 12A_S of the first channel region 12A can be spaced apart from the substrate 10 in the third direction D3) but may not collapse, because the first channel region 12A is connected to the second channel region 12B, and the second channel region 12B is connected to the substrate 10. In some embodiments, the protective layer 16 can extend on the side of the channel region 12 including the first channel region 12A and the second channel region 12B while forming the first cavity 21, as shown. Figures 3 to 4C Therefore, the protection layer 16 can help the first channel region 12A to completely float without collapsing while forming the first cavity 21A.

[0021] The mask film 20 may include a material different from that of the protective layer 16, and may have an etching selectivity with respect to the protective layer 16. The mask film 20 may be, for example, a photoresist film.

[0022] Figure 5A 、 Figure 5B and Figure 5C According to some embodiments of the present invention, Figure 3 The cross-sectional view taken along line II', line II-II' and line III-III' of FIG. Figure 5A 、 Figure 5B and Figure 5C When the first cavity 21A is formed by removing a portion of the substrate 10, a lower portion of the first channel region 12A may be removed, and a lower surface 12A_S of the first channel region 12A may be located at a level higher than the upper surface 10_S of the substrate 10 in the third direction D3 by a first distance X. The first distance X is the distance between the lower surface 12A_S of the first channel region 12A and the upper surface 10_S of the substrate 10 in the third direction D3.

[0023] refer to Figure 6 , a first bottom source / drain 22A may be formed in the first cavity 21A. In some embodiments, the first bottom source / drain 22A may be formed by performing an epitaxial growth process using an exposed surface of the substrate 10 as a seed layer, the exposed surface defining the surface of the first cavity 21A. It should be understood that the relatively large area of the surface of the first cavity 21A may allow for the growth of an epitaxial layer with fewer defects associated with the epitaxial growth process.

[0024] It will also be understood that forming the first cavity 21A exposing the entire lower surface 12A_S of the first channel region 12A allows the entire lower surface 12A_S of the first channel region 12A to overlap with the first bottom source / drain 22A, thereby forming an abrupt junction between the first channel region 12A and the first bottom source / drain 22A.

[0025] In some embodiments, the two first channel regions 12A may overlap with a single first bottom source / drain 22A, such as Figure 6 As shown, the single first bottom source / drain 22A may be referred to as a merged first bottom source / drain 22A. The entire lower surface of each of the two first channel regions 12A may overlap with the merged first bottom source / drain 22A, and in some embodiments, the entire lower surface of each of the two first channel regions 12A may contact the merged first bottom source / drain 22A.

[0026] Figure 7A 、 Figure 7B and Figure 7C According to some embodiments of the present invention, Figure 6 The cross-sectional view taken along line II', line II-II' and line III-III' of FIG. Figure 7A 、 Figure 7B and Figure 7C , the lower surface 12A_S of the first channel region 12A can directly contact the first bottom source / drain 22A. In some embodiments, the entire lower surface 12A_S of the first channel region 12A can directly contact the first bottom source / drain 22A. In addition, in some embodiments, the entire lower surface 12A_S of the first channel region 12A can overlap with the first bottom source / drain 22A, such as Figure 7A and Figure 7C In some embodiments, the first bottom source / drain 22A may include a portion having a unitary structure (eg, a structure having no interface therein), and the entire lower surface 12A_S of the first channel region 12A may overlap with the portion having the unitary structure.

[0027] In some embodiments, the first bottom source / drain 22A may be a bottom source / drain of an N-type field effect transistor, and the first bottom source / drain 22A may include, for example, a silicon layer. In some embodiments, the first bottom source / drain 22A (e.g., a silicon layer) may include phosphorus (P) as a dopant.

[0028] Figure 8A 、 Figure 8B and Figure 8C According to some embodiments of the present invention, Figure 6The cross-sectional view taken along line II', line II-II' and line III-III' of FIG. Figure 8A 、 Figure 8B and Figure 8C The first bottom source / drain 22A may include a first protrusion 22A_P protruding from an upper surface 22A_S of the first bottom source / drain 22A toward the first channel region 12A. The first protrusion 22A_P may directly contact the lower surface 12A_S of the first channel region 12A.

[0029] In some embodiments, the first cavity 21A and the first bottom source / drain 22A can be formed in situ (e.g., formed in a single processing chamber). For example, the first cavity 21A and the first bottom source / drain 22A can be in a processing chamber used for an epitaxial growth process. The first cavity 21A can be formed by an etching process using HCl as an etching gas and using H2 gas as a carrier gas. For example, the HCl gas can be supplied at a flow rate of about 100 sccm (standard cubic centimeters per minute) to about 300 sccm, the H2 gas can be supplied at a flow rate of about 20,000 sccm to 30,000 sccm, and the process temperature can be in the range of about 700°C to about 850°C. In some embodiments, the process temperature can be in the range of about 700°C to about 770°C.

[0030] In some embodiments, the first cavity 21A can be formed by a two-step process in a processing chamber for an epitaxial growth process. In the first step of the two-step process, in addition to HCl gas and H2 gas, GeH4 gas can also be supplied to form a thin SiGe layer (e.g., about 10 nm) on the substrate 10. For example, the flow rate of the GeH4 gas can be in the range of about 5 sccm to 20 sccm, and the first step can be performed for about 30 seconds to 60 seconds. In the second step of the two-step process, HCl gas and H2 gas can be supplied without GeH4 gas, and the second step can be performed for about 60 seconds to 120 seconds, for example. After the first cavity 21A, the first bottom source / drain 22A can be formed in the processing chamber by changing the processing gas and conditions (e.g., temperature, pressure).

[0031] refer to Figure 9 , can be performed on the second region B of the substrate 10 with reference Figure 3 and Figure 6A mask film may be formed on the first region A of the substrate 10, and a second cavity 21B may be formed in the second region B of the substrate 10 by removing a portion of the protective layer 16 on the second region B of the substrate 10 and a portion of the second region B of the substrate 10. Subsequently, a second bottom source / drain 22B may be formed in the second cavity 21B. In some embodiments, the second bottom source / drain 22B may be formed only in the second region B of the substrate 10.

[0032] It should be understood that forming the second cavity 21B exposing the entire lower surface 12B_S of the second channel region 12B may allow the entire lower surface 12B_S of the second channel region 12B to overlap with the second bottom source / drain 22B, thereby forming an abrupt junction between the second channel region 12B and the second bottom source / drain 22B.

[0033] In some embodiments, the second bottom source / drain 22B may be a bottom source / drain of a P-type field effect transistor. The second bottom source / drain 22B may include, for example, a silicon germanium layer. In some embodiments, the second bottom source / drain 22B (e.g., a silicon germanium layer) may include boron (B) as a dopant.

[0034] Figure 10A 、 Figure 10B and Figure 10C According to some embodiments of the present invention, Figure 9 The cross-sectional view taken along line II', line II-II' and line III-III' of FIG. Figure 10A 、 Figure 10B and Figure 10C The second cavity 21B is formed after the first bottom source / drain 22A is formed, and thus the first bottom source / drain 22A (e.g., one side of the first bottom source / drain 22A) can be partially removed while the second cavity 21B is formed (i.e., while a portion of the second region B of the substrate 10 is removed). Therefore, the material included in the first bottom source / drain 22A can be selected to reduce or possibly prevent the first bottom source / drain 22A from being removed while the second cavity 21B is formed. For example, when the substrate 10 includes a silicon layer, it may be desirable to form the first bottom source / drain 22A including a silicon layer rather than a silicon germanium layer because the silicon germanium layer is easily removed while a portion of the silicon layer of the substrate 10 is removed.

[0035] In some embodiments, the lower surface 12B_S of the second channel region 12B may directly contact the second bottom source / drain 22B. In some embodiments, the entire lower surface 12B_S of the second channel region 12B may directly contact the second bottom source / drain 22B. Figure 10B and Figure 10CFurthermore, in some embodiments, the entire lower surface 12B_S of the second channel region 12B may overlap with the second bottom source / drain 22B, as shown in FIG. Figure 10B and Figure 10C shown.

[0036] Figure 11A 、 Figure 11B and Figure 11C According to some embodiments of the present invention, Figure 9 The cross-sectional view taken along line II', line II-II' and line III-III' of FIG. Figure 11A 、 Figure 11B and Figure 11C The second bottom source / drain 22B may include a second protrusion 22B_P protruding from an upper surface 22B_S of the second bottom source / drain 22B toward the second channel region 12B. The second protrusion 22B_P may directly contact the lower surface 12B_S of the second channel region 12B.

[0037] refer to Figures 12 to 13C A portion of the channel region 12 may be removed to separate the first channel region 12A and the second channel region 12B from each other. Portions of the channel region 12 may be removed until the first bottom source / drain 22A and the second bottom source / drain 22B are exposed.

[0038] Figure 14A 、 Figure 14B and Figure 14C is after subsequent processing Figure 13A 、 Figure 13B and Figure 13C Reference Figure 14A 、 Figure 14B and Figure 14C , the protective layer 16 and the mask layer 14 may be removed to expose the first channel region 12A and the second channel region 12B, and an isolation layer 38 may be formed between the first bottom source / drain 22A and the second bottom source / drain 22B to electrically isolate the first bottom source / drain 22A from the second bottom source / drain 22B. The isolation layer 38 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0039] Furthermore, an insulating layer 32 may be formed on the first and second bottom source / drain electrodes 22A and 22B. A first gate structure 34A may then be formed on one side of the first channel region 12A, and a second gate structure 34B may be formed on one side of the second channel region 12B. The insulating layer 32 electrically isolates the first and second bottom source / drain electrodes 22A and 22B from the first and second gate structures 34A and 34B, respectively. The insulating layer 32 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0040] Each of the first gate structure 34A and the second gate structure 34B may include a plurality of layers sequentially stacked on the sides of the first channel region 12A and the second channel region 12B. The plurality of layers of the first gate structure 34A and the second gate structure 34B may include a gate insulator, a work function regulating layer, a diffusion barrier layer, an etch stop layer, and / or a conductive gate electrode.

[0041] Still refer to Figure 14A 、 Figure 14B and Figure 14C , a first top source / drain 36A can be formed on the first channel region 12A, and a second top source / drain 36B can be formed on the second channel region 12B, so that the first transistor 40A and the second transistor 40B can be formed on the first region A and the second region B of the substrate 10, respectively. In some embodiments, each of the first top source / drain 36A and the second top source / drain 36B can be formed by performing an epitaxial growth process using one of the first channel region 12A and the second channel region 12B as a seed layer. It should be understood that the first top source / drain 36A and the second top source / drain 36B can be formed using any of a variety of methods.

[0042] Figure 15A 、 Figure 15B and Figure 15C is after subsequent processing Figure 13A 、 Figure 13B and Figure 13C The cross-sectional view of the Figure 14A 、 Figure 14B and Figure 14C The first bottom source / drain 22A may include a first protruding portion 22A_P having a first thickness X in the third direction D3, and the second bottom source / drain 22B may include a second protruding portion 22B_P having a second thickness Y in the third direction D3. For example, each of the first thickness X and the second thickness Y may be in the range of 0 nm to about 10 nm. In some embodiments, the first thickness X and the second thickness Y may be different, such as Figure 15A and Figure 15B In some embodiments, at least one of the first thickness X and the second thickness Y can be non-zero (ie, greater than zero). In some embodiments, the first thickness X and the second thickness Y can be the same.

[0043] According to the method for forming a VFET device described herein, the first thickness X and the second thickness Y can have different values because the first cavity 21A and the second cavity 21B are formed through separate processes. For example, the first thickness X and the second thickness Y can be determined independently by controlling the process conditions (e.g., etching time) used to form the first cavity 21A and the second cavity 21B. Therefore, it can be understood that by considering the performance of the first transistor 40A and the second transistor 40B, the bottom source / drain side junction overlap of the first transistor 40A and the second transistor 40B can be controlled separately.

[0044] According to the method for forming a VFET device described in this article, the entire lower surface 12A_S of the first channel region 12A and the entire lower surface 12B_S of the second channel region 12B overlap with the first bottom source / drain 22A and the second bottom source / drain 22B, respectively. Therefore, an abrupt junction between the first channel region 12A and the first bottom source / drain 22A and an abrupt junction between the second channel region 12B and the second bottom source / drain 22B can be formed.

[0045] refer to Figure 16 , the method according to some embodiments of the present inventive concept may include: forming a channel region 12 on a substrate 10 (block 110 ) (see, for example, Figure 1 ); forming a first bottom source / drain 22A in the substrate 10 (block 120) (see, for example, Figures 3 to 8C ); forming a second bottom source / drain 22B in the substrate 10 (block 130) (see, for example, Figures 9 to 11C ); forming a first channel region 12A and a second channel region 12B (block 140) (see, for example, Figures 12 to 13C ); and forming a first gate structure 34A and a second gate structure 34B (block 150) (see, e.g., 14A to 15C ).

[0046] refer to Figure 17 In some embodiments, forming the first bottom source / drain 22A in the substrate 10 may include forming a first cavity 21A in the substrate 10 (block 120 - 1 ) (see, for example, Figures 2 to 5C ) and forming a first bottom source / drain 22A in the first cavity 21A (block 120-2) (see e.g. Figures 6 to 8C In some embodiments, forming the second bottom source / drain 22B in the substrate 10 may include forming a second cavity 21B in the substrate 10 (block 130-1) and forming the second bottom source / drain 22B in the second cavity 21B (block 130-2) (see, e.g., Figures 9 to 11C ).

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be understood as idealized or overly formal unless explicitly defined herein.

[0048] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present inventive concept. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "including", and / or "comprising" specify the presence of the features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0049] It should be understood that reference herein to "element A vertically overlapping element B" (or similar language) means that there is a vertical line that intersects both elements A and B.

[0050] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the first element can be called the second element.

[0051] It should also be noted that in some alternative embodiments, the functions / actions mentioned in the flowchart blocks of this article may not occur in the order mentioned in the flowchart. For example, two blocks shown in succession may actually be performed substantially simultaneously, or these blocks may sometimes be performed in reverse order, depending on the functions / actions involved. In addition, the functions of a given block of a flowchart and / or block diagram may be divided into multiple blocks and / or the functions of two or more blocks of a flowchart and / or block diagram may be at least partially integrated. Finally, other blocks may be added / inserted between the blocks shown, and / or blocks / operations may be omitted without departing from the scope of the present invention.

[0052] The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A method for forming a vertical field effect transistor device, the method comprising: forming a channel region protruding from an upper surface of the substrate and extending longitudinally along a first horizontal direction, wherein the channel region includes a first channel region and a second channel region aligned in the first horizontal direction, and the first channel region and the second channel region overlap with a first portion and a second portion of the substrate, respectively; forming a first cavity in the substrate by removing a first portion of the substrate, wherein the first cavity exposes a lower surface of the first channel region; forming a first bottom source / drain in a first cavity of the substrate; forming a second cavity in the substrate by removing a second portion of the substrate, wherein the second cavity exposes a lower surface of the second channel region; forming a second bottom source / drain in a second cavity of the substrate; After forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and A first gate structure is formed on one side of the first channel region, and a second gate structure is formed on one side of the second channel region.

2. The method according to claim 1, wherein The first bottom source / drain includes a first protruding portion protruding from an upper surface of the first bottom source / drain toward the first channel region, wherein the second bottom source / drain comprises a second protruding portion protruding from an upper surface of the second bottom source / drain toward the second channel region, and The first protruding portion has a first thickness in a vertical direction, the second protruding portion has a second thickness in the vertical direction, and the first thickness and the second thickness are different.

3. The method according to claim 1, wherein The first bottom source / drain includes a different material than the second bottom source / drain.

4. The method according to claim 3, wherein: forming the first bottom source / drain is performed before forming the second bottom source / drain, and The first bottom source / drain comprises a bottom source / drain of an N-type field effect transistor, and the second bottom source / drain comprises a bottom source / drain of a P-type field effect transistor. 5 . The method of claim 1 , further comprising forming a protection layer extending on one side of the channel region, wherein the forming the first cavity and the forming the second cavity are performed while the protection layer is located on one side of the channel region.

6. The method according to claim 1, wherein Forming the first cavity includes removing a lower portion of the first channel region, and forming the second cavity includes removing a lower portion of the second channel region.

7. The method according to claim 1, wherein Forming the second cavity is performed after forming the first bottom source / drain.

8. The method according to claim 1, wherein The first cavity exposes the entire lower surface of the first channel region, and The second cavity exposes the entire lower surface of the second channel region.

9. The method according to claim 1, wherein Forming the channel region includes: forming a mask layer on the substrate; and The substrate is etched using the mask layer as an etch mask to form the channel region.

10. The method according to claim 1, wherein Forming the channel region includes forming a plurality of channel regions on the substrate, wherein each of the plurality of channel regions extends longitudinally in the first horizontal direction, and the plurality of channel regions are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of channel regions includes a corresponding one of the plurality of first channel regions and a corresponding one of the plurality of second channel regions, wherein the plurality of first channel regions overlap with the first bottom source / drain, wherein the plurality of second channel regions overlap with the second bottom source / drain, The removing of a portion of the channel region between the first channel region and the second channel region includes: removing a plurality of portions of the plurality of channel regions respectively to separate the plurality of first channel regions from the plurality of second channel regions.

11. A method of forming a vertical field effect transistor device, the method comprising: forming a channel region on a substrate, wherein the channel region extends longitudinally along a first horizontal direction and includes a first channel region and a second channel region, wherein the first channel region and the second channel region are aligned in the first horizontal direction; forming a first cavity in the substrate; forming a first bottom source / drain in the first cavity, wherein the first channel region overlaps with the first bottom source / drain; After forming the first bottom source / drain, forming a second cavity in the substrate; forming a second bottom source / drain in the second cavity, wherein the second channel region overlaps the second bottom source / drain; After forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and forming a first gate structure on one side of the first channel region and forming a second gate structure on one side of the second channel region, wherein the first bottom source / drain comprises a first protruding portion protruding from an upper surface of the first bottom source / drain toward the first channel region, and The second bottom source / drain includes a second protruding portion protruding from an upper surface of the second bottom source / drain toward the second channel region.

12. The method according to claim 11, wherein The first channel region includes a lower surface facing the first bottom source / drain, and wherein the entire lower surface of the first channel region contacts the first bottom source / drain, and The second channel region includes a lower surface facing the second bottom source / drain, and the entire lower surface of the second channel region contacts the second bottom source / drain.

13. The method according to claim 11, in, The first protruding portion has a first thickness in a vertical direction, and the second protruding portion has a second thickness in the vertical direction, the first thickness being different from the second thickness.

14. The method according to claim 11, wherein Forming the channel region includes: forming a mask layer on the substrate; and The substrate is etched using the mask layer as an etch mask to form the channel region.

15. The method according to claim 11, wherein forming the first bottom source / drain is performed before forming the second bottom source / drain, and The first bottom source / drain is a bottom source / drain of an N-type field effect transistor, and the second bottom source / drain is a bottom source / drain of a P-type field effect transistor.

16. The method according to claim 11, wherein The first channel region includes a plurality of first channel regions spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and each of the plurality of first channel regions overlaps with the first bottom source / drain, and The second channel region includes a plurality of second channel regions spaced apart from each other in the second horizontal direction, and each of the plurality of second channel regions overlaps with the second bottom source / drain.

17. The method according to claim 11, wherein The first protruding portion of the first bottom source / drain contacts the first channel region, and each of the first channel region and the first protruding portion of the first bottom source / drain has a first width in a second horizontal direction perpendicular to the first horizontal direction at an interface between the first channel region and the first protruding portion of the first bottom source / drain.

18. A method of forming a vertical field effect transistor device, the method comprising: forming a channel region on a substrate, wherein the channel region extends longitudinally along a first horizontal direction and includes a first channel region and a second channel region, wherein the first channel region and the second channel region are arranged in the first horizontal direction; forming a first cavity in the substrate; forming a first bottom source / drain in the first cavity, wherein the first channel region contacts the first bottom source / drain; After forming the first bottom source / drain, forming a second cavity in the substrate; forming a second bottom source / drain in the second cavity, wherein the second channel region contacts the second bottom source / drain; After forming the first bottom source / drain and the second bottom source / drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region; and A first gate structure is formed on one side of the first channel region, and a second gate structure is formed on one side of the second channel region.

19. The method according to claim 18, wherein The second cavity exposes a portion of the first bottom source / drain, and the second bottom source / drain contacts the first bottom source / drain.

20. The method according to claim 18, wherein The first channel region includes a lower portion connected to the substrate, and forming the first cavity includes removing the lower portion of the first channel region.

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