Chip packaging method and chip structure

Abstract

The present disclosure provides a chip packaging method and a chip structure, the chip packaging method comprising: providing a wafer, forming a protective layer on the active surface of the wafer; cutting and separating the wafer to form a bare chip; providing a metal structure, the metal structure comprising at least one metal unit; mounting the bare chip and the metal structure on a carrier; and forming a plastic encapsulation layer. The chip structure comprises: at least one bare chip; a protective layer; a metal unit, the metal unit comprising at least one metal feature; a plastic encapsulation layer for encapsulating the bare chip and the metal unit; wherein the chip structure is connected to an external circuit via at least one metal feature. The present disclosure achieves an improvement in packaging performance brought about by different metal features by utilizing multiple metal features of the metal unit, and in the present disclosure, a protective layer is formed on the active surface of the wafer, eliminating the step of applying an insulating layer after the step of forming the plastic encapsulation layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a chip packaging method and a chip structure. Background Art

[0002] Panel-level packaging is to cut a wafer into a number of dies, arrange the dies and paste them on a carrier, and package the dies simultaneously in the same process. Panel-level packaging has been a technology that has emerged in recent years and has received widespread attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and suitability for large-scale production. Summary of the invention

[0003] The present disclosure aims to provide a chip packaging method, which includes: providing a wafer, forming a protective layer on the active surface of the wafer; cutting and separating the wafer to form bare chips; providing a metal structure, wherein the metal structure includes at least one metal unit; mounting the bare chip and the metal structure on a carrier; and forming a plastic packaging layer.

[0004] The present disclosure also provides a chip structure, which includes: at least one bare die; a protective layer; a metal unit, wherein the metal unit includes at least one metal feature; and a plastic encapsulation layer for encapsulating the bare die and the metal unit; wherein the chip structure is connected to an external circuit via at least one metal feature.

[0005] The present disclosure improves packaging performance brought about by different metal features by utilizing multiple metal features of a metal unit.

[0006] The metal feature may include a connection structure and a heat dissipation structure. The connection structure is connected to the electrical connection point on the active surface of the die in the chip through the conductive structure. The packaged chip structure is connected to the external circuit element, such as a PCB board, through the connection structure, thereby replacing the wire bonding structure. Compared with the wire bonding packaging structure, the present invention has a simple packaging process, eliminates the mutual interference of signals between the leads in the wire bonding structure, and eliminates the noise generated by the leads due to vibration when the chip is working. And using the connection structure to replace the lead structure is more suitable for chip packaging with large electric flux.

[0007] Furthermore, the bare chip arranged on the carrier together with the metal structure is a bare chip with a protective layer. Since in the present disclosure, the bare chip arranged on the carrier already has a protective layer, the step of forming the panel-level conductive layer can be directly performed without first performing the step of applying the insulating layer after the step of forming the plastic encapsulation layer. In particular, in large-size panels, if an insulating layer is formed on the entire panel, firstly, the process difficulty is much greater than that of forming a protective layer of a small area, and secondly, forming an insulating layer on the entire panel will also increase the amount of insulating layer material used.

[0008] Furthermore, the protective layer and plastic encapsulation layer used in the present disclosure have certain material properties, which can help reduce warping during the panel packaging process and make the packaged chip structure have a durable service life, and are particularly suitable for large panel-level packaging and packaging of large current flux, thin chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flow chart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure;

[0010] Figures 2 to 15 is a flow chart of a chip packaging method proposed according to an exemplary embodiment of the present disclosure;

[0011] Figures 16 to 20 is a schematic flow chart of a chip packaging method proposed according to another exemplary embodiment of the present disclosure;

[0012] Figure 21 to Figure 25 is a flow chart of a chip packaging method proposed according to another exemplary embodiment of the present disclosure;

[0013] Figure 26 to Figure 28 is a schematic flow chart of a chip packaging method proposed according to another exemplary embodiment of the present disclosure;

[0014] Fig.29a , 29b , 29c, 29d, and 29e are schematic diagrams of chip structures obtained by using the above packaging method according to exemplary embodiments of the present disclosure;

[0015] Fig.30 FIG. 4 is a schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to make the technical solution of the present disclosure clearer and the technical effects more obvious, the following detailed and specific description and illustration of the preferred embodiments of the present disclosure are given in conjunction with the accompanying drawings. It should not be understood that the following description is the only implementation form of the present disclosure or a limitation to the present disclosure.

[0017] Figure 1is a flow chart of a chip packaging method according to Embodiment 1 of the present disclosure. Figure 1 , the method of the present disclosure comprises the steps of:

[0018] Step S1, providing a wafer 100.

[0019] like Figure 2 As shown, at least one wafer 100 is provided, and the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002. The wafer 100 includes a plurality of bare chips 113, wherein the active surface of each bare chip constitutes the wafer active surface 1001. The active surface of each bare chip in the wafer 100 is formed into a series of active components and passive components through a series of processes such as doping, deposition, and etching. The active components include diodes, triodes, etc., and the passive components include transformers, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits, thereby realizing various functions. The wafer active surface 1001 also includes an electrical connection point 103 for leading out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103.

[0020] Step S2, applying a protective layer 107 on the active surface 1001 of the wafer.

[0021] Figure 3a-3b The optional process step of applying a protective layer 107 on the active surface 1001 of the wafer is shown:

[0022] like Figure 3a As shown, a protective layer 107 is applied to the active surface 1001 of the wafer.

[0023] Preferably, the protective layer 107 is applied to the active surface 1001 of the wafer by lamination.

[0024] Optionally, before the step of applying the protective layer 107 on the active surface 1001 of the wafer, the active surface 1001 of the wafer and / or the side of the protective layer 107 applied to the wafer 100 is physically and / or chemically treated to make the bonding between the protective layer 107 and the wafer 100 tighter. The treatment method may be plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter modifier treatment to introduce promoter modification groups between the wafer 100 and the protective layer 107, such as a surface modifier with both organic and inorganic affinity groups, to increase the adhesion between the organic / inorganic interface layer.

[0025] like Figure 3b As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0026] A protective layer opening 109 is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the wafer active surface 1001 , exposing the electrical connection point 103 on the wafer active surface 1001 .

[0027] Preferably, there is a one-to-one correspondence between the protection layer openings 109 and the electrical connection points 103 on the wafer active surface 1001 .

[0028] Optionally, each of the protection layer openings 109 in at least a portion of the protection layer openings 109 corresponds to a plurality of electrical connection points 103 .

[0029] Optionally, at least a portion of the electrical connection points 103 corresponds to a plurality of protection layer openings 109 .

[0030] Optionally, at least a portion of the protection layer openings 109 do not have corresponding electrical connection points 103 , or at least a portion of the electrical connection points 103 do not have corresponding protection layer openings 109 .

[0031] The protective layer opening is formed by laser patterning or photolithography patterning.

[0032] If the protective layer opening is formed by laser patterning, preferably, before the protective layer 107 is applied to the active surface 1001 of the wafer, a chemical plating process step is performed on the active surface 1001 of the wafer to form a conductive covering layer on the electrical connection point 103. Optionally, the conductive covering layer is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive covering layer is not shown in the figure. The conductive covering layer can protect the electrical connection point 103 on the active surface 1001 of the wafer from laser damage in the subsequent protective layer opening formation step.

[0033] Preferably, Figure 3b As shown in the partial enlarged view in FIG. 1 , there is a gap between the lower surface 109 a of the protective layer opening and the insulating layer 105 . Preferably, the lower surface 109 a of the protective layer opening is located near the center of the electrical connection point 103 .

[0034] In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of ​​the upper surface 109b of the protective layer opening is larger than the area of ​​the lower surface 109a of the protective layer opening, and the area ratio of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening is 60% to 90%.

[0035] At this time, the slope of the side wall 109 c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the side wall.

[0036] Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the carrier is peeled off.

[0037] Optionally, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductive filled through hole 124. At least a portion of the conductive filled through hole 111 is connected to the electrical connection point 103 on the wafer active surface 1001. The conductive filled through hole 111 extends the electrical connection point 103 on the wafer active surface 1001 to the protective layer surface in a single direction, and the protective layer is formed around the conductive filled through hole 111. The conductive medium can be gold, silver, copper, tin, aluminum or other materials or a combination thereof, or other suitable conductive materials formed in the protective layer opening 109 by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form a conductive filled through hole 111.

[0038] Figure 4a-4c Another optional process step for applying a protective layer 107 on the active surface 1001 of the wafer is shown:

[0039] like Figure 4a As shown, a wafer conductive layer 130 is formed on the wafer active surface 1001 .

[0040] The wafer conductive layer 130 is a wafer conductive trace 106. The wafer conductive trace 106 can be made of copper, gold, silver, tin, aluminum or a combination thereof, or can be made of other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0041] At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active surface 1001.

[0042] Optionally, the wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active surface 1001, thereby forming a bare die. Figure 6b Schematic diagram of the bare die in A.

[0043] The formation of the chip conductive traces 106 can reduce the number of protective layer openings 109 formed in the subsequent process. By using the chip conductive traces 106 to first interconnect multiple electrical connection points 103 according to the circuit design, the need to form a protective layer opening 109 on each electrical connection point 103 is eliminated.

[0044] Optionally, the wafer conductive traces 106 lead out at least a portion of the electrical connection points 103 on the wafer active surface 1001 separately, and the bare die formed thereby is shown in FIG. Figure 6b Schematic diagram of the bare die in B.

[0045] The formation of the chip conductive trace 106 helps to reduce the difficulty of the subsequent formation process of the protective layer opening 109. Due to the existence of the chip conductive trace 106, the lower surface 109a of the protective layer opening can have a larger area. Correspondingly, the protective layer opening 109 can have a larger area, especially on the chip 100 with a smaller exposed electrical connection point 103, which makes the formation of the protective layer opening possible.

[0046] Although not shown in the figure, it can be understood that the wafer conductive traces 106 lead out a portion of the electrical connection points 103 on the wafer active surface 1001 separately and interconnect and lead out another portion of the electrical connection points 103 on the wafer active surface 1001.

[0047] like Figure 4b As shown, a protective layer 107 is applied on the wafer active surface 1001 and the wafer conductive layer 130 .

[0048] In one embodiment, the protective layer 107 is applied by lamination.

[0049] Optionally, before the step of applying the protective layer 107, the wafer active surface 1001 and / or the side of the protective layer 107 applied to the wafer 100 is physically and / or chemically treated to make the bonding between the protective layer 107 and the wafer 100 tighter. The treatment method may be plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter modifier treatment to introduce promoter modification groups between the wafer 100 and the protective layer 107, such as a surface modifier with both organic and inorganic affinity groups, to increase the adhesion between the organic / inorganic interface layer.

[0050] like Figure 4c As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0051] At least a portion of the protective layer opening 109 is located corresponding to the wafer conductive layer 130 , and the wafer conductive layer 130 is exposed through the protective layer opening 109 ; the protective layer opening 109 has a protective layer opening lower surface 109 a and a protective layer opening upper surface 109 b .

[0052] In a preferred embodiment, the shape of the protective layer opening 109 is that the area of ​​the upper surface 109b of the protective layer opening is larger than the area of ​​the lower surface 109a of the protective layer opening. At this time, the slope of the side wall 109c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be evenly and continuously formed on the side wall.

[0053] Preferably, the contact area of ​​a single contact region between the wafer conductive layer 130 and the electrical connection point 103 is smaller than the contact area of ​​a single contact region between the wafer conductive layer 130 and the protective layer opening 109 .

[0054] When the chip 100 is of a type in which the exposed electrical connection point 103 is small in area, a conductive layer is formed on the active surface 1001 of the chip, and then a protective layer opening is formed. This can effectively reduce the difficulty of forming the protective layer opening and avoid the protective layer opening 109 being difficult to form due to the lower surface 109a of the protective layer opening being too small.

[0055] The protective layer opening is formed by laser patterning or photolithography patterning.

[0056] Optionally, the protective layer opening 109 may not be formed temporarily, and the protective layer opening 109 may be formed on the protective layer after the carrier is peeled off.

[0057] Optionally, a conductive medium is filled in the protective layer opening 109 , so that the protective layer opening 109 becomes a conductive filled through hole 124 , at least a portion of the conductive filled through hole 124 is connected to the wafer conductive layer 130 , and the protective layer surrounds the conductive filled through hole 124 .

[0058] Figure 5a to Figure 5c A further optional process step of applying a protective layer 107 on the active surface 1001 of the wafer is shown.

[0059] like Figure 5a As shown, wafer conductive traces 106 are formed on the active surface 1001 of the wafer.

[0060] The wafer conductive traces 106 may be made of copper, gold, silver, tin, aluminum or a combination thereof, or may be other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0061] The at least a portion of the wafer conductive traces 106 may be configured to interconnect and lead out a plurality of the electrical connection points 103 in at least a portion.

[0062] The at least a portion of the wafer conductive traces 106 may also be formed by separately leading out at least a portion of the electrical connection points 103. Figure 6c Schematic diagram of the bare die in B.

[0063] like Figure 5b As shown, wafer conductive studs 111 are formed on pads or connection points of wafer conductive traces 106 .

[0064] The shape of the wafer conductive protrusion 111 can be round, or other shapes such as oval, square, linear, etc. The wafer conductive protrusion 111 can be one or more layers of copper, gold, silver, tin, aluminum, or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0065] Optionally, the wafer conductive protrusion 111 may also be directly formed at the electrical connection point 103 on the wafer active surface 1001, and the electrical connection point 103 is led out, and the bare chip formed thereby is shown in FIG. Figure 6c Schematic diagram of the bare die in C.

[0066] The wafer conductive traces 106 and / or the wafer conductive bumps 111 are referred to as a wafer conductive layer 130 .

[0067] like Figure 5c As shown, a protective layer 107 is applied over the conductive layer 130 of the wafer.

[0068] The protection layer 107 is applied on the wafer conductive layer 130 to cover the wafer conductive layer 130 .

[0069] In one embodiment, the protective layer is applied by lamination.

[0070] In one embodiment, the protective layer 107 is applied so that the protective layer 107 completely covers the wafer conductive layer 130 . In this case, after the protective layer 107 is applied, the thickness of the protective layer 107 is reduced to expose the surface of the wafer conductive layer.

[0071] In another embodiment, the thickness of the applied protection layer 107 is just enough to expose the surface of the wafer conductive layer 130 .

[0072] Optionally, before the step of applying the protective layer 107, the wafer active surface 1001 formed with the wafer conductive layer 130 and / or the side of the protective layer 107 applied to the wafer 100 is subjected to physical and / or chemical treatment to make the protective layer 107 and the wafer 100 more tightly bonded. The treatment method may be plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter modifier treatment to introduce promoter modification groups between the wafer 100 and the protective layer 107, such as a surface modifier having both organic and inorganic affinity groups, to increase the adhesion between the organic / inorganic interface layer.

[0073] In step S2, during the process of applying the protective layer 107 to the active surface 1001 of the chip, the protective layer 107 can protect the active surface 1131 of the die from the infiltration of the molding material during the molding process, thereby protecting the active surface 1131 of the die from damage; at the same time, during the molding process, the molding pressure is not likely to cause the position of the die 113 on the carrier 117 to move; in addition, the alignment accuracy requirement of the subsequent panel-level conductive layer formation process can also be reduced.

[0074] The protective layer 107 is made of insulating material, such as BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, polymer matrix dielectric film, organic polymer film, or other materials with similar insulating and structural properties, and is formed by lamination, coating, printing, etc.

[0075] Preferably, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 7000, 4000 to 7000 or 4000 to 8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

[0076] Preferably, the thickness of the protective layer 107 is in the range of 15 to 50 μm; more preferably, the thickness of the protective layer is in the range of 20 to 50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

[0077] When the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient supporting force, so that the protective layer 107 has sufficient support for the conductive layer formed on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffering and support.

[0078] In particular, in some types of chips, it is necessary to use a thin bare chip for packaging, and the conductive layer needs to reach a certain thickness value to form a large electric flux. At this time, the thickness range of the protective layer 107 is selected to be 15-50μm, and the value range of the Young's modulus of the protective layer 107 is 1000-10000MPa. The soft and flexible protective layer 107 can form a buffer layer between the bare chip 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the chip, the conductive layer on the surface of the protective layer will not excessively press the bare chip 113, and prevent the pressure of the thick conductive layer from breaking the bare chip 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

[0079] When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the material properties of the protective layer 107, the protective layer 107 can effectively protect the die against the ejector pin pressure of the die transfer equipment during the subsequent die transfer process.

[0080] The die transfer process is a process (reconstruction process) of rearranging and bonding the cut and separated die 113 to the carrier 117. The die transfer process requires the use of a die transfer device (bonder machine). The die transfer device includes a pin, which is used to lift the die 113 on the wafer 100, and a bonder head is used to suck up the lifted die 113, transfer it, and bond it to the carrier 117.

[0081] During the process of the bare die 113 being lifted by the ejector pin, the bare die 113, especially the thin bare die 113, is brittle and easily broken by the lifting pressure of the ejector pin. The protective layer 107 with material properties can protect the brittle bare die 113 in this process and keep the bare die 113 intact even under a larger lifting pressure.

[0082] Preferably, the protective layer 107 is an organic / inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO 2 In one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as SiO 2 Mixed TiO 2 Preferably, the filler particles in the protective layer 107 are inorganic oxide particles, such as SiO 2 Particles, such as SiO 2 Mixed TiO 2The particles are spherical or quasi-spherical. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 particles, such as SiO 2 mixed TiO 2 particles, have a filling amount of more than 50%.

[0083] The organic material has the advantages of being easy to operate and apply. The die 113 to be encapsulated is an inorganic material such as silicon. When the protective layer 107 is made of an organic material alone, due to the differences between the material properties of the organic material and the inorganic material, the encapsulation process is difficult and the encapsulation effect is affected. By using an organic / inorganic composite material with inorganic particles added to the organic material, the material properties of the organic material can be modified, making the material have the characteristics of both organic and inorganic materials.

[0084] Especially the coefficient of thermal expansion (CTE) of the material. The silicon die 113 has a relatively low coefficient of thermal expansion, usually about 3 ppm / K. The protective layer 107 being an organic / inorganic composite material layer including filler particles can reduce the coefficient of thermal expansion of the protective layer, reducing the property differences between the organic layer and the inorganic layer in the encapsulation structure.

[0085] In a preferred embodiment, when (T < Tg), the range of the coefficient of thermal expansion of the protective layer 107 is 3 - 10 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the protective layer 107 is 5 ppm / K; in a preferred embodiment; the coefficient of thermal expansion of the protective layer 107 is 7 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the protective layer 107 is 10 ppm / K.

[0086] In the subsequent encapsulation process, the die 113 with the protective layer 107 applied will expand and contract correspondingly during the heating and cooling processes of the encapsulation. When the coefficient of thermal expansion of the protective layer 107 is in the range of 3 - 10 ppm / K, the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, and the interface stress is not easily generated at the connection interface between the protective layer 107 and the die 113, and the bond between the protective layer 107 and the die 113 is not easily damaged, making the encapsulated chip structure more stable.

[0087] During the use of the encapsulated chip, it often needs to undergo thermal cycling. The coefficient of thermal expansion of the protective layer 107 ranges from 3 - 10 ppm / K and has the same or similar coefficient of thermal expansion as the die 113. During the thermal cycling process, the protective layer 107 and the die 113 maintain a relatively consistent degree of expansion and contraction, avoiding the accumulation of interface fatigue at the interface between the protective layer 107 and the die 113, making the encapsulated chip durable and extending the service life of the chip.

[0088] On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill too many filler particles in the composite material of the protective layer 107. While further reducing the thermal expansion coefficient, the Young's modulus of the material will also increase, reducing the flexibility of the protective layer material, making the rigidity too strong, and the buffering effect of the protective layer 107 is poor. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10ppm / k.

[0089] When the step of forming the protective layer opening by laser patterning is included, preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 The diameter of the particles is less than 3 μm. Preferably, the diameter of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 particles, is between 1 and 2 μm.

[0090] Controlling the diameter of the filler particles to be less than 3 μm is beneficial to forming a protective layer opening with smoother side walls on the protective layer 107 during the laser patterning process, so that the material can be fully filled during the conductive material filling process, thereby avoiding the situation where the conductive material cannot be filled on the protective layer opening side wall 109c with large-sized bumps behind the side wall blocked by the protrusions, thereby affecting the conductive performance of the conductive filled through hole 124.

[0091] At the same time, the filling size of 1 to 2 μm will expose small-particle fillers during the laser patterning process, so that the side wall 109c of the protective layer opening has a certain degree of roughness. This side wall with a certain degree of roughness will have a larger contact area with the conductive material and a closer contact, forming a conductive filled through hole 124 with good conductive performance.

[0092] The diameter size of the filler mentioned above is the average value of the particle diameter.

[0093] Optionally, the tensile strength of the protective layer 107 has a value ranging from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

[0094] Optionally, after applying the protective layer 107 on the active surface 1001 of the wafer, the back side 1002 of the wafer is ground to thin the wafer 100 to a desired thickness.

[0095] Modern electronic devices are small and lightweight, and chips have a trend of becoming thinner. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 is difficult, and the grinding and thinning process is difficult, and it is often difficult to thin the wafer 100 to an ideal thickness. When the surface of the wafer 100 has a protective layer 107, the protective layer 107 with material properties will support the wafer 100, reducing the difficulty of processing, transferring and thinning the wafer 100.

[0096] Step S3 , cutting the wafer 100 with the protection layer 109 applied thereto to form bare chips 113 with the protection layer 109 .

[0097] like Figure 6a As shown, the wafer 100 with the protection layer 107 applied thereto is cut along the dicing lines to obtain a plurality of bare chips 113 with the protection layer formed thereon. The bare chips 113 have bare chip active surfaces 1131 and bare chip back surfaces 1132 .

[0098] like Figure 6b As shown, the wafer 100 having a wafer conductive layer 130 and a protective layer 107 with protective layer openings 109 is cut along the cutting path to obtain a plurality of dies 113 . The dies 113 have a die active surface 1131 and a die back surface 1132 .

[0099] in, Figure 6b The middle die schematic diagram A shows that the wafer conductive traces 106 interconnect and lead out multiple electrical connection points 103 on the die active surface 1131 .

[0100] Figure 6b The middle die schematic diagram B shows that the wafer conductive traces 106 lead out the electrical connection points 103 on the die active surface 1131 separately.

[0101] like Figure 6c As shown, the wafer 100 formed with the wafer conductive layer 130 and the protective layer 107 is cut along the dicing line to obtain a plurality of dies 113 . The dies 113 have a die active surface 1131 and a die back surface 1132 .

[0102] in, Figure 6c The middle die schematic diagram A shows that the wafer conductive traces 106 interconnect and lead out multiple electrical connection points 103 on the die active surface 1131 .

[0103] Figure 6c The middle die schematic diagram B shows that the wafer conductive traces 106 lead out the electrical connection points 103 on the die active surface 1131 separately.

[0104] Figure 6c The middle bare die schematic diagram C shows that the wafer conductive protrusion 111 is directly formed at the electrical connection point 103 on the wafer active surface 1001, and the electrical connection point 103 is led out.

[0105] Optionally, before the step of cutting the wafer 100 to separate the bare die 113, the step further includes performing plasma surface treatment on the side of the wafer 100 having the protective layer 107 to increase the surface roughness, so as to increase the adhesion of the bare die 113 to the carrier 117 in subsequent processes and to prevent the bare die 113 from moving under the pressure of the plastic package.

[0106] Due to the material properties of the protection layer, during the dicing process of the wafer 100 , the separated dies 113 are free of burrs and die chips.

[0107] It is understandable that, if the process allows, according to the actual situation, after the wafer 100 is cut into the bare chips 113 to be packaged, a wafer conductive layer 130 and / or a protective layer 107 can be formed on the bare chip active surface 1131 of each bare chip 113. The wafer conductive layer 130 refers to the conductive layer formed before the bare chips 113 cut from the wafer 100 are mounted on the carrier.

[0108] Step S4, providing a metal structure.

[0109] according to Figure 7 In the embodiment shown, the metal structure is a metal frame 200, which is composed of a metal unit array. The metal frame 200 can use the existing lead frame in the industry, or it can be formed by etching or mechanical stamping a piece or piece of metal according to actual needs. The metal to be engraved can be a single metal, such as copper, or an alloy. A second metal, such as nickel and / or gold, can be partially or completely coated on the surface of the metal to protect the metal sheet from environmental corrosion, such as oxidation. The thickness of the metal is not less than the thickness of the bare chip 113. The metal to be engraved can be a rectangle, or a square or other shapes, such as Figure 7 As shown in the figure, the metal is engraved to include four identical metal units, and the outer contour of each metal unit is a rectangle. This is also exemplary. The number of metal units is not limited to four and can be set according to actual needs. The shape of the metal unit can also be a rectangle or other shapes. The blank area in the metal unit indicates that the metal is completely etched away, and the retained metal part includes metal features. Different metal features can bring different performance improvements.

[0110] exist Figure 7The metal features include at least one connection pad 201, which is arranged inside the edge of the contour of the metal frame 200, and can also be arranged in other positions according to actual needs. The connection pads 201 are connected by connecting rods 203 of metal that have not been etched. The connection pads 201 are equivalent to the pins of the packaged bare chip. According to the present disclosure, after the bare chip 113 is packaged, the connection pads 201 are in an exposed state. The packaged bare chip 113 is soldered to the circuit board through these connection pads 201 to achieve connection with other circuit elements. When the metal is engraved, the connecting rods 203 are retained to ensure that the connection pads 201 and other features formed by the engraving are connected to the outer contour line of the metal frame 200, so that when the metal frame 200 is transferred, it can be ensured that the features engraved thereon will not fall off. Optionally, the metal sheet can be mounted on a temporary support for engraving first, and the position of the metal frame can be transferred with the help of the support after the engraving is completed. This method does not require engraving connecting wires / connecting rods.

[0111] like Figure 7 Each metal unit in the metal frame 200 shown includes a vacancy 202, which is shown as a blank area in the figure. The blank area is formed by completely etching a part of the metal, and its area is larger than the surface area of ​​the die 113, so that the die 113 and the metal frame 200 are attached to the carrier in the subsequent steps without contacting the die 113. According to the example in the figure, each metal unit includes one vacancy 202. In another example, a metal unit may also include two or more vacancy 202, and each vacancy 202 accommodates one or more die 113. Adjacent metal frames 200 have a common outer contour edge, such as Figure 7 As shown, the metal frame 200 at the upper left corner and the metal frames 200 at the right and bottom thereof each have a common outer contour edge, so that all the metal frames 200 are connected to form a whole.

[0112] like Figure 7 The metal frame 200 of the present disclosure shown is only exemplary. The area of ​​a whole piece of metal can be the same as the surface area of ​​the carrier 117, and the shape is also the same as the shape of the carrier 117, preferably a rectangle or a rectangular, but it can also be designed to other shapes according to actual needs. However, it was found during the experiment that when the area of ​​the carrier 117 is relatively large, if a metal of the same size as the carrier 117 is used to etch the metal frame 200, since the metal is relatively thin, when its area is large, it will easily cause deformation during the transfer process and it is not easy to operate. Therefore, preferably, two or more pieces of metal whose total area is the same as the surface area of ​​the carrier 117 can be used, and one or more metal frames 200 can be etched on each piece of metal. During the manufacturing process, each piece of metal after etching is sequentially set on the carrier 117, and put together to have the same surface area as the carrier 117.

[0113] Step S5 , placing the bare chip 113 with the protection layer 107 and the metal structure on the carrier 117 .

[0114] Figure 8a-Figure 9 A preferred embodiment of setting the metal frame on the carrier board in step S5 is shown.

[0115] Since the metal material used in the metal frame 200 is relatively thin, especially when the area is relatively large, the surface is easily bent and deformed when being taken and placed. Therefore, in order to more conveniently adhere the metal frame 200 to the carrier 117 accurately while maintaining a flat surface, the following method can be used:

[0116] like Figure 8a and 8b As shown, a temporary support plate 300 is provided, and an adhesive layer 301 is formed on the surface of the temporary support plate 300, and the metal frame 200 to be engraved is attached to the temporary support plate 300 by pasting. Optionally, the temporary support plate 300 may not be used, and the thick adhesive layer 301 may be directly used as the temporary support plate 300 to transport the engraved metal frame 200. Preferably, the temporary support plate 300, the adhesive layer 301 and the carrier plate 117 are consistent in shape and size.

[0117] Preferably, Figure 8a As shown, after the metal frame 200 is pasted on the temporary support plate 300, the connecting rod 203 is cut to separate the metal frame 200. Optionally, each connecting rod 203 connecting each metal unit is cut, so that each metal unit pasted on the temporary support plate 300 is separated from each other; it is also possible to cut the connecting rod 203 in a specific area to separate the metal frame 200 on the entire temporary support plate 300 into two parts, four parts, six parts, or any other number of parts. Preferably, the cutting line is along the center line of the connecting rod 203. The advantage of this method is that during the packaging process, it is often necessary to go through heating and cooling steps to separate an entire metal frame 200 into units with smaller areas, or directly separate them into metal units separated from each other, so that during the heating and cooling steps of the packaging, the metal frame 200 or metal units with smaller areas expand and contract independently of each other. Due to the small area, the degree of expansion and contraction of each unit or unit is small, making the packaging process easier to control and operate.

[0118] Preferably, Figure 8b As shown, after the metal frame 200 is pasted onto the temporary support plate 300, the connecting rod 203 is separated and removed from the metal frame 200, so that the metal units in the metal frame 200 are separated. Figure 8b In the embodiment, the connection pads 201 are independent of each other. Since the features on the metal frame can be independent of each other, board-level testing can be performed before cutting, which can greatly reduce testing costs and time.

[0119] like Fig. 9 As shown, a carrier 117 is provided, and the carrier 117 has a carrier front 1171 and a carrier back 1172. The shape of the carrier 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier 117 can be a small-sized wafer substrate, or a rectangular carrier of various sizes, especially a large size. The material of the carrier 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier 117 is a large-sized quadrilateral panel made of stainless steel.

[0120] The carrier 117 has a carrier front side 113 and a carrier back side 115 , and the carrier front side 113 is a plane.

[0121] The die 113 is bonded and fixed on the carrier 117 by using the adhesive layer 121 .

[0122] The adhesive layer 121 can be formed on the front side of the carrier 1171 by lamination, printing, spraying, coating, etc. In order to facilitate separation of the carrier 117 and the bare die 113 with plastic encapsulation completed on the back in the subsequent process, the adhesive layer 121 preferably uses an easily separable material, such as a thermally separable material.

[0123] The temporary support plate 300 is mounted with the side of the metal frame 200 facing the front side 1171 of the carrier. The surface area of ​​the temporary support plate 300 is the same as the surface area of ​​the carrier 117, and the shape is also the same. The two are aligned and contacted, and the metal frame 200 can be mounted on the adhesive layer 121. The temporary support plate 300 is then peeled off, and the adhesive layer 301 on the metal frame 200 is removed, and the mounting of the metal frame 200 is completed.

[0124] In this step, preferably, the metal frame 200 is aligned to the carrier 117 through alignment marks pre-formed on the carrier 117 and the metal frame 200 (the mark is not shown in the figure), and the metal frame 200 is adhered to the carrier 117 through the adhesive layer 301.

[0125] In addition, the metal foil or metal sheet can be attached to the temporary support plate 300 through the adhesive layer 301 on the temporary support plate 300, and then the metal foil or metal sheet can be etched into a desired pattern to form an engraved metal frame 200, and then the metal frame 200 can be transferred to the carrier 117.

[0126] The side of the metal frame 200 facing the carrier 117 is defined as the front side of the metal frame, and the side facing away from the carrier 117 is defined as the back side of the metal frame. The front side and back side of the metal structure, the front side and back side of the metal unit, and the front side and back side of the metal feature are also defined in the same way.

[0127] Fig.10 The embodiment of placing the die 113 on the carrier 117 in step S5 is shown.

[0128] Since the metal frame 200 has been pasted on the adhesive layer 121 on the front side 1171 of the carrier board, Fig.10 The metal frame 200 is embodied as a connection pad 201, so when the bare die 113 is continued to be pasted, it is necessary to ensure that the bare die 113 does not contact the metal frame 200. In the present disclosure, the bare die 113 is pasted in the empty space 202 of the metal frame 200, and one empty space 202 can be selected to correspond to one bare die 113 or one empty space 202 can correspond to multiple bare die 113. Preferably, a position mark for the arrangement of the bare die 113 is set on the carrier 117, and the mark can be formed on the carrier 117 by laser, mechanical engraving, etc. At the same time, an alignment mark is also set on the bare die 113 to aim and align with the pasting position on the carrier 117 when pasting. Fig.10 This is just an example picture. Fig.10 Only the bare chip 113 attached to the adhesive layer 121 of the carrier 117 is shown in the following manner: Figure 6a The bare chip 113 shown has the protective layer 107 and the protective layer opening; the bare chip attached to the adhesive layer 121 of the carrier 117 can also be Figure 6b The bare chip form with the wafer conductive layer 130, the protective layer 107 and the protective layer opening 109 shown in FIG. Figure 6c The bare chip shown in FIG. 1 has a wafer conductive layer 130 and a protective layer 107. Meanwhile, the metal frame 200 pasted on the adhesive layer 121 can also be as follows: Figure 8a The metal frame 200 shown is only cut but the connecting rods 203 are not removed, but the metal frame 200 with the connecting rods 203 intact may also be used.

[0129] like Fig.10 As shown, one metal unit corresponds to one bare die 113, the number of bare die 113 on the carrier 117 is the same as the number of metal units on the carrier 117, and the arrangement of the bare die 113 corresponds to the arrangement of the metal units on the carrier 117. The number and arrangement of the metal units are not limited to Fig.10 The method shown in the figure can be customized according to actual needs.

[0130] In addition, one metal unit may correspond to a plurality of bare chips 113, and the plurality of bare chips 113 are placed in predetermined spaces 202. In particular, the plurality of bare chips are plurality of bare chips with different functions, which are arranged in the metal unit on the carrier 117 according to the requirements of the actual product, and packaged. After the packaging is completed, the plurality of bare chips are cut into a plurality of packages; thus, a package includes a plurality of bare chips to form a multi-chip module (MCM), and the positions of the plurality of bare chips can be freely set according to the requirements of the actual product.

[0131] Figure 9-10 The installation sequence shown in the figure is to first install the metal frame 200 on the carrier 117 and then install the bare chip 113 on the carrier 117, but this is only exemplary and the bare chip 113 can also be installed on the carrier 117 first and then install the metal frame 200 on the carrier 117.

[0132] Step S6 , forming a plastic packaging layer 123 on the carrier 117 .

[0133] like Fig.11 As shown, the plastic layer 123 covers the entire carrier 117 and is used to encapsulate all the bare chips 113 and the metal frame 200. Fig.11 The connecting pad 201 is embodied in the figure to reconstruct a flat structure, so that after the carrier 117 is peeled off, the next packaging step can be continued on the reconstructed flat structure.

[0134] The side of the plastic encapsulation layer 123 in contact with the carrier front side 1171 or the adhesive layer 121 is defined as the plastic encapsulation layer front side 1231. The side of the plastic encapsulation layer 123 facing away from the carrier front side 1171 or the adhesive layer 121 is defined as the plastic encapsulation layer back side 1232.

[0135] Preferably, the front side 1231 of the plastic encapsulation layer and the back side 1232 of the plastic encapsulation layer are substantially flat and parallel to the front side 1171 of the carrier board.

[0136] The plastic layer 123 may be formed by slurry printing, injection molding, hot pressing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The plastic layer 123 may be formed by organic composite materials, resin composite materials, macromolecular composite materials, polymer composite materials, such as epoxy resin with fillers, ABF (Ajinomoto buildup film) or other polymers with suitable fillers.

[0137] In one embodiment, the plastic encapsulation layer 123 is formed by using an organic / inorganic composite material through compression molding.

[0138] Optionally, before forming the plastic encapsulation layer 123, some pre-treatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities on the surface of the bare chip 113 and the metal frame 200, so that the plastic encapsulation layer 123 can be more closely connected to the bare chip 113, the metal frame 200 and the carrier 117 without delamination or cracking.

[0139] Preferably, the thermal expansion coefficient of the plastic layer 123 is 3-10 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the plastic layer 123 is 5 ppm / K; in another preferred embodiment, the thermal expansion coefficient of the plastic layer 123 is 7 ppm / K; in yet another preferred embodiment, the thermal expansion coefficient of the plastic layer 123 is 10 ppm / K.

[0140] Preferably, the plastic encapsulation layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

[0141] The thermal expansion coefficient of the molding layer 123 is selected to be 3 to 10 ppm / K and is selected to have the same or similar thermal expansion coefficient as the protective layer 107. During the heating and cooling process of the molding process, the expansion and contraction degrees between the protective layer 107 and the molding layer 123 are kept consistent, and the two materials are not prone to generate interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the molding layer, the protective layer and the bare chip close, so that the interfaces of the molding layer 123, the protective layer 107 and the bare chip 113 are tightly bonded, avoiding the occurrence of interface layer separation.

[0142] During use, the packaged chip often needs to undergo hot and cold cycles. Since the thermal expansion coefficients of the protective layer 107, the plastic layer 123 and the bare chip 113 are similar, during the hot and cold cycles, the interface fatigue of the protective layer 107, the plastic layer 123 and the bare chip 113 is small, and it is not easy to have an interface gap between the protective layer 107, the plastic layer 123 and the bare chip 113, which increases the service life of the chip and the chip can be used in a wide range of fields.

[0143] The difference in thermal expansion coefficients between the bare chip 113 and the plastic layer 123 will also cause warping of the panel assembly after plastic packaging. Due to the warping phenomenon, it is difficult to locate the precise position of the bare chip 113 in the panel assembly in the subsequent conductive layer formation process, which has a great impact on the conductive layer formation process.

[0144] In particular, in the large panel packaging process, due to the large size of the panel, even a slight warping of the panel will cause a large size change in the position of the bare chips in the outer surrounding parts of the panel away from the center relative to before molding. Therefore, in the large panel packaging process, solving the warping problem becomes one of the keys to the entire process. The warping problem even limits the enlargement of the panel size and becomes a technical barrier in large-size panel packaging.

[0145] The thermal expansion coefficients of the protective layer 107 and the plastic layer 123 are limited to the range of 3 to 10 ppm / K, and preferably the plastic layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively avoid the warping of the panel assembly and realize the packaging process using large panels.

[0146] At the same time, during the molding process, the molding pressure will generate pressure on the back of the bare chip 113 toward the carrier 117. This pressure can easily press the bare chip 113 into the adhesive layer 121, so that the bare chip 113 is sunken into the adhesive layer 121 during the formation of the molding layer 123. After the molding layer 123 is formed, the bare chip 113 and the front side 1231 of the molding layer are not in the same plane, and the surface of the bare chip 113 protrudes beyond the front side 1231 of the molding layer to form a step-like structure. In the subsequent process of forming the panel-level conductive layer, the panel-level conductive layer will also have a step-like structure accordingly, making the packaging structure unstable.

[0147] When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the molding pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the formation of a step-like structure on the front side 1231 of the molding layer.

[0148] In order to expose the metal frame 200, the plastic layer 123 needs to be thinned, which can be done by mechanically grinding or polishing the front side 1231 of the plastic layer. The thickness of the plastic layer 123 is thinned to the back side of the metal frame 200, thereby exposing the surface features of the metal frame 200. Fig.12 As shown, when the thickness of the metal frame 200 is thicker than the bare die 113 , the plastic encapsulation layer can be further thinned to the back side of the bare die 113 , so that the back sides of the metal frame 200 and the bare die 113 are both exposed.

[0149] In step S7 , the carrier board 117 is peeled off to form the panel assembly 150 .

[0150] After the carrier 117 is peeled off, the protection layer 107 on the active surface 1131 of the die, the lower surface of the metal frame 200 and the front surface 1231 of the plastic packaging layer are exposed.

[0151] After the carrier 117 is separated, the structure of the plastic encapsulation layer 123 encapsulating the bare chip 113 and the metal frame 200 is defined as a panel assembly 150 .

[0152] Step S8 , forming a panel-level conductive layer and a dielectric layer 129 .

[0153] A panel-level conductive layer is formed on the surface of the protective layer 107, and the panel-level conductive layer is connected to the electrical connection point 103 on the active surface 1131 of the die through the wafer conductive layer 130 and / or the conductive filled through hole 124, and is connected to the metal frame 200. A dielectric layer 129 is formed on the panel-level conductive layer, and the dielectric layer 129 is used to cover and protect the panel-level conductive layer. The panel-level conductive layer and the dielectric layer 129 can be one layer or multiple layers.

[0154] like Fig.13 As shown, the panel-level conductive layer is embodied as a panel-level conductive trace 125 in the figure. Since the conductive filled via 124 has not been formed in the process flow shown in the figure, optionally, the conductive filled via 124 and the panel-level conductive trace 125 are formed in the same conductive layer forming step. The conductive filled via 124 and the panel-level conductive trace 125 are formed by a patterned conductive layer forming method. The conductive filled via 124 and the panel-level conductive trace 125 can be copper, gold, silver, tin, aluminum or other materials or a combination thereof, or can be other suitable conductive materials formed by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.

[0155] At least a portion of the panel-level conductive traces 125 are connected to the electrical connection points 103 on the die active surface 103 through the conductive filled vias 124 and to the connection pads 201 , and the electrical connection points 103 on the die active surface are led to the connection pads 201 through the panel-level conductive traces 125 and the conductive filled vias 124 .

[0156] Fig.13 The pattern traces of the panel-level conductive traces 125 are merely exemplary, and the pattern traces of the panel-level conductive traces 125 are connected according to a specific circuit design.

[0157] Optionally, the conductive filled vias 124 and the panel-level conductive traces 125 may also be formed in separate steps, where the conductive filled vias 124 are formed first and then the panel-level conductive traces 125 are formed.

[0158] When the conductive filled vias 124 have been formed in the previous step of applying a protective layer, the step of forming a panel-level conductive layer may be directly performed.

[0159] When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 is required.

[0160] like Fig.14 As shown, a dielectric layer 129 is formed on the panel-level conductive traces 125 .

[0161] The dielectric layer 129 is formed on the surface of the panel-level conductive layer by lamination, coating, spraying, printing, molding and other suitable methods.

[0162] The dielectric layer 129 can be BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, ABF (Ajinomoto Build up Film), silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, polymer matrix dielectric film, organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymer composite material, such as epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulation and structural properties. In a preferred embodiment, the dielectric layer 129 is ABF. The dielectric layer 129 plays the role of protecting the conductive layer and insulation.

[0163] like Fig.14 As shown, the height of the dielectric layer 129 is higher than the height of the panel-level conductive trace 125 , and the dielectric layer 129 completely encapsulates the panel-level conductive trace 125 .

[0164] Due to the presence of the protection layer 107 , the step of forming the panel-level conductive layer can be performed directly after the plastic encapsulation process is completed, avoiding the need to form an insulating layer first before performing the step of forming the panel-level conductive layer after the plastic encapsulation process is completed.

[0165] Fig.13 and Fig.14 The panel-level conductive layer and dielectric layer 129 shown in FIG. 1 has only one layer, but optionally, the panel-level conductive layer and dielectric layer can be multiple layers.

[0166] When the panel-level conductive layer and the dielectric layer are multiple layers, the steps of forming the multiple layers of the panel-level conductive layer and the dielectric layer are as follows:

[0167] Forming a first layer of panel-level conductive traces on the surface of the protective layer, and forming a first layer of panel-level conductive protrusions at electrical connection points of the first layer of panel-level conductive traces for connecting with the first layer of panel-level conductive traces and leading them out;

[0168] Forming a first dielectric layer on the first panel-level conductive traces and the first panel-level conductive protrusions to cover the first panel-level conductive traces and the first panel-level conductive protrusions and expose the surfaces of the first panel-level conductive protrusions;

[0169] A second panel-level conductive trace connected to the first panel-level conductive protrusion is formed on the surface of the first dielectric layer, and the second panel-level conductive trace is completely covered by the second dielectric layer.

[0170] At this point, a packaging structure having two panel-level conductive layers and a dielectric layer is formed.

[0171] By analogy, a packaging structure with multiple panel-level conductive layers and dielectric layers can be formed.

[0172] When the panel-level conductive layer and the dielectric layer are multiple layers, the steps of forming the multiple layers of the panel-level conductive layer and the dielectric layer may also be:

[0173] forming a first layer of panel-level conductive traces on a surface of the protective layer;

[0174] forming a first dielectric layer on the first panel-level conductive trace, wherein the thickness of the first dielectric layer is greater than the thickness of the first panel-level conductive trace to completely cover the first panel-level conductive trace;

[0175] Forming openings on the first dielectric layer by laser patterning or photolithography, wherein the openings are formed on electrical connection points of the first panel-level conductive traces to expose the electrical connection points of the first panel-level conductive traces;

[0176] filling the opening with a conductive material and forming a second layer of panel-level conductive traces on the first layer of dielectric layer and at corresponding locations of the filled openings;

[0177] A second dielectric layer is formed on the second panel-level conductive trace. The second dielectric layer is thicker than the second panel-level conductive trace. The second panel-level conductive trace is completely covered by the second dielectric layer.

[0178] At this point, a packaging structure having two panel-level conductive layers and a dielectric layer is formed.

[0179] By analogy, a packaging structure with multiple panel-level conductive layers and dielectric layers can be formed.

[0180] When each metal unit of the metal frame 200 corresponds to multiple bare chips 113, especially multiple bare chips with different functions, the package becomes a multi-chip package component with metal characteristics, and the pattern design of the panel-level conductive layer of the multiple bare chips is designed according to the electrical connection requirements of the actual product. Fig.29e shown.

[0181] In step S8, in the step of forming a panel-level conductive layer and a dielectric layer 129 on the surface of the protection layer 107 of the bare die 113, Fig.13 and Fig.14 It is shown that, using Figure 6a The bare die 113 shown in FIG. is packaged. It can be understood that the bare die 113 can also be packaged using Figure 6bThe bare chip shown in is packaged, and the protective layer opening 109 is filled with a conductive material to form a conductive filled through-hole 124. At least a portion of the conductive filled through-hole 124 is connected to the chip conductive trace 106, and the chip conductive trace 106 is led out of the protective layer 107 to form a panel-level conductive trace 125 on the surface of the protective layer 107. Preferably, the conductive filled through-hole 124 and the panel-level conductive trace 125 are formed in the same metal layer formation step. At least a portion of the panel-level conductive trace 125 is connected to at least a portion of the conductive filled through-hole 124, and is connected to at least a portion of the connection pad 201 of the metal frame 200. The electrical connection point 103 on the active surface 1131 of the bare chip is led to the connection pad 201 of the metal frame 200 through the chip conductive layer 130, the conductive filled through-hole 124 and the panel-level conductive trace 125, and then electrically connected to the outside world through the connection pad 201. It can be understood that it is also possible to use Figure 6c The bare chip shown in the figure is packaged, and a panel-level conductive trace 125 is formed on the surface of the protective layer 107. At least a portion of the panel-level conductive trace 125 is connected to the wafer conductive protrusion 111 and to at least a portion of the metal frame 200. The electrical connection point 103 on the active surface 1131 of the bare chip is led to the connection pad 201 of the metal frame 200 through the wafer conductive layer 130 and the panel-level conductive layer to achieve electrical connection with the outside world.

[0182] Step S9 , cutting to form a plurality of chips 500 .

[0183] like Fig.15 As shown, the packaged units are cut and separated to form packaged chips, which can be cut mechanically or by laser.

[0184] When the metal frame 200 is sealed as Figure 8a When the metal frame 200 shown includes connecting rods 203, it is necessary to cut around the periphery of the connecting rods 203 to remove the connecting rods 203 during cutting and separation, so that the packaged chip 500 formed after the package does not include the connecting rods, thereby making each metal feature in the metal unit of the metal frame 200 independent.

[0185] Preferably, before or after the cutting and separation step, a surface treatment layer 131 is formed on the back side 1132 of the bare chip and / or the exposed metal frame surface by electroplating, electroless electroplating or other suitable methods, such as nickel-palladium-gold plating (ENEPIG) or tin plating (Tin).

[0186] Optionally, the surface treatment layer 131 can also be configured to achieve back side grounding (backgrounding) of the chip 500, that is, the surface treatment layer 131 electrically connects the back side 1132 of the die and the connection pad 201 for specific back side grounding according to the specific design of the circuit (the connection pad for specific back side grounding is: the connection pad is connected to the electrical connection point of the back side grounding on the active surface of the die through a conductive structure).

[0187] The difference between Embodiment 2 of the present disclosure and Embodiment 1 is mainly the structure of the metal frame 200, and other identical parts are not repeated here. In this embodiment, only the parts different from Embodiment 1 are described.

[0188] Fig.16 The structure diagram of the metal frame 200 in the second embodiment of the present disclosure is shown. Based on the metal feature of the metal frame 200 in the first embodiment being the connection pad 201, in the second embodiment, the metal feature of the metal frame 200 also includes a heat dissipation structure for heat dissipation. Fig.16 It is embodied as a heat dissipation pad 207. The heat dissipation pad 207 can be as large as possible under conditions to improve the heat dissipation effect. Its shape is not limited to the rectangle as shown in the figure, but can also be a square or other shapes. The number of heat dissipation pads 207 is not limited to one, and can be two or more as needed. In order to prevent the heat dissipation pad 207 from separating from the metal frame 200, the heat dissipation pad 207 and the outer contour of the metal frame 200 retain one or more connecting rods 203 to ensure that the heat dissipation pad 207 is connected to the metal frame 200 during the transfer of the metal frame 200. If the metal is first fixed to the temporary support plate 300 and then the metal frame 200 is formed in the manner described in Example 1, it is not necessary to form the connecting rod 203, which is also applicable to the present embodiment.

[0189] When transferring the metal frame 200, the metal frame 200 may be transported using the temporary support plate 300 and / or the adhesive layer 301 in the manner described in Example 1. After the metal frame 200 is attached to the temporary support plate 300, the connecting rod 203 may be cut to separate the metal frame 200, or the connecting rod 203 may be separated and removed from the metal frame 200, thereby separating the metal units in the metal frame 200.

[0190] The steps for forming the protective layer in Example 2 are as follows: Figure 3a-3b, a protective layer 107 is applied on the active surface 1001 of the wafer; a protective layer opening 109 is formed on the surface of the protective layer 107. At least a portion of the protective layer opening 109 is formed at a position corresponding to the electrical connection point 103 on the active surface 1001 of the wafer and / or at a heat dissipation position on the active surface 1001 of the wafer, exposing the electrical connection point 103 and the heat dissipation position. The heat dissipation position may be at the electrical connection point 103, because there is often accumulated heat at the electrical connection point that needs to be dissipated. Figure 3b Only the heat dissipation position at the electrical connection point 103 is shown, however, Figure 3b This is merely an example, and the heat dissipation position may also be at other positions where heat dissipation is required except for the electrical connection point 103 .

[0191] Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 and / or heat dissipation positions on the wafer active surface 1001 .

[0192] Optionally, each of the protection layer openings 109 in at least a portion of the protection layer openings 109 corresponds to a plurality of electrical connection points 103 and / or heat dissipation positions.

[0193] Optionally, at least a portion of the electrical connection points 103 and / or the heat dissipation positions correspond to a plurality of protection layer openings 109 .

[0194] Optionally, a conductive material is filled in the protective layer opening 109 to form a conductive filled through hole 124 . This step may also be performed after the plastic packaging process.

[0195] The step of forming the opening of the protection layer may also be performed after the molding process.

[0196] Another optional process step for applying the protective layer 107 on the active surface 1001 of the wafer is shown in Figure 4a-4c :

[0197] like Figure 4a As shown in FIG. 1 , a wafer conductive layer 130 is formed on the wafer active surface 1001. The wafer conductive layer 130 is formed on the wafer active surface 1001. Figure 4a embodied as wafer conductive traces 106.

[0198] At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active surface 1001.

[0199] Optionally, the wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active surface 1001 .

[0200] Optionally, the wafer conductive traces 106 lead out at least a portion of the electrical connection points 103 on the wafer active surface 1001 separately.

[0201] Although not shown in the figure, it can be understood that the wafer conductive traces 106 lead out a portion of the electrical connection points 103 on the wafer active surface 1001 separately and interconnect and lead out another portion of the electrical connection points 103 on the wafer active surface 1001.

[0202] At least a portion of the wafer conductive traces 106 correspond to at least a portion of the heat sink locations on the wafer active surface 1001 .

[0203] Figure 4a Only the heat dissipation position at the electrical connection point 103 is shown, however, Figure 4a This is merely an example, and the heat dissipation position may also be at other positions where heat dissipation is required except for the electrical connection point 103 .

[0204] like Figure 4b As shown, a protective layer 107 is applied over the wafer active surface 1001 and the wafer conductive traces 106 .

[0205] like Figure 4c As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0206] At least a portion of the protection layer openings 109 are located corresponding to the wafer conductive traces 106 , and the wafer conductive traces 106 are exposed through the protection layer openings 109 .

[0207] Optionally, a conductive material is filled in the protective layer opening 109 to form a conductive filled through hole 124 . This step may also be performed after the plastic encapsulation process.

[0208] The step of forming the opening of the protection layer may also be performed after the molding process.

[0209] Another optional process step of applying the protective layer 107 on the active surface 1001 of the wafer is shown in Figure 5a to Figure 5c .

[0210] A wafer conductive layer 130 is formed on the wafer active surface 1001 , and the wafer conductive layer 130 is a wafer conductive trace 106 and / or a wafer conductive protrusion 111 .

[0211] like Figure 5a As shown, wafer conductive traces 106 are formed on the wafer active surface 1001 .

[0212] At least a portion of the wafer conductive traces 106 are connected to at least a portion of the electrical connection points 103 on the wafer active surface 1001.

[0213] Optionally, the wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 in at least a portion of the wafer active surface 1001 .

[0214] Optionally, the wafer conductive traces 106 lead out at least a portion of the electrical connection points 103 on the wafer active surface 1001 separately.

[0215] Although not shown in the figure, it can be understood that the wafer conductive traces 106 lead out a portion of the electrical connection points 103 on the wafer active surface 1001 separately and interconnect and lead out another portion of the electrical connection points 103 on the wafer active surface 1001.

[0216] At least a portion of the wafer conductive traces 106 correspond to at least a portion of the heat sink locations on the wafer active surface 1001 .

[0217] Figure 5a Only the heat dissipation position at the electrical connection point 103 is shown, however, Figure 5a For illustrative purposes only,

[0218] like Figure 5b As shown, wafer conductive studs 111 are formed on pads or connection points of wafer conductive traces 106 .

[0219] like Figure 5c As shown, a protective layer 107 is applied over the conductive layer 130 of the wafer.

[0220] The conductive layer, the forming method and material of the protective layer in the protective layer forming step in Example 2, the shape and forming method of the protective layer opening, etc. are the same as those in Example 1 and will not be repeated here.

[0221] The wafer 100 to which the protective layer is applied according to the above method is cut into bare chips 113 .

[0222] Fig.17 FIG. 1 shows that a bare chip 113 and a metal frame 200 are arranged on a carrier board 117, and the steps of the arrangement are similar to those described in the method of Embodiment 1. Fig.17 The connecting rod 203 of the metal frame 200 is cut to separate the metal frame 200 into several parts, but the connecting rod 203 of the metal frame 200 is not removed. Optionally, the connecting rod 203 can also be removed from the metal frame 200. Fig.17 The bare die 113 shown in FIG. Figure 6b The bare chip 113 includes the wafer conductive layer 130 and the protective layer opening 109. Fig.17 For example only, the bare chips 113 arranged on the carrier 117 may also be in the form of Figure 6a or Figure 6c Shown in bare die form.

[0223] Fig.18It is shown that a plastic encapsulation layer 123 is formed on the carrier 117 to encapsulate all the bare chips 113 and the metal frame 200, and a flat structure is reconstructed, and then the plastic encapsulation layer 123 is thinned to expose the metal frame 200, and the carrier 117 is peeled off to form a panel assembly 150. The method and steps are similar to those described in Example 1.

[0224] Fig.19 The formation of panel level conductive and dielectric layers 129 is shown.

[0225] A panel-level conductive layer is formed on the surface of the protective layer 107. Fig.19 In the figure, the panel-level conductive layer is embodied as a panel-level conductive trace 125. Since the conductive filled through hole 124 has not been formed in the process flow shown in the figure, it is necessary to use a conductive filling material to fill the protective layer opening 109 to form a conductive filled through hole 124 connected to the chip conductive trace 106. Optionally, the conductive filled through hole 124 and the panel-level conductive trace 125 are formed in the same conductive layer formation step.

[0226] At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the chip conductive traces 106 through the conductive filled through-holes 124 to be connected to the electrical connection points 1131 on the active surface 1131 of the die, and to the connection pads 201 in the metal unit. The electrical connection points 103 on the active surface of the die are connected to the connection pads 201 through the panel-level conductive traces 125, the conductive filled through-holes 124 and the chip conductive layer 130.

[0227] At least a portion of the panel-level conductive traces 125 are connected to at least a portion of the wafer conductive traces 106 through the conductive filled vias 124, thereby being connected to the heat dissipation position on the die active surface 1131, and connected to the heat dissipation pad 207 in the metal unit. Since the metal conductive material is also a good conductor of heat, the heat can be transferred to the heat dissipation pad 207 through the wafer conductive layer 130, the conductive filled vias 124 and the panel-level conductive layer, and then dissipated to the outside through the heat dissipation pad 207. Of course, it is understandable that the heat dissipation position can also be set to only a thermal conductive material, and the heat can be transferred to the heat dissipation pad 207 using the thermal conductive material.

[0228] Fig.19 The pattern traces of the panel-level conductive traces 125 are merely exemplary, and the pattern traces of the panel-level conductive traces 125 are connected according to a specific circuit design.

[0229] When the conductive filled vias 124 have been formed in the previous step of applying a protective layer, the step of forming a panel-level conductive layer may be directly performed.

[0230] When the protective layer opening 109 has not been formed in the previous step of applying the protective layer, a step of forming the protective layer opening 109 is required.

[0231] Next, a dielectric layer 129 is formed on the panel-level conductive layer.

[0232] The panel-level conductive layer and the dielectric layer 129 can be single-layer or multi-layer.

[0233] The materials and formation methods of the panel-level conductive layer and the dielectric layer 129 are similar to those in Embodiment 1.

[0234] Fig.19 It is shown that in the formation steps of the panel-level conductive layer and the dielectric layer 129, the die 113 shown in Figure 6b is used for encapsulation. It can be understood that the die shown in Figure 6a can also be used for encapsulation. The conductive filling vias 124 that are formed by filling the protective layer opening 109 with a conductive material and are connected to the electrical connection points 103 and / or the heat dissipation positions; a panel-level conductive trace 125 is formed on the surface of the protective layer 107. At least a part of the panel-level conductive trace 125 is connected to the conductive filling via 124 corresponding to the electrical connection point 103 and is connected to at least a part of the connection pad 201 of the metal frame 200. The electrical connection point 103 on the active surface 1131 of the die is led to the connection pad 201 of the metal frame 200 through the conductive filling via 124 and the panel-level conductive trace 125, and then is electrically connected to the outside through the connection pad 201. At least a part of the panel-level conductive trace 125 is connected to at least a part of the conductive filling via 124 corresponding to the heat dissipation position. The heat dissipation position can be the position of the electrical connection point 103 or other positions other than the electrical connection point 103, and is connected to at least a part of the heat dissipation pad 207 of the metal frame 200, and the heat is dissipated to the outside through the heat dissipation pad 207. It can be understood that the die shown in Figure 6c can also be used for encapsulation.

[0235] As Fig. 20 shown, the encapsulated monomers are cut and separated to form the encapsulated completed chip, and mechanical or laser cutting can be used.

[0236] Fig. 20 The metal frame 200 in includes a connecting rod 203. When cutting and separating, cutting needs to be performed around the connecting rod 203 to remove the connecting rod 203, so that the encapsulated completed encapsulated chip 500 does not include the connecting rod, so that each metal feature in the metal unit of the metal frame 200 is independent.

[0237] Preferably, before or after the cutting and separating step, a surface treatment layer 131 is optionally formed on the back surface 1132 of the die and / or the exposed surface of the metal frame by electroplating, electroless plating or other suitable methods. For example, electroless nickel immersion gold plating (ENEPIG), tin plating (Tin) is used.

[0238] Optionally, the surface treatment layer 131 can also be configured to achieve back side grounding (backgrounding) of the chip 500, that is, the surface treatment layer 131 electrically connects the back side 1132 of the die and the connection pad 201 for specific back side grounding according to the specific design of the circuit (the connection pad for specific back side grounding is: the connection pad is connected to the electrical connection point of the back side grounding on the active surface of the die through a conductive structure).

[0239] Compared with the solution of the embodiment 1, the solution of the embodiment 2 is provided with a heat dissipation structure heat dissipation pad 207 , so that the heat generated during the use of the chip can be dissipated in time with the help of the heat dissipation pad 207 .

[0240] The difference between Example 3 of the present disclosure and Example 1 is mainly the structure of the metal frame 200, and other identical parts are not repeated here. In this embodiment, only the parts different from Example 1 are described.

[0241] The steps for forming the protective layer 107 are similar to those in Embodiment 1 and will not be described again.

[0242] Fig.21 The structure diagram of the metal frame 200 in the third embodiment of the present disclosure is shown. Based on the metal feature of the metal frame 200 in the first embodiment being the connection pad 201, in the third embodiment, the metal feature of the metal frame 200 also includes a heat dissipation structure for heat dissipation. Fig.21 The back heat sink 205 is shown in the figure. Although not shown in the figure, the heat dissipation structure can also be embodied as a back heat sink plus a heat dissipation pad. Fig.21 As shown, the back heat sink 205 is connected to the metal frame 200 as a whole by the connecting rod 203 to ensure that the back heat sink 205 is connected to the metal frame 200 during the transfer of the metal frame 200. The back heat sink 205 is formed by half-etching (or stamping) the metal, which can also be understood as thinning a part from the lower surface of the metal. Since the upper surface, that is, the back heat sink 507, is retained during the etching (or stamping) process, the lower surface is removed to form a blank area, which is the vacancy 202 for placing the bare die 113. The connecting rod 203 connecting the back heat sink 205 and the metal frame 200 has not been half-etched (or stamped), and its thickness is the same as that of the metal sheet. In addition to connecting the back heat sink 205 and the metal frame 200, the connecting rod 203 can also support the back heat dissipation surface 205 when the back heat sink 205 is applied to the back side 1132 of the bare die, so that it remains horizontal and is not easy to tilt. Fig.212, but the optional number can also be 4, that is, the four corners of the back heat sink 205 are connected to the connecting rods 203, or any other number. When the die 113 is accommodated in the empty space 202, the back side 1002 of the die is in contact with the back heat sink 205 for heat dissipation.

[0243] Fig. 22 It shows that the bare chip 113 is arranged on the carrier 117, and the thermal conductive material 209 is applied to the back side 1132 of the bare chip. The bare chip 113 is connected to the back heat sink through the thermal conductive material 209. The thermal conductive material 209 is preferably a liquid substance or a paste, which reduces the interface resistance of heat transfer.

[0244] Fig.23 The metal frame 200 is bonded to the carrier 117, and the back side 1132 of the bare chip is connected to the back side heat sink 205 through the thermal conductive material 209. The heat generated by the chip formed after packaging during use is dissipated to the outside through the thermal conductive material 209 and the back side heat sink 205. The process of applying the metal frame 200 to the carrier 117 can also be transferred through a temporary support plate as in Example 1.

[0245] Fig.24 The steps of applying the plastic layer 123 and forming the panel-level conductive layer and the dielectric layer 129 are shown. The steps are similar to those described in Example 1 and will not be repeated here.

[0246] Optionally, according to the specific design of the circuit, a conductive structure can be used to Fig.24 It is embodied as a wafer-level conductive layer and a panel-level conductive layer, electrically connecting the electrical connection point 103 of the back grounding on the active surface of the die and the back heat sink 20 to realize back grounding using the back heat sink 205.

[0247] Fig.25 It shows the process of cutting and separating the packaged units to form packaged chips.

[0248] Preferably, before or after the cutting and separation step, a surface treatment layer 131 is formed on the back side 1132 of the bare chip and / or the exposed metal frame surface by electroplating, electroless electroplating or other suitable methods, such as nickel-palladium-gold plating (ENEPIG) or tin plating (Tin).

[0249] When the conductive structure is not used to realize the back grounding of the chip, the surface treatment layer 131 can optionally be configured to realize the back grounding of the chip 500, that is, the surface treatment layer 131 electrically connects the back heat sink 205 and the connection pad 201 for the specific connection back grounding according to the specific design of the circuit (the connection pad for the specific connection back grounding is: the connection pad connected to the electrical connection point of the back grounding on the active surface of the die through the conductive structure). At this time, the back heat sink 205 is applied to the back of the die through the thermal conductive material 209, and the thermal conductive material 209 is a conductive material, such as a metal thermal conductive glue.

[0250] The main difference between Example 4 of the present disclosure and Example 1 is that a metal layer is formed on the back side of the chip before the molding step. Other identical parts are not described in detail. In this embodiment, only the parts different from Example 1 are described.

[0251] Fig.26 It is shown that a metal layer 210 is formed on the back side 1002 of the chip 100 in Example 4 of the present disclosure. The metal layer 210 can optionally be one or more layers of aluminum, tin, nickel, gold, silver, lead, bismuth, copper, and combinations thereof, preferably copper, and is formed by electroplating, electroless plating, sputtering or other suitable methods.

[0252] A protective layer is formed on the active surface 1001 of the wafer 100 . The steps for forming the protective layer 107 are similar to those in Embodiment 1 and are not described again. The wafer 100 formed with the metal layer 210 and the protective layer 107 is cut and separated into bare chips 113 having the metal layer 210 and the protective layer 107 .

[0253] Optionally, the step of forming the metal layer 210 is performed after the step of forming the protection layer 107 or the step of cutting and separating.

[0254] Next, the bare chip 113 and the metal frame 200 are arranged on the carrier 117 , and a plastic encapsulation layer 123 is formed on the carrier 117 .

[0255] Fig. 27 It shows the formation of a plastic encapsulation layer 123 for encapsulating the bare chip 113 and the metal frame 200 on the carrier 117, and the formation of a panel-level conductive layer and a dielectric layer 129. The steps are similar to those described in Example 1 and will not be repeated here. Fig. 27 This is just an example picture. Fig. 27 Only the bare die 113 is shown in the form of Figure 6a The die 113 shown has a protective layer 107 and a protective layer opening; the die 113 may also be Figure 6b The bare chip form having the wafer conductive layer 130, the protective layer 107 and the protective layer opening 109 shown in FIG. can also be as shown in FIG. Figure 6c The bare die shown in FIG. 1 has a wafer conductive layer 130 and a protective layer 107. Meanwhile, the metal frame 200 can also be a metal frame with a heat dissipation pad 207. The metal layer surface of the bare die back side 1132 and the metal feature back side are exposed from the back side of the plastic layer by thinning the plastic layer.

[0256] Preferably, according to the design, the metal layer on the back side 1132 of the die and at least one metal feature are electrically connected through a conductive material, and the material can be a conductive glue 211. At this time, the metal layer on the back side 1132 of the die and the entire metal frame are in an electrically connected state. In the next step, when the surface treatment layer is formed by electroplating, the metal layer and the metal frame can form an electrical connection path for current conduction, so that the surface treatment layer can be formed on the surface of the metal layer and the back side of the metal frame without a seed layer. In this case, the connecting rod 203 should be retained in the metal frame.

[0257] In some embodiments, the conductive adhesive 211 can also be configured to achieve back side grounding (backgrounding) of the chip 500, that is, the conductive adhesive 211 electrically connects the metal layer 210 on the back side of the die and the connection pad 201 for specific back side grounding according to the specific design of the circuit (the connection pad for specific back side grounding is: the connection pad is connected to the electrical connection point for back side grounding on the active surface of the die through the conductive structure).

[0258] like Fig.28 As shown, the packaged units are cut and separated to form packaged chips.

[0259] Preferably, before or after the cutting and separation step, a surface treatment layer 131 may be formed on the back side 1132 of the bare die and / or the exposed metal frame surface by electroplating, electroless electroplating or other suitable methods. For example, nickel-palladium-gold plating (ENEPIG) or tin plating (Tin) may be used. When the surface treatment layer 131 is formed by electroplating, the metal layer on the back side of the bare die and the metal frame are electrically connected as a whole due to the presence of the conductive adhesive 211, forming a whole body in which the electroplating current is conducted during electroplating, so the electroplating step can be directly performed without forming a seed layer.

[0260] Compared with the solution of the embodiment 1, the solution of the embodiment 4 adds a metal layer 210 on the back of the bare chip 113. The metal layer can enhance the heat dissipation so that the heat generated during the use of the chip can be dissipated in time; and combined with the conductive glue 211, the step of forming the surface treatment layer is simpler.

[0261] According to another aspect of the present disclosure, a chip structure is further provided. The structure is preferably manufactured by the method of the present disclosure described above, but is not limited to the above method.

[0262] Fig.29a ,29b , 29c, 29d, and 29e are schematic diagrams of chip structures obtained according to the packaging method provided by the exemplary embodiment of the present disclosure. As shown in the figure, a chip 500 includes: at least one bare die 113; a protective layer 107; a metal unit, the metal unit includes at least one metal feature; a plastic encapsulation layer 123, which is used to encapsulate the bare die 113 and the metal unit; wherein the chip structure is connected to an external circuit through at least one metal feature.

[0263] In some embodiments, the chip 500 further includes a conductive structure, and at least one metal feature on the metal unit is connected to the die 113 via the conductive structure. In some embodiments, the metal feature includes a connection structure and / or a heat dissipation structure.

[0264] Specifically, Fig.29a As shown, the metal feature is a connection structure, and the connection structure is embodied as a connection pad 201 . The chip 500 is connected to an external circuit via at least one connection pad 201 .

[0265] Fig.29a As shown in the figure, the conductive structure includes a conductive filled through hole 124 and a panel-level conductive layer, which is embodied as a panel-level conductive trace 125 in the figure. The panel-level conductive layer can also be a panel-level conductive trace 125 and a panel-level conductive boss. The panel-level conductive layer can be a single layer as shown in the figure, or it can be multiple layers; the conductive filled through hole 124 is formed by filling the opening of the protective layer with a conductive material, and at least a portion of the conductive filled through hole 124 is connected to the electrical connection point 103; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front side 1231 of the plastic sealing layer, at least a portion of the panel-level conductive layer is connected to the conductive filled through hole 124 and to the connection pad 201, and the surface of the protective layer 107, the front side 1231 of the plastic sealing layer and the front side of the connection pad 201 are flush.

[0266] In some embodiments, the conductive filled via 124 has a conductive filled via lower surface and a conductive filled via upper surface, and the area ratio of the conductive filled via lower surface to the conductive filled via upper surface is 60%-90%.

[0267] In some embodiments, there is a gap between the lower surface of the conductive filled via and the insulating layer 105 . Preferably, the lower surface of the conductive filled via is located near the center of the electrical connection point 103 .

[0268] In some embodiments, a conductive covering layer is formed on the electrical connection point 103 .

[0269] Fig.29a It is merely exemplary, and the conductive structure may also include a wafer conductive layer 130 , conductive filled vias 124 , and a panel-level conductive layer. The conductive structure may also include a wafer conductive layer 130 and a panel-level conductive layer.

[0270] The back side 1132 of the bare die and the back side of the metal unit, specifically the back side of the connection pad, are exposed from the back side 1232 of the plastic encapsulation layer, and the portion exposed from the back side 1232 of the plastic encapsulation layer has a surface treatment layer 131. Optionally, the surface treatment layer 131 can also be configured to achieve back side grounding (backgrounding) of the chip 500, that is, the surface treatment layer 131 electrically connects the back side 1132 of the bare die and the connection pad 201 for specific back side grounding according to the specific design of the circuit (the connection pad for specific back side grounding is: the connection pad is connected to the electrical connection point for back side grounding on the active surface of the bare die through the conductive structure).

[0271] The chip 500 further includes a dielectric layer 129 covering the panel-level conductive layer. The outermost dielectric layer 129 completely covers the panel-level conductive layer.

[0272] like Fig.29b As shown, the metal features are a connection structure and a heat dissipation structure. The connection structure is embodied as a connection pad 201 , and the chip 500 is connected to an external circuit via at least one connection pad 201 ; the heat dissipation structure is embodied as a heat dissipation pad 207 .

[0273] Fig.29b As shown in the figure, the conductive structure includes a chip conductive layer 130, which is embodied as a chip conductive trace 106, a conductive filled through-hole 124 and a panel-level conductive layer. The panel-level conductive layer is embodied as a panel-level conductive trace 125 in the figure. The panel-level conductive layer can also be a panel-level conductive trace 125 and a panel-level conductive protrusion. The panel-level conductive layer can be a single layer as shown in the figure, or it can be multiple layers; at least a portion of the chip conductive layer 130 is connected to the electrical connection point 103 and / or the heat dissipation position; the conductive filled through-hole 124 is formed by filling the protective layer opening 109 with a conductive material; at least a portion of the conductive filled through-hole 124 is connected to the chip conductive layer; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front side 1231 of the plastic sealing layer, at least a portion of the panel-level conductive layer is connected to the conductive filled through-hole 124 and to the metal unit, and the surface of the protective layer 107, the front side 1231 of the plastic sealing layer and the front side of the metal unit are flush.

[0274] In some embodiments, at least a portion of the wafer conductive layer 130 interconnects and leads out a plurality of electrical connection points 103 . In other embodiments, at least a portion of the wafer conductive layer 130 leads out the electrical connection points 103 individually.

[0275] Optionally, the contact area of ​​a single contact region between the wafer conductive layer 130 and the electrical connection point 103 is smaller than the contact area of ​​a single contact region between the wafer conductive layer 130 and the conductive filled via 124 .

[0276] The conductive filled via has a conductive filled via lower surface and a conductive filled via upper surface. Optionally, the area of ​​the conductive filled via lower surface is smaller than the area of ​​the conductive filled via upper surface.

[0277] Fig.29b It is merely exemplary, and the conductive structure may also include the conductive filled via 124 and the panel-level conductive layer; the conductive structure may also include the wafer conductive layer 130 and the panel-level conductive layer.

[0278] The back side 1132 of the bare die and the back side of the metal unit, specifically the back side of the connection pad and the back side of the heat dissipation pad, are exposed from the back side 1232 of the plastic encapsulation layer, and the portion exposed from the back side 1232 of the plastic encapsulation layer has a surface treatment layer 131. Optionally, the surface treatment layer 131 can also be configured to achieve back grounding of the chip 500, that is, the surface treatment layer 131 electrically connects the back side 1132 of the bare die and the connection pad 201 for the specific back grounding connection according to the specific design of the circuit (the connection pad for the specific back grounding connection is: the connection pad is connected to the electrical connection point for the back grounding on the active surface of the bare die through the conductive structure).

[0279] The chip 500 further includes a dielectric layer 129 covering the panel-level conductive layer. The outermost dielectric layer 129 completely covers the panel-level conductive layer.

[0280] like Fig.29c As shown, the metal features are connection structures and heat dissipation structures, the connection structure is embodied as connection pads 201, and the heat dissipation structure is embodied as back heat sink 205. Optionally, back heat sink 205 is applied to the back of the die through thermal conductive material 209. The chip 500 is connected to an external circuit through at least one connection pad 201. In some embodiments, the heat dissipation structure can be a heat dissipation pad 207 and a back heat sink 205.

[0281] Fig.29c As shown in the figure, the conductive structure includes a chip conductive layer 130 and a panel-level conductive layer, which is embodied as a panel-level conductive trace 125 in the figure. The panel-level conductive layer can also be a panel-level conductive trace 125 and a panel-level conductive boss. The panel-level conductive layer can be a single layer as shown in the figure, or it can be multiple layers; the chip conductive layer includes a chip conductive trace 106 and a chip conductive boss 111; at least a portion of the chip conductive trace 106 is connected to the electrical connection point 103 and / or the heat dissipation position; at least a portion of the chip conductive boss 111 is formed on the chip conductive trace 106; the panel-level conductive layer is formed on the surface of the protective layer 107 and the front side 1231 of the plastic sealing layer, at least a portion of the panel-level conductive layer is connected to the chip conductive boss 111 and to the metal unit, and the surface of the protective layer 107, the front side 1231 of the plastic sealing layer and the front side of the metal unit are flush.

[0282] In some embodiments, at least a portion of the wafer conductive traces 106 lead out the electrical connection points 103 individually; in other embodiments, at least a portion of the wafer conductive traces 106 interconnect and lead out a plurality of electrical connection points 103 .

[0283] Optionally, the wafer conductive layer is a wafer conductive protrusion 111, and at least a portion of the wafer conductive protrusion is connected to the electrical connection point 103 and / or the heat dissipation position.

[0284] Fig.29c It is merely exemplary, and the conductive structure may also include a conductive filled via 124 and a panel-level conductive layer, and the conductive structure may also include a wafer conductive layer 130 , a conductive filled via 124 and a panel-level conductive layer.

[0285] Optionally, according to the specific design of the circuit, a conductive structure may be used to electrically connect the back-side grounding electrical connection point 103 on the active surface of the die and the back heat sink 20 to achieve back-side grounding using the back heat sink 205 .

[0286] The back side 1132 of the bare chip and the back side of the metal unit, specifically the back side of the back side heat sink 205, are exposed from the back side 1232 of the plastic layer, and the portion exposed from the back side 1232 of the plastic layer has a surface treatment layer 131. When the conductive structure is not used to realize the back side grounding of the chip, optionally, the surface treatment layer 131 can also be configured to realize the back side grounding of the chip 500, that is, the surface treatment layer 131 electrically connects the back side heat sink 205 and the connection pad 201 for the specific connection back side grounding according to the specific design of the circuit (the connection pad for the specific connection back side grounding is: the connection pad connected by the conductive structure and the electrical connection point of the back side grounding on the active surface of the bare chip). At this time, the back side heat sink 205 is applied to the back side of the bare chip through the thermal conductive material 209, and the thermal conductive material 209 is a conductive material, such as a metal thermal conductive glue.

[0287] The chip 500 further includes a dielectric layer 129 covering the panel-level conductive layer. The outermost dielectric layer 129 completely covers the panel-level conductive layer.

[0288] According to e.g. Fig.29a and Fig.29b In the structure shown in , optionally, the back side 1132 of the bare die may also have a metal layer 210, and the surface of the metal layer 210 is exposed from the back side 1232 of the plastic layer. The metal feature has a metal feature back side, and the metal feature back side is exposed from the back side 1232 of the plastic layer. Preferably, the surface of the metal layer 201 and the back side of at least one metal feature are connected by a conductive adhesive 211.

[0289] In some embodiments, the conductive adhesive 211 can also be configured to achieve back side grounding (backgrounding) of the chip 500, that is, the conductive adhesive 211 electrically connects the metal layer 210 on the back side of the die and the connection pad 201 for specific back side grounding according to the specific design of the circuit (the connection pad for specific back side grounding is: the connection pad is connected to the electrical connection point for back side grounding on the active surface of the die through the conductive structure).

[0290] Some embodiments of the packaging structure having the metal layer 210 and the conductive adhesive 211 are as follows: Fig.29d shown.

[0291] According to e.g. Fig.29a , Fig.29b and Fig.29c In the structure shown in , optionally, the chip structure has multiple bare chips 113. Preferably, the multiple bare chips 113 have different functions, and the multiple bare chips 113 are electrically connected according to the product design. An embodiment of the package structure with multiple bare chips 113 is as follows: Fig.29e shown.

[0292] In the chip structure, preferably, the Young's modulus of the protective layer 107 is any of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

[0293] The protective layer 107 is soft, has good flexibility and elasticity, and has sufficient support for the panel conductive layer formed on its surface, and is particularly suitable for packaging thin bare chips with large electric flux.

[0294] In some embodiments, the material of the protective layer 107 is an organic / inorganic composite material. Preferably, the organic / inorganic composite material with inorganic particles added to the organic material can modify the material properties of the organic material, so that the material has the characteristics of both organic and inorganic materials.

[0295] In some embodiments, the thickness of the protective layer 107 is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm. This thickness range ensures that the protective layer 107 can provide sufficient cushioning and support.

[0296] In some embodiments, the thermal expansion coefficient of the protection layer 107 is any of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0297] In some embodiments, the thermal expansion coefficient of the plastic layer 123 is any one of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0298] In some embodiments, the protective layer 107 and the plastic layer 123 have the same or similar thermal expansion coefficients, so as to avoid the accumulation of interface fatigue at the interface between the protective layer 107, the plastic layer 123 and the bare chip 113, so that the packaged chip has durability and the service life of the chip is extended.

[0299] Fig.30 FIG. 5 is an exemplary schematic diagram of the chip 500 when in use. During use, the chip 500 is connected to the circuit board or substrate 400 through at least one metal feature, which is shown as a connection pad 201 in the figure.

[0300] The chip structure in the present disclosure can replace the wire bonding structure. Compared with the wire bonding packaging structure, the present disclosure has a simple packaging process, eliminates the mutual interference of signals between the wires in the wire bonding structure, and eliminates the noise caused by the vibration of the wires when the chip is working. In addition, the connection structure is used to replace the wire structure, which is more suitable for chip packaging with large current flux.

[0301] The specific embodiments described above are intended to further illustrate the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the inventive concept of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A chip structure, It is characterized in that include: at least one bare die including a wafer active surface, the wafer active surface including an electrical connection point and an insulating layer, the insulating layer having a top surface remote from the wafer active surface; A wafer conductive layer, formed on the wafer active surface and electrically connected to the electrical connection point; A protective layer is formed on the wafer conductive layer, the protective layer is a single-layer structure and has an upper surface of the protective layer away from the wafer active surface and a lower surface of the protective layer facing the wafer active surface, the lower surface of the protective layer contacts the wafer active surface; A panel-level conductive layer is formed on the upper surface of the protective layer, wherein the panel-level conductive layer contacts the upper surface of the protective layer and is electrically connected to the wafer conductive layer; a metal unit, the metal unit comprising at least one metal feature; A plastic encapsulation layer, used to encapsulate the bare chip and the metal unit, wherein the plastic encapsulation layer has a front surface of the plastic encapsulation layer located on the same side as the active surface of the wafer, and the front surface of the plastic encapsulation layer is higher than the top surface of the insulating layer; a dielectric layer formed on the panel-level conductive layer; The chip structure is connected to an external circuit via at least one metal feature.

2. The chip structure according to claim 1, It is characterized in that The wafer conductive layer has a conductive filling through hole on the wafer active surface, the conductive filling through hole is formed by filling the protective layer opening in the protective layer with a conductive material, and the conductive filling through hole is directly connected to the electrical connection point of the wafer active surface.

3. The chip structure according to claim 1, It is characterized in that The wafer conductive layer has a wafer conductive protrusion on the wafer active surface, and the wafer conductive protrusion is directly connected to the electrical connection point of the wafer active surface.

4. The chip structure according to claim 1, It is characterized in that The chip conductive layer has a chip conductive trace on the active surface of the chip, and a conductive filled through-hole is formed on the pad or connection point of the chip conductive trace, wherein the conductive filled through-hole is formed by filling the protective layer opening in the protective layer with a conductive material, and the chip conductive trace is directly connected to the electrical connection point on the active surface of the chip.

5. The chip structure according to claim 1, It is characterized in that The wafer conductive layer has a wafer conductive trace on the wafer active surface, and a wafer conductive protrusion formed on a pad or a connection point of the wafer conductive trace, wherein the wafer conductive trace is directly connected to the electrical connection point on the wafer active surface.

6. The chip structure according to claim 1, It is characterized in that At least one metal feature on the metal unit is connected to the die through the wafer-level conductive layer and the panel-level conductive layer.

7. The chip structure according to claim 1, It is characterized in that The upper surface of the protection layer, the front surface of the plastic sealing layer and the front surface of the metal unit are flush.

8. The chip structure according to any one of claims 1 to 7, It is characterized in that The metal feature includes a connection structure and / or a heat dissipation structure; the connection structure includes a connection pad; and the heat dissipation structure includes a heat dissipation pad.

9. The chip structure according to claim 8, It is characterized in that The heat dissipation structure further comprises a back heat sink, which is applied to the back side of the die through a thermal conductive material.

10. The chip structure according to any one of claims 1 to 7, It is characterized in that A metal layer is applied on the back side of the die, and a surface of the metal layer is exposed from the back side of the plastic packaging layer.

11. The chip structure according to claim 10, It is characterized in that The metal feature has a metal feature back side, the metal feature back side is exposed from the back side of the plastic packaging layer, and the metal layer surface and at least one of the metal feature back sides are connected via conductive adhesive.

12. The chip structure according to any one of claims 1 to 7, It is characterized in that The back side of the bare chip and the back side of the metal unit are exposed from the back side of the plastic packaging layer, and the portion exposed from the back side of the plastic packaging layer has a surface treatment layer.

13. The chip structure according to any one of claims 1 to 7, It is characterized in that The at least one bare chip is a plurality of bare chips, the plurality of bare chips are bare chips with different functions, and the plurality of bare chips are electrically connected according to product design.

14. The chip structure according to claim 7, It is characterized in that The outermost dielectric layer completely covers the panel-level conductive layer.

15. A chip packaging method, It is characterized in that include: providing a wafer and forming a protective layer on an active surface of the wafer; Cutting and separating the wafer into dies; providing a metal structure, the metal structure comprising at least one metal unit; Mounting the bare die and the metal structure on a carrier board; forming a plastic sealing layer; The metal structure is a metal frame, which is transferred to the carrier plate via a temporary support plate. Wherein, after the metal frame is set on the temporary support plate, the method further includes cutting and separating the connecting rods so that the metal units in the metal frame are independent of each other. Alternatively, after the metal frame is disposed on the temporary support plate, the method further includes removing connecting rods from the metal frame so that the metal units in the metal frame are independent of each other.

16. The chip packaging method according to claim 15, It is characterized in that Also included is forming a conductive structure, the die and at least one metal feature of the metal unit being connected by the conductive structure.

17. The chip packaging method according to claim 16, It is characterized in that The steps of forming the conductive structure include: A protective layer opening is formed in the protective layer on the active surface of the chip, and at least a portion of the protective layer opening is formed at an electrical connection point and / or a heat dissipation position; a conductive material is filled in the protective layer opening to form a conductive filled through hole and a panel-level conductive layer, and the panel-level conductive layer is formed on the upper surface of the protective layer and the front side of the plastic sealing layer, at least a portion of the panel-level conductive layer is connected to the conductive filled through hole and to the metal unit, and the upper surface of the protective layer, the front side of the plastic sealing layer and the front side of the metal unit are flush.

18. The chip packaging method according to claim 16 or 17, It is characterized in that The metal feature includes a connection structure and / or a heat dissipation structure; the connection structure includes a connection pad; and the heat dissipation structure includes a heat dissipation pad.

19. The chip packaging method according to claim 18, It is characterized in that The heat dissipation structure further comprises a back heat sink, which is applied to the back side of the die through a thermal conductive material.

20. The chip packaging method according to any one of claims 15 to 17, It is characterized in that The method also includes applying a metal layer on the back side of the die, and connecting the surface of the metal layer and the back side of at least one metal feature via a conductive adhesive.

21. The chip packaging method according to claim 17, It is characterized in that The method also includes the step of forming a dielectric layer covering the panel-level conductive layer, wherein the outermost dielectric layer completely covers the panel-level conductive layer.

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