Chip packaging method and packaging structure

Abstract

The present disclosure provides a chip packaging method and packaging structure, a chip packaging method, comprising: forming a protective layer with material properties on the active surface of a bare chip; mounting the bare chip with the protective layer formed on the active surface of the bare chip on a carrier, with the active surface of the bare chip facing the carrier and the back of the bare chip facing away from the carrier; forming a plastic sealing layer with material properties for encapsulating the bare chip; peeling off the carrier to expose the protective layer; forming a conductive layer and a dielectric layer; the packaging method can reduce or eliminate warping during panel packaging, reduce the accuracy requirements of the bare chip on the panel, reduce the difficulty of the panel packaging process, and enable the packaged chip structure to have a durable service life, and is particularly suitable for large panel-level packaging and packaging of large current flux and thin chips.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a chip packaging method and packaging structure. Background Art

[0002] Panel-level packaging is to cut a wafer into a number of dies, arrange the dies and paste them on a carrier, and package the dies simultaneously in the same process. Panel-level packaging has been a technology that has emerged in recent years and has received widespread attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and suitability for large-scale production.

[0003] However, there are many technical barriers to panel packaging, such as panel warping and the accuracy of die alignment on the panel.

[0004] Especially with the current trend of miniaturization and lightness of electronic devices, small and thin chips are increasingly favored by the market. However, the difficulty of packaging small and thin chips using large panel packaging technology cannot be underestimated. Summary of the invention

[0005] The present disclosure aims to provide a semiconductor chip packaging method and a chip packaging structure, which can reduce or eliminate warping during panel packaging, reduce the accuracy requirements of bare chips on the panel, reduce the difficulty of the panel packaging process, and enable the packaged chip structure to have a durable service life. The method is particularly suitable for large panel-level packaging and packaging of large current flux, thin chips.

[0006] The present disclosure provides a chip packaging structure, comprising: at least one bare chip; a protective layer formed on the active surface of the bare chip, and having conductive filled through holes formed in the protective layer, at least a portion of the conductive filled through holes being electrically connected to at least a portion of the electrical connection points; a plastic encapsulation layer, the plastic encapsulation layer being used to encapsulate the bare chip; a conductive layer at least partially formed on the surface of the protective layer, the conductive layer being electrically connected to at least a portion of the conductive filled through holes; and a dielectric layer formed on the conductive layer.

[0007] In one embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

[0008] In one embodiment, the material of the protective layer is an organic / inorganic composite material.

[0009] In another embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

[0010] In yet another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0011] In a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer is any one of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0012] In another preferred embodiment, the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficient.

[0013] In another preferred embodiment, the protective layer comprises inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

[0014] In an advantageous embodiment, the diameter of the inorganic filler particles is 1 to 2 μm.

[0015] In a preferred embodiment, the conductive filled via is formed by filling a protective layer opening with a conductive medium, and the conductive filled via has a conductive filled via lower surface and a conductive filled via upper surface, and an area ratio of the conductive filled via lower surface to the conductive filled via upper surface is 60% to 90%.

[0016] In an advantageous embodiment, there is a gap between the lower surface of the conductive filled via and the insulating layer, and / or the lower surface of the conductive filled via is located near the center of the electrical connection point.

[0017] In a preferred embodiment, the protective layer opening is a protective layer opening formed by laser patterning.

[0018] In another preferred embodiment, the conductive layer includes conductive traces and / or conductive protrusions; wherein: at least a portion of the conductive trace closest to the active surface of the die is formed on the surface of the protective layer and is electrically connected to the conductive filled through-hole; the conductive protrusion is formed on the solder pad or connection point of the conductive trace.

[0019] In yet another preferred embodiment, the conductive layer is one layer or multiple layers.

[0020] In a preferred embodiment, a conductive covering layer is formed on the electrical connection point.

[0021] In an advantageous embodiment, the thickness of the conductive covering layer is 2-3 μm.

[0022] In an advantageous embodiment, the conductive cover layer is a Cu layer.

[0023] In a preferred embodiment, at least a portion of the conductive trace closest to the active surface of the die is formed on the front side of the plastic layer and extends to the edge of the package body.

[0024] In a preferred embodiment, the back side of the die is exposed from the molding layer.

[0025] In a preferred embodiment, the surface of the dielectric layer has grooves at positions corresponding to the conductive layer.

[0026] In a preferred embodiment, the at least one bare die is a plurality of bare die, and the plurality of bare die are electrically connected to each other according to product design.

[0027] In a preferred embodiment, the plurality of dies are dies with different functions to form a multi-chip module.

[0028] The present disclosure provides a chip packaging method, comprising: forming a protective layer on the active surface of a bare chip; mounting the bare chip with the protective layer formed on the active surface of the bare chip on a carrier, with the active surface of the bare chip facing the carrier and the back of the bare chip facing away from the carrier; forming a plastic sealing layer for encapsulating the bare chip; and peeling off the carrier to expose the protective layer.

[0029] In one embodiment, forming a protective layer on an active surface of a die includes: forming a protective layer on an active surface of a wafer, and cutting the wafer with the protective layer into a plurality of die with the protective layer.

[0030] In one embodiment, the material of the protective layer is an organic / inorganic composite material.

[0031] In one embodiment, the Young's modulus of the protective layer is any of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

[0032] In one embodiment, the thickness of the protective layer is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

[0033] In another embodiment, the thermal expansion coefficient of the protective layer is any of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0034] In one embodiment, the thermal expansion coefficient of the plastic encapsulation layer is any one of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0035] In yet another embodiment, the protection layer and the plastic encapsulation layer have the same or similar thermal expansion coefficient.

[0036] In a preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1-2 μm.

[0037] In another preferred embodiment, the method further comprises the step of forming a protective layer opening on the protective layer, wherein the area ratio of the lower surface of the protective layer opening to the upper surface of the protective layer opening is 60% to 90%.

[0038] In a preferred embodiment, the protective layer openings are formed by laser patterning.

[0039] In yet another preferred embodiment, the step further includes thinning the back side of the plastic packaging layer to expose the back side of the die.

[0040] In a preferred embodiment, the method further comprises the step of forming grooves at positions corresponding to the conductive layer on the dielectric layer by metal etching.

[0041] In a preferred embodiment, the method further comprises the step of subjecting the wafer and / or the protective layer surface to plasma surface treatment and / or chemically accelerated modifier treatment.

[0042] In a preferred embodiment, the method further includes performing a chemical plating process on the active surface of the wafer to form a conductive covering layer on the electrical connection points. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figures 1 to 12 is a process of a chip packaging method proposed according to an exemplary embodiment of the present disclosure;

[0044] Figure 1 is a schematic diagram of a semiconductor wafer according to an exemplary embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of a semiconductor wafer after a protective layer is applied according to an exemplary embodiment of the present disclosure;

[0046] Figure 3a is a schematic diagram of a semiconductor wafer in which a protective layer opening is formed according to an exemplary embodiment of the present disclosure;

[0047] Figure 3b is a schematic diagram of a semiconductor wafer in which a conductive filled via is formed according to an exemplary embodiment of the present disclosure;

[0048] Figure 4 is a schematic diagram of cutting a semiconductor wafer to form dies with a protection layer according to an exemplary embodiment of the present disclosure;

[0049] Figure 5a is a schematic diagram of attaching a bare die to a carrier board according to an exemplary embodiment of the present disclosure;

[0050] Figure 5b is a schematic diagram of a die assembly attached to a carrier board according to an exemplary embodiment of the present disclosure;

[0051] Figure 6 is a schematic diagram of forming a plastic encapsulation layer on a carrier according to an exemplary embodiment of the present disclosure;

[0052] Figure 7a is a schematic diagram of reducing the thickness of the plastic encapsulation layer according to an exemplary embodiment of the present disclosure;

[0053] Figure 7b is a schematic diagram of thinning the plastic encapsulation layer to expose the back side of the die according to an exemplary embodiment of the present disclosure;

[0054] Figure 8 is a schematic diagram of peeling off a carrier plate and an adhesive layer according to an exemplary embodiment of the present disclosure;

[0055] Fig. 9 is a schematic diagram of forming conductive filled vias and conductive traces on a panel assembly according to an exemplary embodiment of the present disclosure;

[0056] Fig.10 is a schematic diagram of forming a conductive protrusion on a panel assembly according to an exemplary embodiment of the present disclosure;

[0057] Fig.11a and Fig.11b is a schematic diagram of forming a dielectric layer on a panel assembly according to an exemplary embodiment of the present disclosure;

[0058] Fig.12 is a schematic diagram of cutting a panel assembly to form a packaged chip according to an exemplary embodiment of the present disclosure;

[0059] Fig.13a is a schematic diagram of a chip packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure;

[0060] Fig.13b is a schematic diagram of a chip packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure;

[0061] Fig.13c is a schematic diagram of a chip component packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure;

[0062] Fig.14a is a schematic diagram of a packaged chip in use according to an exemplary embodiment of the present disclosure;

[0063] Fig.14b FIG. 4 is a schematic diagram of a packaged chip assembly in use according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] In order to make the technical solution of the present disclosure clearer and the technical effects more obvious, the following detailed and specific description and illustration of the preferred embodiments of the present disclosure are given in conjunction with the accompanying drawings. It should not be understood that the following description is the only implementation form of the present disclosure or a limitation to the present disclosure.

[0065] Figures 1 to 12 The present invention provides a process for a chip packaging method according to an exemplary embodiment of the present invention.

[0066] like Figure 1 As shown, at least one wafer 100 is provided, and the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002. The wafer 100 includes a plurality of bare chips 113, wherein the active surface of each bare chip constitutes the wafer active surface 1001. The active surface of each bare chip in the wafer 100 is formed into a series of active components and passive components through a series of processes such as doping, deposition, and etching. The active components include diodes, triodes, etc., and the passive components include transformers, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits, thereby realizing various functions of the chip. The wafer active surface 1001 also includes an electrical connection point 103 for leading out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103.

[0067] Preferably, a chemical plating process is performed on the active surface 1001 of the wafer to form a conductive coating on the electrical connection point 103. Optionally, the conductive coating is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive coating is not Figure 1 The conductive cover layer can protect the electrical connection points 103 on the wafer active surface 1001 from being damaged by laser in the subsequent step of forming a protective layer opening.

[0068] like Figure 2 As shown, a protective layer 107 is applied on the active surface 1001 of the wafer.

[0069] In one embodiment, the protective layer is applied to the wafer active surface 1001 by lamination.

[0070] Optionally, before the step of applying the protective layer 107 on the active surface 1001 of the wafer, the active surface 1001 of the wafer and / or the side of the protective layer 107 applied to the wafer 100 is physically and / or chemically treated to make the bonding between the protective layer 107 and the wafer 100 tighter. The treatment method may be plasma surface treatment to roughen the surface and increase the bonding area and / or chemical promoter modifier treatment to introduce promoter modification groups between the wafer 100 and the protective layer 107, such as a surface modifier with both organic and inorganic affinity groups, to increase the adhesion between the organic / inorganic interface layer.

[0071] The protective layer 107 can be used to protect the die active surface 1131. In the subsequent plastic packaging process, due to the plastic packaging pressure, the plastic packaging material flowing under the heating condition can easily penetrate into the gap between the die 113 and the carrier 117, thereby destroying the circuit on the die active surface 1131. When the die active surface 1131 has a protective layer, the protective layer 107 can protect the die active surface 1131 from the plastic packaging material penetrating into it, thereby protecting the die active surface 1131 from damage.

[0072] The presence of the protection layer 107 can also make the bonding between the bare chip 113 and the adhesive layer 121 stronger, so that during the molding process, the molding pressure is not likely to cause the bare chip 113 to move on the carrier 117.

[0073] In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000 to 20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 to 10000 MPa; further preferably the Young's modulus of the protective layer 107 is 1000 to 7000, 4000 to 7000 or 4000 to 8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

[0074] In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15 to 50 μm; more preferably, the thickness of the protective layer is in the range of 20 to 50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

[0075] When the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient supporting force, so that the protective layer 107 has sufficient support for the conductive layer on its surface. At the same time, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffering and support.

[0076] In particular, in some types of chips, it is necessary to use a thin bare chip for packaging, and the conductive layer needs to reach a certain thickness value to form a large electric flux. At this time, the thickness range of the protective layer 107 is selected to be 15-50 μm, and the numerical range of the Young's modulus of the protective layer 107 is 1000-10000 MPa. The soft and flexible protective layer 107 can form a buffer layer between the bare chip 113 and the conductive layer, so that during the use of the chip, the conductive layer will not over-press the bare chip 113, and prevent the pressure of the thick conductive layer from breaking the bare chip 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

[0077] When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the material properties of the protective layer 107, the protective layer 107 can effectively protect the die against the ejector pressure of the die transfer device during the subsequent die transfer process;

[0078] The die transfer process is a process (reconstruction process) of rearranging and bonding the cut and separated die 113 to the carrier 117. The die transfer process requires the use of a die transfer device (bonder machine). The die transfer device includes a pin, which is used to lift the die 113 on the wafer 100, and a bonder head is used to suck up the lifted die 113, transfer it, and bond it to the carrier 117.

[0079] During the process of the bare die 113 being lifted by the ejector pin, the bare die 113, especially the thin bare die 113, is brittle and easily broken by the lifting pressure of the ejector pin. The protective layer 100 with material properties can protect the brittle bare die 113 in this process and keep the bare die 113 intact even under a larger lifting pressure.

[0080] In a preferred embodiment, the protective layer 107 is an organic / inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO 2 particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as SiO 2 mixed with TiO 2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 particles, such as SiO 2 mixed with TiO 2 particles, are spherical or quasi-spherical. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 particles, such as SiO 2 mixed with TiO 2 particles, have a filling amount of more than 50%.

[0081] The organic material has the advantages of being easy to operate and apply. The die 113 to be encapsulated is an inorganic material such as silicon. When the protective layer 107 is made of organic material alone, due to the difference between the material properties of the organic material and the inorganic material, the encapsulation process is difficult and the encapsulation effect is affected. Using an organic / inorganic composite material with inorganic particles added to the organic material can modify the material properties of the organic material, making the material have the characteristics of both organic and inorganic materials.

[0082] In a preferred embodiment, when (T < Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm / K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm / K.

[0083] In the subsequent encapsulation process, the die 113 with the protective layer 107 applied will expand and contract correspondingly during the heating and cooling processes of the encapsulation process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3 to 10 ppm / K, the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, and the interface stress is not easily generated at the connection interface between the protective layer 107 and the die 113, and the bond between the protective layer 107 and the die 113 is not easily damaged, making the structure of the encapsulated chip more stable.

[0084] During use, the packaged chip often needs to undergo hot and cold cycles. The thermal expansion coefficient of the protective layer 107 is in the range of 3 to 10 ppm / K and has the same or similar thermal expansion coefficient as the bare chip 113. During the hot and cold cycles, the protective layer 107 and the bare chip 113 maintain relatively consistent expansion and contraction levels, avoiding the accumulation of interface fatigue at the interface between the protective layer 107 and the bare chip 113, making the packaged chip durable and extending the chip service life.

[0085] On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill too many filler particles in the composite material of the protective layer 107. While further reducing the thermal expansion coefficient, the Young's modulus of the material will also increase, reducing the flexibility of the protective layer material, making the rigidity too strong, and the buffering effect of the protective layer 107 is poor. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10ppm / k.

[0086] In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO 2 The diameter of the particles is less than 3 μm. Preferably, the filler particles in the protective layer 107 are inorganic oxide particles, such as SiO 2 The diameter of the particles is between 1 and 2 μm.

[0087] Controlling the diameter of the filler particles to be less than 3 μm is beneficial to forming a protective layer opening with smoother side walls on the protective layer 107 during the laser patterning process, so that the material can be fully filled during the conductive material filling process, thereby avoiding the situation where the conductive material cannot be filled on the protective layer opening side wall 109c with large-sized bumps behind the side wall blocked by the protrusions, thereby affecting the conductive performance of the conductive filled through hole 111.

[0088] At the same time, the filling size of 1 to 2 μm will expose small-particle fillers during the laser patterning process, so that the side wall 109c of the protective layer opening has a certain degree of roughness. This side wall with a certain degree of roughness will have a larger contact area with the conductive material and a closer contact, forming a conductive filled through hole 111 with good conductive performance.

[0089] The diameter size of the filler mentioned above is the average value of the particle diameter.

[0090] In a preferred embodiment, the tensile strength of the protective layer 107 has a value ranging from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

[0091] Optionally, after applying the protective layer 107 on the active surface 1001 of the wafer, the back side 1002 of the wafer is ground to thin the wafer to a desired thickness.

[0092] Modern electronic devices are small and lightweight, and chips tend to be thinner. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of the thin wafer 100 is difficult, and the grinding and thinning process is difficult, and it is often difficult to thin the wafer 100 to an ideal thickness. When the surface of the wafer 100 has a protective layer 107, the protective layer 107 with material properties will support the wafer 100, reducing the difficulty of processing, transferring and thinning the wafer 100.

[0093] like Figure 3a As shown, a protection layer opening 109 is formed on the surface of the protection layer 107 .

[0094] A protective layer opening 109 is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the wafer active surface 1001 , exposing the electrical connection point 103 on the wafer active surface 1001 .

[0095] Preferably, there is a one-to-one correspondence between the protection layer openings 109 and the electrical connection points 103 on the wafer active surface 1001 .

[0096] Optionally, each of the protection layer openings 109 in at least a portion of the protection layer openings 109 corresponds to a plurality of the electrical connection points 103 .

[0097] Optionally, at least a portion of the electrical connection points 103 corresponds to a plurality of the protection layer openings 109 .

[0098] Optionally, at least a portion of the protection layer openings 109 have no corresponding electrical connection points 103 , or at least a portion of the electrical connection points 103 have no corresponding protection layer openings 109 .

[0099] Preferably, the protective layer opening is formed by laser patterning.

[0100] In the process flow of forming the protection layer opening 2021 by laser patterning, the conductive covering layer formed on the electrical connection point 103 in the chemical plating process step can protect the electrical connection point 103 on the wafer active surface 1001 from laser damage.

[0101] Preferably, Figure 3a As shown in the partial enlarged view in FIG. 1 , there is a gap between the lower surface 109 a of the protective layer opening and the insulating layer 105 , and / or the lower surface 109 a of the protective layer opening is located near the center of the electrical connection point 103 .

[0102] In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of ​​the upper surface 109b of the protective layer opening is larger than the area of ​​the lower surface 109a of the protective layer opening, and the area ratio of the lower surface 109a of the protective layer opening to the upper surface 109b of the protective layer opening is 60% to 90%.

[0103] At this time, the slope of the side wall 109 c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the side wall.

[0104] Optional, such as Figure 3b As shown, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductive filling through hole 111, and at least a part of the conductive filling through hole 111 is electrically connected to the electrical connection point 103 on the active surface 1001 of the wafer. The conductive filling through hole 111 extends the electrical connection point 103 on the active surface 1001 of the wafer to the surface of the protective layer in a single direction, and the protective layer is formed around the conductive filling through hole 111. The conductive medium can be gold, silver, copper, tin, aluminum or other materials or a combination thereof, or other suitable conductive materials can be formed in the protective layer opening 109 by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form a conductive filling through hole 111.

[0105] The filling of the conductive medium may be to completely fill the protective layer opening 109, or to form only a layer of conductive material in the protective layer opening 109, which can be electrically connected to the conductive layer. Accordingly, the conductive filled via 111 is understood as long as there is a conductive medium in the protective layer opening, and the conductive medium can be electrically connected to the conductive layer, and it is not necessary to completely fill the protective layer opening.

[0106] By forming a protective layer opening 109 on the protective layer 107 in advance and / or filling it with a conductive medium, the position of the electrical connection point 103 on the active surface 1001 of the chip can be accurately located through the protective layer opening 109, and the area of ​​the protective layer opening 109 can be made smaller, and the spacing between the openings can also be smaller, so that in the subsequent conductive layer formation step, the conductive traces can be tighter and there is no need to worry about the position positioning deviation of the electrical connection point 103.

[0107] like Figure 4 As shown, the wafer 100 with the protection layer 107 applied thereto is cut along the dicing lines to obtain a plurality of die 113 with the protection layer formed thereon, wherein the die 113 has a die active surface 1131 and a die back surface 1132 .

[0108] In one embodiment, cutting Figure 2Wafer 100 is shown with protective layer 107 forming die 113 .

[0109] In one embodiment, cutting Figure 3a Wafer 100 is shown with protective layer 107 and protective layer opening 109 forming die 113 .

[0110] In one embodiment, cutting Figure 3b Wafer 100 is shown with protection layer 107 and conductive filled vias 111 forming die 113 .

[0111] Due to the material properties of the protection layer, during the dicing process of the wafer 100 , the separated dies 113 are free of burrs and die chips.

[0112] In one embodiment, before the step of cutting the wafer 100 to separate the die 113, a plasma surface treatment is performed on the side of the wafer 100 with the protective layer 107 to increase the surface roughness, so as to increase the adhesion of the die 113 on the carrier 117 in the subsequent process and prevent the die 113 from moving under the pressure of the plastic package.

[0113] It is understandable that, if the process permits, according to specific actual conditions, after the wafer 100 is cut into the bare die 113 to be packaged, a protective layer can be formed on the bare die active surface 1131 of each bare die 113 to be packaged.

[0114] like Figure 5a As shown, a carrier 117 is provided, and the carrier 117 has a carrier front side 1171 and a carrier back side 1172 , and the divided bare chips 113 are arranged at a preset position on the carrier front side 1171 , with the bare chip active surface 1131 facing the carrier 117 , and the bare chip back side 1132 being arranged away from the carrier 117 .

[0115] The shape of the carrier 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier 117 can be a small-sized wafer substrate, or a rectangular carrier of various sizes, especially a large-sized one. The material of the carrier 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier 117 is a large-sized quadrilateral panel made of stainless steel.

[0116] The carrier 117 has a carrier front side 113 and a carrier back side 115 , and the carrier front side 113 is preferably a plane.

[0117] In one embodiment, the die 113 is bonded and fixed on the carrier 117 using an adhesive layer 121 .

[0118] The adhesive layer 121 can be formed on the front side of the carrier 1171 by lamination, printing, spraying, coating, etc. In order to facilitate separation of the carrier 117 and the bare die 113 with plastic encapsulation completed on the back in the subsequent process, the adhesive layer 121 preferably uses an easily separable material, such as a thermally separable material.

[0119] Preferably, the position of the bare die 113 can be pre-marked on the carrier 117. The mark can be formed on the carrier 117 by laser, mechanical engraving, etc. At the same time, a positioning mark is also provided on the bare die 113 to align with the pasting position on the carrier 117 during pasting.

[0120] Optional, such as Figure 5b As shown, in a packaging process, multiple bare chips 113a and 113b, especially multiple bare chips 113a and 113b with different functions, two of which are shown in the figure, or more than two, can be arranged on a carrier board 117 according to the needs of actual products, and packaged. After the packaging is completed, they are cut into multiple packages; thus, one package includes multiple bare chips 113a and 113b to form a multi-chip module (MCM), and the positions of the multiple bare chips 113a and 113b can be freely set according to the needs of actual products.

[0121] The bare chip 113 arranged on the carrier 117 may be in the form of Figure 2 The wafer 100 is shown with the protective layer 107 cut into dies 113 .

[0122] It can also be Figure 3a The die 113 cut from the wafer 100 having the protective layer 107 and the protective layer opening 109 is shown. After the die 113 having the protective layer 107 and the protective layer opening 109 is attached to the adhesive layer 121 of the carrier 117 , the protective layer opening 109 is in a hollow state.

[0123] You can also Figure 3b The wafer 100 is shown with the protection layer 107 and the conductive filled vias 111 cut into dies 113 .

[0124] like Figure 6 As shown, a plastic encapsulation layer 123 is formed.

[0125] A plastic encapsulation layer 123 is formed around the bare die 113 to be packaged and the exposed surface of the carrier front side 1171 or the adhesive layer 121. The plastic encapsulation layer 123 is used to completely encapsulate the carrier front side 1171 and the bare die 113 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 117 is peeled off, the next packaging step can be continued on the reconstructed flat plate structure.

[0126] The side of the plastic encapsulation layer 123 in contact with the carrier front side 1171 or the adhesive layer 121 is defined as the plastic encapsulation layer front side 1231. The side of the plastic encapsulation layer 123 facing away from the carrier front side 1171 or the adhesive layer 121 is defined as the plastic encapsulation layer back side 1232.

[0127] Preferably, the front side 1231 of the plastic encapsulation layer and the back side 1232 of the plastic encapsulation layer are substantially flat and parallel to the front side 1171 of the carrier board.

[0128] In one embodiment, the plastic sealing layer 123 is formed by using an organic / inorganic composite material through compression molding.

[0129] Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3-10 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm / K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 7 ppm / K; in yet another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm / K.

[0130] Preferably, the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficient.

[0131] The thermal expansion coefficient of the molding layer 123 is selected to be 3 to 10 ppm / K and is selected to have the same or similar thermal expansion coefficient as the protective layer 107. During the heating and cooling process of the molding process, the expansion and contraction degrees between the protective layer 107 and the molding layer 123 are kept consistent, and the two materials are not prone to generate interface stress. The low thermal expansion coefficient makes the thermal expansion coefficients of the molding layer, the protective layer and the bare chip close, so that the interfaces of the molding layer 123, the protective layer 107 and the bare chip 113 are tightly bonded, avoiding the occurrence of interface layer separation.

[0132] During use, the packaged chip often needs to undergo hot and cold cycles. Since the thermal expansion coefficients of the protective layer 107, the plastic layer 123 and the bare chip 113 are similar, during the hot and cold cycles, the interface fatigue of the protective layer 107, the plastic layer 123 and the bare chip 113 is small, and it is not easy to have an interface gap between the protective layer 107, the plastic layer 123 and the bare chip 113, which increases the service life of the chip and the chip can be used in a wide range of fields.

[0133] The difference in thermal expansion coefficients between the bare chip 113 and the plastic layer 123 will also cause warping of the panel assembly after plastic packaging. Due to the warping phenomenon, it is difficult to locate the precise position of the bare chip 113 in the panel assembly in the subsequent conductive layer formation process, which has a great impact on the conductive layer formation process.

[0134] In particular, in the large panel packaging process, due to the large size of the panel, even a slight warping of the panel will cause a large size change in the position of the bare chips in the outer surrounding parts of the panel away from the center relative to before molding. Therefore, in the large panel packaging process, solving the warping problem becomes one of the keys to the entire process. The warping problem even limits the enlargement of the panel size and becomes a technical barrier in large-size panel packaging.

[0135] The thermal expansion coefficients of the protective layer 107 and the plastic layer 123 are limited to the range of 3 to 10 ppm / K, and preferably the plastic layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively avoid the warping of the panel assembly and realize the packaging process using large panels.

[0136] At the same time, during the molding process, the molding pressure will generate pressure on the back of the bare chip 113. This pressure is likely to press the bare chip 113 into the adhesive layer 121, so that the bare chip 113 is sunken into the adhesive layer 121 during the formation of the molding layer 123. After the molding layer 123 is formed, the bare chip 113 and the front side 1231 of the molding layer are not in the same plane. The surface of the bare chip 113 protrudes beyond the front side 1231 of the molding layer to form a step-like structure. In the subsequent conductive layer formation process, the conductive trace 125 will also have a step-like structure accordingly, making the packaging structure unstable.

[0137] When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the molding pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the formation of a step-like structure on the front side 1231 of the molding layer.

[0138] like Figure 7a As shown, the thickness of the plastic encapsulation layer 123 can be reduced by grinding or polishing the back side 1232 of the plastic encapsulation layer.

[0139] In one embodiment, if Figure 7b As shown, the thickness of the plastic encapsulation layer 123 can be reduced to the back side 1132 of the die 113, thereby exposing the back side 1132 of the die. Fig.13b shown.

[0140] like Figure 8 As shown, the carrier board 117 is peeled off to expose the front side 1231 of the plastic sealing layer and the protective layer 107 .

[0141] In one embodiment, when the bare chips 113 arranged on the carrier 117 are in the form of Figure 3aThe die 113 shown has the protection layer 107 and the protection layer opening 109 . When the carrier 1172 is peeled off, the protection layer opening 109 is also exposed.

[0142] In one embodiment, when the bare chips 113 arranged on the carrier 117 are in the form of Figure 2 When the die 113 is cut from the wafer 100 having the protective layer 107 but without a protective layer opening formed on the protective layer 107 as shown, after the carrier 117 is peeled off, there is a step of forming a protective layer opening on the protective layer 107 on the die 113 covered by the plastic layer 123 .

[0143] In one embodiment, when the bare chip 113 arranged on the carrier 117 is in the form of Figure 3b When the wafer 100 with the protection layer 107 and the conductive filled vias 111 is cut into dies 113 , the conductive filled vias 111 are also exposed.

[0144] The structure of the plastic layer 123 covering the bare chip 113 after the carrier 117 is separated is defined as a panel assembly 150 .

[0145] Fig. 9 and Fig.10 An embodiment of the process of forming a conductive filled via on the die 113 in the molding layer 123 and patterning the conductive layer is shown.

[0146] When the protective layer 107 on the surface of the bare chip 113 wrapped in the plastic layer 123 has not formed a conductive filling through hole 111, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductive filling through hole 111, and the conductive filling through hole 111 is electrically connected to the electrical connection point 103 on the active surface 1001 of the wafer. The conductive filling through hole 111 extends the electrical connection point 103 on the active surface 1001 of the wafer to the protective layer surface, and the protective layer is formed around the conductive filling through hole 111. The conductive medium can be gold, silver, copper, tin, aluminum or other materials or a combination thereof, or other suitable conductive materials formed in the protective layer opening 109 by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form a conductive filling through hole 111.

[0147] The filling of the conductive medium may be to completely fill the protective layer opening 109, or to form only a layer of conductive material in the protective layer opening 109, which can be electrically connected to the conductive layer. Accordingly, the conductive filled via 111 is understood as long as there is a conductive medium in the protective layer opening, and the conductive medium can be electrically connected to the conductive layer, and it is not necessary to completely fill the protective layer opening.

[0148] A conductive trace 125 is formed on the die 113 in the plastic layer 123; at least a portion of the conductive trace 125 is formed on the surface of the protective layer 107 on the active surface 1131 of the die, and is electrically connected to at least a portion of the conductive filled through hole 111; in one embodiment, the conductive trace 125 extends along the surface of the protective layer 107 and the front side 1231 of the plastic layer, and extends to the edge of the chip package body when the package is completed, and the packaged chip structure is as follows Fig.13b The conductive trace 125 extends to the edge of the package body, and at this time, the conductive trace 125 covers and connects the interface between the protection layer 107 and the plastic layer 132, thereby increasing the stability of the chip structure after packaging.

[0149] Conductive trace 125 may be one or more layers of copper, gold, silver, tin, aluminum or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0150] Preferably, the conductive filling of the vias 111 and the conductive traces 125 are performed in the same conductive layer forming step.

[0151] Of course, it is also possible to first form the conductive filled via 111 and then form the conductive trace 125 .

[0152] Fig.10 It is shown that a conductive stud 127 is formed on the pad or connection point of the conductive trace 125; the shape of the conductive stud 127 can be round, or other shapes such as oval, square, linear, etc. The conductive stud 127 can be one or more layers of copper, gold, silver, tin, aluminum, etc. or a combination thereof, or other suitable conductive materials formed by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition processes.

[0153] The conductive layer is composed of conductive traces 125 and / or conductive protrusions 127. The conductive layer may be a single layer or multiple layers. The conductive layer may have a fan-out redistribution (fan-out RDL) function.

[0154] like Fig.11a and Fig.11b As shown, a dielectric layer 129 is formed on the conductive layer.

[0155] One or more dielectric layers 129 are formed on the surface of the conductive layer by lamination, coating, spraying, printing, molding and other suitable methods.

[0156] The dielectric layer 129 can be BCB benzocyclobutene, PI polyimide, PBO polybenzoxazole, ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, polymer matrix dielectric film, organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymer composite material, such as epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulation and structural properties. In a preferred embodiment, the dielectric layer 129 is ABF. The dielectric layer 129 plays the role of protecting the conductive layer and insulating. In one embodiment, the thickness of the dielectric layer 129 applied is thicker than the thickness of the conductive layer, and the conductive layer is exposed through the grinding process; in another embodiment, the thickness of the dielectric layer 133 applied is the same as the thickness of the conductive layer, and the conductive layer is just exposed after the dielectric layer 129 is applied.

[0157] In one embodiment, repeat Figures 9 to 11b In the step of forming a plurality of conductive layers on the die active surface 1131 of the die 113.

[0158] Back to Figures 9 to 11b In one embodiment, the step of forming the conductive layer may be:

[0159] forming conductive traces 125 on a die active surface 1131 of the die 113;

[0160] Form one or more dielectric layers 129 on the surface of the conductive trace 125 by lamination, coating, spraying, printing, molding or other suitable methods, wherein the height of the dielectric layer 129 is higher than the height of the conductive trace 125, and the conductive trace 125 is completely encapsulated in the dielectric layer 129;

[0161] Openings are formed on the dielectric layer 129 at locations corresponding to pads or connection points of the conductive traces 125 , and conductive studs 127 are formed in the openings.

[0162] In another embodiment, the conductive protrusion 127 may not be formed in the opening, so that the pads or connection points of the conductive traces 125 of the completed package are exposed from the opening.

[0163] In a preferred embodiment, after the step of applying the dielectric layer 129, the thickness of the outermost conductive layer is thinned by etching to form a groove 131 on the outer surface of the dielectric layer 129. Fig.13b shown.

[0164] Optional, such as Fig.11bAs shown, in a packaging process, multiple bare chips 113a and 113b, especially multiple bare chips 113a and 113b with different functions, two of which are shown in the figure, or more than two, can be packaged into a multi-chip package component, and the pattern design of the conductive layer of the multiple bare chips 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged chip structure is as follows Fig.13c shown.

[0165] like Fig.12 As shown, the packaged units are cut and separated to form packaged chips, which can be cut mechanically or by laser.

[0166] Fig.13a , Fig.13b and Fig.13c It is a schematic diagram of the chip packaging structure.

[0167] Fig.13a It is a schematic diagram of a chip packaging structure obtained according to a packaging method provided by an exemplary embodiment of the present disclosure.

[0168] As shown in the figure, a chip packaging structure includes: a bare chip 113, wherein the bare chip 113 includes a bare chip active surface 1131 and a bare chip back surface 1132, wherein the bare chip active surface 1131 includes an electrical connection point 103 and an insulating layer 105; a protective layer 107, formed on the bare chip active surface 1131, and having conductive filled through holes 111 formed in the protective layer 107, wherein at least a portion of the conductive filled through holes 111 is electrically connected to at least a portion of the electrical connection points 103, and is used to lead at least a portion of the electrical connection points 103 out of the bare chip active surface 1131; a plastic encapsulation layer 123, wherein the plastic encapsulation layer 123 is used to encapsulate the bare chip 113; a conductive layer, at least partially formed on the surface of the protective layer 107, wherein the conductive layer is electrically connected to at least a portion of the conductive filled through holes 111; and a dielectric layer, formed on the conductive layers 125, 127.

[0169] In one embodiment, the Young's modulus of the protective layer 107 is any of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

[0170] In one embodiment, the material of the protection layer 107 is an organic / inorganic composite material.

[0171] In one embodiment, the thickness of the protective layer 107 is any of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

[0172] In one embodiment, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0173] In one embodiment, the thermal expansion coefficient of the plastic layer 123 is any one of the following numerical ranges or values: 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.

[0174] In one embodiment, the protection layer 107 and the plastic encapsulation layer 123 have the same or similar thermal expansion coefficient.

[0175] In one embodiment, the protective layer 107 includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1-2 μm.

[0176] In one embodiment, the area ratio of the conductive filled via lower surface 111 a to the conductive filled via upper surface 111 b is 60% to 90%.

[0177] In one embodiment, the conductive filled via 111 is formed by filling the protective layer opening 109 with a conductive medium.

[0178] In one embodiment, a conductive covering layer is formed on the electrical connection point 103 .

[0179] In one embodiment, Fig.13a As shown in the partial enlarged view in FIG. 1 , there is a gap between the lower surface 111 a of the conductive filled through hole and the insulating layer 105 .

[0180] In one embodiment, Fig.13a As shown in the partial enlarged view in FIG. 1 , the lower surface 111 a of the conductive filled through hole is located near the center of the electrical connection point 103 .

[0181] In one embodiment, the conductive layer includes conductive traces 125 and / or conductive protrusions 127 ; wherein: at least a portion of the conductive traces 125 closest to the die active surface 1131 is formed on the surface of the protection layer 107 and is electrically connected to the conductive filled vias 111 .

[0182] The conductive studs 127 are formed on pads or connection points of the conductive traces 125 .

[0183] The conductive layer may be one layer or multiple layers.

[0184] In one embodiment, Fig.13bAs shown, at least a portion of the conductive trace 125 closest to the die active surface 1131 is formed on the front side 1231 of the plastic layer and extends to the edge of the package body.

[0185] In yet another embodiment, Fig.13b As shown, the back side 1132 of the die is exposed from the molding layer 123 .

[0186] In yet another embodiment, Fig.13b As shown, the surface of the dielectric layer 129 has grooves at positions corresponding to the conductive layer.

[0187] In one embodiment, Fig.13c As shown, the package structure includes a plurality of bare chips 113, and the plurality of bare chips 113 are electrically connected according to product design. Optionally, the plurality of bare chips 113 are bare chips with different functions to form a multi-chip module.

[0188] Fig.14a The schematic diagram of the packaged chip in use is shown. During use, the packaged chip is connected to a circuit board or substrate 161 through solder 160 and then connected to other circuit components.

[0189] When the surface of the dielectric layer 129 of the packaged chip has the groove 131 , the solder 160 can be stably connected and not easily moved.

[0190] Fig.14b The schematic diagram of the packaged chip assembly in use is shown. During use, the packaged chip assembly is connected to a circuit board or substrate 161 through solder 160 and then connected to other circuit components.

[0191] The specific embodiments described above are intended to further illustrate the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the inventive concept of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A chip packaging structure, It is characterized in that include: at least one die; A protective layer, located on one side of the active surface of the die, wherein the protective layer is provided with conductive filled through holes, and at least a portion of the conductive filled through holes are electrically connected to the electrical connection points; A plastic encapsulation layer, the plastic encapsulation layer is used to encapsulate the bare chip; A conductive layer, at least partially formed on a surface of the protective layer, at least a portion of the conductive layer being electrically connected to the conductive filled through hole; a dielectric layer formed on the conductive layer; The Young's modulus of the protective layer is 1000-20000 MPa, and when the temperature T is less than the glass transition temperature Tg, the thermal expansion coefficient of the protective layer is 3-10 ppm / K, and The thickness of the protective layer is 20-50 μm.

2. The chip packaging structure according to claim 1, Features The Young's modulus of the protective layer is 1000-10000 MPa.

3. The chip packaging structure according to claim 2, Features The Young's modulus of the protective layer is 4000-8000 MPa.

4. The chip packaging structure according to claim 3, Features The Young's modulus of the protective layer is 5500 MPa.

5. The chip packaging structure according to claim 1, It is characterized in that The material of the protective layer is an organic / inorganic composite material, wherein the filling amount of the inorganic material is more than 50%.

6. The chip packaging structure according to claim 1, It is characterized in that The thickness of the protective layer is 35 μm, 45 μm, or 50 μm.

7. The chip packaging structure according to claim 1, It is characterized in that The thermal expansion coefficient of the protective layer is 5 ppm / K, 7 ppm / K, and 10 ppm / K.

8. The chip packaging structure according to claim 1, It is characterized in that The thermal expansion coefficient of the plastic sealing layer is 3-10 ppm / K.

9. The chip packaging structure according to claim 8, It is characterized in that The thermal expansion coefficient of the plastic sealing layer is 5ppm / K, 7ppm / K, and 10ppm / K.

10. The chip packaging structure according to claim 1, It is characterized in that The protection layer and the molding layer have substantially the same thermal expansion coefficient.

11. The chip packaging structure according to claim 1, It is characterized in that The protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

12. The chip packaging structure according to claim 11, It is characterized in that The diameter of the inorganic filler particles is 1 to 2 μm.

13. The chip packaging structure according to claim 1, It is characterized in that The conductive filled via is formed by filling the protective layer opening with a conductive medium. The conductive filled via has a conductive filled via lower surface and a conductive filled via upper surface. The area ratio of the conductive filled via lower surface to the conductive filled via upper surface is 60% to 90%.

14. The chip packaging structure according to claim 13, It is characterized in that There is a gap between the lower surface of the conductive filled via and the insulating layer, and / or the lower surface of the conductive filled via is located near the center of the electrical connection point.

15. The chip packaging structure according to any one of claims 1 to 14, It is characterized in that The conductive layer includes conductive traces and / or conductive protrusions; Wherein: at least a portion of the conductive trace closest to the active surface of the die is formed on the surface of the protective layer and is electrically connected to the conductive filled through hole; The conductive layer is one layer or multiple layers.

16. The chip packaging structure according to any one of claims 1 to 14, It is characterized in that A conductive covering layer is formed on the electrical connection point, wherein the thickness of the conductive covering layer is 2-3 microns.

17. The chip packaging structure according to claim 15, It is characterized in that At least a portion of the conductive trace closest to the active surface of the die is formed on the front side of the plastic encapsulation layer and extends to the edge of the package body, covering and connecting the interface between the protection layer and the plastic encapsulation layer.

18. The chip packaging structure according to any one of claims 1 to 14, It is characterized in that The back side of the die is exposed from the molding layer.

19. The chip packaging structure according to any one of claims 1 to 14, It is characterized in that The surface of the dielectric layer has a groove at a position corresponding to the conductive layer.

20. The chip packaging structure according to any one of claims 1 to 14, It is characterized in that The at least one bare chip is a plurality of bare chips, and the plurality of bare chips are electrically connected to each other according to product design.

21. The chip packaging structure according to claim 20, It is characterized in that The plurality of dies are dies having different functions to form a multi-chip module.

22. The chip packaging structure according to claim 1, It is characterized in that The tensile strength of the protective layer is 20-50 MPa.

23. A chip packaging method, It is characterized in that include: forming a protective layer on a die active surface of the die; Mounting the bare chip with the protective layer formed thereon on a carrier, with the active surface of the bare chip facing the carrier and the back surface of the bare chip facing away from the carrier; forming a plastic encapsulation layer for encapsulating the die; Peeling off the carrier to expose the protective layer; The Young's modulus of the protective layer is 1000-20000 MPa, and when the temperature T is less than the glass transition temperature Tg, the thermal expansion coefficient of the protective layer is 3-10 ppm / K, and The thickness of the protective layer is 20-50 μm.

24. The chip packaging method according to claim 23, It is characterized in that The Young's modulus of the protective layer is 1000-10000 MPa.

25. The chip packaging method according to claim 24, It is characterized in that The Young's modulus of the protective layer is 4000-8000 MPa.

26. The chip packaging method according to claim 25, It is characterized in that The Young's modulus of the protective layer is 5500 MPa.

27. The chip packaging method according to claim 23, It is characterized in that The protective layer is formed on the active surface of the die, including: forming the protective layer on the active surface of the wafer, and cutting the wafer with the protective layer into a plurality of die with the protective layer.

28. The chip packaging method according to claim 23, Features: The thickness of the protective layer is 35 μm, 45 μm, or 50 μm.

29. The chip packaging method according to claim 23, It is characterized in that The thermal expansion coefficient of the protective layer is 5 ppm / K, 7 ppm / K, 10 ppm / K, and / or the thermal expansion coefficient of the plastic sealing layer is 3-10 ppm / K.

30. The chip packaging method according to claim 29, It is characterized in that The thermal expansion coefficient of the plastic sealing layer is 5ppm / K, 7ppm / K, and 10ppm / K.

31. The chip packaging method according to claim 23, It is characterized in that The material of the protective layer is an organic / inorganic composite material and / or the protective layer and the plastic encapsulation layer have substantially the same thermal expansion coefficient.

32. The chip packaging method according to claim 23, It is characterized in that The protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

33. The chip packaging method according to claim 32, It is characterized in that The diameter of the inorganic filler particles is 1 to 2 μm.

34. The chip packaging method according to claim 23, It is characterized in that The method further comprises the step of forming a protective layer opening on the protective layer, wherein the ratio of the area of ​​the lower surface of the protective layer opening to the area of ​​the upper surface of the protective layer opening is 60% to 90%.

35. The chip packaging method according to claim 34, It is characterized in that The step of filling the protective layer opening with a conductive material to form a conductive filled through hole is also included.

36. The chip packaging method according to any one of claims 24 to 35, It is characterized in that The step also includes thinning the back side of the plastic packaging layer to expose the back side of the die.

37. The chip packaging method according to any one of claims 24 to 35, It is characterized in that The method also includes the steps of forming a dielectric layer and a conductive layer, and forming grooves at positions corresponding to the conductive layer on the dielectric layer by metal etching.

38. The chip packaging method according to claim 27, It is characterized in that The method further comprises the step of performing plasma surface treatment and / or chemically accelerated modifier treatment on the surface of the wafer and / or the protective layer.

39. The chip packaging method according to any one of claims 24 to 35, It is characterized in that The method also includes performing an electroless plating process on the active surface of the wafer to form a conductive covering layer on the electrical connection points.

40. The chip packaging method according to claim 23, It is characterized in that The tensile strength of the protective layer is 20-50 MPa.

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