Light-receiving element and ranging module

Abstract

The present invention provides a light-receiving element and a ranging module, which can improve characteristics. The light-receiving element includes: an on-chip lens; a wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes: a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion, and is configured to detect a phase difference using signals detected by the first tap and the second tap. This technology can be applied, for example, to a light-receiving element that generates distance information by the ToF method, etc.

Description

Technical Field

[0001] The present invention relates to a light receiving element and a distance measuring module, and particularly to a light receiving element and a distance measuring module capable of improving characteristics. Background Art

[0002] Conventionally, a distance measuring system using an indirect ToF (Time of Flight) method has been known to the public. In such a distance measuring system, a sensor capable of rapidly distributing signal charges obtained by receiving light reflected from an active light irradiated with an LED (Light Emitting Diode) or a laser at a certain phase to different regions is essential.

[0003] Therefore, for example, a technique has been proposed in which a current is generated in a sensor substrate by directly applying a voltage to the substrate, and a wide range of regions in the substrate can be modulated at high speed (for example, refer to Patent Document 1). Such a sensor is also called a CAPD (Current Assisted Photonic Demodulator) sensor.

[0004] Patent Document 1: Japanese Patent Laid-Open Publication No. 2011-86904

[0005] However, it is difficult to obtain a CAPD sensor with sufficient characteristics in the above-described technique.

[0006] For example, the above-described CAPD sensor is a surface irradiation type sensor in which wirings and the like are arranged on the surface of the substrate on the side that receives light from the outside.

[0007] In order to ensure a photoelectric conversion region, it is preferable that there are no components such as wirings on the light receiving surface side of the PD (Photodiode), that is, the photoelectric conversion unit, that block the optical path of incident light. However, in a surface irradiation type CAPD sensor, depending on the structure, it is sometimes necessary to arrange charge extraction wirings, various control lines, and signal lines on the light receiving surface side of the PD, and the photoelectric conversion region is limited. That is, it is impossible to ensure a sufficient photoelectric conversion region, and characteristics such as pixel sensitivity sometimes decrease.

[0008] In addition, when considering using a CAPD sensor in a place where external light exists, since the external light component becomes a noise component for the indirect ToF method using active light for distance measurement, in order to ensure a sufficient SN ratio (Signal to Noise ratio) and obtain distance information, it is necessary to ensure a sufficient saturated signal amount (Qs). However, in a surface irradiation type CAPD sensor, due to limitations in wiring layout, in order to ensure capacitance, it is necessary to use methods other than wiring capacitance, such as providing additional transistors.

[0009] Furthermore, in a surface-irradiation type CAPD sensor, a signal extraction portion called a Tap is disposed on the light-incident side within the substrate. On the other hand, considering photoelectric conversion within the Si substrate, although the attenuation rate varies depending on the wavelength of light, the proportion of photoelectric conversion caused on the light-incident surface side is high. Therefore, in a surface-type CAPD sensor, the probability of photoelectric conversion may be high in the Inactive Tap region of the Tap region where the signal extraction portion is provided and no signal charge is allocated. In an indirect ToF sensor, since ranging information is obtained using signals assigned to each charge storage region according to the phase of active light, the component directly subjected to photoelectric conversion in the Inactive Tap region becomes noise, and as a result, the ranging accuracy may deteriorate. That is, the characteristics of the CAPD sensor may be degraded. Summary of the Invention

[0010] The present invention has been made in view of such circumstances, and an object thereof is to improve characteristics.

[0011] The light-receiving element according to the first aspect of the present invention includes:

[0012] An on-chip lens;

[0013] A wiring layer; and

[0014] A semiconductor layer disposed between the on-chip lens and the wiring layer,

[0015] The semiconductor layer includes:

[0016] A first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and

[0017] A second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion,

[0018] The phase difference is detected using signals detected by the first tap and the second tap.

[0019] In the first aspect of the present invention, an on-chip lens, a wiring layer, and a semiconductor layer disposed between the on-chip lens and the wiring layer are provided. In the semiconductor layer, a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion are provided, and the phase difference is detected using signals detected by the first tap and the second tap.

[0020] The light-receiving element according to the second aspect of the present invention includes:

[0021] On-chip lens;

[0022] Wiring layer;

[0023] A semiconductor layer disposed between the on-chip lens and the wiring layer; and

[0024] A polarizer disposed between the on-chip lens and the semiconductor layer,

[0025] The semiconductor layer includes:

[0026] A first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and

[0027] A second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion.

[0028] In a second aspect of the present invention, an on-chip lens, a wiring layer, a semiconductor layer disposed between the on-chip lens and the wiring layer, and a polarizer disposed between the on-chip lens and the semiconductor layer are provided. In the semiconductor layer, a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion are provided.

[0029] The light receiving element according to a third aspect of the present invention includes:

[0030] On-chip lens;

[0031] Wiring layer;

[0032] A semiconductor layer disposed between the on-chip lens and the wiring layer; and

[0033] A color filter disposed between the on-chip lens and the semiconductor layer,

[0034] The semiconductor layer includes:

[0035] A first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and

[0036] A second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion.

[0037] In a third aspect of the present invention, there are provided an on-chip lens, a wiring layer, a semiconductor layer disposed between the on-chip lens and the wiring layer, and a color filter disposed between the on-chip lens and the semiconductor layer. In the semiconductor layer, there are provided a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion.

[0038] The distance measurement module according to a fourth aspect of the present invention includes:

[0039] The light receiving element according to any one of the first to third aspects described above;

[0040] A light source that irradiates illumination light with a periodically changing brightness; and

[0041] A light emission control unit that controls the irradiation timing of the illumination light.

[0042] In a fourth aspect of the present invention, there are provided the light receiving element according to any one of the first to third aspects described above, a light source that irradiates illumination light with a periodically changing brightness, and a light emission control unit that controls the irradiation timing of the illumination light.

[0043] According to the first to fourth aspects of the present invention, the characteristics of the element can be improved.

[0044] In addition, the effects described here are non-limiting, and may also be any one of the effects described in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a block diagram showing a structural example of a light receiving element.

[0046] Figure 2 It is a diagram showing a structural example of a pixel.

[0047] Figure 3 It is a diagram showing a structural example of a part of a signal extraction unit of a pixel.

[0048] Figure 4 It is a diagram for explaining the improvement of sensitivity.

[0049] Figure 5 It is a diagram for explaining the improvement of charge separation efficiency.

[0050] Figure 6 It is a diagram for explaining the improvement of the extraction efficiency of electrons.

[0051] Figure 7 It is a diagram for explaining the moving speed of signal carriers in a surface illumination type.

[0052] Figure 8 This is a diagram for explaining the moving speed of the signal carrier in the back-illuminated type.

[0053] Figure 9 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0054] Figure 10 This is a diagram for explaining the relationship between the pixel and the on-chip lens.

[0055] Figure 11 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0056] Figure 12 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0057] Figure 13 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0058] Figure 14 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0059] Figure 15 This is a diagram showing another structural example of a part of the signal extraction section of the pixel.

[0060] Figure 16 This is a diagram showing another structural example of the pixel.

[0061] Figure 17 This is a diagram showing another structural example of the pixel.

[0062] Figure 18 This is a diagram showing another structural example of the pixel.

[0063] Figure 19 This is a diagram showing another structural example of the pixel.

[0064] Figure 20 This is a diagram showing another structural example of the pixel.

[0065] Figure 21 This is a diagram showing another structural example of the pixel.

[0066] Figure 22 This is a diagram showing another structural example of the pixel.

[0067] Figure 23 This is a diagram showing another structural example of the pixel.

[0068] Figure 24 This is a diagram showing another structural example of the pixel.

[0069] Figure 25 This is a diagram showing another structural example of the pixel.

[0070] Figure 26 It is a diagram showing other structural examples of pixels.

[0071] Figure 27 It is a diagram showing other structural examples of pixels.

[0072] Figure 28 It is a diagram showing other structural examples of pixels.

[0073] Figure 29 It is a diagram showing other structural examples of pixels.

[0074] Figure 30 It is a diagram showing other structural examples of pixels.

[0075] Figure 31 It is a diagram showing the equivalent circuit of a pixel.

[0076] Figure 32 It is a diagram showing other equivalent circuits of pixels.

[0077] Figure 33 It is a diagram showing a configuration example of a voltage supply line adopting a Periodic configuration.

[0078] Figure 34 It is a diagram showing a configuration example of a voltage supply line adopting a Mirror configuration.

[0079] Figure 35 It is a diagram explaining the characteristics of the Periodic configuration and the Mirror configuration.

[0080] Figure 36 It is a cross-sectional view of multiple pixels in the fourteenth embodiment.

[0081] Figure 37 It is a cross-sectional view of multiple pixels in the fourteenth embodiment.

[0082] Figure 38 It is a cross-sectional view of multiple pixels in the ninth embodiment.

[0083] Figure 39 It is a cross-sectional view of multiple pixels in Modification 1 of the ninth embodiment.

[0084] Figure 40 It is a cross-sectional view of multiple pixels in the fifteenth embodiment.

[0085] Figure 41 It is a cross-sectional view of multiple pixels in the tenth embodiment.

[0086] Figure 42 It is a diagram explaining the five metal films of the multilayer wiring layer.

[0087] Figure 43 This is a diagram illustrating a 5-layer metal film of a multi-layer wiring layer.

[0088] Figure 44 This is a diagram illustrating a polysilicon layer.

[0089] Figure 45 This is a diagram of a modified example of a reflection component formed on a metal film.

[0090] Figure 46 This is a diagram of a modified example of a reflection component formed on a metal film.

[0091] Figure 47 This is a diagram illustrating the substrate structure of a light-receiving element.

[0092] Figure 48 This is a diagram illustrating the noise around a pixel transistor region.

[0093] Figure 49 This is a diagram illustrating a noise suppression structure around a pixel transistor region.

[0094] Figure 50 This is a diagram illustrating a charge discharge structure around a pixel transistor region.

[0095] Figure 51 This is a diagram illustrating a charge discharge structure around a pixel transistor region.

[0096] Figure 52 This is a diagram illustrating the charge discharge around the effective pixel region.

[0097] Figure 53 This is a top view showing a structural example of a charge discharge region provided on the outer periphery of an effective pixel region.

[0098] Figure 54 This is a cross-sectional view in the case where the charge discharge region is composed of a light-shielding pixel region and an N-type region.

[0099] Figure 55 This is a diagram illustrating the flow of current in the case where a pixel transistor is arranged on a substrate having a photoelectric conversion region.

[0100] Figure 56 This is a cross-sectional view of multiple pixels of the eighteenth embodiment.

[0101] Figure 57 This is a diagram illustrating the circuit sharing between two substrates.

[0102] Figure 58 This is a diagram illustrating the substrate structure of the eighteenth embodiment.

[0103] Figure 59 It is a top view showing the arrangement of the MIX joint and the DET joint.

[0104] Figure 60 It is a top view showing the arrangement of the MIX joint and the DET joint.

[0105] Figure 61 It is a diagram for explaining the problem of an increase in the consumption power flow.

[0106] Figure 62 It is a top view and a cross-sectional view of a pixel of the first structural example of the nineteenth embodiment.

[0107] Figure 63 It is a top view and a cross-sectional view of a pixel of the second structural example of the nineteenth embodiment.

[0108] Figure 64 It is a diagram showing other planar shapes of the first structural example and the second structural example of the nineteenth embodiment.

[0109] Figure 65 It is a diagram showing other planar shapes of the first structural example and the second structural example of the nineteenth embodiment.

[0110] Figure 66 It is a top view and a cross-sectional view of a pixel of the third structural example of the nineteenth embodiment.

[0111] Figure 67 It is a diagram showing other planar shapes of the third structural example of the nineteenth embodiment.

[0112] Figure 68 It is a diagram showing other planar shapes of the third structural example of the nineteenth embodiment.

[0113] Figure 69 It is a diagram showing a circuit structure example of a pixel array section when pixel signals of four taps are output simultaneously.

[0114] Figure 70 It is a diagram showing a wiring layout in which four vertical signal lines are arranged.

[0115] Figure 71 It is a diagram showing a first modification example of the wiring layout in which four vertical signal lines are arranged.

[0116] Figure 72 It is a diagram showing a second modification example of the wiring layout in which four vertical signal lines are arranged.

[0117] Figure 73 It is a diagram showing a modification example of an arrangement example of pixel transistors.

[0118] Figure 74 It is showingFigure 73 A diagram of the connection layout in the pixel transistor layout of B.

[0119] Figure 75 It represents Figure 73 A diagram of the wiring layout in the pixel transistor layout of B.

[0120] Figure 76 A diagram of the wiring layout with two power supply lines configured in one pixel column.

[0121] Figure 77 A top view of an example of the wiring of the VSS wiring.

[0122] Figure 78 A top view of an example of the wiring of the VSS wiring.

[0123] Figure 79 A diagram for explaining the first method of pupil correction.

[0124] Figure 80 A diagram for explaining the first method of pupil correction.

[0125] Figure 81 A diagram for explaining the first method of pupil correction.

[0126] Figure 82 A diagram for explaining the first method of pupil correction.

[0127] Figure 83 A diagram for explaining the offset of the on-chip lens in the first method of pupil correction.

[0128] Figure 84 A diagram for explaining the 2Phase method and the 4Phase method.

[0129] Figure 85 A diagram for explaining an example of the wiring of the voltage supply line.

[0130] Figure 86 A cross-sectional view and a top view of the pixel of the first structural example of the twentieth embodiment.

[0131] Figure 87 A diagram of an example of the arrangement of the first tap and the second tap.

[0132] Figure 88 A diagram for explaining the driving mode of the first tap and the second tap.

[0133] Figure 89 A cross-sectional view and a top view of the pixel of the second structural example of the twentieth embodiment.

[0134] Figure 90 A diagram showing an example of the configuration of the phase difference light shielding film and the on-chip lens.

[0135] Figure 91 It is a cross-sectional view of a pixel of the twenty-first embodiment.

[0136] Figure 92 It is a top view of a pixel of the twenty-first embodiment.

[0137] Figure 93 It is a cross-sectional view of a pixel of the twenty-second embodiment.

[0138] Figure 94 It is a top view of a pixel of the twenty-second embodiment.

[0139] Figure 95 It is a block diagram showing a structural example of a distance measurement module.

[0140] Figure 96 It is a block diagram showing an example of the schematic structure of a vehicle control system.

[0141] Figure 97 It is a diagram for explaining an example of the installation positions of an out-vehicle information detection unit and a camera unit.

[0142] Explanation of reference numerals:

[0143] 1: Light-receiving element; 20: Pixel array section; 21: Tap driving section; 22: Vertical driving section; 29: Vertical signal line; 30: Voltage supply line; 51: Pixel; 51X: Light-shielding pixel; 61: Substrate; 62: On-chip lens; 63: Inter-pixel light-shielding film; 64: Oxide film; 65, 65-1, 65-2: Signal extraction section; 66: Fixed charge film; 71-1, 71-2, 71: N+ semiconductor region; 73-1, 73-2, 73: P+ semiconductor region; 441-1, 441-2, 441: Separation region; 471-1, 471-2, 471: Separation region; 631: Reflective component; 721: Transfer transistor; 722: FD; 723: Reset transistor; 724: Amplification transistor; 725: Selection transistor; 727: Additional capacitor; 728: Switching transistor; 741: Voltage supply line; 811: Multi-layer wiring layer; 812: Interlayer insulating film; 813: Power supply line; 814: Voltage application wiring; 815: Reflective component; 816: Voltage application wiring; 817: Control line; M1 to M5: Metal film; 1021: P-well region; 1022: P-type semiconductor region; 1031: P-well region; 1032, 1033: Oxide film; 1051: Effective pixel region; 1052: Invalid pixel region; 1061: N-type diffusion layer; 1071: Pixel separation section; 1101: Charge discharge region; 1102: OPB region; 1121: Open pixel region; 1122: Light-shielding pixel region; 1123: N-type region; 1131: N-type diffusion layer; 1201, 1211: Substrate; 1231: Pixel array region; 1232: Region control circuit; 1251: MIX junction; 1252: DET junction; 1253: Voltage supply line; 1261: Peripheral section; 1311: Electrode section; 1311A: Embedded section; 1311B: Protruding section; 1312: P+ semiconductor region; 1313: Insulating film; 1314: Hole concentration enhancement layer; 1401, 1401A to 1401D: Power supply line; 1411, 1411A to E: VSS wiring; 1421: Gap; 1511: Vertical wiring; 1512: Horizontal wiring; 1513: Wiring; 1521: First wiring layer; 1522: Second wiring layer; 1523: Third wiring layer; 1542, 1543: Outer peripheral section; 1801, 1811: Phase difference light-shielding film; 1821: On-chip lens; 1841: Polarization filter; 1861: Color filter; 1871: IR cut-off filter; 1872: Color filter; 1881: Photodiode; 1882: Pixel separation section; 5000: Distance measurement module; 5011: Light-emitting section; 5012: Light-emitting control section; 5013: Light-receiving section. Detailed implementation mode

[0144] Hereinafter, embodiments to which the present invention is applied will be described with reference to the drawings.

[0145] (First Embodiment)

[0146] (Structural Example of Light-Receiving Element)

[0147] By configuring the CAPD sensor of the present invention to have a back-illuminated structure, characteristics such as pixel sensitivity can be improved.

[0148] The present invention can also be applied, for example, to a light-receiving element that constitutes a distance measurement system for performing distance measurement by the indirect ToF method, a imaging device having such a light-receiving element, and the like.

[0149] For example, the distance measurement system can be applied to an in-vehicle system mounted on a vehicle and for measuring the distance to an object outside the vehicle, a gesture recognition system for measuring the distance to an object such as a user's hand and recognizing the user's gesture based on the measurement result, and the like. In this case, the result of gesture recognition can be used, for example, for the operation of an automotive navigation system.

[0150] Figure 1 It is a block diagram showing a structural example of an embodiment of a light-receiving element to which this technology is applied.

[0151] Figure 1 The shown light-receiving element 1 is a back-illuminated CAPD sensor, and is provided, for example, in an imaging device having a distance measurement function.

[0152] The light-receiving element 1 is configured to have: a pixel array unit 20 formed on a semiconductor substrate (not shown); and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 20. The peripheral circuit unit is constituted, for example, by a tap driving unit 21, a vertical driving unit 22, a column processing unit 23, a horizontal driving unit 24, and a system control unit 25.

[0153] A signal processing unit 31 and a data storage unit 32 are also provided in the light-receiving element 1. In addition, the signal processing unit 31 and the data storage unit 32 can be mounted on the same substrate as the light-receiving element 1, or can be arranged on a substrate different from the light-receiving element 1 in the imaging device.

[0154] The pixel array unit 20 is configured such that pixels 51 that generate charges corresponding to the received light amount and output signals corresponding to the charges are two-dimensionally arranged in a matrix in the row direction and the column direction. That is, the pixel array unit 20 has a plurality of pixels 51, and the plurality of pixels 51 perform photoelectric conversion on the incident light and output signals corresponding to the resulting charges. Here, the row direction refers to the arrangement direction of the pixels 51 in the horizontal direction, and the column direction refers to the arrangement direction of the pixels 51 in the vertical direction. The row direction is horizontal in the figure, and the column direction is vertical in the figure.

[0155] The pixel 51 receives light incident from the outside, particularly infrared light, and performs photoelectric conversion, outputting a pixel signal corresponding to the resulting charge. The pixel 51 has: a first tap TA to which a prescribed voltage MIX0 (first voltage) is applied to detect the charge after photoelectric conversion; and a second tap TB to which a prescribed voltage MIX1 (second voltage) is applied to detect the charge after photoelectric conversion.

[0156] The tap driving unit 21 supplies the prescribed voltage MIX0 to the first tap TA of each pixel 51 in the pixel array unit 20 via a prescribed voltage supply line 30, and supplies the prescribed voltage MIX1 to the second tap TB via the prescribed voltage supply line 30. Accordingly, two voltage supply lines 30 for transmitting the voltage MIX0 and the voltage supply line 30 for transmitting the voltage MIX1 are arranged in one pixel column of the pixel array unit 20.

[0157] In the pixel array unit 20, for the matrix-like pixel arrangement, pixel driving lines 28 are wired along the row direction for each pixel row, and two vertical signal lines 29 are wired along the column direction for each pixel column. For example, the pixel driving line 28 transmits a driving signal for driving when reading out a signal from the pixel. Additionally, in Figure 1 it, the pixel driving line 28 is shown as one wiring, but it is not limited to one. One end of the pixel driving line 28 is connected to the output terminal corresponding to each row of the vertical driving unit 22.

[0158] The vertical driving unit 22 is composed of a shift register, an address decoder, etc., and drives all the pixels in the pixel array unit 20 at the same time, or drives each pixel in the pixel array unit 20 in units of rows. That is, the vertical driving unit 22 and the system control unit 25 that controls the vertical driving unit 22 together constitute a driving unit that controls the operation of each pixel in the pixel array unit 20.

[0159] The signal output from each pixel 51 in the pixel row in response to the driving control of the vertical driving unit 22 is input to the column processing unit 23 through the vertical signal line 29. The column processing unit 23 performs prescribed signal processing on the pixel signals output from each pixel 51 through the vertical signal line 29, and temporarily holds the pixel signals after the signal processing.

[0160] Specifically, the column processing unit 23 performs noise removal processing, AD (Analog to Digital) conversion processing, etc. as the signal processing.

[0161] The horizontal driving unit 24 is composed of a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 23. Through the selection scan of the horizontal driving unit 24, the pixel signals after the signal processing for each unit circuit in the column processing unit 23 are sequentially output.

[0162] The system control unit 25 is composed of a timing generator that generates various timing signals, etc. Based on the various timing signals generated by this timing generator, it performs drive control of the tap drive unit 21, the vertical drive unit 22, the column processing unit 23, the horizontal drive unit 24, etc.

[0163] The signal processing unit 31 at least has an arithmetic processing function, and performs various signal processing such as arithmetic processing based on the pixel signals output from the column processing unit 23. The data storage unit 32 temporarily stores the data required for this processing during the signal processing of the signal processing unit 31.

[0164] (Example of pixel structure)

[0165] Next, an example of the structure of the pixels provided in the pixel array unit 20 will be described. The pixels provided in the pixel array unit 20 are configured as, for example, Figure 2 shown.

[0166] Figure 2 The cross-section of a single pixel 51 provided in the pixel array unit 20 is shown. This pixel 51 receives light incident from the outside, particularly infrared light, and performs photoelectric conversion, outputting a signal corresponding to the resulting charge.

[0167] The pixel 51 has a substrate 61 made of, for example, a P-type semiconductor layer such as a silicon substrate, and an on-chip lens 62 formed on this substrate 61.

[0168] For example, the thickness of the substrate 61 in the vertical direction in the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 61, is 20 μm or less. Additionally, the thickness of the substrate 61 can of course also be 20 μm or more, as long as this thickness is set according to the characteristics of the light receiving element 1, etc.

[0169] Furthermore, the substrate 61 is, for example, a high-resistance P-Epi substrate with a substrate concentration set to 1E+13 or less, and the resistance (resistivity) of the substrate 61 is, for example, 500 [Ωcm] or more.

[0170] Here, regarding the relationship between the substrate concentration and the resistance of the substrate 61, for example, when the substrate concentration is 6.48E+12 [cm 3 , the resistance is 2000 [Ωcm], when the substrate concentration is 1.30E+13 [cm 3 , the resistance is 1000 [Ωcm], when the substrate concentration is 2.59E+13 [cm 3 , the resistance is 500 [Ωcm], and when the substrate concentration is 1.30E+14 [cm 3 , the resistance is 100 [Ωcm], etc.

[0171] In Figure 2In this case, the upper surface of the substrate 61 is the back surface of the substrate 61 and is the light incident surface where light from the outside is incident on the substrate 61. On the other hand, the lower surface of the substrate 61 is the front surface of the substrate 61 and forms a multilayer wiring layer (not shown). A fixed charge film 66 composed of a single-layer film or a stacked film with positive fixed charges is formed on the light incident surface of the substrate 61, and an on-chip lens 62 that condenses and makes the light incident from the outside enter the substrate 61 is formed on the upper surface of the fixed charge film 66. The fixed charge film 66 makes the light incident surface side of the substrate 61 in a hole accumulation state and suppresses the generation of dark current.

[0172] Furthermore, in the pixel 51, at the end portion of the pixel 51 on the fixed charge film 66, an inter-pixel light shielding film 63-1 and an inter-pixel light shielding film 63-2 for preventing crosstalk between adjacent pixels are formed. Hereinafter, when it is not necessary to particularly distinguish between the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2, they are also simply referred to as the inter-pixel light shielding film 63.

[0173] In this example, light from the outside enters the substrate 61 via the on-chip lens 62, and the inter-pixel light shielding film 63 is formed so that the light incident from the outside does not enter the regions of other pixels adjacent to the pixel 51 in the substrate 61. That is, the light incident from the outside on the on-chip lens 62 and directed into other pixels adjacent to the pixel 51 is shielded by the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2, preventing it from entering the adjacent other pixels.

[0174] Since the light-receiving element 1 is a back-illuminated CAPD sensor, the light incident surface of the substrate 61 becomes the so-called back surface, and no wiring layer composed of wirings, etc. is formed on this back surface. In addition, a wiring layer is formed by stacking on a part of the surface of the substrate 61 opposite to the light incident surface, and wirings for driving transistors, etc. formed in the pixel 51 and wirings for reading signals from the pixel 51 are formed on this wiring layer.

[0175] On the side of the substrate 61 opposite to the light incident surface, that is, the inner part of the lower surface in the figure, an oxide film 64, a signal extraction part 65-1, and a signal extraction part 65-2 are formed. The signal extraction part 65-1 corresponds to Figure 1 the first tap TA described in Figure 1 and the signal extraction part 65-2 corresponds to

[0176] the second tap TB described in

[0177] Here, the signal extraction section 65-1 includes an N+ semiconductor region 71-1 as an N-type semiconductor region, an N− semiconductor region 72-1 with a lower donor impurity concentration than the N+ semiconductor region 71-1, a P+ semiconductor region 73-1 as a P-type semiconductor region, and a P− semiconductor region 74-1 with a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Here, examples of donor impurities include elements belonging to Group 5 in the periodic table such as phosphorus (P) and arsenic (As) relative to Si, and examples of acceptor impurities include elements belonging to Group 3 in the periodic table such as boron (B) relative to Si. The element that becomes a donor impurity is called a donor element, and the element that becomes an acceptor impurity is called an acceptor element.

[0178] In Figure 2 it, an N+ semiconductor region 71-1 is formed at a position adjacent to the right side of the oxide film 64 in the inner part of the surface of the side of the substrate 61 opposite to the light incident surface. Further, an N− semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure in a manner covering (surrounding) the N+ semiconductor region 71-1.

[0179] Furthermore, a P+ semiconductor region 73-1 is formed on the right side of the N+ semiconductor region 71-1. In addition, a P− semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 in the figure in a manner covering (surrounding) the P+ semiconductor region 73-1.

[0180] Furthermore, an N+ semiconductor region 71-1 is formed on the right side of the P+ semiconductor region 73-1. In addition, an N− semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the figure in a manner covering (surrounding) the N+ semiconductor region 71-1.

[0181] Similarly, the signal extraction section 65-2 includes an N+ semiconductor region 71-2 as an N-type semiconductor region, an N− semiconductor region 72-2 with a lower donor impurity concentration than the N+ semiconductor region 71-2, a P+ semiconductor region 73-2 as a P-type semiconductor region, and a P− semiconductor region 74-2 with a lower acceptor impurity concentration than the P+ semiconductor region 73-2.

[0182] In Figure 2 it, an N+ semiconductor region 71-2 is formed at a position adjacent to the left side of the oxide film 64 in the inner part of the surface of the side of the substrate 61 opposite to the light incident surface. Further, an N− semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the figure in a manner covering (surrounding) the N+ semiconductor region 71-2.

[0183] Furthermore, a P+ semiconductor region 73-2 is formed on the left side of the N+ semiconductor region 71-2. In addition, a P− semiconductor region 74-2 is formed on the upper side in the figure of the P+ semiconductor region 73-2 so as to cover (surround) the P+ semiconductor region 73-2.

[0184] Furthermore, an N+ semiconductor region 71-2 is formed on the left side of the P+ semiconductor region 73-2. In addition, an N− semiconductor region 72-2 is formed on the upper side in the figure of the N+ semiconductor region 71-2 so as to cover (surround) the N+ semiconductor region 71-2.

[0185] An oxide film 64 identical to the central portion of the pixel 51 is formed at the end portion of the pixel 51 in the surface inner portion of the surface on the side opposite to the light incident surface of the substrate 61.

[0186] Hereinafter, when there is no need to particularly distinguish between the signal extraction portion 65-1 and the signal extraction portion 65-2, it is also simply referred to as the signal extraction portion 65.

[0187] In addition, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, it is also simply referred to as the N+ semiconductor region 71, and when there is no need to particularly distinguish between the N− semiconductor region 72-1 and the N− semiconductor region 72-2, it is also simply referred to as the N− semiconductor region 72.

[0188] Furthermore, hereinafter, when there is no need to particularly distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, it is also simply referred to as the P+ semiconductor region 73, and when there is no need to particularly distinguish between the P− semiconductor region 74-1 and the P− semiconductor region 74-2, it is also simply referred to as the P− semiconductor region 74.

[0189] In addition, in the substrate 61, a separation portion 75-1 for separating these regions is formed between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 by an oxide film or the like. Similarly, a separation portion 75-2 for separating these regions is also formed between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 by an oxide film or the like. Hereinafter, when there is no need to particularly distinguish between the separation portion 75-1 and the separation portion 75-2, it is also simply referred to as the separation portion 75.

[0190] The N+ semiconductor region 71 provided on the substrate 61 functions as a charge detection unit for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carriers generated by photoelectric conversion based on the substrate 61. In addition, in addition to the N+ semiconductor region 71, an N− semiconductor region 72 with a low donor impurity concentration is also included, which can be understood as a charge detection unit. In addition, the P+ semiconductor region 73 functions as a voltage application unit for injecting a large amount of carrier current into the substrate 61, that is, directly applying a voltage to the substrate 61 to generate an electric field in the substrate 61. In addition, in addition to the P+ semiconductor region 73, a P− semiconductor region 74 with a low acceptor impurity concentration is also included, which can be understood as a voltage application unit.

[0191] In the pixel 51, a floating diffusion region FD (Floating Diffusion) unit (hereinafter, particularly also referred to as the FD unit A) not shown is directly connected to the N+ semiconductor region 71-1. Further, the FD unit A is connected to the vertical signal line 29 via an amplifier transistor or the like not shown.

[0192] Similarly, another FD unit different from the FD unit A (hereinafter, particularly also referred to as the FD unit B) is directly connected to the N+ semiconductor region 71-2. Further, the FD unit B is connected to the vertical signal line 29 via an amplifier transistor or the like not shown. Here, the FD unit A and the FD unit B are connected to different vertical signal lines 29.

[0193] For example, when it is desired to measure the distance to an object by the indirect ToF method, infrared light is emitted from the imaging device provided with the light receiving element 1 toward the object. Then, when the infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 61 of the light receiving element 1 receives the incident reflected light (infrared light) and performs photoelectric conversion. The tap driving unit 21 drives the first tap TA and the second tap TB of the pixel 51, and distributes the signal corresponding to the charge DET obtained by photoelectric conversion to the FD unit A and the FD unit B.

[0194] For example, at a certain moment, the tap driving unit 21 applies a voltage to the two P+ semiconductor regions 73 via contacts or the like. Specifically, for example, the tap driving unit 21 applies a voltage of MIX0 = 1.5V to the P+ semiconductor region 73-1 serving as the first tap TA, and applies a voltage of MIX1 = 0V to the P+ semiconductor region 73-2 serving as the second tap TB.

[0195] Thus, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move in the direction of the P+ semiconductor region 73-2, and electrons move in the direction of the P+ semiconductor region 73-1.

[0196] Therefore, in this state, infrared light (reflected light) from the outside is incident into the substrate 61 via the on-chip lens 62. When this infrared light is photoelectrically converted in the substrate 61 into pairs of electrons and holes, the resulting electrons are guided by the electric field between the P+ semiconductor regions 73 in the direction of the P+ semiconductor region 73-1 and move into the N+ semiconductor region 71-1.

[0197] In this case, the electrons generated by the photoelectric conversion are used as a signal carrier for detecting a signal corresponding to the amount of infrared light incident on the pixel 51, that is, the amount of received infrared light.

[0198] As a result, charges corresponding to the electrons moving into the N+ semiconductor region 71-1 are accumulated in the N+ semiconductor region 71-1, and these charges are detected by the column processing unit 23 via the FD unit A, the amplification transistor, the vertical signal line 29, etc.

[0199] That is, the accumulated charge DET0 in the N+ semiconductor region 71-1 is transferred to the FD unit A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge DET0 transferred to the FD unit A is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, for the read signal, processing such as AD conversion processing is performed in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 31.

[0200] This pixel signal becomes a signal representing the amount of charge corresponding to the electrons detected in the N+ semiconductor region 71-1, that is, the amount of the charge DET0 accumulated in the FD unit A. In other words, it can also be said that the pixel signal is a signal representing the amount of infrared light received by the pixel 51.

[0201] In addition, at this time, similar to the case of the N+ semiconductor region 71-1, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-2 can also be appropriately used for distance measurement.

[0202] In addition, at the next moment, the tap driving unit 21 applies a voltage to the two P+ semiconductor regions 73 via contacts or the like to generate an electric field in a direction opposite to the electric field generated in the substrate 61 so far. Specifically, for example, a voltage of MIX0 = 0V is applied to the P+ semiconductor region 73-1 serving as the first tap TA, and a voltage of MIX1 = 1.5V is applied to the P+ semiconductor region 73-2 serving as the second tap TB.

[0203] Thereby, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from the P+ semiconductor region 73-2 to the P+ semiconductor region 73-1.

[0204] In this state, infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62. When the infrared light is photoelectrically converted in the substrate 61 into pairs of electrons and holes, the obtained electrons are guided by the electric field between the P+ semiconductor regions 73 in the direction of the P+ semiconductor region 73-2 and move into the N+ semiconductor region 71-2.

[0205] Thereby, charges corresponding to the electrons moving into the N+ semiconductor region 71-2 are accumulated in the N+ semiconductor region 71-2, and the charges are detected by the column processing unit 23 via the FD unit B, the amplification transistor, the vertical signal line 29, etc.

[0206] That is, the accumulated charge DET1 in the N+ semiconductor region 71-2 is transferred to the FD unit B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charge DET1 transferred to the FD unit B is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, for the read signal, processing such as AD conversion processing is performed in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 31.

[0207] In addition, at this time, similar to the case of the N+ semiconductor region 71-2, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-1 can also be appropriately used for distance measurement.

[0208] In this way, when pixel signals obtained by photoelectric conversion during different periods are obtained in the same pixel 51, the signal processing unit 31 calculates distance information representing the distance to the object based on these pixel signals and outputs it to the subsequent stage.

[0209] The method of allocating signal carriers to different N+ semiconductor regions 71 in this way and calculating distance information based on the signals corresponding to these signal carriers is called the indirect ToF method.

[0210] When at Figure 2When observing a part of the signal extraction section 65 in the pixel 51 in the direction from top to bottom, i.e., in the direction of the plane perpendicular to the substrate 61, for example, as Figure 3 shown, it is formed in a structure where the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71. Additionally, in Figure 3 , the parts corresponding to the case of Figure 2 are labeled with the same reference numerals, and their descriptions are appropriately omitted.

[0211] In Figure 3 's example, an oxide film 64 (not shown) is formed in the central part of the pixel 51, and the signal extraction section 65 is formed in a part slightly closer to the end side from the center of the pixel 51. In particular, here, two signal extraction sections 65 are formed within the pixel 51.

[0212] Moreover, in each signal extraction section 65, a rectangular P+ semiconductor region 73 is formed at its center position. With the P+ semiconductor region 73 as the center, the P+ semiconductor region 73 is surrounded by a rectangular, more specifically, a rectangular frame-shaped N+ semiconductor region 71. That is, the N+ semiconductor region 71 is formed to surround the periphery of the P+ semiconductor region 73.

[0213] Furthermore, in the pixel 51, an on-chip lens 62 is formed to condense the infrared light incident from the outside to the central part of the pixel 51, i.e., the part indicated by the arrow A11. In other words, the infrared light incident on the on-chip lens 62 from the outside is condensed by the on-chip lens 62 to the position indicated by the arrow A11, i.e., Figure 2 the upper side position of the oxide film 64 in Figure 2 .

[0214] Therefore, the infrared light is condensed to the position between the signal extraction section 65-1 and the signal extraction section 65-2. Thereby, it is possible to suppress crosstalk caused by the infrared light incident on the pixels adjacent to the pixel 51, and it is possible to suppress the infrared light from directly incident on the signal extraction section 65.

[0215] For example, if the infrared light directly enters the signal extraction section 65, the charge separation efficiency, i.e., Cmod (Contrast between active and inactive tap), the modulation contrast will decrease.

[0216] Here, the signal extraction section 65 on the side that reads the signal corresponding to the charge DET obtained by photoelectric conversion, i.e., the signal extraction section 65 that should detect the charge DET obtained by photoelectric conversion, is also called an active tap.

[0217] Conversely, the signal extraction unit 65 on the side that basically does not read the signal corresponding to the charge DET obtained by photoelectric conversion, that is, the signal extraction unit 65 on the side that is not an active tap, is also referred to as an inactive tap.

[0218] In the above example, the signal extraction unit 65 that applies a voltage of 1.5 V to the P+ semiconductor region 73 is an active tap, and the signal extraction unit 65 that applies a voltage of 0 V to the P+ semiconductor region 73 is an inactive tap.

[0219] Cmod is calculated by the following formula (1). Cmod is an index indicating what percentage of the charges generated by the photoelectric conversion of the incident infrared light can be detected in the N+ semiconductor region 71 of the signal extraction unit 65 that is an active tap, that is, it indicates whether the signal corresponding to the charge can be extracted, and represents the charge separation efficiency. In formula (1), I0 is the signal detected by one of the two charge detection units (P+ semiconductor region 73), and I1 is the signal detected by the other.

[0220] Cmod = {|I0 - I1| / (I0 + I1)} × 100……(1)

[0221] Therefore, for example, when infrared light incident from the outside enters the region of the inactive tap and photoelectric conversion occurs within the inactive tap, the signal carriers generated by the photoelectric conversion, that is, electrons, are highly likely to move to the N+ semiconductor region 71 within the inactive tap. As a result, a part of the electrons' charges obtained by photoelectric conversion cannot be detected in the N+ semiconductor region 71 within the active tap, and Cmod, that is, the charge separation efficiency, decreases.

[0222] Therefore, in the pixel 51, by condensing the infrared light near the central portion of the pixel 51 located at a position approximately equidistant from the two signal extraction units 65, the probability that the infrared light incident from the outside is photoelectrically converted in the region of the inactive tap can be reduced, and the charge separation efficiency can be improved. In addition, in the pixel 51, the Modulation contrast can also be improved. In other words, it is possible to easily guide the electrons obtained by photoelectric conversion to the N+ semiconductor region 71 within the active tap.

[0223] According to the light-receiving element 1 as described above, the following effects can be obtained.

[0224] That is, first, since the light-receiving element 1 is a back-illuminated type, the quantum efficiency (QE) × fill factor (FF (Fill Factor)) can be maximized, and the ranging characteristics of the light-receiving element 1 can be improved.

[0225] For example, as Figure 4As shown by arrow W11, in a normal surface-illuminated image sensor, wirings 102 and 103 are formed on the light incident surface side of PD101 which is a photoelectric conversion section, where light from the outside enters.

[0226] Therefore, for example, a part of the light incident from the outside at a certain angle with respect to PD101 as shown by arrows A21 and A22 is blocked by wirings 102 and 103 and does not enter PD101.

[0227] In contrast, a back-illuminated image sensor is configured such that, for example, as shown by arrow W12, wirings 105 and 106 are formed on the surface of PD104 which is a photoelectric conversion section, on the side opposite to the light incident surface where light from the outside enters.

[0228] Therefore, compared with the surface-illuminated case, a sufficient aperture ratio can be ensured. That is, for example, the light incident from the outside at a certain angle with respect to PD104 as shown by arrows A23 and A24 is not blocked by the wiring and enters PD104. Thus, more light can be received and the sensitivity of the pixel can be improved.

[0229] In the light receiving element 1 of the back-illuminated CAPD sensor, the improvement effect of the pixel sensitivity obtained by adopting such a back-illuminated structure can also be achieved.

[0230] In addition, for example, in a surface-illuminated CAPD sensor, as shown by arrow W13, a signal extraction section 112 called a tap is formed on the light incident surface side inside PD111 which is a photoelectric conversion section. More specifically, a P+ semiconductor region and an N+ semiconductor region of the tap are formed. In addition, the surface-illuminated CAPD sensor is configured such that a wiring 113, a contact connected to the signal extraction section 112, and a wiring 114 such as metal are formed on the light incident surface side.

[0231] Therefore, for example, not only a part of the light incident from the outside at a certain angle with respect to PD111 as shown by arrows A25 and A26 is blocked by wirings 113 etc. and does not enter PD111, but also the light incident perpendicularly to PD111 as shown by arrow A27 is blocked by wiring 114 and does not enter PD111.

[0232] In contrast, a back-illuminated CAPD sensor is configured such that, for example, as shown by arrow W14, a signal extraction portion 116 is formed in a part of the surface on the opposite side of the light incident surface of the photoelectric conversion portion PD115 from which light from the outside enters. Further, wirings 117, a contact connected to the signal extraction portion 116, and a wiring 118 such as metal are formed on the surface of PD115 on the opposite side of the light incident surface.

[0233] Here, PD115 corresponds to Figure 2 the substrate 61 shown, and the signal extraction portion 116 corresponds to Figure 2 the signal extraction portion 65 shown.

[0234] In the back-illuminated CAPD sensor having such a structure, a sufficient aperture ratio can be ensured as compared with the case of the front-illuminated type. Thus, the quantum efficiency (QE) × aperture ratio (FF) can be maximized, and the ranging characteristics can be improved.

[0235] That is, for example, light incident on PD115 obliquely from the outside at a certain angle as shown by arrows A28 and A29 is not blocked by the wiring and enters PD115. Similarly, light incident on PD115 perpendicularly as shown by arrow A30 is not blocked by the wiring or the like and enters PD115.

[0236] In this way, in the back-illuminated CAPD sensor, not only can light incident at a certain angle be received, but also light incident perpendicularly on PD115 and reflected by the wiring or the like connected to the signal extraction portion (tap) in the front-illuminated type can be received. As a result, more light can be received and the sensitivity of the pixel can be improved. In other words, the quantum efficiency (QE) × aperture ratio (FF) can be maximized, and as a result, the ranging characteristics can be improved.

[0237] In particular, when the tap is arranged not at the outer edge of the pixel but near the center of the pixel, in the front-illuminated CAPD sensor, a sufficient aperture ratio cannot be ensured and the sensitivity of the pixel is reduced. However, in the light receiving element 1 of the back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured regardless of the arrangement position of the tap, and the sensitivity of the pixel can be improved.

[0238] Further, in the back-illuminated light receiving element 1, since the signal extraction portion 65 is formed near the surface on the opposite side of the light incident surface of the infrared light from the outside in the substrate 61, the occurrence of photoelectric conversion of infrared light in the region of the passive tap can be reduced. As a result, Cmod, that is, the charge separation efficiency, can be improved.

[0239] Figure 5 Shows a pixel cross-sectional view of the front-illuminated and back-illuminated CAPD sensors.

[0240] In Figure 5 In the surface-irradiation type CAPD sensor on the left side, in the figure, the upper side of the substrate 141 is the light incident surface, and a wiring layer 152 including wirings of multiple layers, an inter-pixel light-shielding portion 153, and an on-chip lens 154 are stacked on the light incident surface side of the substrate 141.

[0241] In Figure 5 In the back-irradiation type CAPD sensor on the right side, in the figure, a wiring layer 152 including wirings of multiple layers is formed on the lower side of the substrate 142 on the side opposite to the light incident surface, and an inter-pixel light-shielding portion 153 and an on-chip lens 154 are stacked on the upper side of the substrate 142 which is the light incident surface side.

[0242] In addition, in Figure 5 The gray trapezoidal shape indicates the region where the infrared light is condensed by the on-chip lens 154 and the light intensity is strong.

[0243] For example, in the surface-irradiation type CAPD sensor, there is a region R11 with passive (inactive) taps and active taps on the light incident surface side of the substrate 141. Therefore, there are many components directly incident on the passive taps. If photoelectric conversion is performed in the region of the passive taps, the signal carriers obtained through this photoelectric conversion cannot be detected in the N+ semiconductor region of the active taps.

[0244] In the surface-irradiation type CAPD sensor, since the intensity of the infrared light is strong in the region R11 near the light incident surface of the substrate 141, the probability of performing photoelectric conversion of the infrared light in the region R11 becomes high. That is, since the amount of infrared light incident near the passive taps is large, there are more signal carriers that cannot be detected by the active taps, and the charge separation efficiency is reduced.

[0245] In contrast, in the back-irradiation type CAPD sensor, there is a region R12 with passive taps and active taps at a position far from the light incident surface of the substrate 142, that is, near the surface on the side opposite to the light incident surface side. Here, the substrate 142 corresponds to Figure 2 the substrate 61 shown.

[0246] In this example, since there is a region R12 in a part of the surface on the side opposite to the light incident surface side of the substrate 142, and the region R12 is located at a position far from the light incident surface, the intensity of the incident infrared light becomes relatively weak near the region R12.

[0247] The signal carriers obtained through photoelectric conversion in the regions with strong infrared light intensity such as near the center of the substrate 142 and near the light incident surface are guided to the active taps by the electric field generated in the substrate 142 and are detected in the N+ semiconductor region of the active taps.

[0248] On the other hand, near the region R12 including the passive tap, the intensity of the incident infrared light is relatively weak. Therefore, the probability of performing photoelectric conversion of infrared light in the region R12 becomes low. That is, since the amount of infrared light incident near the passive tap is small, the number of signal carriers (electrons) generated by photoelectric conversion near the passive tap and moving toward the N+ semiconductor region of the passive tap becomes small, and the charge separation efficiency can be improved. As a result, the ranging characteristics can be improved.

[0249] Furthermore, in the back-illuminated light-receiving element 1, since the thinning of the substrate 61 can be achieved, the extraction efficiency of electrons (charges) of the signal carriers can be improved.

[0250] For example, since the aperture ratio cannot be sufficiently ensured in the surface-illuminated CAPD sensor, as Figure 6 shown by the arrow W31, in order to ensure a higher quantum efficiency and suppress the decrease in the quantum efficiency × aperture ratio, it is necessary to thicken the substrate 171 to a certain extent.

[0251] Then, in the region near the surface of the substrate 171 on the side opposite to the light incident surface, for example, in a part of the region R21, the inclination of the electric potential becomes gentle, and the electric field in the direction substantially perpendicular to the substrate 171 becomes weak. In this case, the moving speed of the signal carriers becomes slow. Therefore, the time required from performing photoelectric conversion to detecting the signal carriers in the N+ semiconductor region of the active tap becomes long. In addition, in Figure 6 the arrow in the substrate 171 indicates the electric field in the direction perpendicular to the substrate 171 in the substrate 171.

[0252] In addition, when the substrate 171 is thick, the moving distance of the signal carriers from a position far from the active tap in the substrate 171 to the N+ semiconductor region in the active tap becomes long. Therefore, the time required from performing photoelectric conversion at a position far from the active tap to detecting the signal carriers in the N+ semiconductor region of the active tap becomes further long.

[0253] Figure 7 shows the relationship between the position in the thickness direction of the substrate 171 and the moving speed of the signal carriers. The region R21 corresponds to the diffusion current region.

[0254] In this way, when the substrate 171 becomes thick, for example, when the driving frequency is high, that is, when the active and passive switching of the tap (signal extraction unit) is performed at high speed, the electrons generated at a position far from the active tap in the region R21 etc. cannot be completely introduced into the N+ semiconductor region of the active tap. That is, if the time when the tap becomes active is short, there will be a situation where the electrons (charges) generated in the region R21 etc. cannot be detected in the N+ semiconductor region of the active tap, and the extraction efficiency of the electrons decreases.

[0255] In contrast, in a back-illuminated CAPD sensor, a sufficient aperture ratio can be ensured. Therefore, as shown by the arrow W32 in, for example, Figure 6 , even if the substrate 172 is thinned, a sufficient quantum efficiency × aperture ratio can be ensured. Here, the substrate 172 corresponds to the substrate 61 in Figure 2 , and the arrow in the substrate 172 indicates the electric field in the direction perpendicular to the substrate 172.

[0256] Figure 8 represents the relationship between the position in the thickness direction of the substrate 172 and the moving speed of the signal carrier.

[0257] In this way, when the thickness in the direction perpendicular to the substrate 172 in the substrate 172 is thinned, the electric field in the direction substantially perpendicular to the substrate 172 becomes stronger, and only the electrons (charges) in the drift current region where the moving speed of the signal carrier is fast are used, and the electrons in the diffusion current region where the moving speed of the signal carrier is slow are not used. By using only the electrons (charges) in the drift current region, the time required from photoelectric conversion to detecting the signal carrier in the N+ semiconductor region of the active tap becomes shorter. In addition, when the thickness of the substrate 172 becomes thinner, the moving distance of the signal carrier to the N+ semiconductor region in the active tap also becomes shorter.

[0258] Therefore, in a back-illuminated CAPD sensor, even when the driving frequency is high, the signal carriers (electrons) generated in each region in the substrate 172 can be sufficiently introduced into the N+ semiconductor region of the active tap, and the extraction efficiency of electrons can be improved.

[0259] In addition, through the thinning of the substrate 172, sufficient extraction efficiency of electrons can be ensured even at a high driving frequency, and the high-speed driving tolerance can be improved.

[0260] In particular, in a back-illuminated CAPD sensor, a voltage can be directly applied to the substrate 172, that is, the substrate 61. Therefore, the response speed of switching between the active and passive states of the tap is fast, and it can be driven at a high driving frequency. In addition, since a voltage can be directly applied to the substrate 61, the modifiable region in the substrate 61 becomes wider.

[0261] Furthermore, in the back-illuminated light-receiving element 1 (CAPD sensor), a sufficient aperture ratio can be obtained. Therefore, the pixel can be miniaturized accordingly, and the pixel miniaturization tolerance can be improved.

[0262] In addition, by making the light-receiving element 1 a back-illuminated type, the freedom of BEOL (Back End Of Line) capacitance design can be achieved, and thereby the design freedom of the saturation signal amount (Qs) can be improved.

[0263] (Modification Example 1 of the First Embodiment)

[0264] (Example of Pixel Structure)

[0265] In addition, as described above, the portion of the signal extraction portion 65 in the substrate 61 is set as shown in Figure 3 an example where the N+ semiconductor region 71 and the P+ semiconductor region 73 are rectangular regions. However, the shapes of the N+ semiconductor region 71 and the P+ semiconductor region 73 when viewed from a direction perpendicular to the substrate 61 can be any shape.

[0266] Specifically, for example, as shown in Figure 9 , the N+ semiconductor region 71 and the P+ semiconductor region 73 can be circular. In addition, the same reference numerals are assigned to the portions corresponding to those in Figure 9 , and the description thereof is appropriately omitted. Figure 3

[0267] Figure 9 The N+ semiconductor region 71 and the P+ semiconductor region 73 are shown when viewing the portion of the signal extraction portion 65 in the pixel 51 from a direction perpendicular to the substrate 61.

[0268] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and the signal extraction portion 65 is formed from a portion slightly closer to the end side from the center of the pixel 51. In particular, here, two signal extraction portions 65 are formed in the pixel 51.

[0269] And in each signal extraction portion 65, a circular P+ semiconductor region 73 is formed at its center position, and around the P+ semiconductor region 73, the P+ semiconductor region 73 is surrounded by a circular, more specifically, an annular N+ semiconductor region 71.

[0270] Figure 10 is a top view of a part of the pixel array portion 20 in which the pixels 51 having the signal extraction portion 65 shown in Figure 9 are two-dimensionally arranged in a matrix and overlapping the on-chip lens 62.

[0271] As shown in Figure 10 , the on-chip lens 62 is formed in units of pixels. In other words, the unit region in which one on-chip lens 62 is formed corresponds to one pixel.

[0272] In addition, in Figure 2 , a separation portion 75 formed of an oxide film or the like is disposed between the N+ semiconductor region 71 and the P+ semiconductor region 73, but the separation portion 75 may or may not be provided.

[0273] (Modification Example 2 of the First Embodiment)

[0274] (Example of Pixel Structure)

[0275] Figure 11 It is a plan view showing a modified example of the planar shape of the signal extraction portion 65 in the pixel 51.

[0276] In addition to being formed into the rectangle shown in Figure 3 and the circle shown in Figure 9 , the planar shape of the signal extraction portion 65 can, for example, also be formed into the octagonal shape shown in Figure 11 .

[0277] Furthermore, Figure 11 it is a plan view showing the case where a separation portion 75 formed of an oxide film or the like is formed between the N+ semiconductor region 71 and the P+ semiconductor region 73.

[0278] Figure 11 The line A - A' shown in represents the cross-sectional line of Figure 37 described later, and the line B - B' represents the cross-sectional line of Figure 36 described later.

[0279] (Second Embodiment)

[0280] (Example of Pixel Structure)

[0281] Furthermore, above, the structure where the P+ semiconductor region 73 is surrounded by the N+ semiconductor region within the signal extraction portion 65 has been described as an example, but it can also be the case where the N+ semiconductor region is surrounded by the P+ semiconductor region.

[0282] In this case, the pixel 51 is configured as shown in Figure 12 for example. In addition, the parts corresponding to those in Figure 12 are labeled with the same reference numerals as in the case of Figure 3 , and the description thereof is appropriately omitted.

[0283] Figure 12 It shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when observing the portion of the signal extraction portion 65 in the pixel 51 from a direction perpendicular to the substrate 61.

[0284] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51. The signal extraction portion 65 - 1 is formed from a portion slightly above the center of the pixel 51 in the figure, and the signal extraction portion 65 - 2 is formed from a portion slightly below the center of the pixel 51 in the figure. Particularly in this example, the formation position of the signal extraction portion 65 within the pixel 51 becomes the same position as in the case of Figure 3 .

[0285] Within the signal extraction portion 65 - 1, corresponding to Figure 3The rectangular N+ semiconductor region 201-1 corresponding to the N+ semiconductor region 71-1 shown is formed at the center of the signal extraction section 65-1. And, the periphery of this N+ semiconductor region 201-1 is surrounded by a rectangle corresponding to the P+ semiconductor region 73-1 shown, more specifically, a rectangular frame-shaped P+ semiconductor region 202-1. That is, the P+ semiconductor region 202-1 is formed to surround the periphery of the N+ semiconductor region 201-1. Figure 3 The rectangle corresponding to the P+ semiconductor region 73-1 shown, more specifically, a rectangular frame-shaped P+ semiconductor region 202-1 surrounds it.

[0286] Similarly, within the signal extraction section 65-2, a rectangular N+ semiconductor region 201-2 corresponding to the N+ semiconductor region 71-2 shown is formed at the center of the signal extraction section 65-2. And, the periphery of this N+ semiconductor region 201-2 is surrounded by a rectangle corresponding to the P+ semiconductor region 73-2 shown, more specifically, a rectangular frame-shaped P+ semiconductor region 202-2. Figure 3 The rectangle corresponding to the N+ semiconductor region 71-2 shown, more specifically, a rectangular frame-shaped P+ semiconductor region 202-2 surrounds it. Figure 3 The rectangle corresponding to the P+ semiconductor region 73-2 shown, more specifically, a rectangular frame-shaped P+ semiconductor region 202-2 surrounds it.

[0287] In addition, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2, it is also simply referred to as the N+ semiconductor region 201. Further, hereinafter, when there is no need to particularly distinguish between the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2, it is also simply referred to as the P+ semiconductor region 202.

[0288] When the signal extraction section 65 is formed into the Figure 12 structure shown, it is the same as the case of being formed into the Figure 3 structure shown. The N+ semiconductor region 201 functions as a charge detection section for detecting the amount of signal carrier, and the P+ semiconductor region 202 functions as a voltage application section for directly applying a voltage to the substrate 61 to generate an electric field.

[0289] (Modification Example 1 of the Second Embodiment)

[0290] (Structural Example of Pixel)

[0291] In addition, similar to the example of Figure 9 , even in the case of a configuration where the periphery of the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202, the shapes of these N+ semiconductor regions 201 and P+ semiconductor regions 202 can be arbitrary shapes.

[0292] That is, for example, the N+ semiconductor region 201 and the P+ semiconductor region 202 can be formed into circular shapes as shown in Figure 13 . Also, the same reference numerals are assigned to the parts corresponding to the case of Figure 13 in Figure 12 , and the description thereof is appropriately omitted.

[0293] Figure 13 This shows the N+ semiconductor region 201 and the P+ semiconductor region 202 when observing a part of the signal extraction part 65 in the pixel 51 from a direction perpendicular to the substrate 61.

[0294] In this example, an oxide film 64 (not shown) is formed in the central part of the pixel 51, and the signal extraction part 65 is formed in a part slightly closer to the end side from the center of the pixel 51. In particular, here, two signal extraction parts 65 are formed in the pixel 51.

[0295] Moreover, in each signal extraction part 65, a circular N+ semiconductor region 201 is formed at its center position, and around the N+ semiconductor region 201, the N+ semiconductor region 201 is surrounded by a circular, more specifically, an annular P+ semiconductor region 202.

[0296] (Third Embodiment)

[0297] (Structural Example of Pixel)

[0298] Furthermore, the N+ semiconductor region and the P+ semiconductor region formed in the signal extraction part 65 may also be linear (rectangular shape).

[0299] In this case, for example, the pixel 51 is configured as Figure 14 shown. In addition, the parts corresponding to those in Figure 14 are marked with the same reference numerals, and their descriptions are appropriately omitted. Figure 3

[0300] Figure 14 This shows the configuration of the N+ semiconductor region and the P+ semiconductor region when observing a part of the signal extraction part 65 in the pixel 51 from a direction perpendicular to the substrate 61.

[0301] In this example, an oxide film 64 (not shown) is formed in the central part of the pixel 51, the signal extraction part 65-1 is formed in a part slightly closer to the upper side of the figure from the center of the pixel 51, and the signal extraction part 65-2 is formed in a part slightly closer to the lower side of the figure from the center of the pixel 51. In particular, in this example, the formation positions of the signal extraction parts 65 in the pixel 51 are the same as those in Figure 3 the case of

[0302] In the signal extraction part 65-1, a linear P+ semiconductor region 231 corresponding to the P+ semiconductor region 73-1 shown in Figure 3 is formed at the center of the signal extraction part 65-1. And around this P+ semiconductor region 231, in a manner of sandwiching the P+ semiconductor region 231, a region corresponding to Figure 3The linear N+ semiconductor regions 232-1 and 232-2 corresponding to the N+ semiconductor region 71-1 shown. That is, the P+ semiconductor region 231 is formed at a position clamped by the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2.

[0303] In addition, hereinafter, when it is not necessary to particularly distinguish between the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2, it is also simply referred to as the N+ semiconductor region 232.

[0304] In Figure 3 's example, it is formed into a structure in which the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71, but in Figure 14 's example, it is formed into a structure in which the P+ semiconductor region 231 is clamped by two adjacent N+ semiconductor regions 232.

[0305] Similarly, within the signal extraction unit 65-2, a linear P+ semiconductor region 233 corresponding to the P+ semiconductor region 73-2 shown in Figure 3 is formed at the center of the signal extraction unit 65-2. And around this P+ semiconductor region 233, linear N+ semiconductor regions 234-1 and 234-2 corresponding to the N+ semiconductor region 71-2 shown in Figure 3 are formed in a manner of sandwiching the P+ semiconductor region 233.

[0306] In addition, hereinafter, when it is not necessary to particularly distinguish between the N+ semiconductor region 234-1 and the N+ semiconductor region 234-2, it is also simply referred to as the N+ semiconductor region 234.

[0307] In Figure 14 's signal extraction unit 65, the P+ semiconductor region 231 and the P+ semiconductor region 233 function as voltage application units corresponding to the P+ semiconductor region 73 shown in Figure 3 , and the N+ semiconductor region 232 and the N+ semiconductor region 234 function as charge detection units corresponding to the N+ semiconductor region 71 shown in Figure 3 . In this case, for example, both regions of the N+ semiconductor region 232-1 and the N+ semiconductor region 232-2 are connected to the FD unit A.

[0308] In addition, the horizontal length in the figure of each region of the linear P+ semiconductor region 231, N+ semiconductor region 232, P+ semiconductor region 233, and N+ semiconductor region 234 can be any length, and these regions do not have to be of the same length.

[0309] (Fourth Embodiment)

[0310] (Example of Pixel Structure)

[0311] Furthermore, in the example of Figure 14 a structure in which the P+ semiconductor regions 231 and 233 are sandwiched by the N+ semiconductor regions 232 and 234 has been described, but conversely, it can also be formed in a shape in which the N+ semiconductor region is sandwiched by the P+ semiconductor regions.

[0312] In such a case, for example, the pixel 51 is configured as Figure 15 shown. In addition, the parts corresponding to those in Figure 15 are labeled with the same reference numerals as those in Figure 3 and the description thereof is appropriately omitted.

[0313] Figure 15 shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when observing the signal extraction portion 65 in the pixel 51 from a direction perpendicular to the substrate 61.

[0314] In this example, an oxide film 64 (not shown) is formed in the central portion of the pixel 51, and the signal extraction portion 65 is formed in a portion slightly closer to the end side from the center of the pixel 51. In particular, in this example, the formation positions of the two signal extraction portions 65 in the pixel 51 are the same as those in Figure 3 the case of

[0315] In the signal extraction portion 65-1, a linear N+ semiconductor region 261 corresponding to the N+ semiconductor region 71-1 shown in Figure 3 is formed at the center of the signal extraction portion 65-1. And around this N+ semiconductor region 261, linear P+ semiconductor regions 262-1 and 262-2 corresponding to the P+ semiconductor region 73-1 shown in Figure 3 are formed so as to sandwich the N+ semiconductor region 261. That is, the N+ semiconductor region 261 is formed at a position sandwiched by the P+ semiconductor regions 262-1 and 262-2.

[0316] In addition, hereinafter, when it is not necessary to particularly distinguish between the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2, it is also simply referred to as the P+ semiconductor region 262.

[0317] Similarly, in the signal extraction portion 65-2, a linear N+ semiconductor region 263 corresponding to the N+ semiconductor region 71-2 shown in Figure 3 is formed at the center of the signal extraction portion 65-2. And around this N+ semiconductor region 263, linear P+ semiconductor regions corresponding to the P+ semiconductor region shown in Figure 3The linear P+ semiconductor regions 264-1 and 264-2 corresponding to the P+ semiconductor region 73-2 shown.

[0318] In addition, hereinafter, when it is not necessary to particularly distinguish between the P+ semiconductor region 264-1 and the P+ semiconductor region 264-2, it is also simply referred to as the P+ semiconductor region 264.

[0319] In Figure 15 the signal extraction unit 65, the P+ semiconductor region 262 and the P+ semiconductor region 264 function as a voltage application unit corresponding to the P+ semiconductor region 73 shown in Figure 3 , and the N+ semiconductor region 261 and the N+ semiconductor region 263 function as a charge detection unit corresponding to the N+ semiconductor region 71 shown in Figure 3 . In addition, the horizontal length in the drawing of each of the regions of the linear N+ semiconductor region 261, P+ semiconductor region 262, N+ semiconductor region 263, and P+ semiconductor region 264 can be any length, and these regions may not be of the same length.

[0320] (Fifth Embodiment)

[0321] (Example of Pixel Structure)

[0322] Furthermore, heretofore, an example in which two signal extraction units 65 are respectively provided in each pixel constituting the pixel array unit 20 has been described, but the number of signal extraction units provided in the pixel can be one or three or more.

[0323] For example, when one signal extraction unit is formed in the pixel 51, the structure of the pixel is constituted as shown in Figure 16 . In addition, the same reference numerals are given to the parts corresponding to the case in Figure 16 and the description thereof is appropriately omitted. Figure 3

[0324] Figure 16 Shows the arrangement of the N+ semiconductor region and the P+ semiconductor region when observing the part of the signal extraction unit in the pixel provided in a part of the pixel array unit 20 from the direction perpendicular to the substrate.

[0325] In this example, the pixel 51 provided in the pixel array unit 20 and the pixels 291-1 to 291-3 shown as the pixels 51 adjacent to the pixel 51 with different reference numerals are shown, and one signal extraction unit is formed in each of the above pixels.

[0326] That is, in pixel 51, a signal extraction portion 65 is formed in the central portion of pixel 51. And in the signal extraction portion 65, a circular P+ semiconductor region 301 is formed at its center position. Centered on the P+ semiconductor region 301, the periphery of the P+ semiconductor region 301 is surrounded by a circular, more specifically, an annular N+ semiconductor region 302.

[0327] Here, the P+ semiconductor region 301 corresponds to Figure 3 the P+ semiconductor region 73 shown, and functions as a voltage application portion. In addition, the N+ semiconductor region 302 corresponds to Figure 3 the N+ semiconductor region 71 shown, and functions as a charge detection portion. Additionally, the P+ semiconductor region 301 and the N+ semiconductor region 302 can be of any shape.

[0328] In addition, pixels 291-1 to 291-3 located around pixel 51 also form the same structure as pixel 51.

[0329] That is, for example, a signal extraction portion 303 is formed in the central portion of pixel 291-1. And in the signal extraction portion 303, a circular P+ semiconductor region 304 is formed at its center position. Centered on the P+ semiconductor region 304, the periphery of the P+ semiconductor region 304 is surrounded by a circular, more specifically, an annular N+ semiconductor region 305.

[0330] These P+ semiconductor regions 304 and N+ semiconductor regions 305 respectively correspond to the P+ semiconductor region 301 and the N+ semiconductor region 302.

[0331] In addition, hereinafter, when it is not necessary to particularly distinguish pixels 291-1 to 291-3, they are also simply referred to as pixel 291.

[0332] Thus, when forming a signal extraction portion (tap) in each pixel, when wanting to measure the distance to an object by the indirect ToF method, several adjacent pixels are used, and distance information is calculated based on the pixel signals obtained for these pixels.

[0333] For example, when focusing on pixel 51, with the signal extraction portion 65 of pixel 51 in an active tap state, each pixel is driven so that the signal extraction portions 303 of several adjacent pixels 291 including, for example, pixel 291-1 become passive taps.

[0334] As an example, for example, pixels 291-1 and 291-3 are driven so that the signal extraction portions of the pixels adjacent to pixel 51 in the up, down, left, and right directions in the figure become passive taps.

[0335] After that, when the voltage applied is switched such that the signal extraction section 65 of pixel 51 becomes a passive tap, the signal extraction sections 303 of several pixels 291 adjacent to pixel 51, including pixel 291-1, become active taps.

[0336] Then, based on the pixel signals read from the signal extraction section 65 in the state where the signal extraction section 65 is an active tap and the pixel signals read from the signal extraction section 303 in the state where the signal extraction section 303 is an active tap, distance information is calculated.

[0337] In this way, even when the number of signal extraction sections (taps) provided in the pixel is set to 1, ranging can be performed by the indirect ToF method using adjacent pixels.

[0338] (Sixth Embodiment)

[0339] (Example of Pixel Structure)

[0340] In addition, as described above, three or more signal extraction sections (taps) can also be provided in each pixel.

[0341] For example, when four signal extraction sections (taps) are provided in the pixel, the pixel structure of each pixel in the pixel array section 20 is configured as Figure 17 shown. In addition, the parts corresponding to the case of Figure 17 are labeled with the same reference numerals, and their descriptions are appropriately omitted. Figure 16 The cross-sectional view of the C-C' line shown in

[0342] Figure 17 showing the arrangement of the N+ semiconductor region and the P+ semiconductor region when observing the signal extraction section in a part of the pixels provided in the pixel array section 20 from the direction perpendicular to the substrate is as shown in

[0343] Figure 17 the following Figure 36 shown.

[0344] In this example, pixels 51 and 291 provided in the pixel array section 20 are shown, and four signal extraction sections are formed in each of the above pixels.

[0345] That is, in pixel 51, at positions between the center of pixel 51 and the end of pixel 51, namely, at the lower left, upper left, upper right, and lower right positions in the center of pixel 51 in the figure, signal extraction sections 331-1, 331-2, 331-3, and 331-4 are formed.

[0346] The above-mentioned signal extraction sections 331-1 to 331-4 and Figure 16corresponds to the signal extraction unit 65 shown.

[0347] For example, in the signal extraction unit 331-1, a circular P+ semiconductor region 341 is formed at its central position. Centered on the P+ semiconductor region 341, the periphery of the P+ semiconductor region 341 is surrounded by a circular, more specifically, an annular N+ semiconductor region 342.

[0348] Here, the P+ semiconductor region 341 Figure 16 corresponds to the P+ semiconductor region 301 shown and functions as a voltage application unit. In addition, the N+ semiconductor region 342 Figure 16 corresponds to the N+ semiconductor region 302 shown and functions as a charge detection unit. Additionally, the P+ semiconductor region 341 and the N+ semiconductor region 342 can be of any shape.

[0349] Furthermore, the signal extraction units 331-2 to 331-4 are also formed with the same structure as the signal extraction unit 331-1, and each has a P+ semiconductor region that functions as a voltage application unit and an N+ semiconductor region that functions as a charge detection unit. Further, the pixel 291 formed around the pixel 51 is formed with the same structure as the pixel 51.

[0350] In addition, hereinafter, when it is not necessary to particularly distinguish between the signal extraction units 331-1 to 331-4, they are also simply referred to as the signal extraction unit 331.

[0351] In this way, when four signal extraction units are provided in each pixel, for example, when performing ranging by the indirect ToF method, the distance information is calculated using the four signal extraction units within the pixel.

[0352] As an example, when focusing on the pixel 51, the pixel 51 is driven. For example, in a state where the signal extraction units 331-1 and 331-3 are set as active taps, the signal extraction units 331-2 and 331-4 are made into passive taps.

[0353] After that, the voltage applied to each signal extraction unit 331 is switched. That is, the pixel 51 is driven so that the signal extraction units 331-1 and 331-3 become passive taps, and the signal extraction units 331-2 and 331-4 become active taps.

[0354] Then, distance information is calculated based on the pixel signals read from the signal extraction units 331-1 and 331-3 when they are in the active tap state, and the pixel signals read from the signal extraction units 331-2 and 331-4 when they are in the active tap state.

[0355] (Seventh Embodiment)

[0356] (Example of Pixel Structure)

[0357] Furthermore, the signal extraction units (taps) can also be shared between adjacent pixels in the pixel array unit 20.

[0358] In such a case, each pixel in the pixel array unit 20 is configured as shown, for example. Figure 18 In addition, the same reference numerals are assigned to the corresponding parts in Figure 18 as those in the case of Figure 16 , and their descriptions are appropriately omitted.

[0359] Figure 18 It shows the configuration of the N+ semiconductor region and the P+ semiconductor region when observing the signal extraction unit in a part of the pixels provided in the pixel array unit 20 from a direction perpendicular to the substrate.

[0360] In this example, pixels 51 and 291 provided in the pixel array unit 20 are shown, and two signal extraction units are formed in each of the above pixels.

[0361] For example, in pixel 51, a signal extraction unit 371 is formed at the upper end in the figure of pixel 51, and a signal extraction unit 372 is formed at the lower end in the figure of pixel 51.

[0362] The signal extraction unit 371 is shared by pixel 51 and pixel 291-1. That is, the signal extraction unit 371 is used as a tap for pixel 51 and also as a tap for pixel 291-1. In addition, the signal extraction unit 372 is shared by pixel 51 and an unillustrated pixel adjacent to the lower side in the figure of pixel 51.

[0363] In the signal extraction unit 371, a linear P+ semiconductor region 381 corresponding to the P+ semiconductor region 231 shown in Figure 14 is formed at the center position thereof. And at the upper and lower positions in the figure of this P+ semiconductor region 381, linear N+ semiconductor regions 382-1 and 382-2 corresponding to the N+ semiconductor region 232 shown in Figure 14 are formed so as to sandwich the P+ semiconductor region 381.

[0364] In particular, in this example, the P+ semiconductor region 381 is formed at the boundary portion between pixel 51 and pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in the region within pixel 51, and the N+ semiconductor region 382-2 is formed in the region within pixel 291-1.

[0365] Here, the P+ semiconductor region 381 functions as a voltage application portion, and the N+ semiconductor regions 382-1 and 382-2 function as charge detection portions. In addition, hereinafter, when it is not necessary to particularly distinguish between the N+ semiconductor regions 382-1 and 382-2, they are also simply referred to as the N+ semiconductor region 382.

[0366] In addition, the P+ semiconductor region 381 and the N+ semiconductor region 382 can be of any shape. Furthermore, the N+ semiconductor regions 382-1 and 382-2 can be connected to the same FD portion or to different FD portions.

[0367] A linear P+ semiconductor region 383, N+ semiconductor regions 384-1 and 384-2 are formed within the signal extraction portion 372.

[0368] These P+ semiconductor region 383, N+ semiconductor regions 384-1 and 384-2 respectively correspond to the P+ semiconductor region 381, N+ semiconductor regions 382-1 and 382-2, and are provided with the same configuration, shape and function. In addition, hereinafter, when it is not necessary to particularly distinguish between the N+ semiconductor regions 384-1 and 384-2, they are also simply referred to as the N+ semiconductor region 384.

[0369] In the case of sharing the signal extraction portion (tap) between adjacent pixels as described above, indirect ToF ranging can also be performed by the same operation as in the Figure 3 example shown.

[0370] In the case of sharing the signal extraction portion between pixels as Figure 18 shown, for example, the distance between the P+ semiconductor region 381 and the P+ semiconductor region 383, etc., becomes the distance between the P+ semiconductor regions that form a pair for generating an electric field, that is, a current, and becomes longer. In other words, by sharing the signal extraction portion between pixels, the distance between the P+ semiconductor regions can be maximally lengthened.

[0371] As a result, it is difficult for current to flow between the P+ semiconductor regions. Therefore, the power consumption of the pixel can be reduced, and in addition, it is also beneficial for the miniaturization of the pixel.

[0372] In addition, an example in which a signal extraction unit is shared by two adjacent pixels has been described here. However, a signal extraction unit may also be shared by three or more adjacent pixels. Further, when the signal extraction unit is shared by two or more adjacent pixels, only the charge detection unit for detecting the signal carrier in the signal extraction unit may be shared, or only the voltage application unit for generating an electric field may be shared.

[0373] (Eighth Embodiment)

[0374] (Example of Pixel Structure)

[0375] Furthermore, an on-chip lens and an inter-pixel light-shielding portion provided for each pixel such as pixel 51 in the pixel array unit 20 may not be specifically provided.

[0376] Specifically, for example, pixel 51 can be formed into Figure 19 the structure shown. In addition, the parts corresponding to those in Figure 19 are marked with the same reference numerals as those in Figure 2 , and their descriptions are appropriately omitted.

[0377] Figure 19 The structure of pixel 51 shown is different from that of pixel 51 shown in Figure 2 in that no on-chip lens 62 is provided, and is the same as the structure of pixel 51 in Figure 2 in other aspects.

[0378] In Figure 19 the pixel 51 shown, no on-chip lens 62 is provided on the light incident surface side of the substrate 61. Therefore, the attenuation of infrared light incident on the substrate 61 from the outside can be further reduced. As a result, the amount of infrared light that can be received by the substrate 61 increases, and the sensitivity of pixel 51 can be improved.

[0379] (First Modification of the Eighth Embodiment)

[0380] (Example of Pixel Structure)

[0381] In addition, the structure of pixel 51 can be formed into, for example, the structure shown in Figure 20 . In addition, the parts corresponding to those in Figure 20 are marked with the same reference numerals as those in Figure 2 , and their descriptions are appropriately omitted.

[0382] Figure 20 The structure of pixel 51 shown is different from that of pixel 51 shown in Figure 2 in that no inter-pixel light-shielding film 63-1 and inter-pixel light-shielding film 63-2 are provided, and is the same as the structure of pixel 51 in Figure 2 in other aspects.

[0383] InFigure 20 In the example shown, since the inter-pixel light-shielding film 63 is not provided on the light-incident surface side of the substrate 61, the crosstalk suppression effect is reduced. However, since the infrared light shielded by the inter-pixel light-shielding film 63 also enters the substrate 61, the sensitivity of the pixel 51 can be improved.

[0384] In addition, of course, neither the on-chip lens 62 nor the inter-pixel light-shielding film 63 may be provided in the pixel 51.

[0385] (Modification Example 2 of the Eighth Embodiment)

[0386] (Example of Pixel Structure)

[0387] In addition, for example, as Figure 21 shown, the thickness in the optical axis direction of the on-chip lens can also be optimized. In addition, the same reference numerals are assigned to the parts corresponding to those in Figure 21 and the description thereof is appropriately omitted. Figure 2 The structure of the pixel 51 shown in

[0388] Figure 21 is different from the pixel 51 shown in Figure 2 in that the on-chip lens 411 is provided instead of the on-chip lens 62, and is the same as the pixel 51 structure in Figure 2 in other aspects.

[0389] In the pixel 51 shown in Figure 21 , the on-chip lens 411 is formed on the light-incident surface side of the substrate 61, that is, the upper side in the figure. The on-chip lens 411 is thinner in the thickness in the optical axis direction, that is, the longitudinal thickness in the figure, than the on-chip lens 62 shown in Figure 2 .

[0390] Normally, a thick on-chip lens provided on the surface of the substrate 61 is beneficial for the light collection of the light incident on the on-chip lens. However, by thinning the on-chip lens 411, the transmittance can be made correspondingly higher to improve the sensitivity of the pixel 51. Therefore, the thickness of the on-chip lens 411 can be appropriately determined according to the thickness of the substrate 61, the position where the infrared light is to be condensed, etc.

[0391] (Ninth Embodiment)

[0392] (Example of Pixel Structure)

[0393] Furthermore, a separation region for improving the separation characteristics between adjacent pixels and suppressing crosstalk may be provided between the pixels formed in the pixel array unit 20.

[0394] In such a case, the pixel 51 is configured as shown in Figure 22 for example. In addition, the same reference numerals are assigned to the parts corresponding to those in Figure 22 and Figure 2For parts corresponding to the same situation, the same reference numerals are used, and their descriptions are appropriately omitted.

[0395] Figure 22 The structure of the pixel 51 shown is different from that of the Figure 2 shown pixel 51 in that the separation regions 441-1 and 441-2 are provided in the substrate 61, and is the same as the Figure 2 pixel 51 structure in other aspects.

[0396] In Figure 22 the pixel 51 shown, at the boundary between the pixel 51 in the substrate 61 and other adjacent pixels, that is, the left and right end portions of the pixel 51 in the figure, separation regions 441-1 and 441-2 for separating adjacent pixels are formed by a light-shielding film or the like. In addition, hereinafter, when it is not necessary to particularly distinguish between the separation regions 441-1 and 441-2, they are also simply referred to as the separation region 441.

[0397] For example, when forming the separation region 441, a long groove (trench) is formed in the substrate 61 from the light incident surface side of the substrate 61, that is, the upper side in the figure, downward in the figure (the direction perpendicular to the surface of the substrate 61) to a predetermined depth, and the separation region 441 is formed by burying a light-shielding film in this groove portion. The separation region 441 functions as a pixel separation region that blocks infrared light incident from the light incident surface into the substrate 61 and directed toward other pixels adjacent to the pixel 51.

[0398] By forming the buried-type separation region 441 in this way, the separation characteristics of infrared light between pixels can be improved, and the generation of crosstalk can be suppressed.

[0399] (Modification 1 of the Ninth Embodiment)

[0400] (Example of Pixel Structure)

[0401] Furthermore, when forming a buried-type separation region in the pixel 51, for example, as Figure 23 shown, separation regions 471-1 and 471-2 penetrating the entire substrate 61 may also be provided. In addition, for Figure 23 the parts corresponding to the Figure 2 situation, the same reference numerals are used, and their descriptions are appropriately omitted.

[0402] Figure 23 The structure of the pixel 51 shown is different from that of the Figure 2 shown pixel 51 in that the separation regions 471-1 and 471-2 are provided in the substrate 61, and is the same as the Figure 2 pixel 51 structure in other aspects. That is, Figure 23 the pixel 51 shown is configured to replaceFigure 22 The separated region 441 of the pixel 51 shown, in turn, sets the separated region 471-1 and the separated region 471-2.

[0403] In Figure 23 In the pixel 51 shown, at the boundary portion between the pixel 51 in the substrate 61 and other adjacent pixels, that is, the left and right end portions of the pixel 51 in the figure, the separated region 471-1 and the separated region 471-2 that penetrate the entire substrate 61 are formed by a light-shielding film or the like. In addition, hereinafter, when it is not necessary to particularly distinguish between the separated region 471-1 and the separated region 471-2, it is also simply referred to as the separated region 471.

[0404] For example, when forming the separated region 471, long grooves (trenches) are formed from the surface of the substrate 61 on the side opposite to the light incident surface side, that is, the lower side in the figure, toward the upper side in the figure. At this time, these grooves are formed in a manner that penetrates the substrate 61 until they reach the light incident surface of the substrate 61. And the separated region 471 is formed by embedding a light-shielding film in the groove portion formed in this way.

[0405] With such an embedded type of separated region 471, it is also possible to improve the separation characteristics of infrared light between pixels and suppress the generation of crosstalk.

[0406] (Tenth Embodiment)

[0407] (Example of Pixel Structure)

[0408] Furthermore, it is possible to determine the thickness of the substrate on which the signal extraction portion 65 is formed according to various characteristics of the pixel and the like.

[0409] Therefore, for example, as Figure 24 shown, the substrate 501 constituting the pixel 51 can be made thicker than Figure 2 the substrate 61 shown. In addition, the parts corresponding to the situation in Figure 24 are labeled with the same reference numerals as in Figure 2 , and the description thereof is appropriately omitted.

[0410] Figure 24 The structure of the pixel 51 shown is different from the pixel 51 shown in Figure 2 in that the substrate 61 is replaced with the substrate 501, and the other aspects are the same as the pixel 51 structure in Figure 2 .

[0411] That is, in the pixel 51 shown in Figure 24 , an on-chip lens 62, a fixed charge film 66, and a light-shielding film 63 are formed on the light incident surface side in the substrate 501. In addition, an oxide film 64, a signal extraction portion 65, and a separation portion 75 are formed near the surface of the surface of the substrate 501 on the side opposite to the light incident surface side.

[0412] The substrate 501 is formed of, for example, a P-type semiconductor substrate with a thickness of 20 μm or more. The substrate 501 and the substrate 61 only differ in the thickness of the substrate. The positions where the oxide film 64, the signal extraction portion 65, and the separation portion 75 are formed are the same positions in the substrate 501 and the substrate 61.

[0413] In addition, the film thicknesses, etc. of various layers (films) appropriately formed on the light incident surface side of the substrate 501 and the substrate 61 can also be optimized according to the characteristics of the pixel 51, etc.

[0414] (Eleventh Embodiment)

[0415] (Structural Example of Pixel)

[0416] Furthermore, above, an example in which the substrate constituting the pixel 51 is formed of a P-type semiconductor substrate has been described. However, for example, it may be formed of an N-type semiconductor substrate as Figure 25 shown. In addition, the parts corresponding to those in Figure 25 are labeled with the same reference numerals, and the description thereof is appropriately omitted. Figure 2 The structure of the pixel 51 shown in

[0417] Figure 25 differs from the pixel 51 shown in Figure 2 in that the substrate 531 is provided instead of the substrate 61, and the other aspects are the same as the structure of the pixel 51 in Figure 2 .

[0418] In the pixel 51 shown in Figure 25 , on the light incident surface side of the substrate 531 formed of, for example, an N-type semiconductor layer such as a silicon substrate, an on-chip lens 62, a fixed charge film 66, and an inter-pixel light shielding film 63 are formed.

[0419] In addition, on the surface near the surface of the side of the substrate 531 opposite to the light incident surface side, an oxide film 64, a signal extraction portion 65, and a separation portion 75 are formed. The positions where these oxide film 64, signal extraction portion 65, and separation portion 75 are formed are the same positions in the substrate 531 and the substrate 61, and the structure of the signal extraction portion 65 is also the same in the substrate 531 and the substrate 61.

[0420] For example, the longitudinal thickness of the substrate 531 in the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 531, is 20 μm or less.

[0421] In addition, the substrate 531 is, for example, a high-resistance N-Epi substrate with a substrate concentration set to 1E+13 level or less, and the resistance (resistivity) of the substrate 531 is, for example, 500 [Ωcm] or more. Thus, the power consumption in the pixel 51 can be reduced.

[0422] Here, regarding the relationship between the substrate concentration and resistance of the substrate 531, for example, when the substrate concentration is 2.15E+12 [cm 3 , the resistance is 2000 [Ωcm], when the substrate concentration is 4.30E+12 [cm 3 , the resistance is 1000 [Ωcm], when the substrate concentration is 8.61E+12 [cm 3 , the resistance is 500 [Ωcm], and when the substrate concentration is 4.32E+13 [cm 3 , the resistance is 100 [Ωcm], etc.

[0423] Thus, even if the substrate 531 of the pixel 51 is an N-type semiconductor substrate, the same effect can be obtained through the same operation as in the Figure 2 illustrated example.

[0424] (Twelfth Embodiment)

[0425] (Example of Pixel Structure)

[0426] Furthermore, similar to the example described with reference to Figure 24 , the thickness of the N-type semiconductor substrate can also be determined based on various characteristics of the pixel, etc.

[0427] Therefore, for example, the substrate 561 constituting the pixel 51 can be made thicker than the Figure 26 illustrated substrate 531. In addition, the parts corresponding to those in Figure 25 are labeled with the same reference numerals as in Figure 26 , and their descriptions are appropriately omitted. Figure 25 The structure of the pixel 51 illustrated in

[0428] Figure 26 is different from the pixel 51 illustrated in Figure 25 in that the substrate 561 is provided instead of the substrate 531, and is the same as the pixel 51 structure in Figure 25 in other aspects.

[0429] That is, in the pixel 51 illustrated in Figure 26 , an on-chip lens 62, a fixed charge film 66, and an inter-pixel light-shielding film 63 are formed on the light incident surface side of the substrate 561. In addition, an oxide film 64, a signal extraction portion 65, and a separation portion 75 are formed near the surface of the surface of the substrate 561 on the side opposite to the light incident surface side.

[0430] The substrate 561 is made of, for example, an N-type semiconductor substrate with a thickness of 20 μm or more. The substrate 561 and the substrate 531 only differ in the thickness of the substrate, and the positions where the oxide film 64, the signal extraction portion 65, and the separation portion 75 are formed are the same positions in the substrate 561 and the substrate 531.

[0431] (13th Embodiment)

[0432] (Example of Pixel Structure)

[0433] In addition, for example, by applying a bias voltage to the light incident surface side of the substrate 61, the electric field in the direction perpendicular to the surface of the substrate 61 (hereinafter also referred to as the Z direction) in the substrate 61 can be strengthened.

[0434] In such a case, the pixel 51 is formed, for example, Figure 27 into the structure shown. In addition, Figure 27 For the part corresponding to the case of Figure 2 , the same reference numerals are given, and the description thereof is appropriately omitted.

[0435] Figure 27 A in Figure 2 represents the pixel 51 shown, and the arrow in the substrate 61 of this pixel 51 indicates the intensity of the electric field in the Z direction in the substrate 61.

[0436] On the contrary, Figure 27 B in Figure 27 represents the structure of the pixel 51 when a bias voltage (voltage) is applied to the light incident surface of the substrate 61. Figure 2 The structure of the pixel 51 of B in

[0437] is basically the same as the structure of the pixel 51 shown in Figure 27 , but a P+ semiconductor region 601 is newly formed and added at the interface on the light incident surface side of the substrate 61. Figure 27 Figure 27 By applying a voltage of 0 V or less (negative bias voltage) to the P+ semiconductor region 601 formed at the interface on the light incident surface side of the substrate 61 from the inside or outside of the pixel array unit 20, the electric field in the Z direction is strengthened.

[0438] The arrow in the substrate 61 of the pixel 51 of B in

[0439] (14th Embodiment)

[0440] (Example of Pixel Structure)

[0441] Furthermore, in order to improve the sensitivity of pixel 51 with respect to infrared rays, a large-area reflection member may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0442] In such a case, the pixel 51 is configured as, for example, [[ID=2 shown. In addition, the parts corresponding to the case of ​ are denoted by the same reference numerals, and the description thereof is appropriately omitted. ​ The structure of the pixel 51 shown in

[0443] ​ differs from the pixel 51 of ​ in that a reflection member 631 is provided on the surface of the substrate 61 opposite to the light incident surface, and is the same as the pixel 51 of ​ in other respects.

[0444] In the example of ​ a reflection member 631 that reflects infrared light is provided so as to cover the entire surface of the substrate 61 opposite to the light incident surface.

[0445] The reflection member 631 may be any member as long as it has a high reflectance for infrared light. For example, metals such as copper and aluminum provided in the multilayer wiring layer laminated on the surface of the substrate 61 opposite to the light incident surface may be used as the reflection member 631, or a reflection structure such as polysilicon or an oxide film may be formed on the surface of the substrate 61 opposite to the light incident surface as the reflection member 631.

[0446] In this way, by providing the reflection member 631 in the pixel 51, infrared light that enters the substrate 61 from the light incident surface via the on-chip lens 62 and is transmitted through the substrate 61 without being photoelectrically converted in the substrate 61 can be reflected by the reflection member 631 and enter the substrate 61 again. As a result, the amount of infrared light that is photoelectrically converted in the substrate 61 can be increased, and the quantum efficiency (QE), that is, the sensitivity of the pixel 51 with respect to infrared light, can be improved.

[0447] (Fifteenth Embodiment)

[0448] (Example of Pixel Structure)

[0449] Furthermore, in order to suppress the erroneous detection of light in adjacent pixels, a large-area light-shielding member may be provided on the surface of the substrate 61 opposite to the light incident surface.

[0450] In such a case, the pixel 51 can be configured, for example, by replacing the reflection member 631 shown in ​ with a light-shielding member. That is, in ​In the pixel 51 shown, a reflection member 631 that covers the entire surface of the substrate 61 on the side opposite to the light incident surface is provided as a light-shielding member 631' that blocks infrared light. The light-shielding member 631' is replaced by the reflection member 631 of the pixel 51 of ​ .

[0451] As long as the light-shielding rate of the infrared light is high, the light-shielding member 631' can be any member. For example, metals such as copper and aluminum in the multilayer wiring layer provided on the surface of the substrate 61 opposite to the light incident surface can be used as the light-shielding member 631', or a light-shielding structure such as polysilicon or an oxide film can be formed on the surface of the substrate 61 opposite to the light incident surface as the light-shielding member 631'.

[0452] In this way, by providing the light-shielding member 631' on the pixel 51, it is possible to suppress infrared light that is incident into the substrate 61 from the light incident surface via the on-chip lens 62, is not photoelectrically converted in the substrate 61, and transmits through the substrate 61 from scattering in the wiring layer and incident on adjacent pixels. Thereby, it is possible to prevent light from being erroneously detected in adjacent pixels.

[0453] In addition, the light-shielding member 631' can also serve as the reflection member 631, for example, by being formed of a material containing a metal.

[0454] (Sixteenth Embodiment)

[0455] (Example of Pixel Structure)

[0456] Furthermore, instead of the oxide film 64 in the substrate 61 of the pixel 51, a P-well region formed of a P-type semiconductor region can be provided.

[0457] In such a case, the pixel 51 is configured as shown in ​ . In addition, the parts corresponding to those in ​ are labeled with the same reference numerals, and their descriptions are appropriately omitted. ​

[0458] ​ The structure of the pixel 51 shown is different from that of the pixel 51 shown in ​ in that a P-well region (Pwell) 671, a separation part 672-1, and a separation part 672-2 are provided instead of the oxide film 64, and the other aspects are the same as those of the pixel 51 in ​ .

[0459] In ​In the example, a P-well region (Pwell) 671 formed of a P-type semiconductor region is formed at the center of the inner side of the surface of the substrate 61 opposite to the light incident surface, that is, the lower surface in the figure. In addition, a separation portion 672-1 for separating these regions is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 for separating these regions is also formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. In ​ In the pixel 51 shown, the P− semiconductor region 74 is a wider region in the upward direction in the figure than the N− semiconductor region 72.

[0460] (The seventeenth embodiment)

[0461] (Example of pixel structure)

[0462] In addition to the oxide film 64 in the substrate 61 of the pixel 51, a P-well region formed of a P-type semiconductor region may be provided.

[0463] In such a case, the pixel 51 is configured as shown in, for example, ​ In addition, the same reference numerals are assigned to the corresponding portions in ​ as those in ​ , and the description thereof is appropriately omitted.

[0464] ​ The structure of the pixel 51 shown in ​ is different from the pixel 51 shown in ​ in that a new P-well region 701 is provided, and other aspects are the same as the pixel 51 structure in ​ . That is, in the example of ​ , a P-well region 701 formed of a P-type semiconductor region is formed above the oxide film 64 in the substrate 61.

[0465] As described above, according to the present invention, by configuring the CAPD sensor to have a back-illuminated structure, characteristics such as pixel sensitivity can be improved.

[0466] (Example of equivalent circuit structure of pixel)

[0467] ​ The equivalent circuit of the pixel 51 is shown.

[0468] The pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplification transistor 724A, and a selection transistor 725A with respect to a signal extraction portion 65-1 including the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1.

[0469] In addition, pixel 51 includes transfer transistor 721B, FD 722B, reset transistor 723B, amplifying transistor 724B, and selection transistor 725B for signal extraction section 65-2 including N+ semiconductor region 71-2, P+ semiconductor region 73-2, etc.

[0470] Tap drive section 21 applies a prescribed voltage MIX0 (first voltage) to P+ semiconductor region 73-1 and a prescribed voltage MIX1 (second voltage) to P+ semiconductor region 73-2. In the above example, one of voltage MIX0 and MIX1 is 1.5V and the other is 0V. P+ semiconductor regions 73-1 and 73-2 are voltage application sections to which the first voltage or the second voltage is applied.

[0471] N+ semiconductor regions 71-1 and 71-2 are charge detection sections that detect charges generated by photoelectric conversion of light incident on substrate 61 and accumulate them.

[0472] Transfer transistor 721A becomes conductive in response to the drive signal TRG supplied to the gate electrode becoming active, and thereby transfers the charge accumulated in N+ semiconductor region 71-1 to FD 722A. Transfer transistor 721B becomes conductive in response to the drive signal TRG supplied to the gate electrode becoming active, and thereby transfers the charge accumulated in N+ semiconductor region 71-2 to FD 722B.

[0473] FD 722A temporarily holds charge DET0 supplied from N+ semiconductor region 71-1. FD 722B temporarily holds charge DET1 supplied from N+ semiconductor region 71-2. FD 722A corresponds to FD section A described with reference to ​ FD section B corresponds to FD 722B.

[0474] Reset transistor 723A becomes conductive in response to the drive signal RST supplied to the gate electrode becoming active, and thereby resets the potential of FD 722A to a prescribed level (power supply voltage VDD). Reset transistor 723B becomes conductive in response to the drive signal RST supplied to the gate electrode becoming active, and thereby resets the potential of FD 722B to a prescribed level (power supply voltage VDD). In addition, when reset transistors 723A and 723B are made active, transfer transistors 721A and 721B also become active at the same time.

[0475] The amplifying transistor 724A is connected to the vertical signal line 29A via the source through the selection transistor 725A, forming a load MOS and a source follower circuit of the constant current source circuit section 726A connected to one end of the vertical signal line 29A. The amplifying transistor 724B is connected to the vertical signal line 29B via the source through the selection transistor 725B, forming a load MOS and a source follower circuit of the constant current source circuit section 726B connected to one end of the vertical signal line 29B.

[0476] The selection transistor 725A is connected between the source of the amplifying transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725A becomes conductive in response thereto, and outputs the pixel signal output from the amplifying transistor 724A to the vertical signal line 29A.

[0477] The selection transistor 725B is connected between the source of the amplifying transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725B becomes conductive in response thereto, and outputs the pixel signal output from the amplifying transistor 724B to the vertical signal line 29B.

[0478] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplifying transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by the vertical drive unit 22, for example.

[0479] (Another equivalent circuit structure example of the pixel)

[0480] ​ Shows another equivalent circuit of the pixel 51.

[0481] In ​ For the part corresponding to ​ The same reference numerals are assigned, and the description thereof is appropriately omitted.

[0482] ​ For the equivalent circuit of ​ For the equivalent circuit of

[0483] Specifically, an additional capacitor 727 is connected between the transfer transistor 721A and the FD 722A via a switching transistor 728A, and an additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B via a switching transistor 728B.

[0484] The switching transistor 728A becomes conductive in response to the driving signal FDG supplied to the gate electrode becoming active, thereby connecting the additional capacitor 727A to FD722A. The switching transistor 728B becomes conductive in response to the driving signal FDG supplied to the gate electrode becoming active, thereby connecting the additional capacitor 727B to FD722B.

[0485] For example, when the incident light has a large amount, i.e., at high illuminance, the vertical drive unit 22 activates the switching transistors 728A and 728B, connects FD722A and the additional capacitor 727A, and connects FD722B and the additional capacitor 727B. Thereby, more charges can be accumulated at high illuminance.

[0486] On the other hand, when the incident light has a small amount, i.e., at low illuminance, the vertical drive unit 22 deactivates the switching transistors 728A and 728B, and disconnects the additional capacitors 727A and 727B from FD722A and 722B, respectively.

[0487] As ​ shown in the equivalent circuit, the additional capacitor 727 can be omitted, but by providing the additional capacitor 727 and using it separately according to the incident light amount, a high dynamic range can be ensured.

[0488] (Configuration example of voltage supply lines)

[0489] Next, with reference to ​ , the configuration of the voltage supply lines for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the voltage application unit for the signal extraction unit 65 of each pixel 51 will be described. ​ And ​ The voltage supply line 741 shown corresponds to the voltage supply line 30 shown in ​ .

[0490] In addition, in ​ and ​ , a circular structure shown in ​ is used to illustrate the structure of the signal extraction unit 65 of each pixel 51, but of course, other structures are also possible.

[0491] ​ A in

[0492] is a top view showing a first configuration example of the voltage supply lines. In the first configuration example, with respect to a plurality of pixels 51 arranged in a two-dimensional matrix, the voltage supply lines 741-1 or 741-2 are arranged along the vertical direction between two horizontally adjacent pixels (boundaries).

[0493] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, which is one of the two signal extraction units 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, which is the other of the two signal extraction units 65 in the pixel 51.

[0494] In this first configuration example, two voltage supply lines 741-1 and 741-2 are arranged in two pixel columns. Therefore, in the pixel array unit 20, the number of arranged voltage supply lines 741 is substantially equal to the number of columns of the pixels 51.

[0495] ​ B is a top view showing a second configuration example of the voltage supply line.

[0496] In the second configuration example, two voltage supply lines 741-1 and 741-2 are arranged along the vertical direction with respect to one pixel column of the plurality of pixels 51 arranged in a matrix-like two-dimensional manner.

[0497] The voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, which is one of the two signal extraction units 65 in the pixel 51. The voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, which is the other of the two signal extraction units 65 in the pixel 51.

[0498] In this second configuration example, two voltage supply lines 741-1 and 741-2 are arranged with respect to one pixel column. Therefore, four voltage supply lines 741 are arranged with respect to two pixel columns. In the pixel array unit 20, the number of arranged voltage supply lines 741 is approximately twice the number of columns of the pixels 51.

[0499] In ​ In the configuration examples of A and B, the structure in which the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1 and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2 is a Periodic configuration (periodic configuration) that is periodically repeated with respect to the pixels arranged in the vertical direction.

[0500] In ​ In the first configuration example of A, the number of the voltage supply lines 741-1 and 741-2 arranged with respect to the pixel array unit 20 can be reduced.

[0501] ​In the second configuration example of B compared to the first configuration example, although the number of wirings increases, the number of signal extraction units 65 connected to one voltage supply line 741 is 1 / 2. Therefore, the load of the wirings can be reduced, which is effective when driving at high speed and when the total number of pixels in the pixel array unit 20 is large.

[0502] ​ A of [the figure] is a top view showing a third configuration example of the voltage supply line.

[0503] The third configuration example is the same as ​ the first configuration example of A of [the figure], and is an example in which two voltage supply lines 741-1 and 741-2 are arranged with respect to two pixel columns.

[0504] The third configuration example is different from ​ the first configuration example of A of [the figure] in that, among two pixels arranged in the vertical direction, the connection destinations of the signal extraction units 65-1 and 65-2 are different.

[0505] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2. However, in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1.

[0506] ​ B of [the figure] is a top view showing a fourth configuration example of the voltage supply line.

[0507] The fourth configuration example is the same as ​ the second configuration example of B of [the figure], and is an example in which two voltage supply lines 741-1 and 741-2 are arranged with respect to two pixel columns.

[0508] The fourth configuration example is different from ​ the second configuration example of B of [the figure] in that, among two pixels arranged in the vertical direction, the connection destinations of the signal extraction units 65-1 and 65-2 are different.

[0509] Specifically, for example, in a certain pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2. However, in the pixel 51 below or above it, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1.

[0510] In ​ In the third configuration example of A, the number of voltage supply lines 741-1 and 741-2 arranged relative to the pixel array unit 20 can be reduced.

[0511] ​ In the fourth configuration example of B compared with the third configuration example, although the number of wiring lines increases, the number of signal extraction units 65 connected to one voltage supply line 741 is 1 / 2. Therefore, the load of the wiring can be reduced, which is effective when driving at high speed and when the total number of pixels in the pixel array unit 20 is large.

[0512] ​ The configuration examples of A and B are both Mirror configurations (mirror configurations) in which the connection destinations of two pixels adjacent in the vertical (up and down) direction are mirror-inverted.

[0513] In the Periodic configuration, as shown in ​ A of, different voltages are applied to two signal extraction units 65 adjacent across the pixel boundary. Therefore, charge exchange occurs between adjacent pixels. Therefore, the charge transfer efficiency is better than that of the Mirror configuration, but the crosstalk characteristics between adjacent pixels are worse than those of the Mirror configuration.

[0514] On the other hand, in the Mirror configuration, as shown in ​ B of, the same voltage is applied to two signal extraction units 65 adjacent across the pixel boundary. Therefore, the charge exchange between adjacent pixels is suppressed. Therefore, the charge transfer efficiency is worse than that of the Periodic configuration, but the crosstalk characteristics between adjacent pixels are better than those of the Periodic configuration.

[0515] (Cross-sectional structure of multiple pixels of the fourteenth embodiment)

[0516] In ​ In the cross-sectional structure of the pixel shown in etc., the illustration of the multilayer wiring layer formed on the surface side of the substrate 61 opposite to the light incident surface is omitted.

[0517] Therefore, for the above several embodiments, cross-sectional views of adjacent multiple pixels are shown without omitting the multilayer wiring layer.

[0518] First, in ​ and ​ show ​ The cross-sectional view of multiple pixels of the fourteenth embodiment shown.

[0519] ​ The fourteenth embodiment shown is a structure of a pixel having a large-area reflection member 631 on the side of the substrate 61 opposite to the light incident surface.

[0520] ​ Corresponding to ​ The cross-sectional view at the B-B' line corresponding to ​ Corresponding to ​ The cross-sectional view at the A-A' line. In addition ​ The cross-sectional view at the C-C' line corresponding to ​ Can also be as shown

[0521] As shown ​ In each pixel 51, an oxide film 64 is formed in the central portion, and a signal extraction portion 65-1 and a signal extraction portion 65-2 are respectively formed on both sides of the oxide film 64

[0522] In the signal extraction portion 65-1, with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center, in a manner surrounding the periphery of these P+ semiconductor region 73-1 and P- semiconductor region 74-1, an N+ semiconductor region 71-1 and an N- semiconductor region 72-1 are formed. The P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-1 is disposed above the P+ semiconductor region 73-1 (on the side of the on-chip lens 62) so as to cover the P+ semiconductor region 73-1, and the N- semiconductor region 72-1 is disposed above the N+ semiconductor region 71-1 (on the side of the on-chip lens 62) so as to cover the N+ semiconductor region 71-1. In other words, the P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are disposed on the side of the multilayer wiring layer 811 within the substrate 61, and the N- semiconductor region 72-1 and the P- semiconductor region 74-1 are disposed on the side of the on-chip lens 62 within the substrate 61. In addition, between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1, a separation portion 75-1 for separating these regions is formed through an oxide film or the like

[0523] In the signal extraction section 65-2, N+ semiconductor regions 71-2 and N− semiconductor regions 72-2 are formed in such a manner as to surround the P+ semiconductor region 73-2 and the P− semiconductor region 74-2 with the P+ semiconductor region 73-2 and the P− semiconductor region 74-2 at the center. The P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are in contact with the multilayer wiring layer 811. The P− semiconductor region 74-2 is disposed above the P+ semiconductor region 73-2 (on the side of the on-chip lens 62) so as to cover the P+ semiconductor region 73-2, and the N− semiconductor region 72-2 is disposed above the N+ semiconductor region 71-2 (on the side of the on-chip lens 62) so as to cover the N+ semiconductor region 71-2. In other words, the P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are disposed on the side of the multilayer wiring layer 811 within the substrate 61, and the N− semiconductor region 72-2 and the P− semiconductor region 74-2 are disposed on the side of the on-chip lens 62 within the substrate 61. Further, a separation section 75-2 for separating these regions is also formed between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 by an oxide film or the like.

[0524] An oxide film 64 is also formed between the N+ semiconductor region 71-1 of the signal extraction section 65-1 of a prescribed pixel 51, which is a boundary region between adjacent pixels 51, and the N+ semiconductor region 71-2 of the signal extraction section 65-2 of the adjacent pixel 51.

[0525] On the light incident surface side of the substrate 61 ( ​ and ​ the upper surface in), an interface of a fixed charge film 66 is formed.

[0526] As ​ shown, when the on-chip lens 62 formed for each pixel on the light incident surface side of the substrate 61 is divided in the height direction into a rising portion 821 where the thickness uniformly increases over the entire region within the pixel and a curved surface portion 822 where the thickness varies according to the position within the pixel, the thickness of the rising portion 821 is formed thinner than the thickness of the curved surface portion 822. The thicker the thickness of the rising portion 821, the more likely the inclined incident light is to be reflected by the inter-pixel light shielding film 63. Therefore, by forming the thickness of the rising portion 821 thin, the inclined incident light can also be taken into the substrate 61. Further, the thicker the thickness of the curved surface portion 822, the more the incident light can be condensed to the pixel center.

[0527] On the side of the substrate 61 opposite to the light incident surface side where the on-chip lens 62 is formed for each pixel, a multilayer wiring layer 811 is formed. In other words, the substrate 61 as a semiconductor layer is disposed between the on-chip lens 62 and the multilayer wiring layer 811. The multilayer wiring layer 811 is composed of five metal films M1 to M5 and an interlayer insulating film 812 therebetween. Additionally, in ​In this case, the outermost metal film M5 among the five metal films M1 to M5 of the multilayer wiring layer 811 is located in an invisible part and is not shown in the drawing, but is shown in a cross-sectional view observed from a direction different from the cross-sectional view of ​ i.e., ​ In the drawing.

[0528] As ​ shown, a pixel transistor Tr is formed in a pixel boundary region at an interface portion of the multilayer wiring layer 811 with the substrate 61. The pixel transistor Tr is ​ and ​ any one of the transfer transistor 721, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 shown in

[0529] In the metal film M1 closest to the substrate 61 among the five metal films M1 to M5 of the multilayer wiring layer 811, a power supply line 813 for supplying a power supply voltage, a voltage application wiring 814 for applying a prescribed voltage to the P+ semiconductor regions 73-1 or 73-2, and a reflection member 815 as a member for reflecting incident light are included. In ​ the metal film M1, wirings other than the power supply line 813 and the voltage application wiring 814 become the reflection member 815, and some reference numerals are omitted to prevent the drawing from becoming complicated. The reflection member 815 is a virtual wiring provided for the purpose of reflecting incident light and corresponds to ​ the reflection member 631 shown in ​ The reflection member 815 is disposed below the N+ semiconductor regions 71-1 and 71-2 so as to overlap the N+ semiconductor regions 71-1 and 71-2 in a plan view. Further, in the case where the light-shielding member 631' of the fifteenth embodiment is provided instead of ​ the reflection member 631 of the fourteenth embodiment shown in

[0530] a part of the reflection member 815 in ​ becomes the light-shielding member 631'.

[0531] In addition, in the metal film M1, a charge extraction wiring (not shown in ​ ) for connecting the N+ semiconductor region 71 and the transfer transistor 721 is also formed in order to transfer the charge accumulated in the N+ semiconductor region 71 to the FD722.

[0531] In addition, in this example, the reflection member 815 (reflection member 631) and the charge extraction wiring are disposed in the same layer of the metal film M1, but are not necessarily limited to being disposed in the same layer.

[0532] In the metal film M2 of the second layer starting from the substrate 61 side, for example, a voltage application wiring 816 connected to the voltage application wiring 814 of the metal film M1, control lines 817 for transmitting drive signals TRG, RST, selection signals SEL, drive signals FDG, etc., and ground lines are formed. In addition, FD722B and an additional capacitor 727A are formed in the metal film M2.

[0533] In the metal film M3 of the third layer starting from the substrate 61 side, for example, vertical signal lines 29, VSS wirings for shielding, etc. are formed.

[0534] In the metal films M4 and M5 of the fourth and fifth layers starting from the substrate 61 side, for example, voltage supply lines 741-1 and 741-2 for applying a prescribed voltage MIX0 or MIX1 to P+ semiconductor regions 73-1 and 73-2 of a voltage application section that is a signal extraction section 65 ​ 、 ​ ) are formed.

[0535] In addition, regarding the planar configuration of the five metal films M1 to M5 of the multilayer wiring layer 811, reference will be made to Fig.42 and Fig.43 and will be described later.

[0536] (Cross-sectional structure of multiple pixels of the ninth embodiment)

[0537] Fig.38 is a cross-sectional view showing the pixel structure of the ninth embodiment shown for multiple pixels without omitting the multilayer wiring layer. Fig. 22 The ninth embodiment shown in

[0538] Fig. 22 is a structure of a pixel in which a long groove (trench) is formed from the back surface (light incident surface) side of the substrate 61 to a prescribed depth in a pixel boundary portion within the substrate 61 and a light shielding film is buried to form a separation region 441.

[0539] Other structures including signal extraction sections 65-1 and 65-2 and the five metal films M1 to M5 of the multilayer wiring layer 811 are the same as the structure shown in Fig.36 .

[0540] (Cross-sectional structure of multiple pixels of modification 1 of the ninth embodiment)

[0541] Fig.39 is a cross-sectional view showing the pixel structure of modification 1 of the ninth embodiment shown for multiple pixels without omitting the multilayer wiring layer. Fig.23 The structure shown in

[0542] Fig.23Modification Example 1 of the Ninth Embodiment shown has a structure of pixels including a separation region 471 that penetrates the entire substrate 61 at the pixel boundary portion within the substrate 61.

[0543] Other structures such as the five-layer metal films M1 to M5 including the signal extraction portions 65-1 and 65-2 and the multilayer wiring layer 811 are the same as Fig.36 the structure shown.

[0544] (Cross-sectional structure of multiple pixels of the Sixteenth Embodiment)

[0545] Fig.40 This is a cross-sectional view showing the pixel structure of the Sixteenth Embodiment for multiple pixels without omitting the multilayer wiring layer. Fig.29 shown.

[0546] Fig.29 The Sixteenth Embodiment shown has a structure in which a P-well region 671 is provided in the central portion on the side opposite to the light incident surface within the substrate 61, that is, the inner side of the lower surface in the figure. In addition, a separation portion 672-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 is also formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. A P-well region 671 is also formed at the pixel boundary portion of the lower surface of the substrate 61.

[0547] Other structures such as the five-layer metal films M1 to M5 including the signal extraction portions 65-1 and 65-2 and the multilayer wiring layer 811 are the same as Fig.36 the structure shown.

[0548] (Cross-sectional structure of multiple pixels of the Tenth Embodiment)

[0549] Fig.41 This is a cross-sectional view showing the pixel structure of the Tenth Embodiment for multiple pixels without omitting the multilayer wiring layer. Fig.24 shown.

[0550] Fig.24 The Tenth Embodiment shown has a structure of pixels in which a substrate 501 with a thick substrate thickness is provided instead of the substrate 61.

[0551] Other structures such as the five-layer metal films M1 to M5 including the signal extraction portions 65-1 and 65-2 and the multilayer wiring layer 811 are the same as Fig.36 the structure shown.

[0552] (Planar arrangement example of the five-layer metal films M1 to M5)

[0553] Next, with reference to Fig.42 and Fig.43 for Figure 36 to Figure 41An example of the planar configuration of the five-layer metal films M1 to M5 of the multi-layer wiring layer 811 shown will be described.

[0554] Fig.42 A in [Figure] represents an example of the planar configuration of the first metal film M1 among the five-layer metal films M1 to M5 of the multi-layer wiring layer 811.

[0555] Fig.42 B in [Figure] represents an example of the planar configuration of the second metal film M2 among the five-layer metal films M1 to M5 of the multi-layer wiring layer 811.

[0556] Fig.42 C in [Figure] represents an example of the planar configuration of the third metal film M3 among the five-layer metal films M1 to M5 of the multi-layer wiring layer 811.

[0557] Fig.43 A in [Figure] represents an example of the planar configuration of the fourth metal film M4 among the five-layer metal films M1 to M5 of the multi-layer wiring layer 811.

[0558] Fig.43 B in [Figure] represents an example of the planar configuration of the fifth metal film M5 among the five-layer metal films M1 to M5 of the multi-layer wiring layer 811.

[0559] In addition, in Fig.42 A to C of Fig.43 A and B of Fig.11 the region of the pixel 51 and the regions of the signal extraction portions 65-1 and 65-2 having the octagonal shape shown are indicated by dashed lines.

[0560] In Fig.42 A to C of Fig.43 A and B of

[0561] As Fig.42 shown in A of [Figure], a reflection member 631 that reflects infrared light is formed on the metal film M1, which is the first layer of the multi-layer wiring layer 811. In the region of the pixel 51, two reflection members 631 are respectively formed with respect to the signal extraction portions 65-1 and 65-2, and the two reflection members 631 of the signal extraction portion 65-1 and the two reflection members 631 of the signal extraction portion 65-1 are formed symmetrically with respect to the vertical direction.

[0562] In addition, a pixel transistor wiring region 831 is disposed between the reflection members 631 of adjacent pixels 51 in the horizontal direction. In the pixel transistor wiring region 831, wirings are formed to connect the pixel transistors Tr such as the transfer transistor 721, the reset transistor 723, the amplification transistor 724, or the selection transistor 725. The wirings for the pixel transistors Tr are also symmetrically formed in the vertical direction with respect to the intermediate line (not shown) between the two signal extraction portions 65-1 and 65-2.

[0563] In addition, wirings such as a ground line 832, a power supply line 833, and a ground line 834 are formed between the reflection members 631 of adjacent pixels 51 in the vertical direction. These wirings are also symmetrically formed in the vertical direction with respect to the intermediate line between the two signal extraction portions 65-1 and 65-2.

[0564] In this way, the first-layer metal film M1 is symmetrically disposed in the regions on the signal extraction portion 65-1 side and the signal extraction portion 65-2 side within the pixel. As a result, the wiring loads can be adjusted equally in the signal extraction portions 65-1 and 65-2. Thereby, the driving deviation between the signal extraction portions 65-1 and 65-2 is reduced.

[0565] In the first-layer metal film M1, by forming a large-area reflection member 631 below the signal extraction portions 65-1 and 65-2 formed on the substrate 61, infrared light that is incident into the substrate 61 via the on-chip lens 62 and transmits through the substrate 61 without being photoelectrically converted within the substrate 61 can be reflected by the reflection member 631 and incident into the substrate 61 again. As a result, the amount of infrared light that is photoelectrically converted within the substrate 61 can be increased, and the quantum efficiency (QE), that is, the sensitivity of the pixel 51 to infrared light, can be improved.

[0566] On the other hand, in the first-layer metal film M1, when a light-shielding member 631' is disposed in the same region as the reflection member 631 instead of the reflection member 631, infrared light that is incident into the substrate 61 from the light incident surface via the on-chip lens 62 and transmits through the substrate 61 without being photoelectrically converted within the substrate 61 can be suppressed from scattering in the wiring layer and incident on adjacent pixels. Thereby, light can be prevented from being erroneously detected in adjacent pixels.

[0567] As Fig.42 shown in B, in the second-layer metal film M2 which is the multi-layer wiring layer 811, a control line region 851 is disposed at a position between the signal extraction portions 65-1 and 65-2, and control lines 841 to 844 and the like for transmitting a prescribed signal in the horizontal direction are formed in the control line region 851. The control lines 841 to 844 are, for example, lines for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, or a drive signal FDG.

[0568] By disposing the control line region 851 between the two signal extraction portions 65, the influences on the signal extraction portions 65-1 and 65-2 become equal, and the driving deviation between the signal extraction portions 65-1 and 65-2 can be reduced.

[0569] In addition, in a specified region different from the control line region 851 of the metal film M2 of the second layer, a capacitor region 852 in which the FD722B and the additional capacitor 727A are formed is disposed. In the capacitor region 852, by forming the metal film M2 in a comb shape, the FD722B or the additional capacitor 727A is constituted.

[0570] By disposing the FD722B or the additional capacitor 727A in the metal film M2 of the second layer, the pattern of the FD722B or the additional capacitor 727A can be freely disposed according to the desired wiring capacitance in design, and the design freedom can be improved.

[0571] As Fig.42 shown in C, in the metal film M3 of the third layer which is the multilayer wiring layer 811, at least a vertical signal line 29 for transmitting the pixel signal output from each pixel 51 to the column processing unit 23 is formed. In order to improve the readout speed of the pixel signal, three or more vertical signal lines 29 can be disposed with respect to one pixel column. In addition, in addition to the vertical signal line 29, a shield wiring can be disposed to reduce the coupling capacitance.

[0572] In the metal film M4 of the fourth layer and the metal film M5 of the fifth layer which are the multilayer wiring layer 811, voltage supply lines 741-1 and 741-2 for applying a specified voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the signal extraction portion 65 of each pixel 51 are formed.

[0573] Fig.43 The metal films M4 and M5 shown in A and B of Fig.33 show the case of the voltage supply line 741 of the first configuration example shown in A of

[0574] The voltage supply line 741-1 of the metal film M4 is connected to the voltage application wiring 814 of the metal film M1 (for example, Fig.36 ) via the metal films M3 and M2, and the voltage application wiring 814 is connected to the P+ semiconductor region 73-1 of the signal extraction portion 65-1 of the pixel 51. Similarly, the voltage supply line 741-2 of the metal film M4 is connected to the voltage application wiring 814 of the metal film M1 (for example, Fig.36 ) via the metal films M3 and M2, and the voltage application wiring 814 is connected to the P+ semiconductor region 73-2 of the signal extraction portion 65-2 of the pixel 51.

[0575] The voltage supply lines 741-1 and 741-2 of the metal film M5 are connected to the tap driving unit 21 around the pixel array unit 20. The voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 are connected at a specified position of both metal films in the planar region through a via hole (not shown) or the like. The specified voltage MIX0 or MIX1 from the tap driving unit 21 is transmitted in the voltage supply lines 741-1 and 741-2 of the metal film M5, supplied to the voltage supply lines 741-1 and 741-2 of the metal film M4, and supplied from the voltage supply lines 741-1 and 741-2 to the voltage application wiring 814 of the metal film M1 via the metal films M3 and M2.

[0576] By using the light-receiving element 1 as a back-illuminated CAPD sensor, for example, as shown in A and B of Fig.43 , the voltage supply lines 741-1 and 741-2 for applying the specified voltage MIX0 or MIX1 to the signal extraction units 65 of each pixel 51 can be arranged vertically, etc., and the wiring width and layout of the driving wiring can be freely designed. In addition, it can also be a wiring suitable for high-speed driving or a wiring considering load reduction.

[0577] (Example of planar configuration of pixel transistors)

[0578] Fig.44 is a top view showing the coincidence of the metal film M1 of the first layer shown in A of Fig.42 with the polysilicon layer such as the gate electrode of the pixel transistor Tr formed thereon.

[0579] Fig.44 A of Fig.44 is a top view showing the coincidence of the metal film M1 of C of Fig.44 with the polysilicon layer of B of Fig.44 B of Fig.44 is a top view of only the polysilicon layer, Fig.44 C of Fig.42 is a top view of only the metal film M1.

[0580] As described with reference to Fig.42 A, a pixel transistor wiring region 831 is formed between the reflection members 631 of each pixel.

[0581] The pixel transistors Tr corresponding to the signal extraction units 65-1 and 65-2 are arranged in the pixel transistor wiring region 831 as shown in B of Fig.44 for example.

[0582] In Fig.44In B, with respect to the center line (not shown) between the two signal extraction portions 65-1 and 65-2 as a reference, the gate electrodes of the reset transistors 723A and 723B, the transfer transistors 721A and 721B, the switching transistors 728A and 728B, the selection transistors 725A and 725B, and the amplification transistors 724A and 724B are formed starting from the side closer to the center line.

[0583] Connect Fig.44 The wirings between the pixel transistors Tr of the metal film M1 shown in C are also symmetrically formed in the vertical direction with respect to the center line (not shown) between the two signal extraction portions 65-1 and 65-2.

[0584] In this way, by symmetrically arranging the plurality of pixel transistors Tr in the pixel transistor wiring region 831 in the region on the signal extraction portion 65-1 side and the region on the signal extraction portion 65-2 side, the driving deviation between the signal extraction portions 65-1 and 65-2 can be reduced.

[0585] (Modification example of the reflection member 631)

[0586] Next, with reference to Fig.45 And Fig.46 A modification example of the reflection member 631 formed on the metal film M1 will be described.

[0587] In the above example, as shown in Fig.42 A of, a large-area reflection member 631 is arranged in the region around the signal extraction portion 65 within the pixel 51.

[0588] In contrast, the reflection member 631 can also be arranged in a lattice-shaped pattern, for example, as shown in Fig.45 A of. In this way, by forming the reflection member 631 in a lattice-shaped pattern, the pattern anisotropy can be eliminated, and the XY anisotropy of the reflection ability can be reduced. In other words, by forming the reflection member 631 in a lattice-shaped pattern, the reflection of incident light to a partial region of the deflection can be reduced, and isotropic reflection can be facilitated, so the ranging accuracy is improved.

[0589] Alternatively, in addition, the reflection member 631 can also be arranged in a stripe-shaped pattern, for example, as shown in Fig.45 B of. In this way, by forming the reflection member 631 in a stripe-shaped pattern, the pattern of the reflection member 631 can also be used as a wiring capacitance, so a structure that maximizes the dynamic range can be realized.

[0590] In addition, Fig.45 B of is an example of a stripe shape in the vertical direction, but it can also be a stripe shape in the horizontal direction.

[0591] Alternatively, in addition, the reflection member 631 is configured only in the pixel center region, more specifically, only between the two signal extraction portions 65, as shown in C of Fig.45 . In this way, by forming the reflection member 631 in the pixel center region and not forming the reflection member 631 at the pixel ends, the effect of improving the sensitivity of the reflection member 631 to the pixel center region can be obtained, and the component reflected to adjacent pixels in the case of obliquely incident light can be suppressed, and a structure that emphasizes the suppression of crosstalk can be realized. Fig.45 In addition, as shown in A of Fig.46 , the reflection member 631 may also have a part of the pattern configured in a comb shape, whereby a part of the metal film M1 is allocated to the wiring capacitance of the FD722 or the additional capacitor 727. In A of Fig.46 , the comb shapes in the regions 861 to 864 surrounded by the solid-line circles constitute at least a part of the FD722 or the additional capacitor 727. The FD722 or the additional capacitor 727 may also be appropriately and separately arranged on the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflection member 631, the FD722 or the additional capacitor 727.

[0592] In addition, as shown in A of Fig.46 , the reflection member 631 may also have a part of the pattern configured in a comb shape, whereby a part of the metal film M1 is allocated to the wiring capacitance of the FD722 or the additional capacitor 727. In A of Fig.46 , the comb shapes in the regions 861 to 864 surrounded by the solid-line circles constitute at least a part of the FD722 or the additional capacitor 727. The FD722 or the additional capacitor 727 may also be appropriately and separately arranged on the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflection member 631, the FD722 or the additional capacitor 727. Fig.46 In addition, as shown in A of Fig.46 , the reflection member 631 may also have a part of the pattern configured in a comb shape, whereby a part of the metal film M1 is allocated to the wiring capacitance of the FD722 or the additional capacitor 727. In A of Fig.46 , the comb shapes in the regions 861 to 864 surrounded by the solid-line circles constitute at least a part of the FD722 or the additional capacitor 727. The FD722 or the additional capacitor 727 may also be appropriately and separately arranged on the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflection member 631, the FD722 or the additional capacitor 727. Fig.46 In A of Fig.46 , the comb shapes in the regions 861 to 864 surrounded by the solid-line circles constitute at least a part of the FD722 or the additional capacitor 727. The FD722 or the additional capacitor 727 may also be appropriately and separately arranged on the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged with good balance in the capacitance of the reflection member 631, the FD722 or the additional capacitor 727.

[0593] Fig.46 B of

[0593] shows the pattern of the metal film M1 in the case where the reflection member 631 is not arranged. In order to increase the amount of infrared light photoelectrically converted in the substrate 61 and improve the sensitivity of the pixel 51, it is preferable to arrange the reflection member 631, but a structure without arranging the reflection member 631 can also be adopted.

[0594] Fig.45 and Fig.46 The configuration examples of the reflection member 631 shown can also be similarly applied to the light shielding member 631'.

[0595] (Example of the substrate structure of the light receiving element)

[0596] Figure 1 The light receiving element 1 of Figure 1 can adopt the substrate structure of any one of A to C of Fig.47 . Fig.47 The light receiving element 1 of Figure 1 can adopt the substrate structure of any one of A to C of Fig.47 .

[0597] Fig.47 A of

[0597] shows an example in which the light receiving element 1 is composed of one semiconductor substrate 911 and the supporting substrate 912 below it.

[0598] In this case, a pixel array region 951 corresponding to the above-described pixel array unit 20, a control circuit 952 for controlling each pixel in the pixel array region 951, and a logic circuit 953 including a signal processing circuit for pixel signals are formed on the upper semiconductor substrate 911.

[0599] The above-mentioned tap driving unit 21, vertical driving unit 22, horizontal driving unit 24, etc. are included in the control circuit 952. The column processing unit 23 that performs AD conversion processing of pixel signals, etc., and the signal processing unit 31 that performs distance calculation processing, calibration processing, etc. for calculating the distance based on the ratio of pixel signals respectively obtained by two or more signal extraction units 65 in the pixel are included in the logic circuit 953.

[0600] Alternatively, in addition, the light-receiving element 1, as Fig.47 shown in B, may be a structure of a first semiconductor substrate 921 in which a pixel array region 951 and a control circuit 952 are formed in layers, and a second semiconductor substrate 922 in which a logic circuit 953 is formed. In addition, the first semiconductor substrate 921 and the second semiconductor substrate 922 are electrically joined by, for example, a through hole and a Cu-Cu metal bond.

[0601] Alternatively, in addition, the light-receiving element 1, as Fig.47 shown in C, may be a structure of a first semiconductor substrate 931 in which only a pixel array region 951 is formed in layers, and a second semiconductor substrate 932 in which a region control circuit 954 that sets a control circuit for controlling each pixel and a signal processing circuit for processing pixel signals in units of one pixel or in units of a region of a plurality of pixels is formed. The first semiconductor substrate 931 and the second semiconductor substrate 932 are electrically joined by, for example, a through hole and a Cu-Cu metal bond.

[0602] As Fig.47 the light-receiving element 1 shown in C, according to the structure in which the control circuit and the signal processing circuit are set in units of one pixel or in units of a region, it is possible to set the optimal driving timing and gain for each divided control unit, and it is possible to obtain optimized distance information regardless of the distance and reflectivity. In addition, since it is possible to calculate the distance information by driving only a part of the region without driving the entire surface of the pixel array region 951, the power consumption can also be suppressed according to the operation mode.

[0603] (Example of noise countermeasures around pixel transistors)

[0604] However, at the boundary portion of the pixels 51 arranged in the horizontal direction in the pixel array portion 20, as Fig.37 shown in the cross-sectional view, pixel transistors Tr such as a reset transistor 723, an amplification transistor 724, and a selection transistor 725 are arranged.

[0605] When the pixel transistor arrangement region of the pixel boundary portion shown in Fig.37 is illustrated in more detail, as Fig.48 shown, pixel transistors Tr such as a reset transistor 723, an amplification transistor 724, and a selection transistor 725 are formed in a P-well region 1011 formed on the surface side of the substrate 61.

[0606] The P-well region 1011 is formed at a prescribed interval in the planar direction with respect to an oxide film 64 such as STI (Shallow Trench Isolation) formed around the N+ semiconductor region 71 in the signal extraction section 65. Further, an oxide film 1012 that also serves as a gate insulating film of the pixel transistor Tr is formed at the back-side interface of the substrate 61.

[0607] At this time, at the back-side interface of the substrate 61, in the gap region 1013 between the oxide film 64 and the P-well region 1011, electrons are likely to accumulate due to the electric potential generated by the positive charges in the oxide film 1012. In the case where there is no electron discharge mechanism, the electrons overflow and diffuse, and are collected in the N-type semiconductor region to become noise.

[0608] Therefore, as Fig.49 shown in A, the P-well region 1021 can be formed to extend in the planar direction until it contacts the adjacent oxide film 64, so that there is no gap region 1013 at the back-side interface of the substrate 61. Thus, it is possible to prevent electrons from accumulating in the Fig.48 gap region 1013 shown, and therefore noise can be suppressed. The impurity concentration of the P-well region 1021 is formed to be higher than the impurity concentration of the P-type semiconductor region 1022 of the substrate 61 that serves as a photoelectric conversion region.

[0609] Alternatively, further, as Fig.49 shown in B, the oxide film 1032 formed around the N+ semiconductor region 71 in the signal extraction section 65 can be extended in the planar direction to the P-well region 1031, thereby forming a structure in which there is no gap region 1013 at the back-side interface of the substrate 61. In this case, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 in the P-well region 1031 are also element-isolated by the oxide film 1033. The oxide film 1033 can be formed of STI, for example, and is formed in the same process as the oxide film 1032.

[0610] According to Fig.49 the structure of A or B, at the back-side interface of the substrate 61, the insulating films (oxide film 64, oxide film 1032) at the boundary portion of the pixel contact the P-well region (P-well region 1021, P-well region 1031), thereby eliminating the gap region 1013. Therefore, it is possible to prevent the accumulation of electrons and suppress noise. Fig.49 The structure of A or B can also be applied to any of the embodiments described in this specification.

[0611] Alternatively, in the case of a structure in which the gap region 1013 is left as it is, by adopting Fig.50 or Fig.51The structure shown can suppress the accumulation of electrons generated in the gap region 1013.

[0612] Fig.50 The figure shows the layout of the oxide film 64, the P-well region 1011, and the gap region 1013 in a top view of a pixel 51 having two taps with two signal extraction portions 65-1 and 65-2 in one pixel arranged two-dimensionally.

[0613] When the pixels arranged two-dimensionally are not separated by STI and DTI (Deep Trench Isolation), as Fig.50 shown, the P-well region 1011 is formed in a column shape connected to a plurality of pixels arranged in the column direction.

[0614] An N-type diffusion layer 1061 for discharging charges can be provided as a drain in the gap region 1013 of the pixel 51 in the dummy pixel region 1052 disposed outside the effective pixel region 1051 of the pixel array unit 20, and electrons are discharged to the N-type diffusion layer 1061. The N-type diffusion layer 1061 is formed at the back-side interface of the substrate 61, and a GND (0V) or a positive voltage is applied to the N-type diffusion layer 1061. Since the electrons generated in the gap region 1013 of each pixel 51 move in the vertical direction (column direction) to the N-type diffusion layer 1061 in the dummy pixel region 1052 and are collected by the N-type diffusion layer 1061 shared by the pixel columns, noise can be suppressed.

[0615] On the other hand, as Fig.51 shown, when the pixels are separated by a pixel separation portion 1071 using STI, DTI, etc., an N-type diffusion layer 1061 can be provided in the gap region 1013 of each pixel 51. As a result, the electrons generated in the gap region 1013 of each pixel 51 are discharged from the N-type diffusion layer 1061, so that noise can be suppressed. Fig.50 and Fig.51 The structure can also be applied to any of the embodiments described in this specification.

[0616] (Noise around the effective pixel region)

[0617] Next, the charge discharge around the effective pixel region will be further described.

[0618] In the outer peripheral portion adjacent to the effective pixel region, for example, there is a light-shielding pixel region in which light-shielding pixels are arranged.

[0619] As Fig.52As shown, in the light-shielding pixel 51X in the light-shielding pixel region, the signal extraction unit 65 and the like are formed in the same manner as the pixel 51 in the effective pixel region. In addition, in the light-shielding pixel 51X in the light-shielding pixel region, an inter-pixel light-shielding film 63 is formed over the entire surface of the pixel region, forming a structure where light cannot enter. In addition, in the light-shielding pixel 51X, a drive signal is not applied in most cases.

[0620] On the other hand, in the light-shielding pixel region adjacent to the effective pixel region, obliquely incident light from the lens, refracted light from the inter-pixel light-shielding film 63, and reflected light from the multilayer wiring layer 811 are incident, generating photoelectrons. Since the generated photoelectrons do not have a discharge destination, they accumulate in the light-shielding pixel region and diffuse into the effective pixel region due to the concentration gradient, mixing with the signal charges to become noise. The noise around the effective pixel region becomes so-called fringing non-uniformity.

[0621] Therefore, as a countermeasure against the noise generated around the effective pixel region, the light-receiving element 1 can set Fig.53 any one of A to D of the charge discharge regions 1101 on the outer periphery of the effective pixel region 1051.

[0622] Fig.53 A to D in are top views showing structural examples of the charge discharge regions 1101 provided on the outer periphery of the effective pixel region 1051.

[0623] In Fig.53 any one of A to D, a charge discharge region 1101 is provided on the outer periphery of the effective pixel region 1051 disposed at the central portion of the substrate 61, and further, an OPB region 1102 is provided outside the charge discharge region 1101. The charge discharge region 1101 is the region with hatched lines between the inner dotted rectangle and the outer dotted rectangle. The OPB region 1102 is a region where an inter-pixel light-shielding film 63 is formed over the entire surface of the region, and OPB pixels that are driven and detect black level signals in the same manner as the pixels 51 in the effective pixel region are arranged. In Fig.53 A to D, the gray-colored regions represent the regions shielded by forming the inter-pixel light-shielding film 63.

[0624] Fig.53 The charge discharge region 1101 in A is composed of an open pixel region 1121 in which open pixels are arranged and a light-shielding pixel region 1122 in which light-shielding pixels 51X are arranged. The open pixels in the open pixel region 1121 are pixels having the same pixel structure as the pixels 51 in the effective pixel region 1051 and are driven in a specified manner. The light-shielding pixels 51X in the light-shielding pixel region 1122 are pixels having the same pixel structure as the pixels 51 in the effective pixel region 1051 and are driven in a specified manner, except that an inter-pixel light-shielding film 63 is formed over the entire surface of the pixel region.

[0625] The opening pixel region 1121 has pixel columns or pixel rows of one or more pixels in each column or each row on the four sides of the outer periphery of the effective pixel region 1051. The light-shielding pixel region 1122 also has pixel columns or pixel rows of one or more pixels in each column or each row on the four sides of the outer periphery of the opening pixel region 1121.

[0626] Fig.53 The charge discharge region 1101 of B is composed of the light-shielding pixel region 1122 in which the light-shielding pixel 51X is arranged and the N-type region 1123 in which the N-type diffusion layer is arranged.

[0627] Fig.54 FIG. is a cross-sectional view in the case where the charge discharge region 1101 is composed of the light-shielding pixel region 1122 and the N-type region 1123.

[0628] The N-type region 1123 is a region in which the entire surface of the region is shielded by the inter-pixel light-shielding film 63, and a high-concentration N-type semiconductor region, that is, an N-type diffusion layer 1131, is formed instead of the signal extraction portion 65 in the P-type semiconductor region 1022 of the substrate 61. A voltage of 0V or a positive voltage is always or intermittently applied from the metal film M1 of the multilayer wiring layer 811 to the N-type diffusion layer 1131. The N-type diffusion layer 1131 can be formed, for example, in the entire region of the P-type semiconductor region 1022 of the N-type region 1123, and is formed in a continuous substantially circular shape when viewed from above, or can be locally formed in the P-type semiconductor region 1022 of the N-type region 1123, and a plurality of N-type diffusion layers 1131 are arranged in a substantially circular shape and dispersed when viewed from above.

[0629] Return Fig.53 For B, the light-shielding pixel region 1122 has pixel columns or pixel rows of one or more pixels in each column or each row on the four sides of the outer periphery of the effective pixel region 1051. The N-type region 1123 also has a specified column width or row width in each column or each row on the four sides of the outer periphery of the light-shielding pixel region 1122.

[0630] Fig.53 The charge discharge region 1101 of C is composed of the light-shielding pixel region 1122 in which the light-shielding pixel is arranged. The light-shielding pixel region 1122 has pixel columns or pixel rows of one or more pixels in each column or each row on the four sides of the outer periphery of the effective pixel region 1051.

[0631] Fig.53 The charge discharge region 1101 of D is composed of the opening pixel region 1121 in which the opening pixel is arranged and the N-type region 1123 in which the N-type diffusion layer is arranged.

[0632] The prescribed driving performed by the opening pixels in the opening pixel region 1121 and the light-shielding pixels 51X in the light-shielding pixel region 1122 only needs to include an operation of always or intermittently applying a positive voltage to the N-type semiconductor region of the pixel. Preferably, at the moment based on the pixel 51 in the effective pixel region 1051, a driving signal is applied to the pixel transistor, P-type semiconductor region, or N-type semiconductor region in the same manner as the driving of the pixel 51.

[0633] Fig.53 The structural examples of the charge discharge region 1101 shown in A to D of are merely examples and are not limited to these examples. The charge discharge region 1101 only needs to have a structure including any one of an opening pixel that performs a prescribed driving, a light-shielding pixel that performs a prescribed driving, and an N-type region having an N-type diffusion layer to which 0V or a positive voltage is always or intermittently applied. Therefore, for example, the opening pixels, light-shielding pixels, and N-type regions may be mixed in one pixel column or pixel row, or different types of opening pixels, light-shielding pixels, or N-type regions may be arranged in the pixel rows or columns on the four sides around the effective pixel region.

[0634] In this way, by providing the charge discharge region 1101 on the outer periphery of the effective pixel region 1051, the accumulation of electrons outside the effective pixel region 1051 can be suppressed. Therefore, it is possible to suppress the addition of the optical charge diffusing from the outside of the effective pixel region 1051 to the signal charge, which generates noise.

[0635] In addition, by providing the charge discharge region 1101 on the front side near the OPB region 1102, it is possible to prevent the photo electrons generated in the light-shielding region outside the effective pixel region 1051 from diffusing into the OPB region 1102. Therefore, it is possible to prevent noise from being added to the black level signal. Fig.53 The structures shown in A to D of can also be applied to any of the embodiments described in this specification.

[0636] (Eighteenth Embodiment)

[0637] Next, with reference to Fig.55 The flow of current in the case of arranging pixel transistors on the substrate 61 having a photoelectric conversion region will be described.

[0638] In the pixel 51, for example, by applying a positive voltage of 1.5V and a voltage of 0V to the P+ semiconductor regions 73 of the two signal extraction portions 65, an electric field is generated between the two P+ semiconductor regions 73, and current flows from the P+ semiconductor region 73 to which 1.5V is applied to the P+ semiconductor region 73 to which 0V is applied. However, since the P-well region 1011 formed at the pixel boundary portion is also GND (0V), current flows not only between the two signal extraction portions 65 but also as Fig.55As shown in A, current also flows from the P+ semiconductor region 73 to which 1.5 V is applied to the P well region 1011.

[0639] Fig.55 B of is showing Fig.42 a plan view of the pixel transistor wiring region 831 shown in A of.

[0640] The area of the signal extraction unit 65 can be reduced by layout change. In contrast, the area of the pixel transistor wiring region 831 is determined by the area dedicated to one pixel transistor, the number of pixel transistors, and the wiring area. Therefore, it is difficult to reduce the area only through research on layout design. Thus, when attempting to reduce the area of the pixel 51, the area of the pixel transistor wiring region 831 becomes the main limiting factor. To achieve high resolution while maintaining the optical size of the sensor, it is necessary to reduce the pixel size, but the area of the pixel transistor wiring region 831 poses a constraint. Additionally, if the area of the pixel 51 is reduced while maintaining the area of the pixel transistor wiring region 831, then in Fig.55 B of, the path of the current flowing into the pixel transistor wiring region 831 indicated by the dashed arrow is shortened, the resistance decreases, and the current increases. Consequently, reducing the area of the pixel 51 leads to an increase in power consumption.

[0641] (Example of pixel structure)

[0642] Therefore, as Fig.56 shown, it is possible to adopt a structure in which the light receiving element 1 is a stacked structure of two substrates, and all pixel transistors are arranged on a substrate different from the substrate having the photoelectric conversion region.

[0643] Fig.56 is a cross-sectional view of the pixel of the eighteenth embodiment.

[0644] Fig.56 Similar to the above-mentioned Fig.36 etc., it shows a cross-sectional view of a plurality of pixels corresponding to the B - B' line of Fig.11 .

[0645] In Fig.56 , parts corresponding to the cross-sectional view of the plurality of pixels of the fourteenth embodiment shown in Fig.36 are labeled with the same reference numerals, and the description of that part is appropriately omitted.

[0646] In Fig.56 the eighteenth embodiment of, the light receiving element 1 is formed by stacking two substrates, namely, substrate 1201 and substrate 1211. Substrate 1201 is the same as Fig.36The substrate 61 in the fourteenth embodiment shown corresponds to, for example, a silicon substrate or the like having a P-type semiconductor region 1204 as a photoelectric conversion region. The substrate 1211 is also made of a silicon substrate or the like.

[0647] In addition, the substrate 1201 having a photoelectric conversion region may be made of, for example, a compound semiconductor such as GaAs, InP, GaSb, a narrow bandgap semiconductor such as Ge, a glass substrate coated with an organic photoelectric conversion film, or a plastic substrate, in addition to a silicon substrate or the like. When the substrate 1201 is made of a compound semiconductor, an improvement in quantum efficiency, an improvement in sensitivity, and a reduction in the thickness of the sensor due to thinning of the substrate can be expected due to the direct transition type energy band structure. In addition, since the mobility of electrons is high, the electron collection efficiency can be improved, and since the mobility of holes is low, the power consumption can be reduced. When the substrate 1201 is made of a narrow bandgap semiconductor, an improvement in quantum efficiency and an improvement in sensitivity in the near-infrared region due to the narrow bandgap can be expected.

[0648] The substrate 1201 and the substrate 1211 are bonded in such a manner that the wiring layer 1202 of the substrate 1201 faces the wiring layer 1212 of the substrate 1211. And the metal wiring 1203 of the wiring layer 1202 on the substrate 1201 side and the metal wiring 1213 of the wiring layer 1212 on the substrate 1211 side are electrically joined, for example, by Cu-Cu bonding. In addition, the electrical joining of the wiring layers is not limited to Cu-Cu bonding, and may be, for example, the same metal bonding such as Au-Au bonding and Al-Al bonding, or different metal bonding such as Cu-Au bonding, Cu-Al bonding, or Au-Al bonding. Further, a reflection member 631 of the fourteenth embodiment or a light-shielding member 631' of the fifteenth embodiment may be further provided on either the wiring layer 1202 of the substrate 1201 or the wiring layer 1212 of the substrate 1211.

[0649] The difference between the substrate 1201 having a photoelectric conversion region and the substrate 61 of the first to seventeenth embodiments described above is that all the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed on the substrate 1201.

[0650] In Fig.56 In the eighteenth embodiment, pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed on the substrate 1211 side at the lower part in the figure. The reset transistor 723, the amplification transistor 724, and the selection transistor 725 are illustrated in Fig.56 , but a transfer transistor 721 is also formed in an unillustrated region of the substrate 1211.

[0651] An insulating film (oxide film) 1214 that also serves as a gate insulating film of a pixel transistor is formed between a substrate 1211 and a wiring layer 1212.

[0652] Therefore, although not shown in the drawings, when observing the pixel of the eighteenth embodiment in a cross-sectional view taken along line A - A' corresponding to Fig.11 , the pixel transistor Tr formed at the pixel boundary portion in Fig.37 is not formed on the substrate 1201.

[0653] When using the equivalent circuit of the pixel 51 shown in Fig.31 to represent the elements respectively disposed on the substrate 1201 and the substrate 1211, as shown in Fig.57 , a P+ semiconductor region 73 serving as a voltage application portion and an N+ semiconductor region 71 serving as a charge detection portion are formed on the substrate 1201, and a transfer transistor 721, an FD 722, a reset transistor 723, an amplification transistor 724, and a selection transistor 725 are formed on the substrate 1211.

[0654] When referring to Fig.47 showing the light receiving element 1 of the eighteenth embodiment, as shown in Fig.58 , the light receiving element 1 is constituted by laminating the substrate 1201 and the substrate 1211.

[0655] In the pixel array region 1231 of the substrate 1201, a portion excluding the transfer transistor 721, the FD 722, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 from the pixel array region 951 shown in C of Fig.47 is formed.

[0656] In the region control circuit 1232 of the substrate 1211, in addition to Fig.47 the region control circuit 954 shown in C, the transfer transistor 721, the FD 722, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 of each pixel of the pixel array portion 20 are also formed. Figure 1 The tap driving portion 21, the vertical driving portion 22, the column processing portion 23, the horizontal driving portion 24, the system control portion 25, the signal processing portion 31, and the data storage portion 32 shown in

[0657] Fig.59 are also formed on the substrate 1211. Fig.59 is a top view showing an electrical junction portion between the substrate 1201 and the substrate 1211 for receiving and transmitting the voltage MIX, that is, the MIX junction portion, and an electrical junction portion between the substrate 1201 and the substrate 1211 for receiving and transmitting the signal charge DET, that is, the DET junction portion. In addition, in Fig.59 , in order to prevent the drawing from becoming complicated, a part of the reference numerals of the MIX junction portion 1251 and the DET junction portion 1252 is omitted.

[0658] As Fig.59 shown, for example, for each pixel 51, an MIX joint 1251 for supplying voltage MIX and a DET joint 1252 for obtaining signal charge DET are respectively provided. In this case, the voltage MIX and the signal charge DET are transferred between the substrate 1201 and the substrate 1211 in units of pixels.

[0659] Alternatively, in addition, as Fig.60 shown, the DET joint 1252 for obtaining signal charge DET is provided in the pixel area in units of pixels, but the MIX joint 1251 for supplying voltage MIX may also be provided in the peripheral part 1261 outside the pixel array part 20. In the peripheral part 1261, the voltage MIX supplied from the substrate 1211 is supplied to the voltage application part of each pixel 51, that is, the P+ semiconductor region 73, via the voltage supply line 1253 wired in the vertical direction in the substrate 1201. In this way, by sharing the MIX joint 1251 for supplying voltage MIX among a plurality of pixels, the number of MIX joints 1251 on the entire substrate can be reduced, and it is easy to miniaturize the pixel size and the chip size.

[0660] In addition, Fig.60 the example of is an example of sharing in the pixel columns by wiring the voltage supply line 1253 in the vertical direction, but the voltage supply line 1253 may also be wired in the horizontal direction for sharing in the pixel rows.

[0661] In addition, in the above-described eighteenth embodiment, an example in which the electrical connection between the substrate 1201 and the substrate 1211 is electrically connected by Cu-Cu bonding has been described, but other electrical bonding methods may also be used, such as TCV (Through Chip Via), bump bonding using micro-bumps, and the like.

[0662] According to the above-described eighteenth embodiment, the light-receiving element 1 is constituted by the stacked structure of the substrate 1201 and the substrate 1211, and on the substrate 1211 different from the substrate 1201 having the P-type semiconductor region 1204 as the photoelectric conversion region, all the pixel transistors for performing the readout operation of the signal charge DET of the N+ semiconductor region 71 as the charge detection part, that is, the transfer transistor 721, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are arranged. Thereby, the problem described with reference to Fig.55 can be solved.

[0663] That is, the area of pixel 51 can be reduced regardless of the area of the pixel transistor wiring region 831, and high resolution can be achieved without changing the optical size. In addition, since an increase in current from the signal extraction unit 65 to the pixel transistor wiring region 831 is avoided, the power consumption can also be reduced.

[0664] (Nineteenth Embodiment)

[0665] Next, the nineteenth embodiment will be described.

[0666] In order to improve the charge separation efficiency Cmod of the CAPD sensor, it is necessary to strengthen the potential of the P+ semiconductor region 73 or the P− semiconductor region 74 as the voltage application unit. In particular, in the case where it is necessary to detect long-wavelength light such as infrared light with high sensitivity, as Fig.61 shown, it is necessary to extend the P− semiconductor region 74 to a deeper position in the semiconductor layer, or increase the applied positive voltage to a voltage VA2 higher than the voltage VA1. In this case, since the resistance between the voltage application units is reduced, the current Imix easily flows, and an increase in power consumption becomes a problem. In addition, in the case where the pixel size is made finer to improve the resolution, since the distance between the voltage application units is shortened and the resistance is reduced, an increase in power consumption becomes a problem.

[0667] (First Structural Example of the Nineteenth Embodiment)

[0668] Fig.62 A in Fig.62 is a top view of a pixel of the first structural example of the nineteenth embodiment,

[0669] Fig.62 A in Fig.62 is a top view taken along the B - B' line of B in Fig.62 B in Fig.62 is a cross-sectional view taken along the A - A' line of A in

[0670] In addition, in Fig.62 only the portion of the pixel 51 formed on the substrate 61 is shown, and for example, the on-chip lens 62 formed on the light incident surface side, the multilayer wiring layer 811 formed on the opposite side of the light incident surface, etc. are omitted from the illustration. The omitted portions can be configured in the same manner as the other above-described embodiments. For example, a reflection member 631 or a light-shielding member 631' can be provided on the multilayer wiring layer 811 on the opposite side of the light incident surface.

[0671] In the first structural example of the nineteenth embodiment, at a specified position in the P-type semiconductor region 1301 that is the photoelectric conversion region of the substrate 61, an electrode portion 1311-1 that functions as a voltage application portion for applying a specified voltage MIX0 and an electrode portion 1311-2 that functions as a voltage application portion for applying a specified voltage MIX1 are formed.

[0672] The electrode portion 1311-1 is composed of an embedded portion 1311A-1 embedded in the P-type semiconductor region 1301 of the substrate 61 and a protruding portion 1311B-1 protruding above the first surface 1321 of the substrate 61.

[0673] The electrode portion 1311-2 is also composed of an embedded portion 1311A-2 embedded in the P-type semiconductor region 1301 of the substrate 61 and a protruding portion 1311B-2 protruding above the first surface 1321 of the substrate 61. The electrode portions 1311-1 and 1311-2 are formed of, for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu), or a conductive material such as silicon or polysilicon.

[0674] As Fig.62 shown in A of, the electrode portion 1311-1 (the embedded portion 1311A-1 thereof) and the electrode portion 1311-2 (the embedded portion 1311A-2 thereof) having a circular planar shape are symmetrically arranged with the center point of the pixel as the center of symmetry.

[0675] An N+ semiconductor region 1312-1 that functions as a charge detection portion is formed around the outer periphery of the electrode portion 1311-1, and an insulating film 1313-1 and a hole concentration enhancement layer 1314-1 are inserted between the electrode portion 1311-1 and the N+ semiconductor region 1312-1.

[0676] Similarly, an N+ semiconductor region 1312-2 that functions as a charge detection portion is formed around the outer periphery of the electrode portion 1311-2, and an insulating film 1313-2 and a hole concentration enhancement layer 1314-2 are inserted between the electrode portion 1311-2 and the N+ semiconductor region 1312-2.

[0677] The electrode portion 1311-1 and the N+ semiconductor region 1312-1 constitute the above-described signal extraction portion 65-1, and the electrode portion 1311-2 and the N+ semiconductor region 1312-2 constitute the above-described signal extraction portion 65-2.

[0678] The electrode portion 1311-1 is covered in the substrate 61, as Fig.62 shown in B of, by the insulating film 1313-1, and the insulating film 1313-1 is covered by the hole concentration enhancement layer 1314-1. The relationship among the electrode portion 1311-2, the insulating film 1313-2, and the hole concentration enhancement layer 1314-2 is the same.

[0679] The insulating films 1313-1 and 1313-2 are made of, for example, an oxide film (SiO2) and are formed in the same process as the insulating film 1322 formed on the first surface 1321 of the substrate 61. In addition, an insulating film 1332 is also formed on the second surface 1331 of the substrate 61 opposite to the first surface 1321.

[0680] The hole concentration enhancement layers 1314-1 and 1314-2 are composed of P-type semiconductor regions and can be formed, for example, by ion implantation, solid-phase diffusion, plasma doping, etc.

[0681] Hereinafter, when there is no need to particularly distinguish between the electrode portions 1311-1 and 1311-2, they are also simply referred to as the electrode portion 1311. When there is no need to particularly distinguish between the N+ semiconductor regions 1312-1 and 1312-2, they are also simply referred to as the N+ semiconductor region 1312.

[0682] In addition, when there is no need to particularly distinguish between the hole concentration enhancement layers 1314-1 and 1314-2, they are also simply referred to as the hole concentration enhancement layer 1314. When there is no need to particularly distinguish between the insulating films 1313-1 and 1313-2, they are also simply referred to as the insulating film 1313.

[0683] The electrode portion 1311, the insulating film 1313, and the hole concentration enhancement layer 1314 can be formed in the following order. First, a trench with a prescribed depth is formed by etching the P-type semiconductor region 1301 of the substrate 61 from the first surface 1321 side. Then, after forming the hole concentration enhancement layer 1314 by ion implantation, solid-phase diffusion, plasma doping, etc. on the inner periphery of the formed trench, the insulating film 1313 is formed. Next, a buried portion 1311A is formed by burying a conductive material inside the insulating film 1313. After that, a conductive material such as a metal material is formed on the entire surface of the first surface 1321 of the substrate 61, and then only the upper portion of the electrode portion 1311 is left by etching, thereby forming the protruding portion 1311B-1.

[0684] The depth of the electrode portion 1311 is configured to reach at least a position deeper than the N+ semiconductor region 1312 serving as the charge detection portion, and preferably is configured to reach a position deeper than half of the substrate 61.

[0685] For the pixel 51 of the first structural example of the nineteenth embodiment configured as described above, by using the electrode portion 1311 formed by forming a trench in the depth direction of the substrate 61 and burying a conductive material, a charge distribution effect is obtained for the charges photoelectrically converted in a wide region in the depth direction with respect to the substrate 61. Therefore, the charge separation efficiency Cmod with respect to long-wavelength light can be improved.

[0686] In addition, by forming a structure in which the outer peripheral portion of the electrode portion 1311 is covered with the insulating film 1313, the current flowing between the voltage application portions is suppressed, and thus the current consumption can be reduced. Alternatively, in addition, when comparing with the same current consumption, a high voltage can be applied to the voltage application portions. Furthermore, even if the distance between the voltage application portions is shortened, the current consumption can be suppressed. Therefore, by miniaturizing the pixel size and increasing the number of pixels, high resolution can be achieved.

[0687] In addition, in the first structural example of the nineteenth embodiment, the protruding portion 1311B of the electrode portion 1311 may be omitted. However, by providing the protruding portion 1311B, the electric field in the direction perpendicular to the substrate 61 is enhanced, and charges are easily accumulated.

[0688] In addition, when it is desired to increase the modulation degree of the applied voltage and further improve the charge separation efficiency Cmod, the hole concentration enhancement layer 1314 may be omitted. When the hole concentration enhancement layer 1314 is provided, the generation of electrons due to damage and contaminants during the etching for forming the trench can be suppressed.

[0689] In the first structural example of the nineteenth embodiment, either the first surface 1321 or the second surface 1331 of the substrate 61 may be the light incident surface, and it may be either a back-illuminated type or a front-illuminated type, but the back-illuminated type is more preferable.

[0690] (Second Structural Example of the Nineteenth Embodiment)

[0691] Fig.63 A of is a plan view of the pixel of the second structural example of the nineteenth embodiment, Fig.63 B of is a cross-sectional view of the pixel of the second structural example of the nineteenth embodiment.

[0692] Fig.63 A of is Fig.63 a plan view taken along the line B - B' of B of, Fig.63 B of is Fig.63 a cross-sectional view taken along the line A - A' of A of.

[0693] In addition, in Fig.63 the second structural example of, the same reference numerals are assigned to the corresponding parts as Fig.62 in, and the description focuses on the parts different from the first structural example of Fig.62 and the description of the common parts is appropriately omitted.

[0694] In Fig.63In the second structural example, it is different in that the buried portion 1311A of the electrode portion 1311 penetrates the substrate 61 serving as a semiconductor layer, and the other aspects are the same. The buried portion 1311A of the electrode portion 1311 is formed from the first surface 1321 to the second surface 1331 of the substrate 61, and an insulating film 1313 and a hole concentration enhancement layer 1314 are finally formed on the outer peripheral portion of the electrode portion 1311. Regarding the second surface 1331 on the side where the N+ semiconductor region 1312 serving as a charge detection portion is not formed, the entire surface is covered with an insulating film 1332.

[0695] As in this second structural example, it is also possible to configure the buried portion 1311A of the electrode portion 1311 serving as a voltage application portion to penetrate the substrate 61. In this case, for the charges photoelectrically converted in a wide area in the depth direction with respect to the substrate 61, a charge distribution effect is obtained, and thus the charge separation efficiency Cmod with respect to long-wavelength light can be improved.

[0696] Furthermore, by forming a structure in which the outer peripheral portion of the electrode portion 1311 is covered with the insulating film 1313, the current flowing between the voltage application portions is suppressed, and thus the current consumption can be reduced. Alternatively, furthermore, in the case of comparison with the same current consumption, a high voltage can be applied to the voltage application portions. Furthermore, even if the distance between the voltage application portions is shortened, the current consumption can be suppressed. Therefore, by miniaturizing the pixel size and increasing the number of pixels, high resolution can be achieved.

[0697] In the second structural example of the nineteenth embodiment, either the first surface 1321 or the second surface 1331 of the substrate 61 can be a light incident surface, and it can be either a back-illumination type or a front-illumination type, but the back-illumination type is more preferable.

[0698] (Other examples of planar shapes)

[0699] In the first and second structural examples of the above-mentioned nineteenth embodiment, the planar shapes of the electrode portion 1311 serving as a voltage application portion and the N+ semiconductor region 1312 serving as a charge detection portion are circular.

[0700] However, the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are not limited to circular, and can also be Fig.11 the octagon shown, Fig.12 the rectangle or square shown, etc. In addition, the number of signal extraction portions 65 (taps) arranged in one pixel is not limited to 2, and can be Fig.17 4 shown, etc.

[0701] Fig.64 A to C of Fig.62Top view of line B - B' of B, showing an example where the number of signal extraction portions 65 is two and the planar shapes of the electrode portions 1311 and N+ semiconductor regions 1312 constituting the signal extraction portion 65 are shapes other than circular.

[0702] Fig.64 A is an example where the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are vertically long rectangles.

[0703] In Fig.64 In A, the electrode portions 1311-1 and 1311-2 are symmetrically arranged with the center point of the pixel as the center of symmetry. In addition, the electrode portions 1311-1 and 1311-2 are arranged opposite to each other. The shapes and positional relationships of the insulating film 1313, hole concentration enhancement layer 1314, and N+ semiconductor region 1312 formed on the outer periphery of the electrode portion 1311 are also the same as those of the electrode portion 1311.

[0704] Fig.64 B is an example where the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are L-shaped.

[0705] Fig.64 C is an example where the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are comb-shaped.

[0706] In Fig.64 In B and C, the electrode portions 1311-1 and 1311-2 are also symmetrically arranged with the center point of the pixel as the center of symmetry. In addition, the electrode portions 1311-1 and 1311-2 are arranged opposite to each other. The shapes and positional relationships of the insulating film 1313, hole concentration enhancement layer 1314, and N+ semiconductor region 1312 formed on the outer periphery of the electrode portion 1311 are also the same.

[0707] Fig.65 A to C are equivalent to Fig.62 Top view of line B - B' of B, showing an example where the number of signal extraction portions 65 is four and the planar shapes of the electrode portions 1311 and N+ semiconductor regions 1312 constituting the signal extraction portion 65 are shapes other than circular.

[0708] Fig.65 A is an example where the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are vertically long rectangles.

[0709] In Fig.65In A, the longitudinal electrode portions 1311-1 to 1311-4 are arranged at a prescribed interval in the horizontal direction and are arranged point-symmetrically with the center point of the pixel as the symmetry point. Further, the electrode portions 1311-1 and 1311-2 are arranged opposite to the electrode portions 1311-3 and 1311-4.

[0710] The electrode portion 1311-1 and the electrode portion 1311-3 are electrically joined by a wiring 1351 and constitute, for example, a voltage application portion of a signal extraction portion 65-1 (first tap TA) to which a voltage MIX0 is applied. The N+ semiconductor regions 1312-1 and 1312-3 are electrically joined by a wiring 1352 and constitute a charge detection portion of the signal extraction portion 65-1 (first tap TA) for detecting a signal charge DET1.

[0711] The electrode portion 1311-2 and the electrode portion 1311-4 are electrically joined by a wiring 1353 and constitute, for example, a voltage application portion of a signal extraction portion 65-2 (second tap TB) to which a voltage MIX1 is applied. The N+ semiconductor regions 1312-2 and 1312-4 are electrically joined by a wiring 1354 and constitute a charge detection portion of the signal extraction portion 65-2 (second tap TB) for detecting a signal charge DET2.

[0712] Therefore, in other words, in Fig.65 the configuration of A, the group of the voltage application portion and the charge detection portion of the signal extraction portion 65-1 having a rectangular planar shape and the group of the voltage application portion and the charge detection portion of the signal extraction portion 65-2 having a rectangular planar shape are arranged alternately in the horizontal direction.

[0713] The shape and the positional relationship of the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the outer periphery of the electrode portion 1311 are also the same.

[0714] Fig.65 B is an example in which the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are square.

[0715] In Fig.65 the configuration of B, the group of the voltage application portion and the charge detection portion of the signal extraction portion 65-1 having a rectangular planar shape are arranged opposite to each other in the diagonal direction of the pixel 51, and the group of the voltage application portion and the charge detection portion of the signal extraction portion 65-2 having a rectangular planar shape are arranged opposite to each other in a diagonal direction different from that of the signal extraction portion 65-1.

[0716] Fig.65 C is an example in which the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are triangular.

[0717] In Fig.65In the configuration of C, the groups of the voltage application part and the charge detection part of the signal extraction part 65-1 having a triangular planar shape are arranged opposite to each other in the first direction (horizontal direction) of the pixel 51, and the groups of the voltage application part and the charge detection part of the signal extraction part 65-2 having a triangular planar shape are arranged opposite to each other in the second direction (vertical direction) orthogonal to the first direction and different from the signal extraction part 65-1.

[0718] In Fig.65 In B and C, the four electrode parts 1311-1 to 1311-4 are point-symmetrically arranged with the center point of the pixel as the symmetry point, the electrode part 1311-1 and the electrode part 1311-3 are electrically connected by the wiring 1351, the N+ semiconductor regions 1312-1 and 1312-3 are electrically connected by the wiring 1352, the electrode part 1311-2 and the electrode part 1311-4 are electrically connected by the wiring 1353, and the N+ semiconductor regions 1312-2 and 1312-4 are electrically connected by the wiring 1354 are all the same. The shapes and positional relationships of the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the outer periphery of the electrode part 1311 are also the same as those of the electrode part 1311.

[0719] (Third Structural Example of the Nineteenth Embodiment)

[0720] Fig.66 A of Fig.66 is a top view of the pixel of the third structural example of the nineteenth embodiment,

[0721] Fig.66 A of Fig.66 is a top view taken along the line B-B' of B of Fig.66 B of Fig.66 is a cross-sectional view taken along the line A-A' of A of

[0722] In addition, in Fig.66 the third structural example of Fig.62 the same reference numerals are assigned to the parts corresponding to Fig.62 the first structural example of

[0723] In Fig.62 the first structural example of Fig.63 and

[0724] In contrast, in Fig.66In the third structural example, the voltage application unit electrode unit 1311 is disposed on the planar side opposite to the first surface 1321 of the substrate 61 where the N+ semiconductor region 1312 serving as the charge detection unit is formed, that is, on the second surface 1331 side. The protruding portion 1311B of the electrode unit 1311 is formed on the upper portion of the second surface 1331 of the substrate 61.

[0725] In addition, the electrode unit 1311 and the N+ semiconductor region 1312 are disposed at positions where the central positions overlap when viewed from above. Fig.66 The example is an example where the planar regions of the electrode unit 1311 and the N+ semiconductor region 1312 are completely identical, but it is not necessary to be completely identical. As long as the central positions overlap, either planar region can be larger. In addition, the central position can also be a range where they can be regarded as being substantially identical even if they are not completely identical.

[0726] The third structural example is the same as the above-described first structural example except for the positional relationship between the processing electrode unit 1311 and the N+ semiconductor region 1312. As in this third structural example, the buried portion 1311A of the electrode unit 1311 serving as the voltage application unit is formed at a deeper position near the N+ semiconductor region 1312 serving as the charge detection unit, and the N+ semiconductor region 1312 is formed on the first surface 1321 opposite to the second surface 1331 where the electrode unit 1311 is provided. In this case, for the charges photoelectrically converted in a wide region in the depth direction with respect to the substrate 61, a charge distribution effect can be obtained, and thus the charge separation efficiency Cmod with respect to long-wavelength light can be improved.

[0727] In addition, by forming a structure in which the outer peripheral portion of the electrode unit 1311 is covered with the insulating film 1313, the current flowing between the voltage application units is suppressed, and thus the current consumption can be reduced. Alternatively, in addition, when comparing with the same current consumption, a high voltage can be applied to the voltage application unit. Furthermore, even if the distance between the voltage application units is shortened, the current consumption can be suppressed. Therefore, by miniaturizing the pixel size and increasing the number of pixels, high resolution can be achieved.

[0728] In the third structural example of the nineteenth embodiment, either the first surface 1321 or the second surface 1331 of the substrate 61 can be the light incident surface, and it can be either a back-illumination type or a surface-illumination type, but the back-illumination type is more preferable. When the third structural example is configured as the back-illumination type, the second surface 1331 becomes the surface on the side where the on-chip lens 62 is formed. For example, as Fig.60 shown, the voltage supply line 1253 for supplying the applied voltage to the electrode unit 1311 is wired in the vertical direction of the pixel array unit 20, and in the peripheral portion 1261 outside the pixel array unit 20, it can be connected to the wiring on the surface side through the through electrode penetrating the substrate 61.

[0729] (Other examples of plane shapes)

[0730] In the third structural example of the above-mentioned nineteenth embodiment, the planar shapes of the electrode portion 1311 as the voltage applying portion and the N + semiconductor region 1312 as the charge detecting portion are formed into a circle.

[0731] However, the planar shape of the electrode portion 1311 and the N+ semiconductor region 1312 is not limited to a circle, but may also be Fig.11 The octagon shown, Fig.12 In addition, the number of signal extraction units 65 (taps) configured in one pixel is not limited to two, and may be Fig.17 4 etc. shown.

[0732] Fig.67 A to C are equivalent to Fig.66 The plan view taken along the line BB′ of FIG. 1 shows an example in which the number of signal extraction portions 65 is two and the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 constituting the signal extraction portion 65 are shapes other than a circle.

[0733] Fig.67 A is an example in which the planar shape of the electrode portion 1311 and the N + semiconductor region 1312 is a vertically long rectangle.

[0734] exist Fig.67 In A, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 as the charge detection portion are point-symmetrically arranged with the center point of the pixel as the symmetry point. In addition, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 are arranged opposite to each other. The shape and positional relationship of the electrode portion 1311 arranged on the second surface 1331 side opposite to the formation surface of the N+ semiconductor region 1312, and the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the periphery of the electrode portion 1311 are also the same as those of the N+ semiconductor region 1312.

[0735] Fig.67 B is an example in which the planar shape of the electrode portion 1311 and the N+ semiconductor region 1312 is L-shaped.

[0736] Fig.67 C is an example in which the planar shape of the electrode portion 1311 and the N+ semiconductor region 1312 is a comb-tooth shape.

[0737] exist Fig.67Among B and C, the N+ semiconductor regions 1312-1 and 1312-2 are also arranged point-symmetrically with the center point of the pixel as the symmetry point. In addition, the N+ semiconductor regions 1312-1 and 1312-2 are arranged opposite to each other. The shape and positional relationship of the electrode portion 1311 on the second surface 1331 side arranged on the side opposite to the formation surface of the N+ semiconductor region 1312, and the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the outer periphery of the electrode portion 1311 are also the same as those of the N+ semiconductor region 1312.

[0738] Fig.68 A to C of are equivalent to Fig.66 The top view of the B-B' line corresponding to B of shows an example in the case where the number of signal extraction portions 65 is four, and the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 constituting the signal extraction portion 65 are shapes other than circular.

[0739] Fig.68 A of shows an example in which the planar shapes of the electrode portion 1311 and the N+ semiconductor region 1312 are vertically long rectangles that are long in the vertical direction.

[0740] In Fig.68 In A of, the vertically long N+ semiconductor regions 1312-1 to 1312-4 are arranged at a predetermined interval in the horizontal direction and are arranged point-symmetrically with the center point of the pixel as the symmetry point. In addition, the N+ semiconductor regions 1312-1 and 1312-2 are arranged opposite to the N+ semiconductor regions 1312-3 and 1312-4.

[0741] The electrode portion 1311-1 and the electrode portion 1311-3 (not shown) formed on the second surface 1331 side are electrically connected by a wiring 1351. For example, it constitutes a voltage application portion of the signal extraction portion 65-1 (first tap TA) to which a voltage MIX0 is applied. The N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected by a wiring 1352, and constitute a charge detection portion of the signal extraction portion 65-1 (first tap TA) that detects a signal charge DET1.

[0742] The electrode portion 1311-2 and the electrode portion 1311-4 (not shown) formed on the second surface 1331 side are electrically connected by a wiring 1353. For example, it constitutes a voltage application portion of the signal extraction portion 65-2 (second tap TB) to which a voltage MIX1 is applied. The N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected by a wiring 1354, and constitute a charge detection portion of the signal extraction portion 65-2 (second tap TB) that detects a signal charge DET2.

[0743] Therefore, in other words, in Fig.68In the configuration of A, the groups of the voltage application part and the charge detection part of the signal extraction part 65-1 having a rectangular planar shape and the groups of the voltage application part and the charge detection part of the signal extraction part 65-2 having a rectangular planar shape are alternately arranged in the horizontal direction.

[0744] The shapes and positional relationships of the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the outer periphery of the electrode part 1311 are also the same.

[0745] Fig.68 B is an example in which the planar shapes of the electrode part 1311 and the N+ semiconductor region 1312 are square.

[0746] In Fig.68 In the configuration of B, the groups of the voltage application part and the charge detection part of the signal extraction part 65-1 having a rectangular planar shape are arranged opposite to each other in the diagonal direction of the pixel 51, and the groups of the voltage application part and the charge detection part of the signal extraction part 65-2 having a rectangular planar shape are arranged opposite to each other in a diagonal direction different from that of the signal extraction part 65-1.

[0747] Fig.68 C is an example in which the planar shapes of the electrode part 1311 and the N+ semiconductor region 1312 are triangular.

[0748] In Fig.68 In the configuration of C, the groups of the voltage application part and the charge detection part of the signal extraction part 65-1 having a triangular planar shape are arranged opposite to each other in the first direction (horizontal direction), and the groups of the voltage application part and the charge detection part of the signal extraction part 65-2 having a triangular planar shape are arranged opposite to each other in a second direction (vertical direction) orthogonal to the first direction and different from the signal extraction part 65-1.

[0749] In Fig.68 In B and C, the four electrode parts 1311-1 to 1311-4 are point-symmetrically arranged with the center point of the pixel as the symmetry point, the electrode part 1311-1 and the electrode part 1311-3 are electrically connected by the wiring 1351, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected by the wiring 1352, the electrode part 1311-2 and the electrode part 1311-4 are electrically connected by the wiring 1353, and the N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected by the wiring 1354. The shapes and positional relationships of the insulating film 1313 and the hole concentration enhancement layer 1314 formed on the outer periphery of the electrode part 1311 are also the same as those of the electrode part 1311.

[0750] (Other examples of wiring layouts)

[0751] In the above-mentioned Fig.31 and Fig.32 pixel circuit Fig.42 In the example of the metal film M3 of Fig.42 , a structure in which two vertical signal lines 29 are arranged in one pixel column corresponding to two signal extraction units 65 (two taps TA and TB) is illustrated.

[0752] However, for example, it can also be configured such that four vertical signal lines 29 are arranged in one pixel column, and pixel signals of a total of four taps of two pixels adjacent in the vertical direction are output simultaneously.

[0753] Fig.69 FIG. shows a circuit structure example of the pixel array unit 20 in the case where pixel signals of a total of four taps of two pixels adjacent in the vertical direction are output simultaneously.

[0754] Fig.69 FIG. shows a circuit structure of four pixels of 2×2 among a plurality of pixels 51 arranged in a matrix two-dimensionally in the pixel array unit 20. In addition, when distinguishing four pixels 51 of 2×2, they are represented as pixel 511 to pixel 514. Fig.69 In the case of distinguishing four pixels 51 of 2×2, they are represented as pixel 511 to pixel 514.

[0755] The circuit structure of each pixel 51 is a circuit structure including an additional capacitor 727 and a switching transistor 728 for controlling its connection, as described with reference to Fig.32 . Since the description of the circuit structure is repetitive, it is omitted. Fig.32 The circuit structure of each pixel 51 is a circuit structure including an additional capacitor 727 and a switching transistor 728 for controlling its connection, as described with reference to Fig.32 . Since the description of the circuit structure is repetitive, it is omitted.

[0756] In one pixel column of the pixel array unit 20, voltage supply lines 30A and 30B are wired in the vertical direction. And a predetermined voltage MIX0 is supplied to the first tap TA of a plurality of pixels 51 arranged in the vertical direction via the voltage supply line 30A, and a predetermined voltage MIX1 is supplied to the second tap TB via the voltage supply line 30B.

[0757] In addition, in one pixel column of the pixel array unit 20, four vertical signal lines 29A to 29D are wired in the vertical direction.

[0758] In the pixel columns of pixel 511 and pixel 512, for example, the vertical signal line 29A transmits the pixel signal of the first tap TA of pixel 511 to the column processing unit 23 ( Figure 1 ) transmission, the vertical signal line 29B transmits the pixel signal of the second tap TB of pixel 511 to the column processing unit 23, the vertical signal line 29C transmits the pixel signal of the first tap TA of pixel 512 adjacent to pixel 511 in the same column to the column processing unit 23, and the vertical signal line 29D transmits the pixel signal of the second tap TB of pixel 512 to the column processing unit 23.

[0759] In the pixel columns of pixels 513 and 514, for example, the vertical signal line 29A transmits the pixel signal of the first tap TA of pixel 513 to the column processing unit 23( Figure 1 ), the vertical signal line 29B transmits the pixel signal of the second tap TB of pixel 513 to the column processing unit 23, the vertical signal line 29C transmits the pixel signal of the first tap TA of pixel 514 adjacent to pixel 513 in the same column to the column processing unit 23, and the vertical signal line 29D transmits the pixel signal of the second tap TB of pixel 514 to the column processing unit 23.

[0760] On the other hand, in the horizontal direction of the pixel array unit 20, control lines 841 for transmitting the drive signal RST to the reset transistor 723, control lines 842 for transmitting the drive signal TRG to the transfer transistor 721, control lines 843 for transmitting the drive signal FDG to the switching transistor 728, and control lines 844 for transmitting the selection signal SEL to the selection transistor 725 are arranged in units of pixel rows.

[0761] The drive signal RST, the drive signal FDG, the drive signal TRG, and the selection signal SEL supply the same signals from the vertical drive unit 22 to each pixel 51 in two adjacent rows in the vertical direction.

[0762] In this way, in the pixel array unit 20, four vertical signal lines 29A to 29D are arranged in one pixel column, and thus pixel signals can be read out in units of two rows simultaneously.

[0763] Fig.70 Shows the layout of the metal film M3 of the third layer of the multi-layer wiring layer 811 in the case where four vertical signal lines 29A to 29D are arranged in one pixel column.

[0764] In other words, Fig.70 is Fig.42 a modified example of the layout of the metal film M3 shown in C.

[0765] In Fig.70 the layout of the metal film M3, four vertical signal lines 29A to 29D are arranged in one pixel column. In addition, four power supply lines 1401A to 1401D for supplying the power supply voltage VDD are arranged in one pixel column.

[0766] In addition, in Fig.70 , for reference, the area of pixel 51 and the areas of the signal extraction units 65-1 and 65-2 having the Fig.11 shown octagonal shape are shown by dotted lines. The same applies to Figure 71 to Figure 76 described later.

[0767] In Fig.70In the layout of the metal film M3, at the adjacent positions of the vertical signal lines 29A to 29D and the power supply lines 1401A to 1401D, a VSS wiring (ground wiring) 1411 at GND potential is arranged. The VSS wiring 1411 includes: a VSS wiring 1411B with a narrow line width arranged at the adjacent positions of the vertical signal lines 29A to 29D; a VSS wiring 1411A with a thick line width arranged between the vertical signal line 29B and the power supply line 1401C at the pixel boundary portion and between the vertical signal line 29C and the power supply line 1401D at the pixel boundary portion.

[0768] To improve the signal stability, it is effective to increase the power supply voltage VDD supplied to the power supply line 1401 or increase the voltages MIX0 and MIX1 supplied via the voltage supply lines 30A and 30B. On the other hand, the current increases and the reliability of the wiring deteriorates. Therefore, as Fig.70 shown, for at least one VSS wiring 1411 in one pixel column, a VSS wiring 1411A with a line width thicker than that of the power supply line 1401 is provided, whereby the current density can be reduced and the reliability of the wiring can be improved. Fig.70 An example is shown in which two VSS wirings 1411A are symmetrically arranged in the pixel region for one pixel column.

[0769] In addition, in Fig.70 the layout, VSS wirings 1411 (1411A or 1411B) are respectively arranged at the adjacent positions of the vertical signal lines 29A to 29D. Thereby, it is possible to make the vertical signal lines 29 less susceptible to potential fluctuations from the outside.

[0770] In addition, it is not limited to Fig.70 the third-layer metal film M3 of the multi-layer wiring layer 811 shown. For other layers of metal films, it is also possible to set the adjacent wirings of the signal line, the power supply line, and the control line as VSS wirings. For example, for Fig.42 the control lines 841 to 844 of the second-layer metal film M2 shown in B of

[0771] Fig.71

[0772] Fig.71 Fig.70 the layout of the metal film M3 is different from the layout of the metal film M3 shown in Fig.70 in that the VSS wirings 1411 at the adjacent positions of each of the four vertical signal lines 29A to 29D have the same line width.

[0773] More specifically, in the layout of the metal film M3 of Fig.70 , on both sides of the vertical signal line 29C, a VSS wiring 1411A with a thick line width and a VSS wiring 1411B with a thin line width are arranged. On both sides of the vertical signal line 29B, a VSS wiring 1411A with a thick line width and a VSS wiring 1411B with a thin line width are also arranged.

[0774] In contrast, in the layout of the metal film M3 of Fig.71 , on both sides of the vertical signal line 29C, VSS wirings 1411B with a thin line width are arranged. On both sides of the vertical signal line 29B, VSS wirings 1411B with a thin line width are also arranged. On both sides of the other vertical signal lines 29A and 29D, VSS wirings 1411B with a thin line width are arranged. The line widths of the VSS wirings 1411B on both sides of the four vertical signal lines 29A to 29D are the same.

[0775] By making the line widths of the VSS wirings 1411 on both sides of the vertical signal line 29 the same, the influence degree of crosstalk can be made uniform, and the characteristic deviation can be reduced.

[0776] Fig.72 This represents a second modification example of the layout of the metal film M3 as the third layer of the multilayer wiring layer 811 in the case where four vertical signal lines 29A to 29D are arranged in one pixel column.

[0777] Fig.72 The difference between the layout of the metal film M3 of Fig.70 shown and the layout of the metal film M3 shown is that the VSS wiring 1411A with a thick line width is replaced with a VSS wiring 1411C in which a plurality of gaps 1421 are regularly provided inside.

[0778] That is, the VSS wiring 1411C has a line width thicker than that of the power supply line 1401, and a plurality of gaps 1421 are repeatedly arranged in the vertical direction at a prescribed period inside it. In the example of Fig.72 , the shape of the gap 1421 is rectangular, but it is not limited to a rectangle, and it can also be circular or polygonal.

[0779] By providing a plurality of gaps 1421 inside the wiring area, the stability when forming (processing) the wide-width VSS wiring 1411C can be improved.

[0780] In addition, Fig.72 is a layout in which the VSS wiring 1411A of the metal film M3 shown in Fig.70 is replaced with the VSS wiring 1411C. Of course, the VSS wiring 1411A of the metal film M3 shown in Fig.71 can also be replaced with the VSS wiring 1411C.

[0781] (Other layout examples of pixel transistors)

[0782] Next, with reference to Fig.73 to Fig.44 a modified example of the configuration example of the pixel transistor shown in B of

[0783] Fig.73 A of Fig.44 is a diagram showing again the configuration of the pixel transistor shown in B of

[0784] On the other hand, Fig.73 B of

[0785] shows a modified example of the configuration of the pixel transistor. Fig.73 In A of Fig.44 as described in B of

[0786] with the midline (not shown) between the two signal extraction portions 65-1 and 65-2 as a reference, from the side closer to the midline toward the outside, gate electrodes of a reset transistor 723A and 723B, transfer transistors 721A and 721B, switching transistors 728A and 728B, selection transistors 725A and 725B, and amplification transistors 724A and 724B are formed in sequence.

[0787] In this configuration of the pixel transistor, a contact 1451 of a first power supply voltage VDD (VDD_1) is disposed between the reset transistors 723A and 723B, and contacts 1452 and 1453 of a second power supply voltage VDD (VDD_2) are respectively disposed outside the gate electrodes of the amplification transistors 724A and 724B.

[0788] In addition, a contact 1461 in contact with a first VSS wiring (VSS_A) is disposed between the gate electrodes of the selection transistor 725A and the switching transistor 728A, and a contact 1462 in contact with a second VSS wiring (VSS_B) is disposed between the gate electrodes of the selection transistor 725B and the switching transistor 728B. Figure 70 to Figure 72

[0789] Fig.73 On the other hand, in Fig.73 B of

[0790] In the configuration of the pixel transistor, a contact 1471 that contacts the first VSS wiring (VSS_1) is disposed between the switching transistors 728A and 728B, and contacts 1472 and 1473 that contact the second VSS wiring (VSS_2) are respectively disposed outside the gate electrodes of the selection transistors 725A and 725B.

[0791] In addition, a contact 1481 that contacts the first power supply voltage VDD (VDD_A) is disposed between the gate electrodes of the amplification transistor 724A and the reset transistor 723A, and a contact 1482 that contacts the second power supply voltage VDD (VDD_B) is disposed between the gate electrodes of the amplification transistor 724B and the reset transistor 723B.

[0792] In such a configuration of the pixel transistor, compared with the pixel transistor layout of Fig.73 A, the number of contacts of the power supply voltage can be reduced, so that the circuit can be simplified. In addition, the wiring of the power supply line 1401 for arranging the pixel array unit 20 can be reduced, and one pixel column can be constituted by two power supply lines 1401.

[0793] Furthermore, in Fig.73 the pixel transistor layout of B, the contact 1471 that contacts the first VSS wiring (VSS_1) between the switching transistors 728A and 728B can be omitted. Thereby, the density of the pixel transistors in the longitudinal direction can be reduced. In addition, by reducing the contacts that contact the VSS wiring, the current flowing between the voltage supply line 741 ( Fig.33 , Fig.34 ) for applying the voltage MIX0 or MIX1 and the VSS wiring can be reduced.

[0794] When the contact 1471 that contacts the first VSS wiring (VSS_1) is omitted, the amplification transistors 724A and 724B can be formed larger in the vertical direction. Thereby, the noise of the pixel transistor can be reduced and the deviation of the signal can be reduced.

[0795] Or, in addition, in Fig.73 the pixel transistor layout of B, the contacts 1472 and 1473 that contact the second VSS wiring (VSS_2) can be omitted. Thereby, the density of the pixel transistors in the longitudinal direction can be reduced. In addition, by reducing the contacts that contact the VSS wiring, the current flowing between the voltage supply line 741 ( Fig.33 , Fig.34 ) for applying the voltage MIX0 or MIX1 and the VSS wiring can be reduced.

[0796] In the case where contacts 1472 and 1473 that are in contact with the second VSS wiring (VSS_2) are omitted, the amplification transistors 724A and 724B can be formed larger in the vertical direction. As a result, the noise of the pixel transistors can be reduced, and the deviation of the signal can be decreased.

[0797] Fig.74 Indicates Fig.73 The wiring layout between the pixel transistors of the connection metal film M1 in the pixel transistor layout of B. Fig.74 And Fig.44 The wiring between the pixel transistors corresponding to the connection metal film M1 shown in C. The wiring connecting the pixel transistors can be connected across other wiring layers such as the metal films M2 and M3.

[0798] Fig.75 Indicates that in the case where the pixel transistor layout is B as set to Fig.73 And two power supply lines 1401 are arranged in one pixel column, the layout of the metal film M3 as the third layer of the multilayer wiring layer 811.

[0799] In Fig.75 Parts corresponding to Fig.70 Are marked with the same reference numerals, and the description of this part is appropriately omitted.

[0800] When Fig.75 The layout of the metal film M3 is compared with Fig.70 The layout of the metal film M3, among the four power supply lines 1401A to 1401D in Fig.70 Two power supply lines 1401C and 1401D are omitted, and the VSS wiring 1411A with a thicker line width is replaced with the VSS wiring 1411D with an even thicker line width.

[0801] In this way, by increasing the area (line width) of the VSS wiring 1411, the current density can be further reduced, and the reliability of the wiring can be improved.

[0802] Fig.76 Indicates that in the case where the pixel transistor layout is B as set to Fig.73 And two power supply lines 1401 are arranged in one pixel column, another layout of the metal film M3 as the third layer of the multilayer wiring layer 811.

[0803] In Fig.76 Parts corresponding to Fig.70 Are marked with the same reference numerals, and the description of this part is appropriately omitted.

[0804] When Fig.76 The layout of the metal film M3 is compared with Fig.70 The layout of the metal film M3, in Fig.70Among the four power supply lines 1401A to 1401D, two power supply lines 1401A and 1401B are omitted and replaced with a VSS wiring 1411E with a wide line width.

[0805] In this way, by increasing the area (line width) of the VSS wiring 1411, the current density can be further reduced and the reliability of the wiring can be improved.

[0806] In addition, Fig.75 and Fig.76 The layout of the metal film M3 shown is an example of changing the layout of the metal film M3 shown to two power supply lines 1401. However, it is also possible to change the layout of the metal film M3 shown in Fig.70 to two power supply lines 1401. Fig.71 and Fig.72 The layout of the metal film M3 shown in

[0807] That is, for the layout of the metal film M3 in which the VSS wiring 1411 at the adjacent positions of each of the four vertical signal lines 29A to 29D has the same line width, Fig.71 and the layout of the metal film M3 having a VSS wiring 1411C provided with a plurality of gaps 1421, Fig.72 it is also possible to form a structure changed to two power supply lines 1401.

[0808] Thus, the following effects can be further achieved: similar to Fig.71 , the influence degree of crosstalk can be made uniform, the characteristic deviation can be reduced, or similar to Fig.72 , the stability when forming the wide VSS wiring 1411C can be improved.

[0809] (Wiring example of power supply line and VSS wiring)

[0810] Fig.77 It is a top view showing a wiring example of the VSS wiring in the multilayer wiring layer 811.

[0811] The VSS wiring, as shown in Fig.77 , can be formed in a plurality of wiring layers such as the first wiring layer 1521, the second wiring layer 1522, and the third wiring layer 1523 in the multilayer wiring layer 811.

[0812] In the first wiring layer 1521, for example, a plurality of vertical wirings 1511 extending in the vertical direction in the pixel array section 20 are arranged at a prescribed interval with respect to the horizontal direction. In the second wiring layer 1522, for example, a plurality of horizontal wirings 1512 extending in the horizontal direction in the pixel array section 20 are arranged at a prescribed interval with respect to the vertical direction. In the third wiring layer 1523, for example, a wiring 1513 extending in the vertical direction or the horizontal direction is arranged with a line width thicker than that of the vertical wiring 1511 and the horizontal wiring 1512 so as to surround at least the outside of the pixel array section 20 and is connected to the GND potential. The wiring 1513 may also be arranged within the pixel array section 20 to connect the opposing wirings 1513 in the outer peripheral section to each other.

[0813] The vertical wiring 1511 of the first wiring layer 1521 and the horizontal wiring 1512 of the second wiring layer 1522 are respectively connected by vias or the like at an overlapping section 1531 where they overlap in a plan view.

[0814] In addition, the vertical wiring 1511 of the first wiring layer 1521 and the wiring 1513 of the third wiring layer 1523 are respectively connected by vias or the like at an overlapping section 1532 where they overlap in a plan view.

[0815] In addition, the horizontal wiring 1512 of the second wiring layer 1522 and the wiring 1513 of the third wiring layer 1523 are respectively connected by vias or the like at an overlapping section 1533 where they overlap in a plan view.

[0816] In addition, in Fig.77 in order to prevent the drawing from becoming complicated, the overlapping sections 1531 to 1533 are only marked with reference numerals at one place.

[0817] In this way, the VSS wiring is formed in a plurality of wiring layers of the multilayer wiring layer 811 and can be arranged in the pixel array section 20 in a manner that forms a lattice pattern by the vertical wiring 1511 and the horizontal wiring 151 in a plan view. As a result, the transmission delay within the pixel array section 20 can be reduced and characteristic variations can be suppressed.

[0818] Fig.78 is a plan view showing another wiring example of the VSS wiring in the multilayer wiring layer 811.

[0819] In Fig.78 the parts corresponding to Fig.77 are marked with the same reference numerals and their descriptions are appropriately omitted.

[0820] In Fig.77 the vertical wiring 1511 of the first wiring layer 1521 and the horizontal wiring 1512 of the second wiring layer 1522 are not formed outside the wiring 1513 formed on the outer periphery of the pixel array section 20, but in Fig.78extends to the outside of the wiring 1513 that extends to the outer periphery of the pixel array unit 20. Further, the vertical wiring 1511 is connected to the GND potential at the outer peripheral portion 1542 of the substrate 1541 outside the pixel array unit 20, and the horizontal wiring 1512 is connected to the GND potential at the outer peripheral portion 1543 of the substrate 1541 outside the pixel array unit 20, respectively.

[0821] In other words, in Fig.77 , the vertical wiring 1511 of the first wiring layer 1521 and the horizontal wiring 1512 of the second wiring layer 1522 are connected to the GND potential via the outer peripheral wiring 1513. However, in Fig.78 , not only that, but also the vertical wiring 1511 and the horizontal wiring 1512 themselves are directly connected to the GND potential. In addition, the regions where the vertical wiring 1511 and the horizontal wiring 1512 themselves are connected to the GND potential can be the four sides of the substrate 1541, or a specified one side, two sides, or three sides, such as the outer peripheral portions 1542 and 1543 in Fig.78 .

[0822] In this way, the VSS wiring is formed in a plurality of wiring layers of the multilayer wiring layer 811 and can be arranged in a grid-like manner when viewed from above within the pixel array unit 20. As a result, the transmission delay within the pixel array unit 20 can be reduced, and characteristic variations can be suppressed.

[0823] In addition, Fig.77 and Fig.78 Although the wiring example of the VSS wiring has been described, the power supply line can be arranged in the same manner.

[0824] Figure 70 to Figure 76 The VSS wiring 1411 and the power supply line 1401 described in Fig.77 and Fig.78 can be arranged in a plurality of wiring layers of the multilayer wiring layer 811 like the VSS wiring or the power supply line shown. Figure 70 to Figure 76 The VSS wiring 1411 and the power supply line 1401 described in

[0825] (First method of pupil correction)

[0826] Next, a first method of pupil correction in the light receiving element 1 will be described.

[0827] The light receiving element 1 as a CAPD sensor is the same as the image sensor, and pupil correction can be performed by shifting the on-chip lens 62 and the inter-pixel light shielding film 63 toward the plane center of the pixel array unit 20 according to the difference in the incident angle of the principal ray corresponding to the in-plane position of the pixel array unit 20.

[0828] Specifically, as in Fig.79As shown, in the pixel 51 at the position 1701-5 in the central part of the pixel array section 20 among the positions 1701-1 to 1701-9 in the pixel array section 20, the center of the on-chip lens 62 coincides with the center between the signal extraction sections 65-1 and 65-2 formed on the substrate 61. However, in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6, and 1701-9 in the peripheral part of the pixel array section 20, the center of the on-chip lens 62 is offset and arranged toward the plane center side of the pixel array section 20. The inter-pixel light shielding films 63-1 and 63-2 are also arranged offset toward the plane center side of the pixel array section 20 in the same manner as the on-chip lens 62.

[0829] In addition, as Fig.80 shown, in the pixel 51, in the case where DTI 1711-1 and 1711-2 having grooves (slots) formed from the back side on the on-chip lens 62 side of the substrate 61 along the substrate depth direction to a prescribed depth are formed at the pixel boundary part to prevent incident light from entering adjacent pixels, in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6, and 1701-9 in the peripheral part of the pixel array section 20, in addition to the on-chip lens 62, the inter-pixel light shielding films 63-1 and 63-2, DTI 1711-1 and 1711-2 are also arranged offset toward the plane center side of the pixel array section 20.

[0830] Or, in addition, as Fig.81 shown, in the pixel 51, in the case where DTI 1712-1 and 1712-2 having grooves (slots) formed from the surface side on the multi-layer wiring layer 811 side of the substrate 61 along the substrate depth direction to a prescribed depth are formed at the pixel boundary part to prevent incident light from entering adjacent pixels, in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6, and 1701-9 in the peripheral part of the pixel array section 20, in addition to the on-chip lens 62, the inter-pixel light shielding films 63-1 and 63-2, DTI 1712-1 and 1712-2 are also arranged offset toward the plane center side of the pixel array section 20.

[0831] Further, as a pixel separation section that separates the substrates 61 of adjacent pixels from each other and prevents incident light from entering adjacent pixels, instead of DTI 1711-1, 1711-2, 1712-1, and 1712-2, a through-separation section that penetrates the substrate 61 and separates adjacent pixels may be provided. In this case as well, in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6, and 1701-9 in the peripheral part of the pixel array section 20, the through-separation section is arranged offset toward the plane center side of the pixel array section 20.

[0832] As Figure 79 to Figure 81As shown, by shifting the on-chip lens 62 together with the inter-pixel light-shielding film 63 etc. toward the plane center side of the pixel array unit 20, the chief ray can be made to coincide with the center within each pixel. However, in the light-receiving element 1 of the CAPD sensor, since modulation is performed by applying a voltage between the two signal extraction units 65 (taps) and flowing a current, the optimal incident position within each pixel is different. Therefore, in the light-receiving element 1, different from the optical pupil correction performed by an image sensor, a pupil correction technique optimal for distance measurement is sought.

[0833] Refer to Fig.82 The difference between the pupil correction performed by the light-receiving element 1 of the CAPD sensor and the pupil correction performed by the image sensor will be described.

[0834] In addition, in Fig.82 from A to C, the nine 3×3 pixels 51 represent the pixels 51 corresponding to the positions 1701-1 to 1701-9 of the pixel array unit 20 of Figure 79 to Figure 81 The positions 1701-1 to 1701-9 of the pixel array unit 20.

[0835] Fig.82 A of

[0836] shows the position of the on-chip lens 62 and the position 1721 of the chief ray on the substrate surface side in the case where no pupil correction is performed. In the case where no pupil correction is performed, in the pixels 51 at any of the positions 1701-1 to 1701-9 within the pixel array unit 20, the center of the on-chip lens 62 is arranged to coincide with the center of the two taps within the pixel, that is, the center of the first tap TA (signal extraction unit 65-1) and the second tap TB (signal extraction unit 65-2). In this case, the position 1721 of the chief ray on the substrate surface side, as shown in Fig.82 A of

[0837] In the pupil correction performed by the image sensor, as shown in Fig.82 B of Figure 79 to Figure 81 the on-chip lens 62 is arranged such that the position 1721 of the chief ray coincides with the center of the first tap TA and the second tap TB in the pixels 51 at any of the positions 1701-1 to 1701-9 within the pixel array unit 20. More specifically, as shown in

[0838] B of Fig.82 the on-chip lens 62 is arranged to shift toward the plane center side of the pixel array unit 20. Fig.82From the position of the on-chip lens 62 where the position 1721 of the chief ray shown in B becomes the center positions of the first tap TA and the second tap TB, the on-chip lens 62 is further arranged toward the first tap TA side. Fig.82 B of Fig.82 The offset of the position 1721 of the chief ray from the C becomes larger as it approaches the peripheral part from the center position of the pixel array unit 20.

[0839] Fig.83 It is a diagram for explaining the offset amount of the on-chip lens 62 when the position 1721 of the chief ray is offset toward the first tap TA side.

[0840] For example, the position 1721 of the chief ray at the position 1701 - 5 in the center part of the pixel array unit 20 c and the position 1721 of the chief ray at the position 1701 - 4 in the peripheral part of the pixel array unit 20 X The offset amount LD is equal to the optical path difference LD for pupil correction at the position 1701 - 4 in the peripheral part of the pixel array unit 20.

[0841] In other words, it moves from the center position of the first tap TA (signal extraction unit 65 - 1) and the second tap TB (signal extraction unit 65 - 2) toward the first tap TA side so that the optical path length of the chief ray is made consistent in each pixel of the pixel array unit 20.

[0842] Here, the movement toward the first tap TA side is based on the premise that the light reception time is set to 4Phase and the phase shift (Phase) corresponding to the delay time ΔT corresponding to the distance to the object is calculated using only the output value of the first tap TA.

[0843] Fig.84 It is a timing chart for explaining the detection method based on 2Phase (2Phase method) and the detection method based on 4Phase (4Phase method) in a ToF sensor using the indirect ToF method.

[0844] Irradiation light modulated in an on / off manner (1 cycle = 2T) that is repeatedly irradiated at the irradiation time T is output from a prescribed light source, and in the light receiving element 1, the reflected light is received after delaying the delay time ΔT corresponding to the distance to the object.

[0845] In the 2Phase method, the light receiving element 1 receives light at times when the first tap TA and the second tap TB are phase - shifted by 180 degrees. The phase shift amount θ corresponding to the delay time ΔT can be detected based on the signal value q received by the first tap TA A and the signal value q received by the second tap TB B by the distribution ratio.

[0846] In contrast, in the 4Phase method, light reception is performed at four times at phases that are the same as the irradiation light (i.e., Phase0), 90 degrees out of phase (Phase90), 180 degrees out of phase (Phase180), and 270 degrees out of phase (Phase270). Thus, the signal value TA detected at the 180-degree out-of-phase phase180 is the same as the signal value q received by the second tap TB in the 2Phase method B . Therefore, if detection is performed in 4Phase, the phase shift amount θ corresponding to the delay time ΔT can be detected based on the signal value of only either the first tap TA or the second tap TB. In the 4Phase method, the tap for detecting the phase shift amount θ is called the phase shift detection tap

[0847] Here, in the case where the first tap TA among the first tap TA and the second tap TB is set as the phase shift detection tap for detecting the phase shift amount θ, in pupil correction, in each pixel of the pixel array unit 20, it is moved toward the first tap TA so that the optical path length of the chief ray is substantially the same

[0848] When the signal values detected by the first tap TA at Phase0, Phase90, Phase180, and Phase270 in the 4Phase method are respectively set as q 0A , q 1A , q 2A , q 3A , the phase shift amount θA detected by the first tap TA is calculated by the following formula (2)

[0849] (Equation 1)

[0850]

[0851] In addition, Cmod in the 4Phase method in the case of detection by the first tap TA A is calculated by the following formula (3)

[0852] (Equation 2)

[0853]

[0854] As shown in formula (3), Cmod in the 4Phase method A becomes (q 0A - q 2A ) / (q 0A + q 2A ) and (q 1A - q 3A ) / (q 1A + q3A ) The value of the larger one among them.

[0855] As described above, the light-receiving element 1 changes the positions of the on-chip lens 62 and the inter-pixel light-shielding film 63 to perform pupil correction so that the optical path length of the chief ray is substantially the same among the respective pixels in the plane of the pixel array unit 20. In other words, the light-receiving element 1 performs pupil correction so that the phase shift amount θ of the phase shift detection tap, i.e., the first tap TA, of each pixel in the plane of the pixel array unit 20 A is substantially the same. Thereby, the in-plane dependency of the chip can be eliminated, and the ranging accuracy can be improved. Here, the above-mentioned substantially consistent or substantially the same means equal within a specified range that can be regarded as the same in addition to being completely consistent or completely the same. The first method of pupil correction can also be applied to any of the embodiments described in this specification.

[0856] (The second method of pupil correction)

[0857] Next, the second method of pupil correction in the light-receiving element 1 will be described.

[0858] In the above-mentioned first method of pupil correction, it is preferable to calculate the phase shift (Phase) using the signal of the first tap TA among the first tap TA and the second tap TB, but there are also cases where it is impossible to determine which tap to use. In such a case, pupil correction can be performed by the following second method.

[0859] In the second method of pupil correction, the positions of the on-chip lens 62 and the inter-pixel light-shielding film 63 are shifted and arranged toward the plane center side so that the DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are substantially the same among the respective pixels in the plane of the pixel array unit 20. In the case where the DTI 1711 formed from the on-chip lens 62 side of the substrate 61 and the DTI 1712 formed from the surface side are also formed, similar to the first method, their positions are also arranged in a staggered manner.

[0860] The DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are calculated by the following formulas (4) and (5).

[0861] (Formula 3)

[0862]

[0863]

[0864] In formula (4), A HIndicates the signal value detected by the first tap TA to which continuous light that is continuously irradiated without interruption is directly irradiated onto the light receiving element 1, B L Indicates the signal value detected by the second tap TB to which a voltage of 0 or negative is applied. In Equation (5), B H Indicates the signal value detected by the second tap TB to which continuous light that is continuously irradiated without interruption is directly irradiated onto the light receiving element 1, A L Indicates the signal value detected by the first tap TA to which a voltage of 0 or negative is applied.

[0865] Preferably, the DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are equal, and the DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are substantially the same at any position within the plane of the pixel array unit 20. However, depending on the position within the plane of the pixel array unit 20, when the DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are different, the positions of the on-chip lens 62, the inter-pixel light shielding film 63, etc. are arranged to be offset toward the plane center side so that the offset amount of the DC contrast DC of the first tap TA between the center portion and the outer peripheral portion of the pixel array unit 20 A is substantially the same as the offset amount of the DC contrast DC of the second tap TB between the center portion and the outer peripheral portion of the pixel array unit 20 B .

[0866] As described above, the light receiving element 1 changes the positions of the on-chip lens 62 and the inter-pixel light shielding film 63, and performs pupil correction so that the DC contrast DC of the first tap TA A and the DC contrast DC of the second tap TB B are substantially the same in each pixel within the plane of the pixel array unit 20. Thereby, the in-plane dependency of the chip can be eliminated, and the ranging accuracy can be improved. Here, the above-mentioned substantially the same or substantially identical means equal within a specified range that can be regarded as the same in addition to being exactly the same or exactly identical. The second method of pupil correction can also be applied to any of the embodiments described in this specification.

[0867] In addition, Fig.84 The light receiving times of the first tap TA and the second tap TB shown are controlled by the voltages MIX0 and MIX1 supplied from the tap driving unit 21 via the voltage supply line 30. Since the voltage supply line 30 is commonly arranged in one pixel column along the vertical direction of the pixel array unit 20, the farther the distance from the tap driving unit 21, the greater the delay caused by the RC component.

[0868] Therefore, as Fig.85 shown, according to the distance from the tap driving unit 21, the resistance and capacitance of the voltage supply line 30 are changed so that the driving capabilities of the respective pixels 51 are substantially uniform, thereby enabling correction so that the phase shift (Phase) or the DC contrast DC is substantially uniform in the plane of the pixel array unit 20. Specifically, according to the distance from the tap driving unit 21, the voltage supply line 30 is arranged in such a manner that the line width becomes thicker.

[0869] (Twenty - th Embodiment)

[0870] In the following twenty - th to twenty - second embodiments, a structural example of the light - receiving element 1 that can obtain correction information other than the distance - measuring information obtained from the signal distribution ratio of the first tap TA and the second tap TB is described.

[0871] First, a structural example of the light - receiving element 1 that can obtain phase - difference information, which is correction information other than the distance - measuring information obtained from the signal distribution ratio of the first tap TA and the second tap TB, will be described.

[0872] (First Structural Example of Twenty - th Embodiment)

[0873] Fig.86 A in is a cross - sectional view of a pixel of the first structural example of the twenty - th embodiment, Fig.86 B and C in are top - view diagrams of a pixel of the first structural example of the twenty - th embodiment.

[0874] In Fig.86 the cross - sectional view of A, the parts corresponding to the above - mentioned other embodiments are denoted by the same reference numerals, and the description of those parts is appropriately omitted.

[0875] In Fig.86 , in a pixel 51 on a part of the upper surface, which is the surface of the substrate 61 on the side of the on - chip lens 62, a phase - difference light - shielding film 1801 for phase - difference detection is newly provided. The phase - difference light - shielding film 1801, for example, as Fig.86 shown in B and C of, shields one - half of one side of the pixel region on either the first - tap TA side or the second - tap TB side. Fig.86 B of is an example of a pixel 51 in which the first tap TA and the second tap TB are arranged in the vertical direction (up - and - down direction), Fig.86 C of is an example of a pixel 51 in which the first tap TA and the second tap TB are arranged in the horizontal direction (left - and - right direction).

[0876] The pixel 51 of the first structural example of the twenty - th embodiment can be arranged in any one of Fig.87 A to F of shown.

[0877] Figure 87A shows an example of the arrangement of the pixel 51s in a matrix arrangement where the first tap TA and the second tap TB are arranged in the vertical direction.

[0878] Figure 87 B shows an example of the arrangement of the pixel 51s in a matrix arrangement where the first tap TA and the second tap TB are arranged in the horizontal direction.

[0879] Figure 87 C shows an example of the arrangement of the pixel 51s in a matrix arrangement where the first tap TA and the second tap TB are arranged in the vertical direction, and the pixel positions are offset by half a pixel in the vertical direction in adjacent columns.

[0880] Figure 87 D shows an example of the arrangement of the pixel 51s in a matrix arrangement where the first tap TA and the second tap TB are arranged in the horizontal direction, and the pixel positions are offset by half a pixel in the vertical direction in adjacent columns.

[0881] Figure 87 E shows an example of the arrangement of the pixel 51s where the pixel 51s with the first tap TA and the second tap TB arranged in the vertical direction and the pixel 51s with the first tap TA and the second tap TB arranged in the horizontal direction are alternately arranged in the row direction and the column direction.

[0882] Figure 87 F shows an example of the arrangement of the pixel 51s where the pixel 51s with the first tap TA and the second tap TB arranged in the vertical direction and the pixel 51s with the first tap TA and the second tap TB arranged in the horizontal direction are alternately arranged in the row direction and the column direction, and the pixel positions are offset by half a pixel in the vertical direction in adjacent columns.

[0883] Figure 86 The pixel 51s are Figure 87 arranged in any one of the arrangements A to F as shown, within the pixel array unit 20, as Figure 86 shown in B or C, the pixel 51s with one side half shaded on the first tap TA side and the pixel 51s with one side half shaded on the second tap TB side are arranged in nearby positions. In addition, a plurality of groups of the pixel 51s with one side half shaded on the first tap TA side and the pixel 51s with one side half shaded on the second tap TB side are arranged dispersedly within the pixel array unit 20.

[0884] In the first structural example of the twentieth embodiment, except that the phase difference light-shielding film 1801 is provided on a part of the pixel 51s, for example, it is configured in the same manner as the Figure 2 first embodiment shown, Figure 36 the fourteenth or fifteenth embodiment described in Figure 86 However, in

[0885] When briefly explaining the structure other than the phase difference light-shielding film 1801 of Figure 86 , the pixel 51 has a substrate 61 made of a P-type semiconductor layer and an on-chip lens 62 formed on the substrate 61. An inter-pixel light-shielding film 63 and a phase difference light-shielding film 1801 are formed between the on-chip lens 62 and the substrate 61. In the pixel 51 where the phase difference light-shielding film 1801 is formed, the inter-pixel light-shielding film 63 adjacent to the phase difference light-shielding film 1801 is formed continuously (integrally) with the phase difference light-shielding film 1801. Although not shown in the figure, a fixed charge film 66 is also formed on the lower surfaces of the inter-pixel light-shielding film 63 and the phase difference light-shielding film 1801, as shown in Figure 2 .

[0886] On the surface of the substrate 61 opposite to the light incident surface side where the on-chip lens 62 is formed, a first tap TA and a second tap TB are formed. The first tap TA corresponds to the signal extraction part 65-1 described above, and the second tap TB corresponds to the signal extraction part 65-2. A predetermined voltage MIX0 is supplied to the first tap TA from the tap driving part 21 ( Figure 1 ) via the voltage supply line 30A formed in the multilayer wiring layer 811, and a predetermined voltage MIX1 is supplied to the second tap TB via the voltage supply line 30B.

[0887] Figure 88 It is a table summarizing the driving modes when the tap driving part 21 drives the first tap TA and the second tap TB in the first structural example of the twentieth embodiment.

[0888] In the pixel 51 having the phase difference light-shielding film 1801, the phase difference can be detected by five types of driving methods of mode 1 to mode 5 shown in Figure 88 .

[0889] Mode 1 is the same driving as other pixels 51 that do not have the phase difference light-shielding film 1801. In mode 1, during a predetermined light receiving period, the tap driving part 21 applies a positive voltage (for example, 1.5V) to the first tap TA set as the active tap, and applies a voltage of 0V to the second tap TB set as the passive tap. In the next light receiving period, a positive voltage (for example, 1.5V) is applied to the second tap TB set as the active tap, and a voltage of 0V is applied to the first tap TA set as the passive tap. A voltage of 0V (VSS potential) is applied to the pixel transistors Tr ( Figure 37 ), such as the transfer transistor 721 and the reset transistor 723, formed in the pixel boundary region of the substrate 61 in the multilayer wiring layer 811.

[0890] ​​​​​​​​​​In Mode 1, the phase difference can be detected based on the signal with the second tap TB set as the active tap in the pixel 51 where one-sided half on the first tap TA side is shielded, and the signal with the first tap TA set as the active tap in the pixel 51 where one-sided half on the second tap TB side is shielded.

[0891] In Mode 2, the tap driving unit 21 applies a positive voltage (e.g., 1.5 V) to both the first tap TA and the second tap TB. A 0 V (VSS potential) is applied to the pixel transistor Tr in the pixel boundary region of the substrate 61 formed on the multilayer wiring layer 811.

[0892] In Mode 2, since signals can be detected equally by both the first tap TA and the second tap TB, the phase difference can be detected based on the signals of the pixels 51 where one-sided half on the first tap TA side is shielded and the signals of the pixels 51 where one-sided half on the second tap TB side is shielded.

[0893] Mode 3 is a driving method in which, in the driving of Mode 2, weights corresponding to the image height within the pixel array unit 20 are added to the applied voltages of the first tap TA and the second tap TB. More specifically, the greater the image height (distance from the optical center) within the pixel array unit 20, the greater the potential difference applied to the first tap TA and the second tap TB. Further, the driving is performed such that the greater the image height within the pixel array unit 20, the greater the applied voltage on the tap side located inside (center side) of the pixel array unit 20. Thus, pupil correction can be performed based on the potential difference of the voltages applied to the taps.

[0894] Mode 4 is a mode in which, in the driving of Mode 2, a negative bias voltage (e.g., -1.5 V) is applied to the pixel transistor Tr formed in the pixel boundary region of the substrate 61 instead of 0 V (VSS potential). By applying a negative bias voltage to the pixel transistor Tr formed in the pixel boundary region, the electric field from the pixel transistor Tr to the first tap TA and the second tap TB can be strengthened, and electrons as signal charges can be easily introduced into the taps.

[0895] Mode 5 is a mode in which, in the driving of Mode 3, a negative bias voltage (e.g., -1.5 V) is applied to the pixel transistor Tr formed in the pixel boundary region of the substrate 61 instead of 0 V (VSS potential). Thus, the electric field from the pixel transistor Tr to the first tap TA and the second tap TB can be strengthened, and electrons of the signal charges can be easily introduced into the taps.

[0896] In any of the five types of driving methods of the above-described Mode 1 to Mode 5, in the pixels 51 in which one side half on the first tap TA side is shielded and the pixels 51 in which one side half on the second tap TB side is shielded, a phase difference (image shift) is generated in the read signals due to the difference in the shielding regions, and thus the phase difference can be detected.

[0897] According to the first structural example of the twentieth embodiment configured as described above, the light receiving element 1 has, in some of the pixels 51 in the pixel array unit 20 in which a plurality of pixels 51 each having a first tap TA and a second tap TB are arranged: pixels 51 in which one side half on the first tap TA side is shielded by the phase difference shielding film 1801; and pixels 51 in which one side half on the second tap TB side is shielded by the phase difference shielding film 1801. Thereby, as calibration information other than the distance measurement information obtained from the signal distribution ratio of the first tap TA and the second tap TB, phase difference information can be acquired. According to the detected phase difference information, the focal position can be divided and the accuracy in the depth direction can be improved.

[0898] (Second structural example of the twentieth embodiment)

[0899] Figure 89 A cross-sectional view of a pixel showing the second structural example of the twentieth embodiment.

[0900] In Figure 89 the cross-sectional view, the same reference numerals are given to the parts corresponding to the first structural example of the above-described twentieth embodiment, and the description of that part is appropriately omitted.

[0901] In Figure 86 the first structural example shown, the on-chip lens 62 is formed in units of one pixel, but in Figure 89 the second structural example, one on-chip lens 1821 is formed for a plurality of pixels 51. A phase difference shielding film 1811 for phase difference detection is newly provided in the pixels 51 which are a part of the upper surface on the on-chip lens 1821 side of the substrate 61. The phase difference shielding film 1811 is formed in the specified pixels 51 among the plurality of pixels 51 sharing the same on-chip lens 1821. The pixel pitch shielding film 63 adjacent to the phase difference shielding film 1811 and the phase difference shielding film 1811 are formed continuously (integrally), which is the same as the first structural example.

[0902] Figure 90 A to F of are top views showing the configurations of the phase difference shielding film 1811 and the on-chip lens 1821 that can be adopted in the second structural example of the twentieth embodiment.

[0903] Figure 90 A of shows a first configuration example of the phase difference shielding film 1811 and the on-chip lens 1821.

[0904] Figure 90 The pixel group 1831 shown in A of FIG. is composed of two pixels 51 arranged in the vertical direction (up and down direction). One on-chip lens 1821 is arranged with respect to the two pixels 51 arranged in the vertical direction. In addition, the configurations of the first tap TA and the second tap TB of the two pixels 51 sharing one on-chip lens 1821 are the same. And, two pixels 51 that do not form the phase difference light-shielding film 1811 in two sets of pixel groups 1831 where the formation positions of the phase difference light-shielding film 1811 are symmetric are used to detect the phase difference.

[0905] Figure 90 B of FIG. shows a second configuration example of the phase difference light-shielding film 1811 and the on-chip lens 1821.

[0906] Figure 90 The pixel group 1831 shown in A of FIG. is composed of two pixels 51 arranged in the vertical direction (up and down direction). One on-chip lens 1821 is arranged with respect to the two pixels 51 arranged in the vertical direction. In addition, the configurations of the first tap TA and the second tap TB of the two pixels 51 sharing one on-chip lens 1821 are opposite. And, two pixels 51 that do not form the phase difference light-shielding film 1811 in two sets of pixel groups 1831 where the formation positions of the phase difference light-shielding film 1811 are symmetric are used to detect the phase difference.

[0907] Figure 90 C of FIG. shows a third configuration example of the phase difference light-shielding film 1811 and the on-chip lens 1821.

[0908] Figure 90 The pixel group 1831 shown in C of FIG. is composed of two pixels 51 arranged in the horizontal direction (left and right direction). One on-chip lens 1821 is arranged with respect to the two pixels 51 arranged in the horizontal direction. In addition, the configurations of the first tap TA and the second tap TB of the two pixels 51 sharing one on-chip lens 1821 are the same. And, two pixels 51 that do not form the phase difference light-shielding film 1811 in two sets of pixel groups 1831 where the formation positions of the phase difference light-shielding film 1811 are symmetric are used to detect the phase difference.

[0909] Figure 90 D of FIG. shows a fourth configuration example of the phase difference light-shielding film 1811 and the on-chip lens 1821.

[0910] Figure 90The pixel group 1831 shown in D is composed of two pixels 51 arranged in the left - right direction (horizontal direction), and one on - chip lens 1821 is arranged relative to the two pixels 51 arranged in the left - right direction. In addition, the configurations of the first tap TA and the second tap TB of the two pixels 51 sharing one on - chip lens 1821 are opposite. And, two pixels 51 that do not form the phase - difference light - shielding film 1811 in two pixel groups 1831 with symmetric formation positions of the phase - difference light - shielding film 1811 are used to detect the phase difference.

[0911] Figure 90 E shows a fifth configuration example of the phase - difference light - shielding film 1811 and the on - chip lens 1821.

[0912] Figure 90 The pixel group 1831 shown in E is composed of four pixels 51 arranged in a 2×2 array, and one on - chip lens 1821 is arranged relative to the four pixels 51. In addition, the configurations of the first tap TA and the second tap TB of the four pixels 51 sharing one on - chip lens 1821 are the same. And, four pixels 51 that do not form the phase - difference light - shielding film 1811 in two pixel groups 1831 with symmetric formation positions of the phase - difference light - shielding film 1811 are used to detect the phase difference.

[0913] Figure 90 F shows a sixth configuration example of the phase - difference light - shielding film 1811 and the on - chip lens 1821.

[0914] Figure 90 The pixel group 1831 shown in F is composed of four pixels 51 arranged in a 2×2 array, and one on - chip lens 1821 is arranged relative to the four pixels 51. In addition, the configurations of the first tap TA and the second tap TB of the four pixels 51 sharing one on - chip lens 1821 are opposite in the left - right pixels. And, four pixels 51 that do not form the phase - difference light - shielding film 1811 in two pixel groups 1831 with symmetric formation positions of the phase - difference light - shielding film 1811 are used to detect the phase difference.

[0915] As described above, as the configuration in the case of forming one on - chip lens 1821 relative to a plurality of pixels 51, there are configurations of forming one on - chip lens 1821 relative to two pixels and forming one on - chip lens 1821 relative to four pixels, and either one can be adopted. The phase - difference light - shielding film 1811 shields a plurality of pixels that are one - side half under one on - chip lens 1821.

[0916] The driving mode in the second structural example can be five types of driving methods of mode 1 to mode 5 described with reference to Figure 88 Explanation.

[0917] Therefore, according to the second structural example of the twentieth embodiment, in some of the pixels 51 in the pixel array unit 20 where a plurality of pixels 51 each having a first tap TA and a second tap TB are arranged, the light receiving element 1 has two pixel groups 1831 with symmetric formation positions of the phase difference light shielding film 1811. Thus, as calibration information other than the ranging information obtained from the signal distribution ratio of the first tap TA and the second tap TB, phase difference information can be obtained. Based on the detected phase difference information, the focal position can be divided, improving the accuracy in the depth direction.

[0918] In addition, as the plurality of pixels 51 constituting the pixel array unit 20, the pixels 51 of the first structural example of the twentieth embodiment and the pixels 51 of the second structural example of the twentieth embodiment may coexist.

[0919] (Modification example without phase difference light shielding film)

[0920] In the first and second structural examples of the twentieth embodiment described above, a structure in which the phase difference light shielding film 1801 or 1811 is formed between the on-chip lens 62 and the substrate 61 has been described.

[0921] However, even for the pixels 51 that do not have the phase difference light shielding film 1801 or 1811, if the driving methods of the five types of modes 1 to 5 are used, and the driving of modes 2 to 5 in which positive voltages are simultaneously applied to both the first tap TA and the second tap TB is performed, phase difference information can also be obtained. For example, by driving half of the pixels 51 on one side among the plurality of pixels under one on-chip lens 1821 in modes 2 to 5, phase difference information can be obtained. Even in a structure where one on-chip lens 62 is arranged for each pixel, by driving in modes 2 to 5, phase difference information can also be obtained.

[0922] Therefore, in the pixels 51 that do not have the phase difference light shielding film 1801 or 1811, by performing the driving of modes 2 to 5, phase difference information can also be obtained. In this case, based on the detected phase difference information, the focal position can be divided, improving the accuracy in the depth direction.

[0923] In addition, in the pixels 51 that do not have the phase difference light shielding film 1801 or 1811, when it is desired to obtain phase difference information using the driving of mode 1, as long as the irradiation light irradiated from the light source is set to continuous light that is continuously irradiated without interruption, phase difference information can be obtained.

[0924] (Twenty-first embodiment)

[0925] Next, a structural example of the light-receiving element 1 that can obtain the degree-of-polarization information for correction information other than the ranging information obtained as the distribution ratio of the signals of the first tap TA and the second tap TB will be described.

[0926] Figure 91 Cross-sectional view of a pixel showing the twenty-first embodiment.

[0927] In Figure 91 Parts corresponding to the above-described twentieth embodiment are denoted by the same reference numerals, and description thereof is appropriately omitted.

[0928] In Figure 91 In the twenty-first embodiment of Figure 2 a polarization filter 1841 is formed between the on-chip lens 62 and the substrate 61. The pixel 51 of the twenty-first embodiment is configured in the same manner as, for example, the first embodiment shown in Figure 36 the fourteenth or fifteenth embodiment described in

[0929] The polarization filter 1841, the on-chip lens 62, and the first tap TA and the second tap TB are set to the configuration of either A or B in Figure 92 A top view showing a first configuration example of the polarization filter 1841, the on-chip lens 62, and the first tap TA and the second tap TB in the twenty-first embodiment is shown in

[0930] Figure 92 As shown in A of

[0931] As Figure 92 shown in A of

[0932] the polarization filter 1841 has a polarization direction of any one of 0 degrees, 45 degrees, 135 degrees, or 225 degrees, and four different polarization filters 1841 with polarization directions differing by 45 degrees each are formed in the specified pixels 51 within the pixel array unit 20 in units of 2×2 pixels.

[0933] Figure 92 A top view showing a second configuration example of the polarization filter 1841, the on-chip lens 62, and the first tap TA and the second tap TB in the twenty-first embodiment is shown in

[0934] As Figure 92As shown in B of FIG. 0, the polarization filter 1841 has a polarization direction of any one of 0 degrees, 45 degrees, 135 degrees, or 135 degrees, and four different polarization filters 1841 with polarization directions differing by 45 degrees each are formed in a prescribed pixel 51 within the pixel array unit 20 in units of 4 pixels of 2×2.

[0935] The on-chip lens 62 is provided for each pixel, and the positional relationship between the first tap TA and the second tap TB is opposite in horizontally adjacent pixels. In other words, pixel columns in which the configurations of the first tap TA and the second tap TB are opposite are alternately arranged horizontally.

[0936] The driving method of the pixel 51 provided with the polarization filter 1841 can be one of five types of driving methods, namely, Mode 1 to Mode 5 described with reference to the Figure 88 twentieth embodiment.

[0937] In the twenty-first embodiment, among a plurality of pixels 51 arranged in the pixel array unit 20, some of the pixels 51 are provided with Figure 91 and Figure 92 the polarization filter 1841 shown in FIGS.

[0938] By driving the pixel 51 provided with the polarization filter 1841 in any one of Mode 1 to Mode 5, polarization degree information can be obtained. Based on the obtained polarization degree information, information regarding the surface state (concavity and convexity) and relative distance difference of the object surface as the subject can be obtained, or the reflection direction can be calculated, and ranging information of the transparent object itself such as glass and the object in front of the transparent object can be obtained.

[0939] In addition, by setting a plurality of frequencies of the irradiation light irradiated from the light source and making the polarization directions different for each frequency, parallel ranging with multiple frequencies can be performed. For example, by simultaneously irradiating four types of irradiation light of 20 MHz, 40 MHz, 60 MHz, and 100 MHz and making their respective polarization directions coincide with the polarization directions of the polarization filter 1841 to be 0 degrees, 45 degrees, 135 degrees, and 135 degrees, respectively, the reflected light of the four types of irradiation light can be received simultaneously, and ranging information can be obtained.

[0940] Alternatively, all the pixels 51 of the pixel array unit 20 of the light receiving element 1 may be pixels 51 provided with the polarization filter 1841.

[0941] (Twenty-second embodiment)

[0942] Next, a structural example of the light receiving element 1 that can obtain sensitivity information for each wavelength of RGB as correction information other than the ranging information obtained from the signal distribution ratio between the first tap TA and the second tap TB will be described.

[0943] Figure 93Cross-sectional view of a pixel showing the twenty-second embodiment.

[0944] In the twenty-second embodiment, the light-receiving element 1 is provided as a pixel 51 that is part of the pixel array section 20 and has Figure 93 at least one of pixels 51 of A or B.

[0945] In Figure 93 for A and B, the parts corresponding to the above-described twentieth embodiment are denoted by the same reference numerals, and the description of this part is appropriately omitted.

[0946] Figure 93 For the pixel 51 shown in A of, a color filter 1861 that can transmit the wavelength of any one of R (Red), G (Green), or B (Blue) is formed between the on-chip lens 62 and the substrate 61. Figure 93 The pixel 51 shown in A of, except for the provision of the color filter 1861, is configured in the same manner as, for example, Figure 2 the first embodiment shown in, Figure 36 the fourteenth or fifteenth embodiment described in.

[0947] On the other hand, in Figure 93 for B, between the on-chip lens 62 and the substrate 61, pixels 51 formed by laminating an IR cut filter 1871 that cuts off infrared light and a color filter 1872 and pixels 51 in which the IR cut filter 1871 and the color filter 1872 are not formed are arranged adjacent to each other. Further, on the substrate 61 of the pixel 51 in which the IR cut filter 1871 and the color filter 1872 are formed, a first tap TA and a second tap TB are not formed, but a photodiode 1881 is formed. Furthermore, at the pixel boundary portion of the pixel 51 in which the photodiode 1881 is formed, a pixel separation portion 1882 that separates the adjacent pixel from the substrate 61 is formed. The pixel separation portion 1882 is formed, for example, by covering the outer periphery of a metal material such as tungsten (W), aluminum (Al), or copper (Cu) or a conductive material such as polysilicon with an insulating film. The movement of electrons between adjacent pixels is restricted by the pixel separation portion 1882. The pixel 51 having the photodiode 1881 is separately driven via a control wiring different from that of the pixel 51 having the first tap TA and the second tap TB. Other structures are, for example, the same as Figure 2 the first embodiment shown in, Figure 36 the fourteenth embodiment shown in.

[0948] Figure 94 A of is a plan view showing the arrangement of the color filters 1861 in a 4-pixel region in which the pixels 51 shown in A of Figure 93 are arranged in a 2×2 manner.

[0949] For a 2×2 4-pixel region, the color filter 1861 arranges four types, which are a filter transmitting G, a filter transmitting R, a filter transmitting B, and a filter transmitting IR, in a 2×2 pattern.

[0950] Figure 94 B of is with respect to Figure 93 a top view of a 4-pixel region where the pixels 51 shown in A of are arranged in a 2×2 pattern Figure 93 at the A-A' line of A of.

[0951] In Figure 93 the pixel 51 shown in A of, the first tap TA and the second tap TB are arranged in units of pixels.

[0952] Figure 94 C of represents Figure 93 a top view of the arrangement of the color filter 1872 in a 4-pixel region where the pixels 51 shown in B of are arranged in a 2×2 pattern.

[0953] For a 2×2 4-pixel region, the color filter 1872 arranges four types, which are a filter transmitting G, a filter transmitting R, a filter transmitting B, and air (no filter), in a 2×2 pattern. Additionally, instead of air, a transparent filter that transmits all wavelengths (R, G, B, IR) can be arranged.

[0954] In the color filter 187, above the filter transmitting G, the filter transmitting R, and the filter transmitting B, as Figure 93 shown in B of, an IR cut-off filter 1871 is arranged.

[0955] Figure 94 D of is Figure 93 a top view of a 4-pixel region where the pixels 51 shown in B of are arranged in a 2×2 pattern, Figure 93 at the B-B' line of B of.

[0956] In the substrate 61 portion of a 2×2 4-pixel region, a photodiode 1881 is formed in the pixel 51 having a filter transmitting G, R, or B, and the first tap TA and the second tap TB are formed in the pixel 51 having air (no filter). In addition, at the pixel boundary portion of the pixel 51 where the photodiode 1881 is formed, a pixel separation portion 1882 that separates adjacent pixels from the substrate 61 is formed.

[0957] As described above, Figure 93 the pixel 51 shown in A of has Figure 94 the color filter 1861 shown in A of and Figure 94 the combination with the photoelectric conversion region shown in B of, Figure 93 the pixel 51 shown in B of has Figure 94The combination of the color filter 1872 shown in C of Figure 94 and the photoelectric conversion region shown in D of

[0958] However, Figure 94 The combination of the color filters of A and C of Figure 94 and the photoelectric conversion regions of B and D of Figure 94 The color filter 1861 shown in A of Figure 94 and the combination structure of the photoelectric conversion region shown in D of Figure 94 The color filter 1872 shown in C of Figure 94 and the combination structure of the photoelectric conversion region shown in B of

[0959] The driving of the pixel 51 having the first tap TA and the second tap TB can be five types of driving methods of modes 1 to 5 described with reference to Figure 88 The driving of the pixel 51 having the photodiode 1881 is different from the driving of the pixel 51 having the first tap TA and the second tap TB, and is driven in the same manner as the pixel of a normal image sensor.

[0960] According to the twenty-second embodiment, the light receiving element 1, as a part of the pixel array unit 20 in which a plurality of pixels 51 having the first tap TA and the second tap TB are arranged, as

[0961] shown in A of Figure 93 can include the pixel 51 having the color filter 1861 on the light incident surface side of the substrate 61 where the first tap TA and the second tap TB are formed. Thus, signals can be obtained for each wavelength of G, R, B, and IR, and the object recognition ability can be improved.

[0962] Furthermore, according to the twenty-second embodiment, the light receiving element 1, as a part of the pixel array unit 20 in which a plurality of pixels 51 having the first tap TA and the second tap TB are arranged, as Figure 93 shown in B of

[0963] can include the pixel 51 having the photodiode 1881 in the substrate 61 instead of the first tap TA and the second tap TB and having the color filter 1872 on the light incident surface side. Thus, G signals, R signals, and B signals identical to those of an image sensor can be obtained, and the object recognition ability can be improved. Figure 93 Furthermore, both the pixel 51 having the first tap TA and the second tap TB and the color filter 1861 shown in A of Figure 93 and the pixel 51 having the photodiode 1881 and the color filter 1872 shown in B of

[0964] In addition, all the pixels 51 of the pixel array unit 20 of the light receiving element 1 can be composed of Figure 94 pixels of the combination of A and B, Figure 94 pixels of the combination of C and D, Figure 94 pixels of the combination of A and D, Figure 94 at least one of the pixels of the combination of C and B.

[0965] (Structural example of the ranging module)

[0966] Figure 95 It is a block diagram showing a structural example of a ranging module that outputs ranging information using the Figure 1 light receiving element 1.

[0967] The ranging module 5000 includes a light emitting unit 5011, a light emission control unit 5012, and a light receiving unit 5013.

[0968] The light emitting unit 5011 has a light source that emits light of a specified wavelength, emits irradiation light with periodically changing brightness, and irradiates an object. For example, the light emitting unit 5011 has a light emitting diode that emits infrared light with a wavelength in the range of 780 nm to 1000 nm as a light source, and generates irradiation light synchronously with the rectangular wave light emission control signal CLKp supplied from the light emission control unit 5012.

[0969] In addition, as long as the light emission control signal CLKp is a periodic signal, it is not limited to a rectangular wave. For example, the light emission control signal CLKp can also be a sine wave.

[0970] The light emission control unit 5012 supplies the light emission control signal CLKp to the light emitting unit 5011 and the light receiving unit 5013, and controls the irradiation timing of the irradiation light. The frequency of this light emission control signal CLKp is, for example, 20 megahertz (MHz). In addition, the frequency of the light emission control signal CLKp is not limited to 20 megahertz (MHz), and can also be 5 megahertz (MHz) or the like.

[0971] The light receiving unit 5013 receives the reflected light reflected from the object, calculates distance information for each pixel based on the light receiving result, generates a depth image representing the distance from the object with a gray value for each pixel, and outputs it.

[0972] In the light receiving unit 5013, the above-described light receiving element 1 is used. As the light receiving element 1 of the light receiving unit 5013, for example, based on the light emission control signal CLKp, distance information is calculated for each pixel according to the signal intensities detected by the charge detection units (N+ semiconductor regions 71) of the signal extraction units 65-1 and 65-2 of the respective pixels 51 of the pixel array unit 20.

[0973] As described above, the light-receiving unit 5013 of the distance measurement module 5000 that obtains and outputs distance information to the subject by the indirect ToF method can be assembled Figure 1 with the light-receiving element 1. As the light-receiving unit 5013 of the distance measurement module 5000, by adopting the light-receiving element 1 of each of the above-described embodiments, specifically, a light-receiving element that is a back-illuminated type and has improved pixel sensitivity, the distance measurement characteristics of the distance measurement module 5000 can be improved.

[0974] (Application example to a moving body)

[0975] The technology of the present invention (this technology) can be applied to various products. For example, the technology of the present invention can be implemented as a device mounted on any one of moving bodies such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0976] Figure 96 FIG. is a block diagram showing a schematic structural example of a vehicle control system that is an example of a moving body control system to which the technology of the present invention can be applied.

[0977] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In Figure 96 this example, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, an audio-video output unit 12052, and a vehicle-mounted network I / F (interface) 12053 are illustrated.

[0978] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a driving force generation device such as an internal combustion engine or a driving motor that generates the driving force of the vehicle, a driving force transmission mechanism that transmits the driving force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, and a braking device that generates the braking force of the vehicle.

[0979] The vehicle body system control unit 12020 controls the operations of various devices equipped on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, taillights, brake lights, indicator lights, or fog lights. In this case, radio waves or signals from various switches can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives the input of these radio waves or signals and controls the vehicle door lock device, electric window device, lights, etc.

[0980] The vehicle exterior information detection unit 12030 detects the exterior information of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. The vehicle exterior information detection unit 12030 can also perform object detection processing or distance detection processing on objects such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

[0981] The camera unit 12031 is a photosensor that receives light and outputs an electrical signal corresponding to the amount of received light. The camera unit 12031 can output the electrical signal as an image and can also output the electrical signal as ranging information. In addition, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0982] The vehicle interior information detection unit 12040 detects the information inside the vehicle. For example, a driver state detection unit 12041 for detecting the state of the driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures the driver. The vehicle interior information detection unit 12040 can calculate the fatigue level or concentration level of the driver based on the detection information input from the driver state detection unit 12041, and can also determine whether the driver i...

Claims

1. A light-receiving element, characterized in that, The light-receiving element includes: an on-chip lens; a wiring layer; a semiconductor layer disposed between the on-chip lens and the wiring layer, the semiconductor layer including: a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion, detecting a phase difference using signals detected by the first tap and the second tap; and a driving portion that supplies a positive voltage to both the first voltage application portion and the second voltage application portion, wherein, for the positive voltage supplied to the first tap and the second tap, a potential difference is set to be greater toward the outer side of the pixel array portion.

2. The light-receiving element according to claim 1, characterized in that, The wiring layer has at least one layer including a reflection member, and the reflection member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

3. The light-receiving element according to claim 1, characterized in that, The wiring layer has at least one layer including a light-shielding member, and the light-shielding member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

4. The light-receiving element according to claim 1, characterized in that, The on-chip lens is provided in units of one pixel.

5. The light-receiving element according to claim 4, characterized in that, A phase difference light-shielding film that shields one half of the pixel region is further provided between the on-chip lens and the semiconductor layer.

6. The light-receiving element according to claim 1, characterized in that, The on-chip lens is provided in units of a plurality of pixels.

7. The light-receiving element according to claim 6, characterized in that, A phase difference light-shielding film that shields one half of a plurality of pixels below one on-chip lens is further provided between the on-chip lens and the semiconductor layer.

8. The light-receiving element according to claim 1, characterized in that, The first voltage application portion and the second voltage application portion are each constituted by a first P-type semiconductor region and a second P-type semiconductor region formed in the semiconductor layer.

9. The light-receiving element according to claim 1, characterized in that, The first voltage application portion and the second voltage application portion are each constituted by a first transfer transistor and a second transfer transistor formed in the semiconductor layer.

10. A light-receiving element, characterized in that, The light-receiving element includes: an on-chip lens; a wiring layer; a semiconductor layer disposed between the on-chip lens and the wiring layer, the semiconductor layer including: a first tap having a first voltage application portion and a first charge detection portion disposed around the first voltage application portion; and a second tap having a second voltage application portion and a second charge detection portion disposed around the second voltage application portion; a polarizer disposed between the on-chip lens and the semiconductor layer; and a driving portion that supplies a positive voltage to both the first voltage application portion and the second voltage application portion, wherein, for the positive voltage supplied to the first tap and the second tap, a potential difference is set to be greater toward the outer side of the pixel array portion.

11. The light-receiving element according to claim 10, wherein, The wiring layer has at least one layer including a reflection member, and the reflection member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

12. The light-receiving element according to claim 10, wherein, The wiring layer has at least one layer including a light-shielding member, and the light-shielding member is disposed so as to overlap with the first charge detection portion or the second charge detection portion in a plan view.

13. The light-receiving element according to claim 10, wherein, There are at least provided a first pixel having the polarizer with a first degree of polarization and a second pixel having the polarizer with a second degree of polarization.

14. The light-receiving element according to claim 13, wherein, The first pixel and the second pixel receive light of different frequencies.

15. The light-receiving element according to claim 10, wherein, The first voltage application unit and the second voltage application unit are respectively constituted by a first P-type semiconductor region and a second P-type semiconductor region formed in the semiconductor layer.

16. The light-receiving element according to claim 10, wherein, The first voltage application unit and the second voltage application unit are respectively constituted by a first transfer transistor and a second transfer transistor formed in the semiconductor layer.

17. A light-receiving element, wherein, The light receiving element includes: An on-chip lens; A wiring layer; A semiconductor layer disposed between the on-chip lens and the wiring layer, the semiconductor layer including: A first tap having a first voltage application unit and a first charge detection unit disposed around the first voltage application unit; And A second tap having a second voltage application unit and a second charge detection unit disposed around the second voltage application unit; A color filter disposed between the on-chip lens and the semiconductor layer; And A driving unit that supplies a positive voltage to both the first voltage application unit and the second voltage application unit, wherein, for the positive voltage supplied to the first tap and the second tap, a potential difference is set to be larger toward the outside of the pixel array unit.

18. The light-receiving element according to claim 17, wherein, The wiring layer has at least one layer including a reflective member, and the reflective member is disposed so as to overlap with the first charge detection unit or the second charge detection unit in a plan view.

19. The light-receiving element according to claim 17, wherein, The wiring layer has at least one layer including a light-shielding member, and the light-shielding member is disposed so as to overlap with the first charge detection unit or the second charge detection unit in a plan view.

20. The light-receiving element according to claim 17, wherein, A pixel having the color filter further includes an IR cut filter disposed between the on-chip lens and the semiconductor layer.

21. The light-receiving element according to claim 17, wherein, A pixel having the color filter has a photodiode in the semiconductor layer.

22. The light-receiving element according to claim 21, wherein, The pixel having the photodiode further includes a pixel isolation unit that isolates adjacent pixels at a pixel boundary portion of the semiconductor layer.

23. The light-receiving element according to claim 17, wherein, The first voltage application unit and the second voltage application unit are respectively constituted by a first P-type semiconductor region and a second P-type semiconductor region formed in the semiconductor layer.

24. The light-receiving element according to claim 17, wherein, The first voltage application unit and the second voltage application unit are respectively constituted by a first transfer transistor and a second transfer transistor formed in the semiconductor layer.

25. A ranging module, wherein, It includes: The light receiving element according to any one of claims 1, 10, and 17; A light source that irradiates illumination light with a periodically changing luminance; and A light emission control unit that controls an irradiation timing of the illumination light.

Images