Light receiving element and distance measuring module

Abstract

The light-receiving element includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit arranged at a periphery of the first voltage application unit, a second charge detection unit arranged at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region. For example, the present technology is applicable to a light-receiving element or the like that generates distance information in a ToF method.

Description

TECHNICAL FIELD

[0001] The present technology relates to a light-receiving element and a distance measuring module, and particularly to a light-receiving element and a distance measuring module capable of improving characteristics.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Japanese Priority Patent Application JP 2018-135401 filed July 18, 2018, the entire contents of which are incorporated herein by reference. BACKGROUND

[0004] In the related art, a distance measuring system using a time of flight (ToF) method is known. In the distance measuring system, a sensor capable of distributing signal charges, which are obtained by receiving reflected light of active light emitted toward a target object using a light-emitting diode (LED) or a laser at an arbitrary phase, to another region at high speed is required.

[0005] Here, for example, a technology is proposed in which a voltage is directly applied to a substrate of a sensor to generate a current in the substrate, and the technology can modulate a wide region within the substrate at high speed (see, for example, Document JP-A-2011-86904). The sensor is also called a current assisted photonic demodulator (CAPD) sensor. SUMMARY

[0006] However, in this technology, it is difficult to obtain a CAPD sensor having sufficient characteristics.

[0007] For example, the CAPD sensor is a front-illuminated type sensor in which a wiring or the like is arranged on a surface of a substrate on a side that receives light from the outside.

[0008] From the viewpoint of securing a photoelectric conversion region, it is desirable that there be no object such as a wiring or the like that blocks an optical path of incident light on a light-receiving surface side of a photodiode (PD), that is, a photoelectric conversion unit. However, in the front-illuminated type CAPD sensor, it is necessary to arrange a charge extraction wiring, various control lines, and signal lines on the light-receiving surface side of the PD depending on the structure, and the photoelectric conversion region is thus limited. That is, it is difficult to secure a sufficient photoelectric conversion region, and characteristics such as pixel sensitivity can be degraded.

[0009] In addition, when a CAPD sensor is used at a position where external light is present, the external light component becomes a noise component in an indirect ToF method that performs distance measurement by using active light, and thus, in order to obtain distance information by securing a sufficient signal-to-noise ratio (SN ratio), it is necessary to secure a sufficient saturated signal amount (Qs). However, in a front-illuminated CAPD sensor, the wiring layout is limited, and thus, the use of a method other than a wiring capacitance, such as a method of providing an additional transistor to secure a capacitance, is required.

[0010] In addition, in a front-illuminated CAPD sensor, a signal extraction unit called a tap is arranged inside a substrate on the light incident side. On the other hand, when photoelectric conversion in a Si substrate is considered, there is a difference in the attenuation rate between the wavelengths of light, but the rate of photoelectric conversion occurring on the light incident surface side is higher. Thus, in a front-illuminated CAPD sensor, there is a possibility that, among the tap regions provided with signal extraction units, the possibility of photoelectric conversion occurring in a non-active tap region that is a signal charge non-assignment tap region becomes higher. In an indirect ToF sensor, light measurement information is obtained by using signals assigned to each charge accumulation region according to the phase of active light, the component directly photoelectrically converted in the non-active tap region becomes noise, and thus, there is a possibility that the distance measurement accuracy decreases. That is, the characteristics of the CAPD sensor can deteriorate.

[0011] In view of this, the present technology has been proposed, and an object thereof is to improve the characteristics.

[0012] According to a first aspect of the present technology, there is provided a light-receiving element including an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit arranged at a periphery of the first voltage application unit, a second charge detection unit arranged at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region.

[0013] In the first aspect of the present technology, an on-chip lens, a wiring layer, and a semiconductor layer provided between the on-chip lens and the wiring layer are provided. In the semiconductor layer, a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit arranged at a periphery of the first voltage application unit, a second charge detection unit arranged at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region are provided.

[0014] According to a second aspect of the present technology, there is provided a distance measuring module including a light receiving element, a light source, and a light emission control unit, the light receiving element including an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit arranged at a periphery of the first voltage application unit, a second charge detection unit arranged at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region. The light source emits irradiation light, a brightness of the irradiation light periodically fluctuates. The light emission control unit controls an irradiation timing of the irradiation light.

[0015] In the second aspect of the present technology, there is provided a light receiving element, a light source, and a light emission control unit, the light receiving element including an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit arranged at a periphery of the first voltage application unit, a second charge detection unit arranged at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region. The light source emits irradiation light, a brightness of the irradiation light periodically fluctuates. The light emission control unit controls an irradiation timing of the irradiation light.

[0016] According to the first and second aspects of the present technology, characteristics can be improved.

[0017] Note that the effects described here are not limiting, and there can be any one of the effects described in this disclosure.

[0018] These and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description of the best mode embodiments thereof, along with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a block diagram showing a configuration example of a light receiving element.

[0020] Figure 2 is a view showing a configuration example of a pixel.

[0021] Figure 3 is a view showing a configuration example of a part of a signal extraction unit of a pixel.

[0022] Figure 4 is a view illustrating improvement of sensitivity.

[0023] Figure 5 is a view illustrating improvement of charge separation efficiency.

[0024] Figure 6is a view illustrating improvement of electron extraction efficiency.

[0025] Figure 7 is a view illustrating a moving speed of signal carriers in a front-illumination type.

[0026] Figure 8 is a view illustrating a moving speed of signal carriers in a back-illumination type.

[0027] Figure 9 is a view showing another configuration example of a part of a signal extraction unit of a pixel.

[0028] Figure 10 is a view illustrating a relationship between a pixel and an on-chip lens.

[0029] Figure 11 is a view showing still another configuration example of a part of a signal tapping section of a pixel.

[0030] Figure 12 is a view showing still another configuration example of a part of a signal tapping section of a pixel.

[0031] Figure 13 is a view showing still another configuration example of a part of a signal tapping section of a pixel.

[0032] Figure 14 is a view showing still another configuration example of a part of a signal tapping section of a pixel.

[0033] Figure 15 is a view showing still another configuration example of a part of a signal tapping section of a pixel.

[0034] Figure 16 is a view showing another configuration example of a pixel.

[0035] Figure 17 is a view showing still another configuration example of a pixel.

[0036] Figure 18 is a view showing still another configuration example of a pixel.

[0037] Figure 19 is a view showing still another configuration example of a pixel.

[0038] Figure 20 is a view showing still another configuration example of a pixel.

[0039] Figure 21 is a view showing still another configuration example of a pixel.

[0040] Figure 22 is a view showing still another configuration example of a pixel.

[0041] Figure 23 is a view showing another configuration example of a pixel.

[0042] Figure 24 is a view showing another configuration example of a pixel.

[0043] Figure 25 is a view showing another configuration example of a pixel.

[0044] Figure 26 is a view showing another configuration example of a pixel.

[0045] Figure 27A and 27B is a view showing another configuration example of a pixel.

[0046] Figure 28 is a view showing another configuration example of a pixel.

[0047] Figure 29 is a view showing another configuration example of a pixel.

[0048] Figure 30 is a view showing another configuration example of a pixel.

[0049] Figure 31 is a view showing an equivalent circuit of a pixel.

[0050] Figure 32 is a view showing another equivalent circuit of a pixel.

[0051] Figure 33A and 33B is a view showing an arrangement example of voltage supply lines employing a periodic arrangement.

[0052] Figure 34A and 34B is a view showing an arrangement example of voltage supply lines employing a mirror arrangement.

[0053] Figure 35A and 35B are views explaining characteristics of the periodic arrangement and the mirror arrangement.

[0054] Figure 36 is a sectional view of a plurality of pixels in the fourteenth embodiment.

[0055] Figure 37 is a sectional view of a plurality of pixels in the fourteenth embodiment.

[0056] Figure 38 is a sectional view of a plurality of pixels in the ninth embodiment.

[0057] Figure 39 is a sectional view of a plurality of pixels in the first modification of the ninth embodiment.

[0058] Figure 40 is a sectional view of a plurality of pixels in the fifteenth embodiment.

[0059] Figure 41 is a sectional view of a plurality of pixels in the tenth embodiment.

[0060] Figures 42A to 42C is a view illustrating five layers of metal films of a multi-layer wiring layer.

[0061] Figure 43A and 43B is a view illustrating five layers of metal films of a multi-layer wiring layer.

[0062] Figures 44A to 44C is a view illustrating a polysilicon layer.

[0063] Figures 45A to 45C is a view illustrating a modification example of a reflection member formed on a metal film.

[0064] Figure 46A and 46B is a view illustrating a modification example of a reflection member formed on a metal film.

[0065] Figures 47A to 47C is a view illustrating a substrate structure of a light-receiving element.

[0066] Figure 48 is a view illustrating noise at a periphery of a pixel transistor region.

[0067] Figure 49A and 49B is a view illustrating a noise suppression structure at a periphery of a pixel transistor region.

[0068] Figure 50 is a view illustrating a charge discharge structure at a periphery of a pixel transistor region.

[0069] Figure 51 is a view illustrating a charge discharge structure at a periphery of a pixel transistor region.

[0070] Figure 52 is a view illustrating charge discharge at a periphery of an effective pixel region.

[0071] Figure 53 A to D of FIG. 25 are plan views illustrating configuration examples of a charge discharge region arranged at an outer periphery of an effective pixel region.

[0072] Figure 54 is a sectional view in a case where the charge discharge region includes a light-shielding pixel region and an N-type region.

[0073] Figure 55A and 55Bis a view that illustrates current flow in a case where a pixel transistor is arranged in a substrate including a photoelectric conversion region.

[0074] Figure 56 is a sectional view of a plurality of pixels according to the eighteenth embodiment.

[0075] Figure 57 is a view that illustrates sharing of circuits of two substrates.

[0076] Figure 58 is a view that illustrates a substrate configuration according to the eighteenth embodiment.

[0077] Figure 59 is a plan view that shows the arrangement of the MIX bonding portion and the DET bonding portion.

[0078] Figure 60 is a plan view that shows the arrangement of the MIX bonding portion and the DET bonding portion.

[0079] Figure 61 is a view that illustrates a problem of an increase in current consumption.

[0080] Figure 62A and 62B are a plan view and a sectional view of a pixel according to a first configuration example of the nineteenth embodiment.

[0081] Figure 63A and 63B are a plan view and a sectional view of a pixel according to a second configuration example of the nineteenth embodiment.

[0082] Figures 64A to 64C is a view that shows other planar shapes of the first configuration example and the second configuration example of the nineteenth embodiment.

[0083] Figures 65A to 65C is a view that shows other planar shapes of the first configuration example and the second configuration example of the nineteenth embodiment.

[0084] Figure 66A and 66B are a plan view and a sectional view of a pixel according to a third configuration example of the nineteenth embodiment.

[0085] Figures 67A to 67C is a view that shows other planar shapes of the third configuration example of the nineteenth embodiment.

[0086] Figures 68A to 68C is a view that shows other planar shapes of the third configuration example of the nineteenth embodiment.

[0087] Figure 69 is a view that shows a circuit configuration example of a pixel array unit in a case where four tapped pixels signals are simultaneously output.

[0088] Figure 70 is a view showing a wiring layout in which four vertical signal lines are arranged.

[0089] Figure 71 is a view showing a modification example 1 of the wiring layout in which four vertical signal lines are arranged.

[0090] Figure 72 is a view showing a modification example 2 of the wiring layout in which four vertical signal lines are arranged.

[0091] Figure 73A and 73B is a view showing a modification example of the arrangement example of the pixel transistor.

[0092] Figure 74 is a view showing a modification example of the wiring layout in the pixel transistor layout of Figure 73B

[0093] Figure 75 is a view showing a modification example of the wiring layout in the pixel transistor layout of Figure 73B

[0094] Figure 76 is a view showing a wiring layout in which two power supply lines are provided in one pixel column.

[0095] Figure 77 is a plan view showing a wiring example of a VSS wiring.

[0096] Figure 78 is a plan view showing a wiring example of a VSS wiring.

[0097] Figure 79 is a view for explaining a first method of pupil correction.

[0098] Figure 80 is a view for explaining a first method of pupil correction.

[0099] Figure 81 is a view for explaining a first method of pupil correction.

[0100] Figures 82A to 82C is a view for explaining a first method of pupil correction.

[0101] Figure 83 is a view for explaining a shift amount of an on-chip lens in the first method of pupil correction.

[0102] Figure 84 is a view for explaining a two-phase method and a four-phase method.

[0103] Figure 85 is a view for explaining a wiring example of a voltage supply line. ​​

[0104] Figures 86A to 86C is a cross-sectional view and a plan view of a first configuration example of the twentieth embodiment.

[0105] Figures 87A to 87F is a view showing an arrangement example of the first and second tapping sections.

[0106] Figure 88 is a view illustrating a driving mode of the first and second tapping sections.

[0107] Figure 89 is a cross-sectional view and a plan view of a pixel according to a second configuration example of the twentieth embodiment.

[0108] Figures 90A to 90F is a view showing an arrangement example of a phase difference shading film and an on-chip lens.

[0109] Figure 91 is a cross-sectional view of a pixel according to the twenty-first embodiment.

[0110] Figure 92A and 92B is a plan view of a pixel according to the twenty-first embodiment.

[0111] Figure 93A and 93B is a cross-sectional view of a pixel according to the twenty-second embodiment.

[0112] Figures 94A to 94D is a plan view showing a pixel according to the twenty-second embodiment.

[0113] Figure 95 is a block diagram showing a configuration example of a distance measuring module.

[0114] Figure 96 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0115] Figure 97 is a view to assist in explaining an example of a mounting position of an external vehicle information detection section and an imaging section. DETAILED DESCRIPTION

[0116] Hereinafter, an embodiment of the present technology will be described with reference to the drawings.

[0117] <First Embodiment>

[0118] <Configuration Example of Light Receiving Element>

[0119] The present technology proposes a rear-illumination type CAPD sensor to improve characteristics such as pixel sensitivity.

[0120] For example, the present technology is applicable to a light-receiving element that constitutes a distance measuring system that performs distance measurement by an indirect ToF method, an imaging device including the light-receiving element, and the like.

[0121] For example, the distance measuring system is applicable to a vehicle-mounted system that is mounted on a vehicle and measures a distance to a target object, a gesture recognition system that measures a distance to a target object such as a user's hand and the like and recognizes a user gesture based on a measurement result, and the like. In this case, the gesture recognition result can be used, for example, for operation of a car navigation system.

[0122] Figure 1 is a block diagram showing a configuration example of an embodiment of a light-receiving element to which the present technology is applied.

[0123] Figure 1 The light-receiving element 1 shown is a back-illuminated CAPD sensor, and is provided in an imaging device having a distance measuring function, for example.

[0124] The light-receiving element 1 includes a pixel array unit 20 formed on a semiconductor substrate (not shown) and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 20. For example, the peripheral circuit unit includes a tap driving unit 21, a vertical driving unit 22, a column processing unit 23, a horizontal driving unit 24, and a system control unit 25.

[0125] A signal processing unit 31 and a data storage unit 32 are also provided in the light-receiving element 1. Note that the signal processing unit 31 and the data storage unit 32 can be mounted on the same substrate as the light-receiving element 1, or can be provided on different substrates from the light-receiving element 1 in the imaging device.

[0126] The pixel array unit 20 generates charges corresponding to the amount of received light, and in the configuration of the pixel array unit 20, pixels 51 that output signals corresponding to the charges are arranged in a matrix shape two-dimensionally in a row direction and a column direction. That is, the pixel array unit 20 includes a plurality of pixels 51 that photoelectrically convert incident light and output signals corresponding to charges obtained as a result of the photoelectric conversion. Here, the row direction indicates the arrangement direction of the pixels 51 in the horizontal direction, and the column direction indicates the arrangement direction of the pixels 51 in the vertical direction. The row direction is the horizontal direction in the drawing, and the column direction is the vertical direction in the drawing.

[0127] Each of the pixels 51 receives and photoelectrically converts incident light (particularly, infrared light) from the outside, and outputs a pixel signal corresponding to charges obtained as a result of the photoelectric conversion. The pixel 51 includes a first tap TA for applying a predetermined voltage MIX0 (first voltage) and detecting photoelectrically converted charges, and a second tap TB for applying a predetermined voltage MIX1 (second voltage) and detecting photoelectrically converted charges.

[0128] The tap portion drive unit 21 supplies a predetermined voltage MIXO to the first tap portion TA of the pixel 51 of the pixel array unit 20 through the predetermined voltage supply line 30, and supplies a predetermined voltage MIX1 to the second tap portion TB through the predetermined voltage supply line 30. Thus, two voltage supply lines 30 including the voltage supply line 30 for transmitting the voltage MIXO and the voltage supply line 30 for transmitting the voltage MIX1 are wired in one pixel column of the pixel array unit 20.

[0129] In the pixel array unit 20, for the matrix-shaped pixel arrangement, the pixel drive line 28 is wired in the row direction for each pixel row, and two vertical signal lines 29 are wired in the column direction for each pixel column. For example, the pixel drive line 28 transmits a drive signal for performing an operation at the time of reading out a signal from a pixel. Note that, in Figure 1 In the pixel array unit 20, for the matrix-shaped pixel arrangement, the pixel drive line 28 is wired in the row direction for each pixel row, and two vertical signal lines 29 are wired in the column direction for each pixel column. For example, the pixel drive line 28 transmits a drive signal for performing an operation at the time of reading out a signal from a pixel. Note that, in

[0130] The vertical drive unit 22 is constituted by a shift register, an address decoder, or the like, and drives the pixels of the pixel array unit 20 simultaneously or in units of rows. That is, the vertical drive unit 22 constitutes a drive unit for controlling the operation of each pixel of the pixel array unit 20 in combination with a system control unit 25 for controlling the vertical drive unit 22.

[0131] The signal output from each pixel 51 in the pixel row according to the drive control of the vertical drive unit 22 is input to the column processing unit 23 through the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the pixel signal output from the pixel 51 through the vertical signal line 29, and temporarily stores the pixel signal after the signal processing.

[0132] Specifically, the column processing unit 23 performs signal processing such as noise removal processing, analog-digital (AD) conversion processing, or the like.

[0133] The horizontal drive unit 24 is constituted by a shift register, an address decoder, or the like, and sequentially selects the unit circuits of the column processing unit 23 corresponding to the pixel columns. Due to the selective scanning of the horizontal drive unit 24, the signal-processed pixel signal of each unit circuit in the column processing unit 23 is sequentially output.

[0134] The system control unit 25 is constituted by a time generator that generates various timing signals, or the like, and performs drive control of the tap portion drive unit 21, the vertical drive unit 22, the column processing unit 23, the horizontal drive unit 24, and the like, based on the various timing signals generated in the time generator.

[0135] The signal processing unit 31 has at least a computation processing function, and performs various signal processing such as computation processing, based on the pixel signal output from the column processing unit 23. The data storage unit 32 temporarily stores data required for processing at the time of signal processing by the signal processing unit 31.

[0136] <Configuration example of pixel>

[0137] Next, a configuration example of a pixel provided in the pixel array unit 20 will be described. For example, the pixel provided in the pixel array unit 20 has a configuration as shown in FIG. 6. Figure 2

[0138] Figure 2 A cross section of one pixel 51 provided in the pixel array unit 20 is shown, and the pixel 51 optoelectronically receives and optoelectronically converts incident light (particularly, infrared light) from the outside, and outputs a signal corresponding to the electric charge obtained as a result of the optoelectronic conversion.

[0139] For example, the pixel 51 includes a substrate 61 composed of a P-type semiconductor layer such as a silicon substrate, and an on-chip lens 62 formed on the substrate 61.

[0140] For example, the thickness of the substrate 61 in the vertical direction in the drawing (i.e., the thickness perpendicular to the surface of the substrate 61) is set to 20 μm or less. It should be noted that the thickness of the substrate 61 can be 20 μm or more, and the thickness can be determined in accordance with the target characteristics of the light receiving element 1 or the like.

[0141] In addition, for example, the substrate 61 is provided as a high-resistance P-Epi substrate, the substrate concentration of which is set to the order of 1E+13 or less, and the resistance (resistivity) of the substrate 61 is set to, for example, 500 [Ωcm] or more.

[0142] Here, regarding the relationship between the substrate concentration and the resistance of the substrate 61, for example, when the substrate concentration is 6.48E+12 [cm 3 ], the resistance is set to 2000 [Ωcm]; when the substrate concentration is 1.30E+13 [cm 3 ], the resistance is set to 1000 [Ωcm]; when the substrate concentration is 2.59E+13 [cm 3 ], the resistance is set to 500 [Ωcm]; and when the substrate concentration is 1.30E+14 [cm 3 ], the resistance is set to 100 [Ωcm].

[0143] In Figure 2 ​In the present embodiment, the upper surface of the substrate 61 is the rear surface of the substrate 61, and is a light incident surface when light is incident on the substrate 61 from the outside. On the other hand, the lower surface of the substrate 61 is the front surface of the substrate 61, and a multilayer wiring layer (not shown) is formed in the front surface. A fixed charge film 66 composed of a single layer film or a laminated film having a positive fixed charge is formed on the light incident surface of the substrate 61, and an on-chip lens 62 for converging incident light from the outside and allowing the incident light to be incident in the substrate 61 is formed on the upper surface of the fixed charge film 66. The fixed charge film 66 sets the light incident surface side of the substrate 61 to a hole accumulation state, and suppresses generation of dark current.

[0144] In addition, in the pixel 51, an inter-pixel light shielding film 63-1 and an inter-pixel light shielding film 63-2 for preventing crosstalk between adjacent pixels are formed at the end portions of the pixel 51, respectively, and are located on the upper side of the fixed charge film 66. Hereinafter, in the case where it is not particularly necessary to distinguish between the inter-pixel light shielding film 63-1 and the inter-pixel light shielding film 63-2, these films are also simply referred to as the inter-pixel light shielding film 63.

[0145] In this example, light incident from the outside is incident in the substrate 61 through the on-chip lens 62, but the inter-pixel light shielding film 63 is formed so as not to allow light incident from the outside to be incident in a region of another pixel which is disposed adjacent to the pixel 51 in the substrate 61. That is, light incident from the outside to the pixel on-chip lens 62 and propagating toward the inside of the other pixel adjacent to the pixel 51 is shielded by the inter-pixel light shielding film 63-1 or the inter-pixel light shielding film 63-2, and is prevented from being incident in the adjacent other pixel.

[0146] The light receiving element 1 is a rear-illuminated type CAPD sensor, and therefore the light incident surface of the substrate 61 becomes a so-called rear surface, and no wiring layer or the like including a wiring is formed on the rear surface. In addition, a wiring layer is formed on a portion of the surface of the substrate 61 opposite to the light incident surface, in which a wiring for driving a pixel or the like formed in the pixel 51, a wiring for reading out a signal from the pixel 51, or the like is formed.

[0147] In the substrate 61, an oxide film 64, a signal extraction unit 65-1, and a signal extraction unit 65-2 are formed on a portion of the inner side of the surface (i.e., the lower surface in the drawing) opposite to the light incident surface. The signal extraction unit 65-1 corresponds to the first tapping portion TA explained in the Figure 1 The signal extraction unit 65-2 corresponds to the second tapping portion TB explained in the Figure 1

[0148] ​In this example, the oxide film 64 is formed near the surface of the substrate 61 opposite the light incident surface at the center portion of the pixel 51, and the signal extraction unit 65-1 and the signal extraction unit 65 are formed at both ends of the oxide film 64, respectively.

[0149] Here, the signal extraction unit 65-1 includes an N+ semiconductor region 71-1 that is an N-type semiconductor region, an N- semiconductor region 72-1 that has a lower donor impurity concentration than the N+ semiconductor region, a P+ semiconductor region 73-1 that is a P-type semiconductor region, and a P- semiconductor region 74-1 that has a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Here, examples of the donor impurity with respect to Si include elements such as phosphorus (P) and arsenic (As) belonging to Group 5 in the periodic table. Examples of the acceptor impurity with respect to Si include elements such as boron (B) belonging to Group 3 in the periodic table. An element that becomes a donor impurity is referred to as a donor element, and an element that becomes an acceptor impurity is referred to as an acceptor element.

[0150] In Figure 2 , the N+ semiconductor region 71-1 is formed at a position adjacent to the right side of the oxide film 64 at a portion inside the surface of the substrate 61 opposite the light incident surface. In addition, the N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the drawing and covers (encloses) the N+ semiconductor region 71-1.

[0151] In addition, the P+ semiconductor region 73-1 is formed at the right side of the N+ semiconductor region 71-1. In addition, the P- semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 in the drawing and covers (encloses) the P+ semiconductor region 73-1.

[0152] In addition, the N+ semiconductor region 71-1 is formed at the right side of the P+ semiconductor region 73-1. In addition, the N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the drawing and covers (encloses) the N+ semiconductor region 71-1.

[0153] Similarly, the signal extraction unit 65-2 includes an N+ semiconductor region 71-2 that is an N-type semiconductor region, an N- semiconductor region 72-2 that has a lower donor impurity concentration than the N+ semiconductor region 71-2, a P+ semiconductor region 73-2 that is a P-type semiconductor region, and a P- semiconductor region 74-2 that has a lower acceptor impurity concentration than the P+ semiconductor region 73-2.

[0154] In Figure 2In the substrate 61, at a portion inside the surface opposite to the light incident surface, an N+ semiconductor region 71-2 is formed at a position adjacent to the left side of the oxide film 64. In addition, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the drawing, and covers (surrounds) the N+ semiconductor region 71-2.

[0155] In addition, a P+ semiconductor region 73-2 is formed at the left side of the N+ semiconductor region 71-2. In addition, a P- semiconductor region 74-2 is formed above the P+ semiconductor region 73-2 in the drawing, and covers (surrounds) the P+ semiconductor region 73-2.

[0156] In addition, an N+ semiconductor region 71-2 is formed at the left side of the P+ semiconductor region 73-2. In addition, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the drawing, and covers (surrounds) the N+ semiconductor region 71-2.

[0157] In the substrate 61, at a portion inside the surface opposite to the light incident surface, an N+ semiconductor region 71-2 is formed at a position adjacent to the left side of the oxide film 64. In addition, an N- semiconductor region 72-2 is formed above the N+ semiconductor region 71-2 in the drawing, and covers (surrounds) the N+ semiconductor region 71-2.

[0158] Hereinafter, without particularly distinguishing the signal extraction unit 65-1 and the signal extraction unit 65-2, these units are also simply referred to as the signal extraction unit 65.

[0159] In addition, hereinafter, without particularly distinguishing the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, the regions are also simply referred to as the N+ semiconductor region 71, and without particularly distinguishing the N- semiconductor region 72-1 and the N- semiconductor region 72-2, the regions are also simply referred to as the N- semiconductor region 72.

[0160] In addition, hereinafter, without particularly distinguishing the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, the regions are also simply referred to as the P+ semiconductor region 73, and without particularly distinguishing the P- semiconductor region 74-1 and the P- semiconductor region 74-2, the regions are also simply referred to as the P- semiconductor region 74.

[0161] In addition, in the substrate 61, a separation portion 75-1 composed of an oxide film or the like is provided between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1, for separating these regions from each other. Similarly, a separation portion 75-2 composed of an oxide film or the like is also provided between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2, for separating these regions from each other. Hereinafter, without particularly distinguishing the separation portion 75-1 and the separation portion 75-2, these separation portions are also simply referred to as the separation portion 75.

[0162] The N+ semiconductor region 71 formed in the substrate 61 functions as a charge detection unit that detects the amount of light incident from the outside to the pixel 51, that is, the amount of signal carriers generated by photoelectric conversion of the substrate 61. Note that, in addition to the N+ semiconductor region 71, an N- semiconductor region 72 having a low donor impurity concentration can also be considered as a charge detection unit. Also, the P+ semiconductor region 73 functions as a voltage application unit for injecting a large amount of carrier current to the substrate 61, that is, for generating an electric field in the substrate 61 by directly applying a voltage to the substrate 61. Note that, in addition to the P+ semiconductor region 73, a P- semiconductor region 74 having a low acceptor impurity concentration can also be considered as a voltage application unit.

[0163] In the pixel 51, a floating diffusion (FD) portion (hereinafter, also referred to as FD portion A) as a floating diffusion region (not shown) is directly connected to the N+ semiconductor region 71-1, and the FD portion A is connected to the vertical signal line 29 through an amplification transistor (not shown) or the like.

[0164] Similarly, another FD portion (hereinafter, also referred to as FD portion B) different from the FD portion A is directly connected to the N+ semiconductor region 71-2, and the FD portion B is connected to the vertical signal line 29 through an amplification transistor (not shown) or the like. Here, the FD portion A and the FD portion B are connected to different vertical signal lines 29 from each other, respectively.

[0165] For example, in a case where the distance to a target object is measured by an indirect ToF method, infrared light is emitted from an imaging device provided with the light receiving element 1 toward the target object. Also, when the infrared light is reflected from the target object and returns to the imaging device as reflected light, the substrate 61 of the light receiving element 1 receives and photoelectrically converts the incident reflected light (infrared light). The tapping portion drive unit 21 drives the first tapping portion TA and the second tapping portion TB of the pixel 51, and distributes a signal corresponding to the charge DET obtained by the photoelectric conversion to the FD portion A and the FD portion B.

[0166] For example, at an arbitrary time, the tapping portion drive unit 21 applies a voltage to the two P+ semiconductor regions 73 through a contact portion or the like. Specifically, for example, the tapping portion drive unit 21 applies a voltage of MIX0 = 1.5 V to the P+ semiconductor region 73-1 as the first tapping portion TA, and applies a voltage of MIX1 = 0 V to the P+ semiconductor region 73-2 as the second tapping portion TB.

[0167] In this state, an electric field is generated between the two P+ semiconductor regions 73 in the substrate, and a current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes within the substrate 61 migrate in the direction of the P+ semiconductor region 73-2, and electrons migrate in the direction of the P+ semiconductor region 73-1.

[0168] Therefore, in this state, when infrared light (reflected light) from the outside is incident on the substrate 61 from the outside through the on-chip lens 62, and the infrared light is photoelectrically converted into pairs of electrons and holes inside the substrate 61, the obtained electrons are guided in the direction of the P+ semiconductor region 73-1 due to the electric field between the P+ semiconductor regions 73, and migrate into the N+ semiconductor region 71-1.

[0169] In this case, the electrons generated in the photoelectric conversion can be used as signal carriers for detecting a signal corresponding to the amount of infrared light incident on the pixel 51, that is, a signal corresponding to the light amount of the received infrared light.

[0170] Therefore, the charge corresponding to the electrons that migrate into the N+ semiconductor region 71-1 accumulates in the N+ semiconductor region 71-1, and the charge is detected via the column processing unit 23 through the FD section A, the amplification transistor, the vertical signal line 29, and the like.

[0171] That is, the accumulated charge DET0 of the N+ semiconductor region 71-1 is transferred to the FD section A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge DET0 transferred to the FD section A is read out via the column processing unit 23 through the amplification transistor or the vertical signal line 29. Further, processing such as AD conversion processing is performed on the read-out signal in the column processing unit 23, and a pixel signal obtained thereby is supplied to the signal processing unit 31.

[0172] The pixel signal becomes a signal for indicating the amount of charge corresponding to the electrons detected in the N+ semiconductor region 71-1, that is, the amount of charge accumulated in the FD section A, DET0. In other words, the pixel signal can also refer to a signal for indicating the light amount of the infrared light received by the pixel 51.

[0173] Note that, in the same manner as in the case of the N+ semiconductor region 71-1, the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-2 can be used in an appropriate manner for distance measurement.

[0174] In addition, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 by the tapping portion drive unit 21 using a contact portion or the like, thereby generating an electric field in a direction opposite to the direction of the electric field currently generated in the substrate 61. Specifically, for example, a voltage of MIX0 = 0 V is applied to the P+ semiconductor region 73-1 as the first tapping portion TA, and a voltage of MIX1 = 1.5 V is applied to the P+ semiconductor region 73-2 as the first tapping portion TB.

[0175] Accordingly, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and a current flows from the P+ semiconductor region 73-2 to the P+ semiconductor region 73-1.

[0176] In this state, when infrared light (reflected light) is incident from the outside into the substrate 61 through the on-chip lens 62, and the infrared light is photoelectrically converted into a pair of an electron and a hole inside the substrate 61, the obtained electron is guided in the direction of the P+ semiconductor region 73-2 and migrates into the N+ semiconductor region 71-2 due to the electric field between the P+ semiconductor regions 73.

[0177] Accordingly, a charge corresponding to the electron that migrates into the N+ semiconductor region 71-2 accumulates in the N+ semiconductor region 71-2, and the charge is detected by the FD portion B, the amplification transistor, the vertical direction detection signal line 29, or the like via the column processing unit 23.

[0178] That is, the accumulated charge DET1 in the N+ semiconductor region 71-2 is transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charge DET1 transferred to the FD portion B is read out through the amplification transistor or the vertical signal line 29 via the column processing unit 23. Further, processing such as AD conversion processing is performed on the read-out signal in the column processing unit 23, and a pixel signal obtained thereby is supplied to the signal processing unit 31 by the column processing unit 23.

[0179] Note that, in a similar manner to the case of the N+ semiconductor region 71-2, a pixel signal corresponding to an electron detected in the N+ semiconductor region 71-1 can be used for distance measurement in an appropriate manner.

[0180] As described above, when pixel signals are obtained by photoelectric conversion in different time periods in the same pixel 51, the signal processing unit 31 calculates distance information indicating a distance to a target object based on the pixel signals, and outputs the distance information to a later stage.

[0181] As described above, a method in which signal carriers are allocated to different N+ semiconductor regions 71 and distance information is calculated based on signals corresponding to the signal carriers is also referred to as an indirect ToF method.

[0182] When a portion of the signal extraction unit 65 in the pixel 51 is viewed from the upper side toward the lower side (i.e., in a direction perpendicular to the surface of the substrate 61) in Figure 2 FIG. 11, for example, as shown in Figure 3 , the periphery of the P+ semiconductor region 73 has a structure surrounded by the N+ semiconductor region 71. Note that, in Figure 3 , the same reference numerals are given to portions corresponding to the case of Figure 2 , and the description thereof is appropriately omitted.

[0183] In the example shown in Figure 3 , the oxide film 64 (not shown) is formed at a central portion of the pixel 51, and the signal extraction unit 65 is formed at a portion slightly closer to the end side from the center of the pixel. In particular, here, two signal extraction units 65 are formed in the pixel 51.

[0184] Further, in the signal extraction unit 65, the P+ semiconductor region 73 is formed in a rectangular shape at a central position, and in a state in which the P+ semiconductor region 73 is disposed at the center, the periphery of the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71 in a rectangular shape (more specifically, a rectangular frame shape). That is, the N+ semiconductor region 71 is formed so as to surround the periphery of the P+ semiconductor region 73.

[0185] Further, in the pixel 51, the on-chip lens 62 is formed at a central portion of the pixel 51, i.e., at a portion shown by an arrow A11, so that infrared light incident from the outside converges. In other words, infrared light incident from the outside to the on-chip lens 62 is converged by the on-chip lens 62 to a position shown by the arrow A11, i.e., a position in Figure 2 , at a position on the upper side of the oxide film 64.

[0186] Accordingly, infrared light converges to a position between the signal extraction unit 65-1 and the signal extraction unit 65-2. Therefore, occurrence of crosstalk due to infrared light incident to a pixel adjacent to the pixel 51 is suppressed, and also, infrared light is suppressed from being directly incident to the signal extraction unit 65.

[0187] For example, when infrared light is incident to the signal extraction unit 65, the charge separation efficiency (i.e., the contrast (Cmod) or modulation contrast between the active tap and the inactive tap) deteriorates.

[0188] Here, it is assumed that the signal extraction unit 65 that performs reading of a signal corresponding to the charge DET obtained by photoelectric conversion, i.e., the signal extraction unit 64 whose charge DET obtained by photoelectric conversion is subjected to detection, is also referred to as an active tap.

[0189] On the contrary, basically, it is assumed that the signal extraction unit 65 which does not perform the reading of the signal corresponding to the charge DET obtained by the photoelectric conversion, i.e., the signal extraction unit which is not the active tap is also referred to as the inactive tap.

[0190] In the above example, the signal extraction unit 65 to which 1.5 V voltage is applied to the P+ semiconductor region 73 is the active tap, and the signal extraction unit 65 to which 0 V voltage is applied to the P+ semiconductor region 73 is the inactive tap.

[0191] Cmod is an index calculated according to the following expression (1), and indicates how many percentages of the charge (i.e., the signal corresponding to the charge is extracted) among the charges generated by the photoelectric conversion of the incident infrared light can be detected in the N+ semiconductor region 71 of the signal extraction unit 65 which is the active tap, and indicates the charge separation efficiency. In expression (1), I0 indicates the signal detected on one side between the two charge detection units (P+ semiconductor region 73), and I1 indicates the signal detected on the other side.

[0192] Cmod = { | I0 - I1 | / | I0 + I1 | x 100... (1)

[0193] Therefore, for example, when the infrared light incident from the outside is incident to the region of the inactive tap, and the photoelectric conversion is performed in the inactive tap, the electrons as the signal carriers generated by the photoelectric conversion are likely to migrate to the N+ semiconductor region 71 within the inactive tap. In this case, the charges of the partial electrons obtained by the photoelectric conversion are not detected in the N+ semiconductor region 71 in the active tap, and Cmod (i.e., the charge separation efficiency) is deteriorated.

[0194] Here, in the pixel 51, the infrared light is converged to the vicinity of the center of the pixel 51 located at substantially the same distance from the two signal extraction units 65, and thus the possibility that the infrared light incident from the outside is photoelectrically converted in the region of the inactive tap is reduced. Therefore, it is possible to improve the charge separation efficiency. In addition, in the pixel 51, it is also possible to improve the modulation contrast. In other words, it is possible to allow the electrons obtained by the photoelectric conversion to be easily guided to the N+ semiconductor region 71 within the active tap.

[0195] According to the light-receiving element 1 described above, the following effects can be obtained.

[0196] Specifically, first, the light-receiving element 1 is a back-illuminated type, and thus it is possible to maximize the quantum efficiency (QE) x aperture ratio (fill factor) (FF), and thus it is possible to improve the ranging characteristics by the light-receiving element 1.

[0197] For example, as Figure 4As shown by an arrow W11, in a structure of a typical front-illuminated image sensor, the wiring 102 and the wiring 103 are formed on the light-receiving surface side of the PD 101 as a photoelectric conversion unit from which light is incident from the outside.

[0198] Therefore, for example, as shown by an arrow A21 or an arrow A22, a part of light obliquely incident from the outside at a certain angle to the PD 101 is blocked by the wiring 102 or the wiring 103, and is not incident to the PD 101.

[0199] In contrast, for example, as shown by an arrow W12, in a structure of a rear-illuminated image sensor, the wiring 105 and the wiring 106 are formed on the surface on the side opposite to the light-receiving surface of the PD 104 as a photoelectric conversion unit from which light is incident from the outside.

[0200] Therefore, compared to the case of the front-illuminated type, it is possible to secure sufficient aperture ratio. That is, for example, as shown by an arrow A23 or an arrow A24, a part of light obliquely incident from the outside at a certain angle to the PD 104 is not blocked by the wiring, and is incident to the PD 104. Therefore, a large amount of light beams are received and thus it is possible to improve the sensitivity of the pixel.

[0201] The effect of improving the sensitivity of the pixel due to the rear-illuminated type can also be obtained in the light-receiving element 1 as a rear-illuminated CAPD sensor.

[0202] In addition, for example, in the front-illuminated CAPD sensor, as shown by an arrow W13, inside the PD 111 as a photoelectric conversion unit, a signal extraction unit 112 called a tap portion is formed at the light-receiving surface side from which light is incident from the outside, more specifically, a P+ semiconductor region or an N+ semiconductor region forming the tap portion. In addition, in the structure of the front-illuminated CAPD sensor, the wiring 113 and the wiring 114 such as a contact portion connected to the signal extraction unit 112 and a metal are formed on the light-receiving surface side.

[0203] Therefore, for example, as shown by an arrow A25 or an arrow A26, a part of light obliquely incident from the outside at a certain angle to the PD 111 is blocked by the wiring 113 or the like and is not incident to the PD 111, and as shown by an arrow A27, light perpendicularly incident to the PD 111 is blocked by the wiring 114 and is not incident to the PD 111.

[0204] In contrast, for example, as indicated by an arrow W14, in the structure of the rear-illuminated CAPD sensor, the signal extraction unit 116 is formed in a portion of a surface of the PD 115, which is a photoelectric conversion unit, opposite to a light incident surface from which light is incident from the outside. Further, a wiring 117 and a wiring 118 such as a contact portion connected to the signal extraction unit 116 and a metal are formed on the surface of the PD 115 opposite to the light incident surface.

[0205] Here, the PD 115 corresponds to Figure 2 the substrate 61 illustrated in FIG. 1, and the signal extraction unit 116 corresponds to Figure 2 the signal extraction unit 65 illustrated in FIG. 1.

[0206] In the rear-illuminated CAPD sensor having the above-described structure, as compared with the front-illuminated type, it is possible to secure a sufficient aperture ratio. Therefore, it is possible to maximize quantum efficiency (QE) × aperture ratio (FF), and thus it is possible to improve the ranging characteristics.

[0207] That is, for example, as indicated by an arrow A28 or an arrow A29, light obliquely incident to the PD 115 from the outside at a certain angle is not blocked by the wiring and is incident to the PD 115. Similarly, as indicated by an arrow A30, light perpendicularly incident to the PD 115 is also not blocked by the wiring and the like and is incident to the PD 115.

[0208] As described above, the rear-illuminated CAPD sensor can not only receive light incident at a certain angle, but also receive light reflected by the wiring and the like connected to the signal extraction unit (tapping portion) perpendicularly incident to the PD 115 and in the front-illuminated type. Therefore, a large amount of light beams are received, and thus it is possible to improve the sensitivity of the pixel. In other words, it is possible to maximize quantum efficiency (QE) × aperture ratio (FF), and thus it is possible to improve the ranging characteristics.

[0209] In particular, in the front-illuminated CAPD sensor, in the case where the tapping portion is arranged near the center of the pixel rather than the outer edge of the pixel, it is difficult to secure a sufficient aperture ratio, and the sensitivity of the pixel deteriorates. However, in the light-receiving element 1 as the rear-illuminated CAPD sensor, it is possible to secure a sufficient aperture ratio regardless of the arrangement position of the tapping portion, and it is possible to improve the sensitivity of the pixel.

[0210] Further, in the rear-illuminated light-receiving element 1, the signal extraction unit 65 is formed in the substrate 61 near a surface opposite to a light incident surface from which infrared light is incident from the outside, and thus it is possible to reduce the occurrence of photoelectric conversion of infrared light in the region of the inactive tapping portion. Therefore, it is possible to improve Cmod, that is, the charge separation efficiency.

[0211] Figure 5A pixel cross-sectional view of a front-illuminated and a back-illuminated CAPD sensor is shown.

[0212] In Figure 5 In the front-illuminated CAPD sensor on the left, the upper side of the substrate 141 in the drawing is a light incident surface, and the wiring layer 152 including a multilayer wiring, the inter-pixel light shielding portion 153, and the on-chip lens 154 are stacked on the light incident surface side of the substrate 141.

[0213] In Figure 5 In the back-illuminated CAPD sensor on the right, the wiring layer 152 including a multilayer wiring is formed on the lower side of the substrate 142 opposite the light incident surface, and the inter-pixel light shielding portion 153 and the on-chip lens 154 are stacked on the upper side of the substrate 142 as the light incident surface side.

[0214] Note that, Figure 5 The gray trapezoidal shape in the drawing indicates a region having a strong light intensity when infrared light is converged by the on-chip lens 154.

[0215] For example, in the front-illuminated CAPD sensor, the region R11 in which the inactive tap portion and the active tap portion exist is located on the light incident surface side of the substrate 141. Therefore, a large amount of components directly incident to the inactive tap portion, and when photoelectric conversion is performed in the region of the inactive tap portion, no signal carriers obtained by photoelectric conversion are detected in the N+ semiconductor region of the active tap portion.

[0216] In the front-illuminated CAPD sensor, in the region R11 near the light incident surface of the substrate 141, the intensity of the infrared light is strong, and thus it is highly likely that photoelectric conversion of the infrared light is performed in the region R11. That is, the amount of light of the infrared light incident to the vicinity of the inactive tap portion is large, and thus signal carriers that the active tap portion cannot detect increase, and thus the charge separation efficiency deteriorates.

[0217] On the contrary, in the back-illuminated CAPD sensor, the region R12 in which the inactive tap portion and the active tap portion exist is located at a position away from the light incident surface of the substrate 142, that is, at a position near the surface opposite the light incident surface side. Here, the substrate 142 corresponds to Figure 2 the substrate 61 shown in the drawing.

[0218] In this example, the region R12 exists in a part of the surface of the substrate 142 opposite the light incident surface side, and the region R12 is located at a position away from the light incident surface, and thus the intensity of the incident infrared light is relatively weak near the R12 region.

[0219] In regions such as the vicinity of the center of the substrate 142 and the vicinity of a light-incident surface where strong infrared light intensity exists, signal carriers obtained by photoelectric conversion are guided to the active tap due to an electric field generated within the substrate 142, and are detected in the N+ semiconductor region of the active tap.

[0220] On the other hand, near the region R12 including the inactive tap, the intensity of the incident infrared light is relatively weak, and thus photoelectric conversion of the infrared light is unlikely to occur in the region R12. That is, the amount of light of the infrared light incident near the inactive tap is small, and thus the number of signal carriers generated due to photoelectric conversion near the inactive tap and migrated to the N+ semiconductor region of the inactive tap is reduced. Thus, the charge separation efficiency can be improved. This makes it possible to improve the ranging characteristics.

[0221] Further, in the back-illuminated light-receiving element 1, reduction in the thickness of the substrate 61 is possible, and thus the electron extraction efficiency of the electrons (charges) as signal carriers can be improved.

[0222] For example, in a front-illuminated CAPD sensor, it is difficult to secure sufficient aperture ratio, and thus it is necessary to some extent to increase the thickness of the substrate 171 to secure high quantum efficiency and suppress reduction in the quantum efficiency x aperture ratio as indicated by the arrow W31 in FIG. 15. Figure 6

[0223] In this case, the inclination of the potential becomes gentle in a region near the surface of the substrate 171 opposite to the light-incident surface (for example, at a part of the region R21), and thus the electric field in the direction perpendicular to the substrate 171 is substantially weakened. In this case, the migration speed of the signal carriers is slowed, and thus the time taken until the signal carriers are detected in the N+ semiconductor region of the active tap after photoelectric conversion is performed is extended. Note that, in FIG. 16, the arrows within the substrate 171 indicate the electric field in the substrate 171 in the direction perpendicular to the substrate 171. Figure 6

[0224] Further, when the substrate 171 is thick, the migration distance of the signal carriers from a position away from the active tap within the substrate 171 to the N+ semiconductor region within the active tap is long. Thus, at the position away from the active tap, the time taken until the signal carriers are detected in the N+ semiconductor region of the active tap after photoelectric conversion is performed is also extended.

[0225] Figure 7 A relationship between a position in the thickness direction of the substrate 171 and the migration speed of the signal carriers is shown. The region R21 corresponds to a diffusion current region.

[0226] ​​As described above, if the thickness of the substrate 171 is large, for example, when the driving frequency is high, that is, when the switching between the active and inactive of the tapping portion (signal extraction unit) is performed at high speed, it is difficult to completely inject the electrons generated at positions such as the region R21 far from the active tapping portion into the N+ semiconductor region of the active tapping portion. That is, in the case where the time during which the tapping portion is active is short, it can be difficult to detect the electrons (charges) generated in the region R21 in the N+ semiconductor region of the active tapping portion, and thus the electron extraction efficiency deteriorates.

[0227] On the contrary, in the rear-illumination type CAPD sensor, sufficient aperture ratio can be ensured. Thus, for example, when the substrate 172 is thinned as indicated by the arrow W32 in FIG. 32, sufficient quantum efficiency x aperture ratio can be ensured. Here, the substrate 172 corresponds to the substrate 61 in FIG. 31, and the arrow in the substrate 172 indicates the electric field in the direction perpendicular to the substrate 172. Figure 6 Figure 2

[0228] Figure 8 A relationship between the position in the thickness direction of the substrate 172 and the migration speed of the signal carrier is shown.

[0229] As described above, when the thickness of the substrate 172 in the direction perpendicular to the substrate 172 is made small, the electric field in the direction perpendicular to the substrate 172 is substantially strengthened, only the electrons (charges) in the migration current region having a fast signal carrier migration speed are used, and the electrons in the diffusion current region having a slow signal carrier migration speed are not used. Since only the electrons (charges) in the migration current region are used, the time taken until the signal carrier is detected in the N+ semiconductor region of the active tapping portion after photoelectric conversion is performed is shortened. In addition, when the thickness of the substrate 172 is made small, the migration distance of the signal carrier to the N+ semiconductor region in the active tapping portion is also shortened.

[0230] Thus, in the rear-illumination type CAPD sensor, even when the driving frequency is high, the signal carriers (electrons) generated in each region in the substrate 172 can be sufficiently injected into the N+ semiconductor region of the active tapping portion, and thus the electron extraction efficiency can be improved.

[0231] In addition, even at a high driving frequency, since the thickness of the substrate 172 is reduced, sufficient electron extraction efficiency can be ensured, and the high-speed driving tolerance can be improved.

[0232] ​​In particular, in the back-illuminated CAPD sensor, a voltage can be directly applied to the substrate 172 (i.e., the substrate 61), and thus the response speed for switching between the active and inactive of the tap portion is fast, and thus the sensor can be driven at a high drive frequency. In addition, since a voltage can be directly applied to the substrate 61, the modulation possible area within the substrate 61 is wide.

[0233] In addition, in the back-illuminated light-receiving element 1 (CAPD sensor), a sufficient aperture ratio can be obtained, and thus the pixel can be miniaturized in proportion to the aperture ratio, and the miniaturization tolerance of the pixel can be improved.

[0234] In addition, in the light-receiving element 1, since it is back-illuminated, the degree of freedom of the line back end (BEOL: back end of line) capacity design can be achieved, and thus the design degree of freedom of the saturated signal amount (Qs) can be improved.

[0235] Variation 1 of the first embodiment

[0236] Configuration example of a pixel

[0237] Note that the case where the N+ semiconductor region 71 and the P+ semiconductor region 73 are provided as a rectangular region as shown in the example has been described. However, the shape of the N+ semiconductor region 71 and the P+ semiconductor region 73 can be any shape when viewed from the direction perpendicular to the substrate 61. Figure 3

[0238] Specifically, for example, as shown in the example, the N+ semiconductor region 71 and the P+ semiconductor region 73 can be provided as a circular shape. Note that in the example, the same reference numerals are given to the portions corresponding to the case of the example, and the description thereof is appropriately omitted. Figure 9 Figure 9 Figure 3

[0239] Figure 9 The N+ semiconductor region 71 and the P+ semiconductor region 73 when a portion of the signal extraction unit 65 in the pixel 51 is viewed from the direction perpendicular to the substrate 61 are shown.

[0240] In this example, the oxide film 64 (not shown) is formed at the central portion of the pixel 51, and the signal extraction unit 65 is formed at a portion slightly closer to the end side from the center of the pixel 51. In particular, here, two signal extraction units 65 are formed in the pixel 51.

[0241] ​​​​Further, in the signal extraction unit 65, the P+ semiconductor region 73 having a circular shape is formed at a center position, and the periphery of the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71 having a circular shape (more specifically, an annular shape) in a state where the P+ semiconductor region 73 is disposed at the center.

[0242] Figure 10 is a plan view showing that the on-chip lens 62 is superimposed on a part of the pixel array unit 20, in which the on-chip lens 62 is formed in a unit of a pixel. Figure 9 The pixels 51 of the signal extraction unit 65 shown in are two-dimensionally arranged in a matrix shape.

[0243] As shown in the drawing, the on-chip lens 62 is formed in a unit of a pixel. In other words, a unit region in which one on-chip lens 62 is formed corresponds to one pixel.

[0244] Note that, in Figure 2 , the isolation portion 75 composed of an oxide film or the like is provided between the N+ semiconductor region 71 and the P+ semiconductor region 73, but the isolation portion 75 can be present or absent.

[0245] <Modification 2 of the First Embodiment>

[0246] <Configuration Example of a Pixel>

[0247] Figure 11 is a plan view showing a modification of the planar shape of the signal extraction unit 65 in the pixel 51.

[0248] The planar shape of the signal extraction unit 65 can be provided in a shape other than the rectangular shape shown in Figure 3 and the circular shape shown in Figure 9 , for example, an octagonal shape as shown in Figure 11

[0249] Further, in Figure 11 , a case where the isolation portion 75 composed of an oxide film or the like is formed between the N+ semiconductor region 71 and the P+ semiconductor region 73 is shown.

[0250] Figure 11 The line A-A' shown in Figure 37 indicates a cross-sectional line in Figure 36 to be described later, and the line B-B' indicates a cross-sectional line in to be described later.

[0251] <Second Embodiment>

[0252] <Configuration Example of a Pixel>

[0253] Further, the configuration in which the periphery of the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71 in the signal extraction unit 65 has been described, but the periphery of the N+ semiconductor region can be surrounded by the P+ semiconductor region.

[0254] In this case, for example, the pixel 51 has a configuration as shown in Figure 12 Note that, in Figure 12 , the same reference numerals are given to portions corresponding to those in Figure 3 , and the description thereof is appropriately omitted.

[0255] Figure 12 The arrangement of the N+ semiconductor region and the P+ semiconductor region is shown when a portion of the signal extraction unit 65 is observed from a direction perpendicular to the substrate 61.

[0256] In this example, the oxide film 64 (not shown) is formed at a central portion of the pixel 51, and the signal extraction unit 65-1 is formed in the drawing at a portion slightly closer to the upper side from the center of the pixel 51. And the signal extraction unit 65-2 is formed in the drawing at a portion slightly closer to the lower side from the center of the pixel 51. In particular, in this example, the formation position of the signal extraction unit 65 in the pixel 51 is set to the same position as in Figure 3 .

[0257] In the signal extraction unit 65-1, a rectangular N+ semiconductor region 201-1 corresponding to the N+ semiconductor region 71-1 shown in Figure 3 is formed at the center of the signal extraction unit 65-1. Further, the periphery of the N+ semiconductor region 201-1 is surrounded by a P+ semiconductor region 202-1 corresponding to the P+ semiconductor region 73-1 shown in Figure 3 and having a rectangular shape (more specifically, a rectangular frame shape). That is, the P+ semiconductor region 202-1 is formed to surround the periphery of the N+ semiconductor region 201-1.

[0258] Similarly, in the signal extraction unit 65-2, a rectangular N+ semiconductor region 201-2 corresponding to the N+ semiconductor region 71-2 shown in Figure 3 is formed at the center of the signal extraction unit 65-2. Further, the periphery of the N+ semiconductor region 201-2 is surrounded by a P+ semiconductor region 202-2 corresponding to the P+ semiconductor region 73-2 shown in Figure 3 and having a rectangular shape (more specifically, a rectangular frame shape).

[0259] Note that, hereinafter, in a case where it is not necessary to distinguish between the N+ semiconductor region 201-1 and the N+ semiconductor region 201-2, these regions are simply referred to as N+ semiconductor regions 201. Also, hereinafter, in a case where it is not necessary to distinguish between the P+ semiconductor region 202-1 and the P+ semiconductor region 202-2, these regions are simply referred to as P+ semiconductor regions 202.

[0260] Even in a case where the signal extraction unit 65 has the configuration illustrated in FIG. 6, as in a case where the signal extraction unit 65 has the configuration illustrated in FIG. 5, the N+ semiconductor region 201 functions as a charge detection unit for detecting the amount of signal carriers, and the P+ semiconductor region 202 functions as a voltage application unit for generating an electric field by directly applying a voltage to the substrate 61. Figure 12 Figure 3 Even in a case where the signal extraction unit 65 has the configuration illustrated in FIG. 6, as in a case where the signal extraction unit 65 has the configuration illustrated in FIG. 5, the N+ semiconductor region 201 functions as a charge detection unit for detecting the amount of signal carriers, and the P+ semiconductor region 202 functions as a voltage application unit for generating an electric field by directly applying a voltage to the substrate 61.

[0261] <Modification 1 of the Second Embodiment>

[0262] <Configuration Example of a Pixel>

[0263] Also, as in the example illustrated in FIG. 5, even in an arrangement in which the periphery of the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202, the shapes of the N+ semiconductor region 201 and the P+ semiconductor region 202 can be set to arbitrary shapes. Figure 12 That is, for example, as illustrated in FIG. 6, the N+ semiconductor region 201 and the P+ semiconductor region 202 can be set to circular shapes. Note that, in FIG. 6, the same reference numerals are given to portions corresponding to the case of FIG. 5, and the explanation thereof is appropriately omitted.

[0264] Figure 13 Figure 13 Figure 12

[0265] Figure 13 A portion of the N+ semiconductor region 201 and the P+ semiconductor region 202 when a portion of the signal extraction unit 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61 is illustrated.

[0266] In this example, the oxide film 64 (not illustrated) is formed at a central portion of the pixel 51, and the signal extraction unit 65 is formed at a portion slightly closer to the end side from the center of the pixel 51. In particular, here, two signal extraction units 65 are formed in the pixel 51.

[0267] Also, in the signal extraction unit 65, the N+ semiconductor region 201 having a circular shape is formed at a central position, and in a state in which the N+ semiconductor region 201 is set as the center, the periphery of the N+ semiconductor region 201 is surrounded by the P+ semiconductor region 202 having a circular shape (more specifically, a ring shape).

[0268] <Third Embodiment>​​​​​

[0269] <Example of pixel construction>

[0270] In addition, the N+ semiconductor region and P+ semiconductor region formed in the signal extraction unit 65 can be configured as linear (rectangular).

[0271] In this case, for example, pixel 51 has as follows Figure 14 The structure shown. It should be noted that, in Figure 14 In this context, the same reference numerals are given corresponding to... Figure 3 The part in question, and its description appropriately omitted.

[0272] Figure 14 The arrangement of the N+ semiconductor region and the P+ semiconductor region is shown when a portion of the signal extraction unit 65 in pixel 51 is viewed from a direction perpendicular to substrate 61.

[0273] In this example, an oxide film 64 (not shown) is formed at the center of pixel 51, and signal extraction unit 65-1 is formed in the portion slightly above the center of pixel 51, while signal extraction unit 65-2 is formed in the portion slightly below the center of pixel 51. Specifically, in this example, the signal extraction unit 65 is formed in pixel 51 at a position similar to... Figure 3 The same position as the case.

[0274] In signal extraction unit 65-1, and Figure 3 A linear P+ semiconductor region 231 corresponding to the P+ semiconductor region 73-1 shown is formed at the center of the signal extraction unit 65-1. Additionally, with... Figure 3 The linear N+ semiconductor regions 232-1 and 232-2 corresponding to the N+ semiconductor region 71-1 shown are formed around the P+ semiconductor region 231, and the P+ semiconductor region 231 is inserted between them. That is, the P+ semiconductor region 231 is formed at the position between the N+ semiconductor regions 232-1 and 232-2.

[0275] It should be noted that in the following text, without special distinction between N+ semiconductor region 232-1 and N+ semiconductor region 232-2, these regions are also referred to simply as N+ semiconductor region 232.

[0276] exist Figure 3 In the example structure shown, the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71, but... Figure 14 In the example structure shown, the P+ semiconductor region 231 is inserted between two N+ semiconductor regions 232 that are adjacent to the P+ semiconductor region 231.

[0277] Similarly, in signal extraction unit 65-2, with Figure 3 A linear P+ semiconductor region 233 corresponding to the P+ semiconductor region 73-2 shown is formed at the center of the signal extraction unit 65-2. Additionally, with... Figure 3 The linear N+ semiconductor regions 234-1 and 234-2 corresponding to the N+ semiconductor region 71-2 shown are formed around the P+ semiconductor region 233, and the P+ semiconductor region 233 is inserted between them.

[0278] It should be noted that in the following text, without the need to specifically distinguish between N+ semiconductor region 234-1 and N+ semiconductor region 234-2, these regions are also referred to simply as N+ semiconductor region 234.

[0279] exist Figure 14 In the signal extraction unit 65 shown, P+ semiconductor region 231 and P+ semiconductor region 233 act as corresponding to Figure 3 The voltage application unit is shown in the P+ semiconductor region 73, and the N+ semiconductor regions 232 and 234 act as corresponding to... Figure 3 The charge detection unit is shown in the N+ semiconductor region 71. In this case, for example, the two regions, N+ semiconductor region 232-1 and N+ semiconductor region 232-2, are connected to the FD section A.

[0280] Furthermore, the length of each of the line-shaped P+ semiconductor region 231, N+ semiconductor region 232, P+ semiconductor region 233, and N+ semiconductor region 234 in the horizontal direction in the figure can be set to any length, and the regions may not have the same length.

[0281] <Fourth Embodiment>

[0282] <Example of pixel construction>

[0283] In addition, Figure 14 The example shown illustrates a structure in which P+ semiconductor region 231 or P+ semiconductor region 233 is inserted between N+ semiconductor region 232 or N+ semiconductor region 234, but a shape in which N+ semiconductor regions are inserted between P+ semiconductor regions is also possible.

[0284] In this case, for example, pixel 51 has as follows Figure 15 The structure shown. It should be noted that, in Figure 15 In the accompanying drawings, the same reference numerals are given to those corresponding to... Figure 3 The part in question, and its description appropriately omitted.

[0285] Figure 15 The arrangement of the N+ semiconductor region and the P+ semiconductor region is shown when a portion of the signal extraction unit 65 in the pixel 51 is observed from a direction perpendicular to the substrate 61.

[0286] In this example, the oxide film 64 (not shown) is formed at a central portion of the pixel 51, and the signal extraction unit 65 is formed at a portion slightly closer to the end side from the center of the pixel 51. In this example, the formation positions of the two signal extraction units 65 in the pixel 51 are the same positions as in the case of Figure 3 .

[0287] In the signal extraction unit 65-1, a linear N+ semiconductor region 261 corresponding to the N+ semiconductor region 71-1 shown in Figure 3 is formed at the center of the signal extraction unit 65-1. In addition, a linear P+ semiconductor region 262-1 and a linear P+ semiconductor region 262-2 corresponding to the P+ semiconductor region 73-1 shown in Figure 3 are formed at the periphery of the N+ semiconductor region 261, with the N+ semiconductor region 261 interposed therebetween. That is, the N+ semiconductor region 261 is formed at a position between the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2.

[0288] Note that, in the following, in the absence of a need to particularly distinguish the P+ semiconductor region 262-1 and the P+ semiconductor region 262-2, these regions are also simply referred to as the P+ semiconductor region 262.

[0289] Similarly, in the signal extraction unit 65-2, a linear N+ semiconductor region 263 corresponding to the N+ semiconductor region 71-2 shown in Figure 3 is formed at the center of the signal extraction unit 65-2. In addition, a linear P+ semiconductor region 264-1 and a linear P+ semiconductor region 264-2 corresponding to the P+ semiconductor region 73-2 shown in Figure 3 are formed at the periphery of the N+ semiconductor region 263, with the N+ semiconductor region 263 interposed therebetween.

[0290] Note that, in the following, in the absence of a need to particularly distinguish the P+ semiconductor region 264-1 and the P+ semiconductor region 264-2, these regions are also simply referred to as the P+ semiconductor region 264.

[0291] In the signal extraction unit 65 shown in Figure 15 , the P+ semiconductor region 262 and the P+ semiconductor region 264 function as voltage application units corresponding to the P+ semiconductor region 73 shown in Figure 3 , and the N+ semiconductor region 261 and the N+ semiconductor region 263 function as voltage application units corresponding to the N+ semiconductor region 71 shown in Figure 3The charge detection unit of the N+ semiconductor region 71 is shown. Note that the length of each of the N+ semiconductor region 261, the P+ semiconductor region 262, the N+ semiconductor region 263, and the P+ semiconductor region 264 having a linear shape in the horizontal direction of the drawing can be set to an arbitrary length, and the respective regions can not have the same length.

[0292] <The fifth embodiment>

[0293] <Configuration example of a pixel>

[0294] In addition, an example in which two signal extraction units 65 are provided in each pixel constituting the pixel array unit 20 has been described, but the number of signal extraction units provided in a pixel can be one or more than three.

[0295] For example, in the case where one signal extraction unit is formed in the pixel 51, the pixel has a configuration as shown in Figure 16 Note that in Figure 16 , the same reference numerals are given to portions corresponding to Figure 3 , and the description thereof is appropriately omitted.

[0296] Figure 16 The arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of the signal extraction unit provided in a portion of the pixels in the pixel array unit 20 is observed from a direction perpendicular to the substrate is shown.

[0297] In this example, the pixel 51 provided in the pixel array unit 20 and the pixels 291-1 to 291-3 given different reference numerals as pixels adjacent to the pixel 51 are described, and one signal extraction unit is formed in each pixel.

[0298] That is, one signal extraction unit 65 is formed at a central portion of the pixel 51. In addition, in the signal extraction unit 65, a P+ semiconductor region 301 having a circular shape is formed at a central position, and the periphery of the P+ semiconductor region 301 is surrounded by an N+ semiconductor region 302 having a circular shape (more specifically, an annular shape) in a state in which the P+ semiconductor region 301 is provided at the center.

[0299] Here, the P+ semiconductor region 301 corresponds to the P+ semiconductor region 73 shown in Figure 3 , and functions as a voltage application unit. In addition, the N+ semiconductor region 302 corresponds to the N+ semiconductor region 71 shown in Figure 3 , and functions as a charge detection unit. Note that the P+ semiconductor region 301 and the N+ semiconductor region 302 can have an arbitrary shape.

[0300] Further, the pixels 291-1 to 291-3 located at the periphery of the pixel 51 have the same structure as the pixel 51.

[0301] That is, for example, one signal extraction unit 303 is formed at the center portion of the pixel 291-1. Further, in the signal extraction unit 303, a P+ semiconductor region 304 having a circular shape is formed at the center position, and the periphery 304 of the P+ semiconductor region is surrounded by an N+ semiconductor region 305 having a circular shape (more specifically, an annular shape) in a state where the P+ semiconductor region 304 is centered.

[0302] The P+ semiconductor region 304 and the N+ semiconductor region 305 correspond to the P+ semiconductor region 301 and the N+ semiconductor region 302, respectively.

[0303] Note that, without particularly distinguishing the pixel 291-1 and the pixel 291-3, these pixels are also simply referred to as the pixel 291.

[0304] As described above, in a case where one signal extraction unit (tapping) is formed in each pixel, when the distance to the target object is measured by the indirect ToF method, a plurality of pixels adjacent to each other are used, and the distance information is calculated based on the pixel signals obtained for the pixels.

[0305] For example, when the pixel 51 is focused on, in a state where the signal extraction unit 65 of the pixel 51 is set as the active tapping, for example, the pixel 51 is driven so that the plurality of signal extraction units 303 of the plurality of pixels 291 including the pixel 291-1 and adjacent to the pixel 51 become the inactive tapings.

[0306] As an example, for example, the signal extraction units of the pixels such as the pixel 291-1 and the pixel 291-3 adjacent to the pixel 51 on the upper and lower sides and the left and right sides in the drawing are driven to become the inactive tapings.

[0307] Then, when the applied voltage is switched so that the signal extraction unit 65 of the pixel 51 becomes the inactive tapping, at this time, the signal extraction units 303 of the plurality of pixels 291 including the pixel 291-1 and adjacent to the pixel 51 are set as the active tapings.

[0308] Further, the distance information is calculated based on the pixel signal read out from the signal extraction unit 65 in a state where the signal extraction unit 65 is set as the active tapping and the pixel signal read out from the signal extraction unit 303 in a state where the signal extraction unit 303 is set as the active tapping.

[0309] As described above, even when a signal extraction unit (tap) is set in a pixel, ranging can be performed using adjacent pixels according to the indirect ToF method.

[0310] <Sixth Embodiment>

[0311] <Example of pixel construction>

[0312] In addition, as mentioned above, more than three signal extraction units (splitters) can be set in each pixel.

[0313] For example, when four signal extraction units (splitters) are provided in a pixel, each pixel of the pixel array unit 20 has, as Figure 17 The structure shown. It should be noted that, in Figure 17 In the accompanying drawings, the same reference numerals are given to those corresponding to... Figure 16 The part in question, and its description appropriately omitted.

[0314] Figure 17 The arrangement of the N+ semiconductor region and the P+ semiconductor region is shown when a portion of the signal extraction unit disposed in a portion of the pixels in the pixel array unit 20 is viewed from a direction perpendicular to the substrate.

[0315] along Figure 17 The cross-sectional view taken by line C-C' in the diagram will be explained later. Figure 36 .

[0316] In this example, pixels 51 and 291 are set in pixel array unit 20, and four signal extraction units are formed in each pixel.

[0317] In other words, in pixel 51, signal extraction units 331-1, 331-2, 331-3 and 331-4 are respectively formed at positions between the center of pixel 51 and the end of pixel 51, that is, the lower left, upper left, upper right and lower right positions of the center of pixel 51 in the attached figure.

[0318] Signal extraction units 331-1 to 331-4 correspond to Figure 16 The signal extraction unit 65 shown.

[0319] For example, in the signal extraction unit 331-1, a circular P+ semiconductor region 341 is formed at the center, and with the P+ semiconductor region 341 set at the center, the periphery of the P+ semiconductor region 341 is surrounded by an N+ semiconductor region 342 with a circular shape (more specifically, an annular shape).

[0320] Here, P+ semiconductor region 341 corresponds to Figure 16 The P+ semiconductor region 301 illustrated is a voltage application unit. In addition, the N+ semiconductor region 342 corresponds to Figure 16 The N+ semiconductor region 302 illustrated is a charge detection unit. Note that the P+ semiconductor region 341 and the N+ semiconductor region 342 can have an arbitrary shape.

[0321] In addition, the signal extraction units 331-2 to 331-4 have the same configuration as the signal extraction unit 333-1, and include a P+ semiconductor region that functions as a voltage application unit and an N+ semiconductor region that functions as a charge detection unit. In addition, the pixel 291 formed at the periphery of the pixel 51 has the same structure as the pixel 51.

[0322] Note that, in a case where the signal extraction unit 331-1 and the signal extraction unit 331-4 are not particularly distinguished, these units are also simply referred to as signal extraction units 331.

[0323] As described above, in a case where four signal extraction units are provided in each pixel, when distance measurement is performed, for example, according to an indirect ToF method, the four signal extraction units in the pixel are used, and distance information is calculated.

[0324] As an example, when the pixel 51 is focused on, for example, in a state where the signal extraction unit 331-1 and the signal extraction unit 331-3 are set as active taps, the pixel 51 is driven so that the signal extraction unit 331-2 and the signal extraction unit 331-4 become non-active taps.

[0325] Then, the voltage applied to the signal extraction unit 331 is switched. That is, the pixel 51 is driven so that the signal extraction unit 331-1 and the signal extraction unit 331-3 become non-active taps, and the signal extraction unit 331-2 and the signal extraction unit 331-4 become active taps.

[0326] In addition, distance information is calculated on the basis of the pixel signals read out from the signal extraction unit 331-1 and the signal extraction unit 331-3 in a state where the signal extraction unit 331-1 and the signal extraction unit 331-3 are set as active taps, and the pixel signals read out from the signal extraction unit 331-2 and the signal extraction unit 331-4 in a state where the signal extraction unit 331-2 and the signal extraction unit 331-4 are set as active taps.

[0327] <Seventh Embodiment>

[0328] <Configuration Example of Pixel>

[0329] In addition, the signal extraction unit (tap) can be shared by adjacent pixels of the pixel array unit 20.

[0330] In this case, for example, each pixel of the pixel array unit 20 has a configuration as shown in FIG. 37. Figure 18 Note that in Figure 18 , the same reference numerals are given to portions corresponding to Figure 16 , and the description thereof is appropriately omitted.

[0331] Figure 18 An arrangement of the N+ semiconductor region and the P+ semiconductor region when a portion of the signal extraction unit provided in a partial pixel in the pixel array unit 20 is observed from a direction perpendicular to the substrate is shown.

[0332] In this example, a pixel 51 and a pixel 291 provided in the pixel array unit 20 are shown, and two signal extraction units are formed in each of these pixels.

[0333] For example, in the pixel 51, a signal extraction unit 371 is formed at an end portion of the upper side of the pixel 51 in the drawing, and a signal extraction unit 372 is formed at an end portion of the lower side of the pixel 51 in the drawing.

[0334] The signal extraction unit 371 is shared by the pixel 51 and a pixel 291-1. That is, the signal extraction unit 371 functions as a tapping portion of the pixel 51 and as a tapping portion of the pixel 291-1. In addition, the signal extraction unit 372 is shared by the pixel 51 and a pixel (not shown) adjacent to the lower side of the pixel 51 in the drawing.

[0335] In the signal extraction unit 371, a linear P+ semiconductor region 381 corresponding to the P+ semiconductor region 231 shown in FIG. 37 is formed at a central position. In addition, linear N+ semiconductor regions 382-1 and 382-2 corresponding to the N+ semiconductor regions 232 shown in FIG. 37 are formed at an upper position and a lower position of the P+ semiconductor region 381 in the drawing, and the P+ semiconductor region 381 is interposed therebetween. Figure 14 Figure 14 In particular, in this example, the P+ semiconductor region 381 is formed at a boundary portion between the pixel 51 and the pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in a region within the pixel 51, and the N+ semiconductor region 382-2 is formed in a region within the pixel 291-1.

[0336] In particular, in this example, the P+ semiconductor region 381 is formed at a boundary portion between the pixel 51 and the pixel 291-1. In addition, the N+ semiconductor region 382-1 is formed in a region within the pixel 51, and the N+ semiconductor region 382-2 is formed in a region within the pixel 291-1.

[0337] ​Here, the P+ semiconductor region 381 functions as a voltage application unit, and the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 function as charge detection units. Note that hereinafter, in the case where it is not particularly necessary to distinguish between the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2, these regions are also simply referred to as N+ semiconductor regions 382.

[0338] In addition, the P+ semiconductor region 381 or the N+ semiconductor region 382 can have an arbitrary shape. In addition, the N+ semiconductor region 382-1 and the N+ semiconductor region 382-2 can be connected to the same FD portion, or can be connected to different FD portions from each other.

[0339] The P+ semiconductor region 383, the N+ semiconductor region 384-1, and the N+ semiconductor region 384-2 are formed in the signal extraction unit 372 in a linear shape.

[0340] The P+ semiconductor region 383, the N+ semiconductor region 384-1, and the N+ semiconductor region 384-2 correspond to the P+ semiconductor region 381, the N+ semiconductor region 382-1, and the N+ semiconductor region 382-2, respectively, and are provided to have the same arrangement, the same shape, and the same function as these regions. Note that hereinafter, in the case where it is not particularly necessary to distinguish between the N+ semiconductor region 384-1 and the N+ semiconductor region 384-2, these regions are also simply referred to as N+ semiconductor regions 384.

[0341] As described above, even in the case where the signal extraction unit (tapping portion) is shared between adjacent pixels, it is possible to extend the distance between the P+ semiconductor regions by Figure 3 The ranging is performed according to the indirect ToF method by the same operation as in the example shown in FIG. 9.

[0342] As Figure 18 In the case where the signal extraction unit is shared between pixels, for example, the distance between the P+ semiconductor region 381 and the P+ semiconductor region 383, that is, the distance between a pair of P+ semiconductor regions for generating an electric field (current) is extended. In other words, when the signal extraction unit is shared between pixels, it is possible to extend the distance between the P+ semiconductor regions to the maximum.

[0343] Therefore, it is less likely that a current flows between the P+ semiconductor regions, and thus it is possible to reduce the power consumption in the pixel. In addition, the above-described configuration is advantageous for the downsizing of the pixel.

[0344] Note that the example in which one signal extraction unit is shared by two pixels adjacent to each other has been described, but one signal extraction unit can be shared by three or more pixels adjacent to each other. In addition, in a case where signal extraction units are shared by two or more pixels adjacent to each other, in the signal extraction unit, only the charge detection unit for detecting signal carriers can be shared, or only the voltage application unit for generating an electric field can be shared.

[0345] <Eighth Embodiment>

[0346] <Configuration Example of Pixel>

[0347] In addition, an on-chip lens or an inter-pixel light shielding portion provided in each pixel such as the pixel 51 of the pixel array unit 20 can not be particularly provided.

[0348] Specifically, for example, the pixel 51 can be provided as Figure 19 the configuration illustrated. Note that in Figure 19 , the same reference signs are given to portions corresponding to those in Figure 2 , and the description thereof is appropriately omitted.

[0349] Figure 19 The configuration of the pixel 51 illustrated in Figure 2 is different from the configuration of the pixel 51 illustrated in Figure 2 in that the on-chip lens 62 is not provided, and the other configurations are the same as those of the pixel 51 in .

[0350] In the pixel 51 illustrated in Figure 19 , since the on-chip lens 62 is not provided on the light incident surface side of the substrate 61, it is possible to make the attenuation of infrared light incident from the outside to the substrate 61 smaller. Therefore, the amount of infrared light that can be received by the substrate 61 increases, and thus it is possible to improve the sensitivity of the pixel 51.

[0351] <Modification 1 of Eighth Embodiment>

[0352] <Configuration Example of Pixel>

[0353] In addition, the configuration of the pixel 51 can be provided as, for example, the configuration illustrated in Figure 20 . Note that in Figure 20 , the same reference signs are given to portions corresponding to those in Figure 2 , and the description thereof is appropriately omitted.

[0354] Figure 20 The configuration of the pixel 51 illustrated in Figure 2 is different from the configuration of the pixel 51 illustrated in Figure 2The construction of pixel 51 is the same.

[0355] exist Figure 20 In the example shown, since no inter-pixel light-shielding film 63 is provided on the light incident surface side of the substrate 61, the crosstalk suppression effect is reduced. However, the infrared light shielded by the inter-pixel light-shielding film 63 is also incident on the substrate 61, thus improving the sensitivity of the pixel 51.

[0356] It should be noted that the on-chip lens 62 and the inter-pixel light-shielding film 63 may not be set in the pixel 51.

[0357] <Variation 2 of the Eighth Embodiment>

[0358] <Example of pixel construction>

[0359] Additionally, for example, such as Figure 21 As shown, the thickness of the on-chip lens along the optical axis can also be optimized. It should be noted that... Figure 21 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0360] Figure 21 The structure of pixel 51 shown is similar to Figure 2 The difference in the construction of pixel 51 shown is that an on-chip lens 411 is used instead of on-chip lens 62, while the other constructions are the same. Figure 2 The construction of pixel 51 is the same.

[0361] exist Figure 21 In pixel 51 shown, an on-chip lens 411 is formed on the light-incident surface side of the substrate 61 (i.e., the upper side in the figure). Figure 2 Compared to the on-chip lens 62 shown, the on-chip lens 411 has a smaller thickness in the optical axis direction (i.e., the thickness in the vertical direction in the figure).

[0362] Generally, a larger thickness of the on-chip lens disposed on the front surface of the substrate 61 is more conducive to converging the light incident on the on-chip lens. However, when the thickness of the on-chip lens 411 decreases, the transmittance increases proportionally to the decrease, thereby improving the sensitivity of the pixel 51. Therefore, the thickness of the on-chip lens 411 can be appropriately determined based on the thickness of the substrate 61, the focusing position of the infrared light, etc.

[0363] <Ninth Embodiment>

[0364] <Example of pixel construction>

[0365] Additionally, isolation regions can be provided between pixels formed in the pixel array unit 20 to suppress crosstalk by improving the isolation characteristics between adjacent pixels.

[0366] In this case, for example, the pixel 51 has a configuration as shown in Figure 22 Note that, in Figure 22 , the same reference numerals are given to portions corresponding to those in Figure 2 , and the description thereof is appropriately omitted.

[0367] Figure 22 The configuration of the pixel 51 shown in Figure 2 differs from that of the pixel 51 shown in Figure 2 in that isolation regions 441-1 and 441-2 are provided inside the substrate 61, and the other configuration is the same as that of the pixel 51 in

[0368] In the pixel 51 shown in Figure 22 , isolation regions 441-1 and 441-2 for isolating adjacent pixels are formed inside the substrate 61 at boundary portions between the pixel 51 and other pixels adjacent to the pixel 51, that is, at end portions of the right and left sides of the pixel 51 in the drawing, by a light shielding film or the like. Note that, in a case where it is not particularly necessary to distinguish the isolation regions 441-1 and 441-2, these regions are also simply referred to as isolation regions 441.

[0369] For example, when the isolation regions 441 are formed, an elongated groove (trench) is formed in the substrate 61 at a predetermined depth (in a direction perpendicular to the surface of the substrate 61) from the light incident surface side of the substrate 61, that is, from the upper side surface toward the lower side in the drawing. Then, a light shielding film is formed in the trench portion by embedding, and becomes the isolation regions 441. The isolation regions 441 function as pixel isolation regions that shield infrared light incident from the light incident surface into the substrate 61 and propagating toward other pixels adjacent to the pixel 51.

[0370] As described above, when the embedded-type isolation regions 441 are formed, the infrared light separation characteristics between pixels can be improved, and thus occurrence of crosstalk can be suppressed.

[0371] <Modification Example 1 of the Ninth Embodiment>

[0372] <Configuration Example of a Pixel>

[0373] In addition, in a case where the embedded-type isolation regions are formed in the pixel 51, for example, as shown in Figure 23 , isolation regions 471-1 and 471-2 that penetrate the entire substrate 61 can be provided. Note that, in Figure 23 , the same reference numerals are given to portions corresponding to those in Figure 2 , and the description thereof is appropriately omitted.

[0374] Figure 23 The structure of pixel 51 shown is similar to Figure 2 The difference in the structure of pixel 51 shown is that isolation regions 471-1 and 471-2 are provided within the substrate 61, while other structures are the same. Figure 2 The construction of pixel 51 is the same. That is to say, in Figure 23 The pixel 51 shown has isolation regions 471-1 and 471-2 in its structure, to replace Figure 22 The isolated region 441 of pixel 51 shown.

[0375] exist Figure 23 In the pixel 51 shown, isolation regions 471-1 and 471-2, which penetrate the entire substrate 61 through a light-shielding film or the like, are formed within the substrate 61 at the boundary between pixel 51 and other pixels adjacent to pixel 51, that is, at the right and left ends of pixel 51 in the attached figure. It should be noted that, unless otherwise specified, isolation regions 471-1 and 471-2 are simply referred to as isolation region 471.

[0376] For example, when forming the isolation region 471, an elongated groove (trench) is formed in the surface of the substrate 61 opposite to the light incident surface side (i.e., from the lower surface in the figure towards the upper surface in the figure). At this time, the trench is formed until it reaches the light incident surface of the substrate 61 to penetrate the substrate 61. In addition, a light-shielding film is formed by embedding it in the trench portion formed as described above, and the light-shielding film becomes the isolation region 471.

[0377] The embedded isolation region 471 can also improve the infrared light separation characteristics between pixels, thus suppressing crosstalk.

[0378] <Tenth Embodiment>

[0379] <Example of pixel construction>

[0380] In addition, the thickness of the substrate on which the signal extraction unit 65 is formed can be determined based on various characteristics of the pixels.

[0381] Therefore, for example, such as Figure 24 As shown, with Figure 2 Compared to the substrate 61 shown, the substrate 501 constituting the pixel 51 can be made thicker. It should be noted that... Figure 24 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0382] Figure 24 The structure of pixel 51 shown is similar to Figure 2The difference in the structure of pixel 51 shown is that substrate 501 is provided instead of substrate 61, while other structures are the same. Figure 2 The construction of pixel 51 is the same.

[0383] In other words, Figure 24 In the pixel 51 shown, an on-chip lens 62, a fixed charge film 66, and an inter-pixel light-shielding film 63 are formed on the light incident surface side of the substrate 501. An oxide film 64, a signal extraction unit 65, and an isolation portion 75 are formed near the front surface of the substrate 501 opposite to the light incident surface side.

[0384] For example, substrate 501 is made of a P-type semiconductor substrate with a thickness of 20 μm or more. Substrate 501 and substrate 61 differ only in substrate thickness, and the oxide film 64, signal extraction unit 65 and isolation portion 75 are formed at the same locations between substrate 501 and substrate 61.

[0385] It should be noted that the film thickness of various layers (films) formed on the light incident surface side of substrate 501 or substrate 61 can be optimized appropriately according to the characteristics of pixel 51, etc.

[0386] <Eleventh Embodiment>

[0387] <Example of pixel construction>

[0388] Furthermore, an example has already been given of the substrate constituting pixel 51 being formed from a P-type semiconductor substrate, but this substrate could, for example, be formed from a P-type semiconductor substrate. Figure 25 The N-type semiconductor substrate shown is constructed. It should be noted that... Figure 25 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0389] Figure 25 The structure of pixel 51 shown is similar to Figure 2 The difference in the structure of pixel 51 shown is that substrate 531 is provided instead of substrate 61, while other structures are the same. Figure 2 The construction of pixel 51 is the same.

[0390] exist Figure 25 In the pixel 51 shown, for example, an on-chip lens 62, a fixed charge film 66, and an inter-pixel light-shielding film 63 are formed on the light incident surface side of a substrate 531 composed of an N-type semiconductor layer.

[0391] Furthermore, the oxide film 64, the signal extraction unit 65, and the isolation portion 75 are formed near the surface of the substrate 531 opposite to the light incident surface. The formation positions of the oxide film 64, the signal extraction unit 65, and the isolation portion 75 are the same between the substrate 531 and the substrate 61, and the structure of the signal extraction unit 65 is also the same between the substrate 531 and the substrate 61.

[0392] For example, the thickness of the substrate 531 in the vertical direction in the figure, that is, the thickness in the direction perpendicular to the surface of the substrate 531, is set to less than 20 μm.

[0393] Furthermore, for example, the substrate 531 is configured as a high-resistivity N-Epi substrate, with a substrate density on the order of 1E+13 or less, and the resistance (resistivity) of the substrate 531 is set to, for example, 500 [Ωcm] or more. Therefore, the power consumption in the pixel 51 can be reduced.

[0394] Here, regarding the relationship between substrate concentration and resistance of substrate 531, for example, when the substrate concentration is 2.15E+12 [cm] 3 When the substrate concentration is 4.30E+12 [cm], the resistance is set to 2000 [Ωcm]; 3 When the substrate concentration is 8.61E+12 [cm], the resistance is set to 1000 [Ωcm]; 3 When the substrate concentration is 4.32E+13 [cm], the resistance is set to 500 [Ωcm]; and when the substrate concentration is 4.32E+13 [cm] 3 When ], the resistance is set to 100 [Ωcm].

[0395] As described above, even when the substrate 531 of pixel 51 is configured as an N-type semiconductor substrate, it can still be connected to... Figure 2 The same operation is used in the example shown to achieve the same effect.

[0396] <Twelfth Embodiment>

[0397] <Example of pixel construction>

[0398] Additionally, as in reference Figure 24 In the illustrated example, the thickness of the N-type semiconductor substrate can also be determined based on various characteristics of the pixels.

[0399] Therefore, for example, such as Figure 26 As shown, with Figure 25 Compared to the substrate 531 shown, the substrate 561 constituting the pixel 51 can be made thicker. It should be noted that... Figure 26 In the accompanying drawings, the same reference numerals are given to... Figure 25 The corresponding parts are omitted as appropriate.

[0400] Figure 26 The configuration of the pixel 51 shown in FIG. 6 is different from the configuration of the pixel 51 shown in FIG. 5 in that the substrate 561 is provided in place of the substrate 531, and the other configurations are the same as those of the pixel 51. Figure 25 The configuration of the pixel 51 shown in FIG. 6 is different from the configuration of the pixel 51 shown in FIG. 5 in that the substrate 561 is provided in place of the substrate 531, and the other configurations are the same as those of the pixel 51.

[0401] That is, in the pixel 51 shown in FIG. 6, the on-chip lens 62, the fixed charge film 66, and the inter-pixel light-shielding film 63 are formed on the light-incident surface side in the substrate 561. The oxide film 64, the signal extraction unit 65, and the isolation portion 75 are formed in the vicinity of the surface of the substrate 561 opposite to the light-incident surface side. Figure 26 In the pixel 51 shown in FIG. 6, the on-chip lens 62, the fixed charge film 66, and the inter-pixel light-shielding film 63 are formed on the light-incident surface side in the substrate 561. The oxide film 64, the signal extraction unit 65, and the isolation portion 75 are formed in the vicinity of the surface of the substrate 561 opposite to the light-incident surface side.

[0402] For example, the substrate 561 is composed of an N-type semiconductor substrate having a thickness of 20 μm or more. The substrate 561 and the substrate 531 differ only in the substrate thickness, and the formation positions of the oxide film 64, the signal extraction unit 65, and the isolation portion 75 are the same between the substrates 561 and 531.

[0403] <Thirteenth Embodiment>

[0404] <Configuration Example of Pixel>

[0405] In addition, for example, the electric field in the substrate 61 in the direction perpendicular to the surface of the substrate 61 (hereinafter, can also be referred to as the Z direction) can be enhanced by applying a bias to the light-incident surface side of the substrate 61.

[0406] In this case, for example, the pixel 51 has the configuration shown in FIG. 7 and FIG. 8. Figure 27A and 27B The configuration shown in FIG. 7 and FIG. 8. Note that in FIG. 7 and FIG. 8, the same reference numerals are given to portions corresponding to the case of FIG. 6, and the description thereof is appropriately omitted. Figure 27A and 27B The configuration of the pixel 51 in FIG. 7 and FIG. 8 is basically the same as the configuration of the pixel 51 shown in FIG. 6, but the P+ semiconductor region 601 is newly added to the interface of the light-incident surface side of the substrate 61. Figure 2

[0407] The pixel 51 shown in FIG. 7 is shown, and the arrow in the substrate 61 of the pixel 51 represents the strength of the electric field in the Z direction in the substrate 61. Figure 27A Figure 2 On the contrary, the configuration of the pixel 51 in the case where a bias (voltage) is applied to the light-incident surface of the substrate 61 is shown.

[0408] The configuration of the pixel 51 in FIG. 7 and FIG. 8 is basically the same as the configuration of the pixel 51 shown in FIG. 6, but the P+ semiconductor region 601 is newly added to the interface of the light-incident surface side of the substrate 61. Figure 27B Figure 27B The configuration of the pixel 51 in FIG. 7 and FIG. 8 is basically the same as the configuration of the pixel 51 shown in FIG. 6, but the P+ semiconductor region 601 is newly added to the interface of the light-incident surface side of the substrate 61. Figure 2

[0409] ​​​In the P+ semiconductor region 601 formed at the light incident surface side interface of the substrate 61, a voltage of 0V or less (negative bias) is applied from inside or outside the pixel array unit 20, thereby enhancing the electric field in the Z direction. Figure 27B The arrow in the substrate 61 of pixel 51 indicates the intensity of the electric field in the Z direction within the substrate 61. Figure 27B The thickness of the arrow drawn within substrate 61 is greater than Figure 27A The thickness of the arrow in pixel 51 is increased, and the electric field in the Z direction becomes stronger. As described above, when a negative bias is applied to the P+ semiconductor region 601 formed on the light incident surface side of the substrate 61, the electric field in the Z direction is strengthened, thereby improving the electron extraction efficiency in the signal extraction unit 65.

[0410] It should be noted that the configuration for applying a voltage to the light incident surface side of the substrate 61 is not limited to the configuration with the P+ semiconductor region 601, and can be any other configuration. For example, a transparent electrode film can be formed by stacking it between the light incident surface of the substrate 61 and the on-chip lens 62, and a negative bias can be applied by applying a voltage to the transparent electrode film.

[0411] <Fourteenth Embodiment>

[0412] <Example of pixel construction>

[0413] In addition, a large-area reflective component can be provided on the surface of the substrate 61 opposite to the light incident surface to improve the sensitivity of the pixel 51 to infrared light.

[0414] In this case, for example, pixel 51 has as follows Figure 28 The structure shown. It should be noted that, in Figure 28 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0415] Figure 28 The structure of pixel 51 shown is similar to Figure 2 The difference in the structure of pixel 51 is that a reflective component 631 is provided on the surface of substrate 61 opposite to the light incident surface, while the other structures are the same as those in the original text. Figure 2 The construction of pixel 51 is the same.

[0416] exist Figure 28 The example shown includes a reflective component 631 that reflects infrared light and covers the entire surface of the substrate 61 opposite to the light incident surface.

[0417] The reflection member 631 can be any member as long as it has a high reflectance with respect to infrared light. For example, a metal such as copper or aluminum provided in a multilayer wiring layer laminated on the surface of the substrate 61 opposite to the light incident surface can be used as the reflection member 631, or a reflection structure such as a polysilicon and an oxide film can be formed on the surface of the substrate 61 opposite to the light incident surface as the reflection member 631.

[0418] As described above, when the reflection member 631 is provided in the pixel 51, the infrared light that has been incident into the substrate 61 from the light incident surface through the on-chip lens 62 and has been transmitted through the substrate 61 without being photoelectrically converted is reflected by the reflection member 631 and is incident into the substrate 61 again. Thus, the amount of infrared light that is photoelectrically converted inside the substrate 61 can be increased, and therefore the quantum efficiency (QE), that is, the sensitivity of the pixel 51 with respect to infrared light can be improved.

[0419] <15th Embodiment>

[0420] <Configuration Example of Pixel>

[0421] In addition, a large-area light-shielding member can be provided on the surface of the substrate 61 opposite to the light incident surface to suppress erroneous detection of light in the vicinity of the pixel.

[0422] In this case, for example, the pixel 51 can have a configuration in which the reflection member 631 illustrated in FIG. 6 is replaced with a light-shielding member. That is, in the pixel 51 illustrated in FIG. 7, the reflection member 631 covering the entire surface of the substrate 61 opposite to the light incident surface is provided as a light-shielding member 631'. Figure 28 Figure 28 In this case, for example, the pixel 51 can have a configuration in which the reflection member 631 illustrated in FIG. 6 is replaced with a light-shielding member. That is, in the pixel 51 illustrated in FIG. 7, the reflection member 631 covering the entire surface of the substrate 61 opposite to the light incident surface is provided as a light-shielding member 631'. Figure 28

[0423] The light-shielding member 631' can be any member as long as it has a high light-shielding rate with respect to infrared light. For example, a metal such as copper or aluminum provided in a multilayer wiring layer laminated on the surface of the substrate 61 opposite to the light incident surface can be used as the light-shielding member 631', or a light-shielding structure such as a polysilicon and an oxide film can be formed on the surface of the substrate 61 opposite to the light incident surface as the light-shielding member 631'.

[0424] As described above, when the light-shielding member 631' is provided in the pixel 51, the infrared light that has been incident into the substrate 61 from the light incident surface through the on-chip lens 62 and has been transmitted through the substrate 61 without being photoelectrically converted inside the substrate 61 can be suppressed from being scattered into the wiring layer and incident into the vicinity of the pixel. Thus, erroneous detection of light in the vicinity of the pixel can be prevented.

[0425] ​​It should be noted that, for example, when the light-shielding member 631' is made of a material including metal, the light-shielding member 631' can also act as a reflective member 631.

[0426] <Sixteenth Embodiment>

[0427] <Example of pixel construction>

[0428] Alternatively, a P-well region composed of a P-type semiconductor region can be provided in the substrate 61 of pixel 51 to replace the oxide film 64.

[0429] In this case, for example, pixel 51 has as follows Figure 29 The structure shown. It should be noted that, in Figure 29 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0430] Figure 29 The pixel 51 shown is Figure 2 The difference in the structure of pixel 51 shown is that a P-well region 671, isolation portion 672-1, and isolation portion 672-2 are provided instead of oxide film 64, while other structures are the same. Figure 2 The construction of pixel 51 is the same.

[0431] exist Figure 29 In the example shown, the P-well region 671, composed of a P-type semiconductor region, is formed inside the substrate 61 at the center of the surface side opposite to the light incident surface; that is, it is formed on the inner side of the lower surface in the figure. Furthermore, an isolation portion 672-1 is formed between regions having oxide films or the like to isolate the P-well region 671 and the N+ semiconductor region 71-1 from each other. Similarly, an isolation portion 672-2 is also formed between regions having oxide films or the like to isolate the P-well region 671 and the N+ semiconductor region 71-2 from each other. Figure 29 In pixel 51 shown, the P-semiconductor region 74 is wider in the upward direction in the attached figure compared to the N-semiconductor region 72.

[0432] <Seventeenth Embodiment>

[0433] <Example of pixel construction>

[0434] In addition to the oxide film 64 in the substrate 61 of pixel 51, a P-well region composed of a P-type semiconductor region may also be provided.

[0435] In this case, for example, pixel 51 has as follows Figure 30 The structure shown. It should be noted that, in Figure 30 In the accompanying drawings, the same reference numerals are given to... Figure 2 The corresponding parts are omitted as appropriate.

[0436] Figure 30 The configuration of the pixel 51 shown in FIG. 7 is different from the configuration of the pixel 51 shown in FIG. 6 in that a P-well region 701 is newly provided, and the other configurations are the same as those of the pixel 51 in FIG. 6. Figure 2 That is, in the example shown in FIG. 7, the P-well region 701 composed of a P-type semiconductor region is formed on the upper side of the oxide film 64 in the substrate 61. Figure 2 Figure 30 In the example shown in FIG. 7, the P-well region 701 composed of a P-type semiconductor region is formed on the upper side of the oxide film 64 in the substrate 61.

[0437] As described above, according to the present technology, since the CAPD sensor is configured as a rear-illumination type, it is possible to improve characteristics such as pixel sensitivity.

[0438] <Configuration example of equivalent circuit of pixel>

[0439] Figure 31 An equivalent circuit of the pixel 51 is shown.

[0440] With respect to the signal extraction unit 65-1 including the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 and the like, the pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplification transistor 724A, and a selection transistor 725A.

[0441] In addition, with respect to the signal extraction unit 65-2 including the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 and the like, the pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplification transistor 724B, and a selection transistor 725B.

[0442] The tap driving unit 21 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of the voltage MIX0 and the voltage MIX1 is 1.5 V, and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 are voltage application units to which the first voltage or the second voltage is applied.

[0443] The N+ semiconductor regions 71-1 and 71-2 are charge detection units that detect charges generated by photoelectric conversion of light incident to the substrate 61 and accumulate the charges.

[0444] ​When the drive signal TRG supplied to the gate electrode enters the active state, the transfer transistor 721A enters the on state in response to the active state, and transfers the electric charge accumulated in the N+ semiconductor region 71-1 to the FD 722A. When the drive signal TRG applied to the gate electrode enters the active state, the transfer transistor 721B enters the on state in response to the active state, and transfers the electric charge accumulated in the N+ semiconductor region 71-2 to the FD 722B.

[0445] The FD 722A temporarily holds the electric charge DET0 supplied from the N+ semiconductor region 71-1. The FD 722B temporarily holds the electric charge DET1 supplied from the N+ semiconductor region 71-2. The FD 722A corresponds to the reference Figure 2 described FD section A, and the FD 722B corresponds to the reference Figure 2 described FD section B.

[0446] When the drive signal RST supplied to the gate electrode enters the active state, the reset transistor 723A enters the on state in response to the active state, and resets the potential of the FD 722A to a predetermined level (power supply voltage VDD). When the drive signal RST supplied to the gate electrode enters the active state, the reset transistor 723B enters the on state in response to the active state, and resets the potential of the FD 722B to a predetermined level (power supply voltage VDD). Note that when the reset transistors 723A and 723B enter the active state, the transfer transistors 721A and 721B simultaneously enter the active state.

[0447] In the amplification transistor 724A, the source electrode is connected to the vertical signal line 29A through the selection transistor 725A, and the amplification transistor 724A constitutes a source follower circuit in combination with a load MOS of a constant current source circuit unit 726A connected to one end of the vertical signal line 29A. In the amplification transistor 724B, the source electrode is connected to the vertical signal line 29B through the selection transistor 725B, and the amplification transistor 724B constitutes a source follower circuit in combination with a load MOS of a constant current source circuit unit 726B connected to one end of the vertical signal line 29B.

[0448] The selection transistor 725A is connected between the source electrode of the amplification transistor 724A and the vertical signal line 29A. When the selection signal SEL applied to the gate electrode enters the active state, the selection transistor 725A enters the on state in response to the active state, and outputs the pixel signal output from the amplification transistor 724A to the vertical signal line 29A.

[0449] The selection transistor 725B is connected between the source electrode of the amplification transistor 724B and the vertical signal line 29B. When the selection signal SEL applied to the gate electrode enters the active state, the selection transistor 725B enters the on state in response to the active state and outputs the pixel signal output from the amplification transistor 724B to the vertical signal line 29B.

[0450] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by the vertical drive unit 22, for example.

[0451] <Another configuration example of an equivalent circuit of a pixel>

[0452] Figure 32 Another equivalent circuit of the pixel 51 is shown.

[0453] In Figure 32 , the same reference numerals are given to portions corresponding to Figure 31 , and the description thereof is omitted as appropriate.

[0454] In the equivalent circuit in Figure 31 , an additional capacitor 727 and a switching transistor 728 for controlling the connection of the additional capacitor 727 are added to the signal extraction units 65-1 and 65-2, compared to the equivalent circuit in Figure 32

[0455] Specifically, the additional capacitor 727A is connected between the transfer transistor 721A and the FD 722A through the switching transistor 728A, and the additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B through the switching transistor 728B.

[0456] When the drive signal FDG supplied to the gate electrode enters the active state, the switching transistor 728A enters the on state in response to the active state and connects the additional capacitor 727A to the FD 722A. When the drive signal FDG supplied to the gate electrode enters the active state, the switching transistor 728B enters the on state in response to the active state and connects the additional capacitor 727B to the FD 722B.

[0457] For example, in a high-illuminance state in which the amount of light of incident light is large, the vertical drive unit 22 sets the switching transistors 728A and 728B to the active state to connect the FD 722A and the additional capacitor 727A to each other and to connect the FD 722B and the additional capacitor 727B to each other. Thus, relatively large amounts of electric charges can be accumulated in the high-brightness state.

[0458] ​On the other hand, in a low-illuminance state in which the light quantity of incident light is small, the vertical drive unit 22 sets the switching transistors 728A and 728B to an inactive state to separate the additional capacitances 727A and 727B from the FDs 722A and 722B, respectively.

[0459] As in the equivalent circuit in Figure 31 , the additional capacitances 727 can be omitted, but when the additional capacitances 727 are provided and the additional capacitances 727 are selectively and appropriately used in accordance with the incident light quantity, a high dynamic range can be ensured.

[0460] <Arrangement example of voltage supply line>

[0461] Next, the arrangement of the voltage supply line for applying the predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the voltage application unit of the signal extraction unit 65 of the pixel 51 will be described with reference to Figures 33A to 35B Figure 33A and 33B as well as Figure 34A and 34B illustrated in FIG. 8. Figure 1 The voltage supply line 741 corresponds to the voltage supply line 30 illustrated in

[0462] Note that, regarding Figure 33A and 33B as well as Figure 34A and Figure 34B , the description will be given by adopting the circular configuration illustrated in FIG. 9 as the configuration of the signal extraction unit 65 of the pixel 51, but other configurations can also be adopted. Figure 9

[0463] Figure 33A is a plan view illustrating a first arrangement example of the voltage supply line.

[0464] In the first arrangement example, for a plurality of pixels 51 arranged two-dimensionally in a matrix shape, the voltage supply line 741-1 or 741-2 is arranged between (at the boundary of) two pixels adjacent to each other in the horizontal direction along the vertical direction.

[0465] On one side between the two signal extraction units 65 in each pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1. On the other side between the two signal extraction units 65 in the pixel 51, the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2.

[0466] ​​In the first arrangement example, two voltage supply lines 741-1 and 741-2 are arranged for two pixel columns, and thus the number of voltage supply lines 741 arranged in the pixel array unit 20 becomes substantially the same as the number of columns of the pixels 51.

[0467] Figure 33B is a plan view showing a second arrangement example of the voltage supply lines.

[0468] In the second arrangement example, two voltage supply lines 741-1 and 741-2 are provided along the vertical direction for one pixel column among the plurality of pixels 51 arranged in a matrix shape in two dimensions.

[0469] On one side between the two signal extraction units 65 in each pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1. On the other side between the two signal extraction units 65 in the pixel 51, the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2.

[0470] In the second arrangement example, two voltage supply lines 741-1 and 741-2 are wired for one pixel column, and thus four voltage supply lines 741 are arranged for two pixel columns. Thus, the number of voltage supply lines 741 arranged becomes approximately twice the number of columns of the pixels 51.

[0471] Figure 33A and Figure 33B Any of the arrangement examples in

[0472] In the first arrangement example shown in Figure 33A , it is possible to reduce the number of voltage supply lines 741-1 and 741-2 provided for the pixel array unit 20.

[0473] In the second arrangement example shown in Figure 33B , the number of provided lines is further increased compared to the first arrangement example, but the number of signal extraction units 65 connected to one voltage supply line 741 becomes half. Thus, it is possible to reduce the load of the wiring, and thus the second arrangement example is effective for a case of high-speed driving or a large total number of pixels in the pixel array unit 20.

[0474] Figure 34A is a plan view showing a third arrangement example of the voltage supply lines.

[0475] The third arrangement example is an example in which two voltage supply lines 741-1 and 741-2 are arranged for two pixel columns as in the first arrangement example in FIG. 8. Figure 33A

[0476] The third arrangement example differs from the first arrangement example in FIG. 8 in that the connection destinations of the signal extraction units 65-1 and 65-2 are different from each other between two pixels arranged in the vertical direction. Figure 33A

[0477] Specifically, for example, in the pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, but in the pixel 51 on the lower side or the upper side of the pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2 and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1.

[0478] FIG. 34B is a plan view showing a fourth arrangement example of voltage supply lines.

[0479] The fourth arrangement example is an example in which two voltage supply lines 741-1 and 741-2 are arranged for two pixel columns as in the second arrangement example in FIG. 9. FIG. 33B

[0480] The fourth arrangement example differs from the second arrangement example in FIG. 9 in that the connection destinations of the signal extraction units 65-1 and 65-2 are different from each other between two pixels arranged in the vertical direction. FIG. 33B

[0481] Specifically, for example, in the pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1, and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2, but in the pixel 51 on the lower side or the upper side of the pixel 51, the voltage supply line 741-1 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2 and the voltage supply line 741-2 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1.

[0482] In the third arrangement example shown in FIG. 10, it is possible to reduce the number of voltage supply lines 741-1 and 741-2 provided for the pixel array unit 20. FIG. 34A

[0483] In the third arrangement example shown in FIG. 10, it is possible to reduce the number of voltage supply lines 741-1 and 741-2 provided for the pixel array unit 20. FIG. 34B ​​​​​In the fourth arrangement example shown, the number of units is further increased compared to the third arrangement example, but the number of signal extraction units 65 connected to a single voltage supply line 741 is halved. Therefore, the wiring load can be reduced, making the fourth arrangement example effective for high-speed driving or situations where the total number of pixels in the pixel array unit 20 is large.

[0484] FIG. 34A and 34B Any example of an arrangement is a mirrored arrangement, where the connection destinations of two pixels that are adjacent to each other in the up-down (vertical) direction are mirror-symmetric.

[0485] like FIG. 35A As shown, in the periodic arrangement, the voltages applied to two signal extraction units 65 that are adjacent to each other and separated by a pixel boundary become different, thus causing charge exchange between adjacent pixels. Therefore, the charge transfer efficiency is better than that of the mirror arrangement, but the crosstalk characteristics of adjacent pixels are worse than those of the mirror arrangement.

[0486] On the other hand, such as FIG. 35B As shown, in the mirror arrangement, the voltages applied to the two signal extraction units 65 that are adjacent to each other and separated by a pixel boundary are the same, thus suppressing charge exchange between adjacent pixels. Therefore, the charge transfer efficiency is inferior to that of the periodic arrangement, but the crosstalk characteristics of adjacent pixels are better than those of the periodic arrangement.

[0487] <Cross-sectional structure of multiple pixels in the fourteenth embodiment>

[0488] In such FIG. 2 In the cross-sectional structure of the pixel shown, the multilayer wiring layer formed on the front surface side of the substrate 61 opposite to the light incident surface is omitted.

[0489] In the following text, cross-sectional views of multiple adjacent pixels are described with respect to the above embodiments without omitting multiple wiring layers.

[0490] first, FIG. 36 and FIG. 37 Show FIG. 28 A cross-sectional view of multiple pixels in the fourteenth embodiment shown.

[0491] FIG. 28 The fourteenth embodiment shown relates to a pixel configuration that includes a large-area reflective element 631 on the side of the substrate 61 opposite to the light incident surface.

[0492] FIG. 36 Corresponding to along FIG. 11 The cross-sectional view taken by line B-B' in the diagram, and FIG. 37 This corresponds to the cross-sectional view taken along line A-A'. Alternatively, it can be as follows: FIG. 36That shows a cross-sectional view taken along line C-C' in FIG. 17

[0493] As shown in FIG. 6, in the pixel 51, the oxide film 64 is formed at the center portion, and the signal extraction unit 65-1 and the signal extraction unit 65-2 are formed on both sides of the oxide film 64, respectively. FIG. 36

[0494] In the signal extraction unit 65-1, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 are formed so as to surround the periphery of the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 in a state in which the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 are centered. The P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-1 is arranged on the upper side (on-chip lens 62 side) of the P+ semiconductor region 73-1 and covers the P+ semiconductor region 73-1, and the N- semiconductor region 72-1 is arranged on the upper side (on-chip lens 62 side) of the N+ semiconductor region 71-1 and covers the N+ semiconductor region 71-1. In other words, the P+ semiconductor region 73-1 and the N+ semiconductor region 71-1 are arranged on the multilayer wiring layer 811 side within the substrate 61, and the N- semiconductor region 72-1 and the P- semiconductor region 74-1 are arranged on the on-chip lens 62 side within the substrate 61. In addition, an isolation portion 75-1 for isolating the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 from each other is formed between these regions by an oxide film or the like.

[0495] In the signal extraction unit 65-2, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 are formed so as to surround the periphery of the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 in a state in which the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 are centered. The P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are in contact with the multilayer wiring layer 811. The P- semiconductor region 74-2 is arranged on the upper side (on-chip lens 62 side) of the P+ semiconductor region 73-2 and covers the P+ semiconductor region 73-2, and the N- semiconductor region 72-2 is formed on the upper side (on-chip lens 62 side) of the N+ semiconductor region 71-2 and covers the N+ semiconductor region 71-2. In other words, the P+ semiconductor region 73-2 and the N+ semiconductor region 71-2 are arranged on the multilayer wiring layer 811 side within the substrate 61, and the N- semiconductor region 72-2 and the P- semiconductor region 74-2 are arranged on the on-chip lens 62 side within the substrate 61. In addition, an isolation portion 75-2 for isolating the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 from each other is also formed between these regions by an oxide film or the like.

[0496] ​​The oxide film 64 is also formed in a boundary region between adjacent pixels 51, that is, between the N+ semiconductor region 71-1 of the signal extraction unit 65-1 of a predetermined pixel 51 and the N+ semiconductor region 71-2 of the signal extraction unit 65-2 of a pixel 51 adjacent to the pixel 51.

[0497] The fixed charge film 66 is formed at an interface on the light incident surface side of the substrate 61 (the upper surface in FIG. 36 and FIG. 37 ).

[0498] As shown in FIG. 37 , when the on-chip lens 62 formed on the light incident surface side of the substrate 61 for each pixel is divided into a protruding portion 821 whose thickness uniformly protrudes over the entire surface of a region within a pixel and a curved portion 822 whose thickness differs in the height direction depending on the position within a pixel, the thickness of the protruding portion 821 is set to be smaller than the thickness of the curved portion 822. The greater the thickness of the protruding portion 821, the more obliquely incident light is easily reflected by the inter-pixel light shielding film 63. Therefore, when the thickness of the protruding portion 821 is set to be smaller, obliquely incident light can be received into the substrate 61. In addition, the greater the thickness of the curved portion 822, the more incident light is concentrated to the center of a pixel.

[0499] The multilayer wiring layer 811 is formed on the side of the substrate 61 opposite to the light incident surface side, in which the on-chip lens 62 is formed for each pixel. In other words, the substrate 61 as a semiconductor layer is disposed between the on-chip lens 62 and the multilayer wiring layer 811. The multilayer wiring layer 811 includes five metal films M1 to M5 and an interlayer insulating film 812 disposed between the metal films. Note that, in FIG. 36 , of the five metal films M1 to M5 of the multilayer wiring layer 811, the outermost metal film M5 exists at a position from which the metal film M5 cannot be observed, and therefore, the metal film M5 is not shown in FIG. 37 . However, the metal film M5 is shown in the cross-sectional view of FIG. 37 , which is a cross-sectional view seen from a direction different from that of FIG. 36 . FIG. 37

[0500] As shown in FIG. 31 , the pixel transistor Tr is formed in a pixel boundary region of an interface portion between the multilayer wiring layer 811 and the substrate 61. The pixel transistor Tr is any one of the transfer transistor 721, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 shown in FIG. 32 and FIG. 36 .

[0501] ​A power supply line 813 that supplies a power supply voltage, a voltage application wiring 814 that supplies a predetermined voltage to the P+ semiconductor region 73-1 or 73-2, and a reflection member 815 that is a member for reflecting incident light are included in the metal film M1 closest to the substrate 61 among the five layers of metal films M1 to M5 of the multilayer wiring layer 811. In the metal film M1, the reflection member 815 is formed in a region other than the power supply line 813 and the voltage application wiring 814, but the reference numerals are omitted to prevent the complexity of the drawing. The reflection member 815 is a dummy wiring for reflecting incident light, and corresponds to the reflection member 631 illustrated in FIG. 28 The reflection member 815 is formed in a region other than the power supply line 813 and the voltage application wiring 814 in the metal film M1 illustrated, but the reference numerals are omitted to prevent the complexity of the drawing. The reflection member 815 is a dummy wiring for reflecting incident light, and corresponds to the reflection member 631 illustrated in FIG. 28 The reflection member 815 is formed in a region other than the power supply line 813 and the voltage application wiring 814 in the metal film M1 illustrated, but the reference numerals are omitted to prevent the complexity of the drawing. The reflection member 815 is a dummy wiring for reflecting incident light, and corresponds to the reflection member 631 illustrated in FIG. 36 The reflection member 815 is formed in a region other than the power supply line 813 and the voltage application wiring 814 in the metal film M1 illustrated, but the reference numerals are omitted to prevent the complexity of the drawing. The reflection member 815 is a dummy wiring for reflecting incident light, and corresponds to the reflection member 631 illustrated in FIG. 36 The reflection member 815 is formed in a region other than the power supply line 813 and the voltage application wiring 814 in the metal film M1 illustrated, but the reference numerals are omitted to prevent the complexity of the drawing. The reflection member 815 is a dummy wiring for reflecting incident light, and corresponds to the reflection member 631 illustrated in

[0502] In addition, in the metal film M1, a charge extraction wiring (not illustrated in FIG. 33A ) that connects the N+ semiconductor region 71 and the transfer transistor 721 is formed to transfer the charge accumulated in the N+ semiconductor region 71 to the FD 722.

[0503] Note that, in this example, the reflection member 815 (the reflection member 631) and the charge extraction wiring are provided to be arranged in the same layer of the metal film M1, but are not limited to the arrangement in the same layer.

[0504] In the metal film M2 that is the second layer from the substrate 61 side, for example, a voltage application wiring 816 that is connected to the voltage application wiring 814 of the metal film M1, a control line 817 for transferring a drive signal TRG, a drive signal RST, a selection signal SEL, a drive signal FDG, and the like, a ground line, and the like are formed. In addition, the FD 722B and the additional capacitor 727A are formed in the metal film M2.

[0505] In the metal film M3 that is the third layer from the substrate 61 side, for example, the vertical signal line 29, a VSS wiring for shielding, and the like are formed.

[0506] In the metal film M4 and the metal film M5 that are the fourth and fifth layers from the substrate 61 side, for example, voltage supply lines 741-1 and 741-2 for applying a predetermined voltage MIX0 or MIX1 to the P+ semiconductor regions 73-1 and 73-2 (voltage application units of the signal extraction unit 65) FIG. 34A and 33B are formed. In addition, the voltage supply lines 741-1 and 741-2 are connected to the voltage application wiring 814 of the metal film M1.FIG. 38 and 34B ).

[0507] Note that the planar arrangement of the five-layer metal films M1 to M5 of the multilayer wiring layer 811 will be described later with reference to FIGS. 42 and 43.

[0508] <Cross-sectional configuration of a plurality of pixels of the ninth embodiment>

[0509] FIG. 22 is a cross-sectional view illustrating a pixel structure with respect to a plurality of pixels of the ninth embodiment illustrated in FIG. 41, in which the multilayer wiring layer is not omitted. FIG. 22

[0510] FIG. 36 The ninth embodiment illustrated in FIG. 41 is a pixel structure including an isolation region 441 that is obtained by forming an elongated groove (trench) of a predetermined depth from the rear surface (light incident surface) side of the substrate 61 at a pixel boundary portion within the substrate 61 and by embedding a light shielding film in the groove.

[0511] Other configurations including the signal extraction units 65-1 and 65-2, the five-layer metal films M1 to M5 of the multilayer wiring layer 811, and the like are similar to those of the configuration illustrated in FIG. 40. FIG. 39

[0512] <Cross-sectional configuration of a plurality of pixels of the first modification of the ninth embodiment>

[0513] FIG. 23 is a cross-sectional view illustrating a pixel structure with respect to a plurality of pixels of the first modification of the ninth embodiment illustrated in FIG. 42, in which the multilayer wiring layer is not omitted. FIG. 23

[0514] FIG. 36 The first modification of the ninth embodiment illustrated in FIG. 42 is a pixel structure including an isolation region 471 that penetrates the entire substrate 61 at a pixel boundary portion within the substrate 61.

[0515] Other configurations including the signal extraction units 65-1 and 65-2, the five-layer metal films M1 to M5 of the multilayer wiring layer 811, and the like are similar to those of the configuration illustrated in FIG. 40. FIG. 40

[0516] <Cross-sectional configuration of a plurality of pixels of the sixteenth embodiment>

[0517] FIG. 29 is a cross-sectional view illustrating a pixel structure with respect to a plurality of pixels of the sixteenth embodiment illustrated in FIG. 45, in which the multilayer wiring layer is not omitted. FIG. 29

[0518] FIG. 36 ​​​​​The configuration of the sixteenth embodiment shown includes a P-well region 671 at a center portion on the surface side (i.e., the inner side of the lower surface in the drawing) of the substrate 61 opposite the light incident surface. In addition, a separation portion 672-1 is formed between the P-well region 671 and the N+ semiconductor region 71-1 by an oxide film or the like. Similarly, a separation portion 672-2 is formed between the P-well region 671 and the N+ semiconductor region 71-2 by an oxide film or the like. The P-well region 671 is also formed at the pixel boundary portion at the lower surface of the substrate 61.

[0519] The other configurations including the signal extraction units 65-1 and 65-2, the five-layer metal films M1 to M5 of the multilayer wiring layer 811, and the like are similar to those of the configuration shown in FIG. 41 .

[0520] <Sectional Configuration of Multiple Pixels of the Tenth Embodiment>

[0521] FIG. 24 is a sectional view showing the pixel structure with respect to multiple pixels of the tenth embodiment shown in FIG. 24 .

[0522] In the pixel structure of the tenth embodiment shown in FIG. 36 , a substrate 501 having a larger substrate thickness is provided in place of the substrate 61.

[0523] The other configurations including the signal extraction units 65-1 and 65-2, the five-layer metal films M1 to M5 of the multilayer wiring layer 811, and the like are similar to those of the configuration shown in FIG. 42A to 42C .

[0524] <Planar Arrangement Example of Five-Layer Metal Films M1 to M5>

[0525] Next, planar arrangement examples of the five-layer metal films M1 to M5 of the multilayer wiring layer 811 shown in FIG. 36 to FIG. 41 and 43A and 43B will be described. FIG. 42A

[0526] FIG. 42B A planar arrangement example of the first-layer metal film M1 among the five-layer metal films M1 to M5 of the multilayer wiring layer 811 is shown.

[0527] FIG. 42C A planar arrangement example of the second-layer metal film M2 among the five-layer metal films M1 to M5 of the multilayer wiring layer 811 is shown.

[0528] FIG. 43A A planar arrangement example of the third-layer metal film M3 among the five-layer metal films M1 to M5 of the multilayer wiring layer 811 is shown.

[0529] FIG. 43B ​A planar arrangement example of the fourth layer metal film M4 among the five layer metal films M1 to M5 of the multilayer wiring layer 811 is shown.

[0530] FIG. 42A to 42C A planar arrangement example of the fifth layer metal film M5 among the five layer metal films M1 to M5 of the multilayer wiring layer 811 is shown.

[0531] Note that, FIG. 43A and FIG. 11 and 43B The region of the pixel 51 in FIG. 42A to 42C and the regions of the signal extraction units 65-1 and 65-2 having an octagonal shape as shown in

[0532] In FIG. 43A and FIG. 42A and 43B In the drawings, the vertical direction is the vertical direction of the pixel array unit 20, and the horizontal direction is the horizontal direction of the pixel array unit 20.

[0533] As shown in FIG. 42B , a reflection member 631 for reflecting infrared light is formed in the first layer metal film M1 of the multilayer wiring layer 811. In the region of the pixel 51, two reflection members 631 are formed for each of the signal extraction units 65-1 and 65-2, and the two reflection members 631 of the signal extraction unit 65-1 and the two reflection members 631 of the signal extraction unit 65-2 are formed symmetrically in the vertical direction.

[0534] In addition, in the horizontal direction, a pixel transistor wiring region 831 is arranged between the reflection members 631 of adjacent pixels 51. A wiring for connecting a pixel transistor Tr such as a transfer transistor 721, a reset transistor 723, an amplification transistor 724, or a selection transistor 725 is formed in the pixel transistor wiring region 831. The wiring of the pixel transistor Tr is formed symmetrically about the center line (not shown) of the two signal extraction units 65-1 and 65-2 in the vertical direction.

[0535] In addition, a wiring such as a ground line 832, a power supply line 833, and a ground line 834 is formed between the reflection members 631 of adjacent pixels 51. These wirings are formed symmetrically about the center line of the two signal extraction units 65-1 and 65-2 in the vertical direction.

[0536] As described above, in the first layer metal film M1, since the region of the signal extraction unit 65-1 side and the region of the signal extraction unit 65-2 side within the pixel are arranged symmetrically, the wiring load is adjusted uniformly between the signal extraction units 65-1 and 65-2. Therefore, the driving deviation of the signal extraction units 65-1 and 65-2 is reduced.

[0537] In the first layer metal film M1, since the large-area reflection member 631 is formed on the lower side of the signal extraction units 65-1 and 65-2 formed in the substrate 61, infrared light that has been incident into the substrate 61 through the on-chip lens 62 and has not been photoelectrically converted in the substrate 61 is reflected by the reflection member 631 and is incident into the substrate 61 again. Thus, the amount of infrared light that is photoelectrically converted inside the substrate 61 can be increased, and thus the quantum efficiency (QE), that is, the sensitivity of the pixel 51 with respect to infrared light can be improved.

[0538] On the other hand, in the first layer metal film M1, in a case where the light-blocking member 631' is arranged in the same region as the reflection member 631 in place of the reflection member 631, infrared light that has been incident into the substrate 61 from the light incident surface through the on-chip lens 62 and has not been photoelectrically converted in the substrate 61 can be suppressed from being scattered in the wiring layer and incident into a nearby pixel. Thus, it is possible to prevent light from being erroneously detected in the nearby pixel.

[0539] As shown in FIG. 8B, in the second layer metal film M2 of the multilayer wiring layer 811, a control line region 851 in which control lines 841 to 844 and the like for transmitting predetermined signals in the horizontal direction are formed is arranged at a position between the signal extraction units 65-1 and 65-2. The control lines 841 to 844 are, for example, lines for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, or a drive signal FDG. FIG. 42C

[0540] When the control line region 851 is arranged between the two signal extraction units 65, the influence on each of the signal extraction units 65-1 and 65-2 becomes uniform, and thus it is possible to reduce a driving deviation between the signal extraction units 65-1 and 65-2.

[0541] In addition, a capacitance region 852 in which the FD 722B or the additional capacitance 727A is formed is provided in a predetermined region of the second layer metal film M2 that is different from the control line region 851. In the capacitance region 852, the metal film M2 is patterned and formed in a comb shape to constitute the FD 722B or the additional capacitance 727A.

[0542] When the FD 722B or the additional capacitance 727A is arranged in the second layer metal film M2, the pattern of the FD 722B or the additional capacitance 727A can be freely set in the design according to the required wiring capacitance, and thus a design with high degrees of freedom can be achieved.

[0543] As shown in FIG. 8B, in the second layer metal film M2 of the multilayer wiring layer 811, a control line region 851 in which control lines 841 to 844 and the like for transmitting predetermined signals in the horizontal direction are formed is arranged at a position between the signal extraction units 65-1 and 65-2. The control lines 841 to 844 are, for example, lines for transmitting a drive signal TRG, a drive signal RST, a selection signal SEL, or a drive signal FDG. FIG. 43A ​As shown, at least a vertical signal line 29 for transmitting a pixel signal output from each pixel 51 to the column processing unit 23 is formed in the third layer metal film M3 of the multi-layer wiring layer 811. Three or more vertical signal lines 29 can be provided for one pixel column to improve the readout speed of the pixel signal. In addition, a shield wiring can be provided in addition to the vertical signal line 29 to reduce coupling capacitance.

[0544] In the fourth layer metal film M4 and the fifth layer metal film M5 of the multi-layer wiring layer 811, voltage supply lines 741-1 and 741-2 for applying a predetermined voltage MIXO or MIX1 to the P+ semiconductor regions 73-1 and 73-2 of the signal extraction unit 65 in the pixel 51 are formed.

[0545] FIG. 33A and 43B The metal film M4 and the metal film M5 shown represent an example in a case where the voltage supply lines 741 in the first arrangement example are employed. FIG. 36

[0546] The voltage supply line 741-1 of the metal film M4 is connected to the voltage application wiring 814 of the metal film M1 through the metal films M3 and M2 (for example, 814-1 and 814-2), and the voltage application wiring 814 is connected to the P+ semiconductor region 73-1 of the signal extraction unit 65-1 of the pixel 51. FIG. 36 Similarly, the voltage supply line 741-2 of the metal film M4 is connected to the voltage application wiring 814 of the metal film M1 through the metal films M3 and M2 (for example, 814-1 and 814-2), and the voltage application wiring 814 is connected to the P+ semiconductor region 73-2 of the signal extraction unit 65-2 of the pixel 51. FIG. 43A

[0547] The voltage supply lines 741-1 and 741-2 of the metal film M5 are connected to the tap driving unit 21 at the periphery of the pixel array unit 20. The voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 are connected to each other through a via (not shown) or the like at a predetermined position in the planar region where these two metal films exist. The predetermined voltage MIXO or MIX1 from the tap driving unit 21 is supplied to the voltage supply line 741-1 of the metal film M4 and the voltage supply line 741-1 of the metal film M5 after being transmitted through the voltage supply lines 741-1 and 741-2 of the metal film M5, and is supplied from these voltage supply lines 741-1 and 741-2 to the voltage application wiring 814 of the metal film M1 through the metal films M3 and M2.

[0548] When the light-receiving element 1 is provided as a back-illuminated CAPD sensor, for example, as shown in FIG. 43B and FIG. 44A to 44C ​​As shown, the voltage supply lines 741-1 and 741-2 for applying the predetermined voltage MIX0 or MIX1 to the signal extraction unit 65 of the pixel 51 can be wired in the vertical direction, that is, the wiring width and layout of the drive wiring can be freely designed. In addition, wiring suitable for high-speed driving or wiring taking into account load reduction can be realized.

[0549] <Example of planar arrangement of pixel transistor>

[0550] FIG. 42A is a plan view showing FIG. 44A the overlapping structure between the first layer metal film M1 and the polysilicon layer formed on the metal film M1 and forming the gate electrode of the pixel transistor Tr.

[0551] FIG. 44C is a plan view obtained by overlapping FIG. 44B the metal film M1 in FIG. 44B and the polysilicon layer in FIG. 44C is a plan view of only the polysilicon layer, and FIG. 44C is a plan view of only the metal film M1. FIG. 42A The plan view of the metal film M1 in FIG. 42A is the same as the plan view shown in

[0552] As described above with reference to FIG. 44B the pixel transistor wiring region 831 is formed between the reflection members 631 of each pixel.

[0553] For example, as shown in FIG. 44B the pixel transistor Tr corresponding to each signal extraction unit 65-1 and 65-2 is formed in the pixel transistor wiring region 831.

[0554] In FIG. 44C , with respect to the middle line (not shown) of the two signal extraction units 65-1 and 65-2, the gate electrodes of the reset transistors 723A and 723B, the transfer transistors 721A and 721B, the switching transistors 728A and 728B, the selection transistors 725A and 725B, and the amplification transistors 724A and 724B are formed in order from the side closer to the middle line.

[0555] The wiring of the pixel transistor Tr for connecting FIG. 45A to 45C the metal film M1 is formed symmetrically with respect to the middle line (not shown) of the two signal extraction units 65-1 and 65-2 in the vertical direction.

[0556] As described above, the plurality of pixel transistors Tr within the pixel transistor wiring region 831 are arranged in the region on the signal extraction unit 65-1 side and the region on the signal extraction unit 65-2 side in a symmetrical manner. Therefore, it is possible to reduce the driving deviation of the signal extraction units 65-1 and 65-2.

[0557] <Modification example of reflective member 631>

[0558] Next, a modification example of the reflective member 631 formed in the metal film M1 will be described with reference to FIG. 46A and FIG. 42A and 46B

[0559] In the above example, as shown in FIG. 45A , the large-area reflective member 631 is arranged in the peripheral region of the signal extraction unit 65 within the pixel 51.

[0560] On the contrary, for example, as shown in FIG. 45B , the reflective member 631 can be arranged in a lattice-shaped pattern. In this way, when the reflective member 631 is formed in a lattice-shaped pattern, the pattern anisotropy can be removed, and the XY anisotropy of the reflection ability can be reduced. In other words, when the reflective member 631 is formed in a lattice-shaped pattern, the reflection of the incident light toward the partial offset region is reduced, and the incident light is easily reflected equally. Therefore, the ranging accuracy is improved.

[0561] Alternatively, for example, as shown in FIG. 45B , the reflective member 631 can be arranged in a strip-shaped pattern. In this way, when the reflective member 631 is formed in a strip-shaped pattern, the pattern of the reflective member 631 can be used as a wiring capacitance, and thus a configuration that maximally expands the dynamic range can be achieved.

[0562] Note that FIG. 45C An example of a vertical stripe shape is shown, but a horizontal stripe shape is also possible.

[0563] Alternatively, for example, as shown in FIG. 46A , the reflective member 631 can be arranged only in the pixel center region, more specifically, only between the two signal extraction units 65. In this way, when the reflective member 631 is formed in the pixel center region without being formed at the pixel end portion, it is possible to suppress the component reflected to the adjacent pixel in the case of oblique light incidence, while the sensitivity improvement effect is obtained due to the reflective member 631 of the pixel center region, and thus a configuration that strengthens the crosstalk suppression can be achieved.

[0564] In addition, for example, as shown in FIG. 46A ​As shown, when a portion of the reflection member 631 is arranged in a comb shape in a pattern, a portion of the metal film M1 can be allocated to the wiring capacitance of the FD 722 or the additional capacitance 727. In FIG. 46B In the example shown in FIG. 8B, the comb shape within the regions 861 to 864 surrounded by solid lines constitutes at least a portion of the FD 722 or the additional capacitance 727. The FD 722 or the additional capacitance 727 can be provided arranged to be appropriately distributed on the metal film M1 and the metal film M2. The pattern of the metal film M1 can be arranged to be balanced with respect to the capacitance of the reflection member 631 and the FD 722 or the additional capacitance 727.

[0565] FIG. 45A to 45C The pattern of the metal film M1 in a case where the reflection member 631 is not arranged is shown. It is desirable to arrange the reflection member 631 to increase the amount of infrared light photoelectrically converted within the substrate 61 and improve the sensitivity of the pixel 51, but a configuration in which the reflection member 631 is not arranged can also be employed.

[0566] FIG. 46A In addition, the arrangement example of the reflection member 631 shown in FIG. 8A is also applicable in a similar manner to the light-shielding member 631'. FIG. 1 46B

[0567] The light-receiving element 1 in

[0568] FIG. 47A to FIG. 47C may employ the substrate configuration in any one of FIG. 47A

[0569] FIG. 47B An example in which the light-receiving element 1 is constituted by one semiconductor substrate 911 and a support substrate 912 located on the lower side of the semiconductor substrate 911 is shown.

[0570] In this case, a pixel array region 951 corresponding to the pixel array unit 20, a control circuit 952 for controlling each pixel of the pixel array region 951, and a logic circuit 953 including a signal processing circuit for processing a pixel signal are formed in the semiconductor substrate 911 on the upper side.

[0571] The control circuit 952 includes the tap driving unit 21, the vertical driving unit 22, the horizontal driving unit 24, and the like. The logic circuit 953 includes the column processing unit 23 for performing AD conversion processing of a pixel signal and a signal processing unit 31 for performing distance calculation processing in which a distance is calculated from the ratio of pixel signals acquired from two or more signal extraction units 65 within a pixel, calibration processing, and the like.

[0572] Alternatively, as shown in FIG. 47C ​​​As shown, the light-receiving element 1 can be configured as a structure consisting of a first semiconductor substrate 921 having a pixel array region 951 and a control circuit 952, and a second semiconductor substrate 922 having a logic circuit 953, stacked together. It should be noted that the first semiconductor substrate 921 and the second semiconductor substrate 922 are electrically connected to each other, for example, through vias or Cu-Cu metal bonding.

[0573] Or, such as FIG. 47C As shown, the light-receiving element 1 can be configured as a structure consisting of a first semiconductor substrate 931 having only a pixel array region 951 and a second semiconductor substrate 932 having a control unit for controlling each pixel and a signal processing circuit for processing pixel signals, stacked together. The control circuit and signal processing circuit are configured on a per-pixel basis or on a region of multiple pixels. The first semiconductor substrate 931 and the second semiconductor substrate 932 are electrically connected to each other, for example, through vias or Cu-Cu metal bonding.

[0574] As in FIG. 37 In the light-receiving element 1, by configuring the control circuit and signal processing circuit on a pixel-by-pixel or region-by-region basis, the optimal driving timing or gain can be set on a per-segment control basis, and optimized distance information can be obtained regardless of distance or reflectivity. Furthermore, distance information can be calculated by driving only a portion of the pixel array region 951 instead of the entire pixel array region 951, thus suppressing power consumption corresponding to the operating mode.

[0575] <Example of measures to deal with noise around pixel transistors>

[0576] However, as FIG. 37 As shown in the cross-sectional view, pixel transistors such as reset transistor 723, amplification transistor 724, and selection transistor 725 are arranged at the boundary portion of pixels 51 arranged in the horizontal direction in pixel array unit 20.

[0577] When explained in more detail FIG. 48 When arranging pixel transistors in the pixel boundary region as shown, such as FIG. 49A As shown, pixel transistors Tr such as reset transistor 723, amplification transistor 724 and selection transistor 725 are formed in P-well region 1011, wherein P-well region 1011 is formed on the front surface side of substrate 61.

[0578] The P-well region 1011 is formed so as to be spaced apart from the oxide film 64, which is, for example, a shallow trench isolation (STI) formed at the periphery of the N+ semiconductor region 71 of the signal extraction unit 65, at a predetermined interval in the planar direction. Also, an oxide film 1012 that also functions as a gate electrode insulating film of the pixel transistor Tr is formed at the interface on the front surface side of the substrate 61.

[0579] At this time, at the interface on the front surface side of the substrate 61, electrons are easily accumulated in a gap region 1013 between the oxide film 64 and the P-well region 1011 due to the electric potential obtained by the positive charges in the oxide film 1012. Therefore, in the absence of an electron discharge mechanism, the electrons overflow and diffuse, and thus the electrons are collected in the N-type semiconductor region and become noise.

[0580] Here, as shown in FIG. 10A, the P-well region 1021 can be extended so as to be in contact with the oxide film 64 adjacent to the P-well region 1021 in the planar direction, so that the gap region 1013 is not present at the interface on the front surface side of the substrate 61. Therefore, it is possible to prevent the accumulation of electrons in the gap region 1013 shown in FIG. 10B, and thus it is possible to suppress noise. The impurity concentration of the P-well region 1021 is set to be higher than the P-type semiconductor region 1022 in the substrate 61, which is a photoelectric conversion region. FIG. 48 FIG. 49B Alternatively, as shown in FIG. 10C, an oxide film 1032 formed at the periphery of the N+ semiconductor region 71 of the signal extraction unit 65 can be formed so as to extend up to the P-well region 1031 in the planar direction, so that the gap region 1013 is not present at the interface on the front surface side of the substrate 61. In this case, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 in the P-well region 1031 are element-isolated by an oxide film 1033. The oxide film 1033 is formed by the STI, for example, and can be formed by the same processing as the oxide film 1032.

[0581] Alternatively, as shown in FIG. 10C, an oxide film 1032 formed at the periphery of the N+ semiconductor region 71 of the signal extraction unit 65 can be formed so as to extend up to the P-well region 1031 in the planar direction, so that the gap region 1013 is not present at the interface on the front surface side of the substrate 61. In this case, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 in the P-well region 1031 are element-isolated by an oxide film 1033. The oxide film 1033 is formed by the STI, for example, and can be formed by the same processing as the oxide film 1032. FIG. 49A According to the configuration in FIGS. 10A and 10B, or the configuration in FIG. 10C, at the interface on the front surface side of the substrate 61, the insulating films (the oxide film 64 and the oxide film 1032) and the P-well regions (the P-well region 1021 and the P-well region 1031) in the boundary portion of the pixel are in contact with each other, and thus it is possible to remove the gap region 1013. Therefore, it is possible to prevent the accumulation of electrons and to suppress noise.

[0582] FIG. 49A 49B According to the configuration in FIGS. 10A and 10B, or the configuration in FIG. 10C, at the interface on the front surface side of the substrate 61, the insulating films (the oxide film 64 and the oxide film 1032) and the P-well regions (the P-well region 1021 and the P-well region 1031) in the boundary portion of the pixel are in contact with each other, and thus it is possible to remove the gap region 1013. Therefore, it is possible to prevent the accumulation of electrons and to suppress noise. FIG. 49B FIG. 50 The configuration in FIGS. 10A to 10C is applicable to any of the embodiments described in this specification.

[0583] ​​​​Alternatively, in a case where a configuration in which a gap region 1013 is reserved is employed, the accumulation of electrons occurring in the gap region 1013 can be suppressed by employing a configuration as shown in FIG. 51 or FIG. 50

[0584] FIG. 50 The arrangement of the oxide film 64, the P-well region 1011, and the gap region 1013 is shown in a plan view, in which two split-pixels 51 each including two signal extraction units 65-1 and 65-2 are two-dimensionally arranged.

[0585] In a case where the two-dimensionally arranged pixels are not isolated by an STI or a deep trench isolation (DTI), as shown in FIG. 51 , a plurality of P-well regions 1011 are formed in a column shape that is continuous with a plurality of pixels arranged in a column direction.

[0586] As a drain for discharging the charge, in an inactive pixel region 1052 arranged outside of an active pixel region 1051 of the pixel array unit 20, an N-type diffusion layer 1061 is provided in the gap region 1013 of the pixel 51, and electrons can be discharged to the N-type diffusion layer 1061. The N-type diffusion layer 1061 is formed on a front surface side interface of the substrate 61, and a GND (0 V) or a positive voltage is applied to the N-type diffusion layer 1061. The electrons generated in the gap region 1013 of the pixel 51 migrate in a vertical direction (a column direction) to the N-type diffusion layer 1061 in the inactive pixel region 1052, and are collected in the N-type diffusion layer 1061 common to the pixel column, and thus noise can be suppressed.

[0587] On the other hand, as shown in FIG. 50 , in a case where the pixels are isolated by a pixel isolation 1071 using an STI, a DTI, or the like, the N-type diffusion layer 1061 can be provided in the gap region 1013 of the pixel 51. Thus, the electrons generated in the gap region 1013 of the pixel 51 are discharged from the N-type diffusion layer 1061, and thus noise can be suppressed. FIG. 51 and FIG. 52 The configuration in and is applicable to any of the embodiments described in this specification.

[0588] <Noise at the periphery of the active pixel region>

[0589] Next, the discharge of the charge at the periphery of the active pixel region will be described.

[0590] For example, a light-shield pixel region in which a light-shield pixel is provided exists at an outer periphery portion adjacent to the active pixel region.

[0591] As shown in FIG. 53 ​As shown, in the light-shielded pixel 51X in the light-shielded pixel region, a signal extraction unit 65 and the like are formed in a similar manner to the pixel 51 in the effective pixel region. In addition, in the structure of the light-shielded pixel 51X in the light-shielded pixel region, the inter-pixel light-shield film 63 is formed on the entire surface of the pixel region, and thus light does not enter. In addition, in the light-shielded pixel 51X, a drive signal can not be applied.

[0592] On the other hand, the oblique light from the lens, the diffracted light from the inter-pixel light-shield film 63, and the reflected light from the multilayer wiring layer 811 are incident in the light-shielded pixel region adjacent to the effective pixel region, and generate photoelectrons. Because there is no discharge destination, the generated photoelectrons accumulate in the light-shielded pixel region, diffuse to the effective pixel region due to a concentration gradient, and mix with signal charges. Thus, the photoelectrons become noise. The noise around the effective pixel region periphery becomes so-called frame unevenness.

[0593] Here, as a countermeasure against the noise that occurs around the effective pixel region, in the light-receiving element 1, FIG. 53 The charge discharge region 1101 in any one of A to D of the present embodiment can be provided at an outer periphery of the effective pixel region 1051.

[0594] FIG. 53 A to D of the present embodiment are plan views that show configuration examples of the charge discharge region 1101 arranged at the outer periphery of the effective pixel region 1051.

[0595] In FIG. 53 In any one of A to D of the present embodiment, the charge discharge region 1101 is provided at the outer periphery of the effective pixel region 1051 arranged at the center portion of the substrate 61, and the OPB region 1102 is provided outside the charge discharge region 1101. The charge discharge region 1101 is a hatched region between the inner dotted rectangular region and the outer dotted rectangular region. The OPB region 1102 is a region in which the inter-pixel light-shield film 63 is formed on the entire surface of the region, and in which an OPB pixel that operates in a similar manner to the pixel 51 in the effective pixel region to detect a black level signal is arranged. In FIG. 53 In A to D of the present embodiment, the gray region indicates a region in which the inter-pixel light-shield film 63 is formed and thus is light-shielded.

[0596] FIG. 53The charge discharge region 1101 in A includes an open pixel region 1121 provided with open pixels and a light shielding pixel region 1122 provided with light shielding pixels 51X. The open pixels in the open pixel region 1121 are pixels having the same pixel structure as the pixels 51 in the effective pixel region 1051 and performing predetermined operations. The light shielding pixels 51X of the light shielding pixel region 1122 are pixels having the same pixel structure as the pixels 51 in the effective pixel region 1051 and performing predetermined operations, except that the interpixel light shielding film 63 is formed on the entire surface of the pixel region.

[0597] The open pixel region 1121 includes a pixel column or a pixel row of one or a plurality of pixels in each column or each row of the four edges of the outer periphery of the effective pixel region 1051. The light shielding pixel region 1122 also includes a pixel column or a pixel row of one or a plurality of pixels in each column or each row of the four edges of the outer periphery of the open pixel region 1121.

[0598] FIG. 54 The charge discharge region 1101 in B includes a light shielding pixel region 1122 provided with light shielding pixels 51X and an N-type region 1123 provided with an N-type diffusion layer.

[0599] FIG. 53 is a cross-sectional view when the charge discharge region 1101 includes the light shielding pixel region 1122 and the N-type region 1123.

[0600] The entire surface of the N-type region 1123 is shielded by the interpixel light shielding film 63, and in the N-type region 1123, an N-type diffusion layer 1131 as a high concentration N-type semiconductor region is formed in the P-type semiconductor region 1022 of the substrate 61 in place of the signal extraction unit 65. A 0V voltage or a positive voltage is applied to the N-type diffusion layer 1131 from the metal film M1 of the multilayer wiring 811 all the time or intermittently. For example, the N-type diffusion layer 1131 can be formed at the entire P-type semiconductor region 1022 in the N-type region 1123 in a substantially continuous annular shape in a plan view. Alternatively, the N-type diffusion layer 1131 can be partially formed at the P-type semiconductor region 1022 in the N-type region 1123, and a plurality of N-type diffusion layers 1131 can be arranged to be scattered in a substantially annular form in a plan view.

[0601] Referring again to FIG. 53 B, the light shielding pixel region 1122 includes a pixel column or a pixel row of one or a plurality of pixels in each row or each column of the four edges of the outer periphery of the effective pixel region 1051. The N-type region 1123 has a predetermined column width or row width in each column or each row of the four edges of the outer periphery of the light shielding pixel region 1122.

[0602] FIG. 53The charge discharge region 1101 in C includes a light-shielding pixel region 1122 in which light-shielding pixels are provided. The light-shielding pixel region 1122 includes one or more pixel columns or pixel rows of pixels in each column or each row of the four sides of the outer periphery of the effective pixel region 1051.

[0603] FIG. 53 The charge discharge region 1101 in D includes an opening pixel region 1121 in which opening pixels are provided and an N-type region 1123 in which an N-type diffusion layer is provided.

[0604] The predetermined operation performed by the opening pixels in the opening pixel region 1121 and the light-shielding pixels 51X in the light-shielding pixel region 1122 can include an operation of applying a positive voltage to the N-type semiconductor region of the pixel continuously or intermittently, and it is desirable that the operation is an operation of applying a drive signal to the pixel transistor, the P-type semiconductor region, or the N-type semiconductor region in accordance with the timing of the pixel 51 as in the operation of the pixel 51 in the effective pixel region 1051.

[0605] FIG. 53 The configuration examples of the charge discharge region 1101 illustrated in A to D are merely illustrative and are not limited thereto. The charge discharge region 1101 can have a configuration including any one of an opening pixel for performing a predetermined operation, a light-shielding pixel for performing a predetermined operation, and an N-type region including an N-type diffusion layer to which 0V or a positive voltage is applied continuously or intermittently. Thus, for example, the opening pixels, the light-shielding pixels, and the N-type regions can be mixed in one pixel column or pixel row, or different kinds of opening pixels, light-shielding pixels, and N-type regions can be arranged in the pixel rows or pixel columns of the four sides of the periphery of the effective pixel region.

[0606] As described above, when the charge discharge region 1101 is provided at the outer periphery of the effective pixel region 1051, accumulation of electrons in a region other than the effective pixel region 1051 can be suppressed. Thus, noise that occurs when photocharges diffused from the outside of the effective pixel region 1051 are added to the signal charges can be suppressed.

[0607] In addition, when the charge discharge region 1101 is arranged in front of the OPB region 1102, photoelectrons generated in the light-shielding region on the outside of the effective pixel region 1051 can be prevented from diffusing into the OPB region 1102, and thus noise can be prevented from being added to the black level signal. FIG. 55A The configurations illustrated in A to D are applicable to any of the embodiments described in this specification.

[0608] <Eighteenth Embodiment>

[0609] Next, reference will be made to FIG. 55A and 55BThe current flow in the case where the pixel transistor is arranged in the substrate 61 including the photoelectric conversion region is described.

[0610] In the pixel 51, for example, when a positive voltage of 1.5 V and a voltage of 0 V are applied to the P+ semiconductor regions 73 of the two signal extraction units 65, respectively, an electric field is generated between the two P+ semiconductor regions 73, and a current flows from the P+ semiconductor region 73 to which the voltage of 1.5 V is applied to the P+ semiconductor region 73 to which the voltage of 0 V is applied. However, the P-well region 1011 formed at the pixel boundary portion is also set to GND (0 V), and thus, as shown in FIG. 10B, a current flows from the P+ semiconductor region 73 to which the voltage of 1.5 V is applied to the P-well region 1011 in addition to the current flow between the two signal extraction units 65. FIG. 55B

[0611] FIG. 42A is a plan view showing the arrangement of the pixel transistor wiring region 831 shown in FIG. 10A. FIG. 55B

[0612] The area of the signal extraction unit 65 can be reduced by layout change. In contrast, the area of the pixel transistor wiring region 831 is determined by the occupied area of one pixel transistor, the number of pixel transistors, and the wiring area, and thus it is difficult to reduce the area only by studying the layout design. Therefore, when it is desired to reduce the area of the pixel 51, the area of the pixel transistor wiring region 831 becomes a major constraint factor. It is necessary to reduce the pixel size while maintaining the optical size of the sensor to achieve high resolution, but the area of the pixel transistor wiring region 831 becomes a constraint. In addition, when the area of the pixel 51 is reduced while maintaining the area of the pixel transistor wiring region 831, as shown by the dotted arrow in FIG. 10B, the path of the current flowing into the pixel transistor wiring region 831 is shortened, and thus the resistance is reduced, and the current is increased. Therefore, the reduction of the area of the pixel 51 results in an increase in power consumption. FIG. 56

[0613] <Configuration Example of Pixel>

[0614] Here, as shown in FIG. 11B, a configuration in which the light receiving element 1 is provided in a stacked structure in which two substrates are stacked, and all the pixel transistors are arranged in a substrate different from the substrate including the photoelectric conversion region can be employed. FIG. 56

[0615] FIG. 56 is a cross-sectional view of a pixel according to the eighteenth embodiment.

[0616] FIG. 36 is a cross-sectional view showing a plurality of pixels, and as in FIG. 12A, corresponds to the line B-B' in FIG. 10A. FIG. 11 FIG. 56 is a cross-sectional view showing a plurality of pixels, and as in FIG. 12A, corresponds to the line B-B' in FIG. 10A.​​​​​

[0617] In FIG. 36 the same reference characters are given to portions corresponding to the cross-sectional view of the plurality of pixels of the fourteenth embodiment according to FIG. 56 , and the description thereof is appropriately omitted.

[0618] In FIG. 36 the eighteenth embodiment, the light-receiving element 1 is configured by two substrates of a laminated substrate 1201 and a substrate 1211. The substrate 1201 corresponds to the substrate 61 in the fourteenth embodiment according to FIG. 56 , and is configured by, for example, a silicon substrate including a P-type semiconductor region 1204 as a photoelectric conversion region, or the like. The substrate 1211 is also configured by a silicon substrate or the like.

[0619] Note that, in addition to the silicon substrate, the substrate 1201 including the photoelectric conversion region can be configured by, for example, a compound semiconductor such as Ga-As, InP, and GaSb, a narrow band gap semiconductor such as Ge, or a glass substrate or a plastic substrate coated with an organic photoelectric conversion film. In the case where the substrate 1201 is configured by a compound semiconductor, it is expected that the quantum efficiency is improved due to a direct transition type band structure, the sensitivity is improved, and the sensor height is reduced due to a reduction in the substrate thickness. In addition, the mobility of an electron is high, and thus the electron collection efficiency can be improved. In addition, the mobility of a hole is low, and thus the power consumption can be reduced. In the case where the substrate 1201 is configured by a narrow band gap semiconductor, it is expected that the quantum efficiency in the near-infrared region is improved, and the sensitivity is improved due to the narrow band gap.

[0620] The substrate 1201 and the substrate 1211 are joined in a state where the wiring layer 1202 of the substrate 1201 and the wiring layer 1212 of the substrate 1211 face each other. In addition, the metal wiring 1203 of the wiring layer 1202 on the substrate 1201 side and the metal wiring 1213 of the wiring layer 1212 on the substrate 1211 side are electrically connected to each other by, for example, Cu-Cu bonding. Note that the electrical connection between the wiring layers is not limited to Cu-Cu bonding, and examples thereof include a same kind metal bonding such as Au-Au bonding and Al-Al bonding, a different kind metal bonding such as Cu-Au bonding, Cu-Al bonding, and Au-Al bonding, and the like. In addition, the reflection member 631 of the fourteenth embodiment or the light-shielding member 631' of the fifteenth embodiment can also be provided in either one of the wiring layer 1202 of the substrate 1201 and the wiring layer 1212 of the substrate 1211.

[0621] The substrate 1201 including the photoelectric conversion region is different from the substrate 61 of the first to seventeenth embodiments in that all of the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are not formed in the substrate 1201.

[0622] In FIG. 56 In the eighteenth embodiment shown in FIG. 12A, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed on the lower side of the substrate 1211 side in the drawing. In FIG. 11 In the eighteenth embodiment shown in FIG. 12A, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed on the lower side of the substrate 1211 side in the drawing. In

[0623] An insulating film (oxide film) 1214 that also functions as a gate electrode insulating film of the pixel transistor is formed between the substrate 1211 and the wiring layer 1212.

[0624] Therefore, although not shown in the drawing, when the pixel according to the eighteenth embodiment is observed in a cross-sectional view corresponding to the line A-A' in FIG. 37 In the eighteenth embodiment shown in FIG. 12A, the pixel transistors Tr such as the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed on the lower side of the substrate 1211 side in the drawing. In FIG. 31 The pixel transistors Tr formed at the pixel boundary portion in

[0625] When the elements arranged in each of the substrate 1201 and the substrate 1211 are explained by using the equivalent circuit of the pixel 51 shown in FIG. 57 As shown in FIG. 47A to 47C the P+ semiconductor region 73 as the voltage application unit and the N+ semiconductor region 71 as the charge detection unit are formed in the substrate 1201, and the transfer transistor 721, the FD 722, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed in the substrate 1211.

[0626] When the light-receiving element 1 according to the eighteenth embodiment is explained with reference to FIG. 58 As shown in FIG. 47C the light-receiving element 1 is constituted by laminating the substrate 1201 and the substrate 1211.

[0627] In the pixel array region 951 shown in FIG. 47C the transfer transistor 721, the FD 722, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are formed in the pixel array region 1231 of the substrate 1201.

[0628] The transfer transistor 721, the FD 722, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 of each pixel of the pixel array unit 20 are formed in the region control circuit 1232 of the substrate 1211 in addition to FIG. 1 the region control circuit 954 shown in FIG. 59The tap driving unit 21, the vertical driving unit 22, the column processing unit 23, the horizontal driving unit 24, the system control unit 25, the signal processing unit 31, and the data storage unit 32 shown are also formed in the substrate 1211.

[0629] FIG. 59 is a plan view showing the MIX junctions between the substrate 1201 and the substrate 1211 as the electrical junctions for transmitting and receiving the voltage MIX and the DET junctions between the substrate 1201 and the substrate 1211 as the electrical junctions for transmitting and receiving the signal charge DET. Note that in FIG. 59 , the reference numerals of the MIX junctions 1251 and the DET junctions 1252 are omitted to prevent the complication of the drawing.

[0630] As shown in FIG. 60 , for example, the MIX junctions 1251 for supplying the voltage MIX and the DET junctions 1252 for acquiring the signal charge DET are provided for each pixel 51. In this case, the voltage MIX and the signal charge DET are transmitted and received between the substrate 1201 and the substrate 1211 in units of pixels.

[0631] Alternatively, as shown in FIG. 60 , the DET junctions 1252 for acquiring the signal charge DET are provided in the pixel region in units of pixels, but the MIX junctions 1251 for supplying the voltage MIX can be formed in a peripheral portion 1261 outside the pixel array unit 20. In the peripheral portion 1261, the voltage MIX supplied from the substrate 1211 is supplied to the P+ semiconductor region 73 as the voltage application unit of the pixel 51 through a voltage supply line 1253 arranged in the vertical direction of the substrate 1201. As described above, the MIX junctions 1251 for supplying the voltage MIX are provided to be shared by a plurality of pixels, and thus the number of MIX junctions 1251 in the entire substrate can be reduced, and the reduction of the pixel size or the chip size becomes easy.

[0632] Note that FIG. 55A the example in is an example in which the voltage supply line 1253 is arranged in the vertical direction and provided to be shared in the pixel column, but the voltage supply line 1253 can be arranged in the horizontal direction and can be provided to be shared in the pixel row.

[0633] Further, in the eighteenth embodiment, an example in which the electrical connection between the substrate 1201 and the substrate 1211 is provided to be electrically connected by the Cu-Cu junction has been described, but other electrical connection methods such as a through chip via (TCV), a bump junction using a micro bump, or the like can also be used.

[0634] According to an eighteenth embodiment, the light-receiving element 1 is constituted by a laminated structure of the substrate 1201 and the substrate 1211, and all of the pixel transistors for performing a readout operation of the signal charge DET of the N+ semiconductor region 71 as the charge detection unit, that is, the transfer transistor 721, the reset transistor 723, the amplification transistor 724, and the selection transistor 725 are arranged in the substrate 1211 different from the substrate 1201 including the P-type semiconductor region 1204 of the outside photoelectric conversion region. Therefore, the problems described with reference to FIG. 61 and 55B can be solved.

[0635] That is, the area of the pixel 51 can be reduced regardless of the area of the pixel transistor wiring region 831, and high resolution can be achieved without changing the optical size. In addition, an increase in current from the signal extraction unit 65 to the pixel transistor wiring region 831 is avoided, and thus current consumption can be reduced.

[0636] <Nineteenth Embodiment>

[0637] Next, the nineteenth embodiment will be described.

[0638] The potential of the P+ semiconductor region 73 or the P- semiconductor region 74 as the voltage application unit needs to be enhanced to improve the charge separation efficiency Cmod of the CAPD sensor. In particular, in a case where long-wavelength light such as infrared light needs to be detected with high sensitivity, as FIG. 62A indicated, the P- semiconductor region 74 needs to be widened to a deep position of the semiconductor layer. Or a positive voltage applied to a voltage VA2 higher than the voltage VA1 is increased. In this case, since the low resistance between the voltage application units, the current Imix can flow, and thus an increase in current consumption becomes a problem. In addition, in a case where the pixel size is miniaturized to improve the resolution, the distance between the voltage application units is shortened, and thus the resistance is reduced. Therefore, an increase in current consumption becomes a problem.

[0639] <First Configuration Example of Nineteenth Embodiment>

[0640] FIG. 62B is a plan view of a pixel according to the first configuration example of the nineteenth embodiment, and FIG. 62A is a cross-sectional view of a pixel according to the first configuration example of the nineteenth embodiment.

[0641] FIG. 62B is a plan view taken along the line B-B' in FIG. 62B , and FIG. 62A is a cross-sectional view taken along the line A-A' in FIG. 62A .

[0642] Note that, in FIG. 62A and62B In this drawing, only the portion formed in the substrate 61 of pixel 51 is shown, and for example, the on-chip lens 62 formed on the light incident surface side, the multilayer wiring layer 811 formed on the side opposite to the light incident surface, etc., are omitted in the drawing. The portions not shown can be configured in a similar manner to the embodiments described above. For example, the reflective member 631 or the light-shielding member 631' can be provided in the multilayer wiring layer 811 opposite to the light incident surface.

[0643] In the first construction example of the nineteenth embodiment, electrode unit 1311-1, which serves as a voltage application unit for applying a predetermined voltage MIX0, and electrode unit 1311-2, which serves as a voltage application unit for applying a predetermined voltage MIX1, are formed at predetermined positions in the P-type semiconductor region 1301.

[0644] The electrode unit 1311-1 includes an embedded portion 1311A-1 embedded in the P-type semiconductor region 1301 of the substrate 61 and a protrusion 1311B-1 protruding to the upper side of the first surface 1321 of the substrate 61.

[0645] Similarly, electrode unit 1311-2 includes an embedding portion 1311A-2 embedded in the P-type semiconductor region 1301 of substrate 61 and a protrusion 1311B-2 protruding to the upper side of the first surface 1321 of substrate 61. For example, electrode units 1311-1 and 1311-2 are formed of metallic materials such as tungsten (W), aluminum (Al) and copper (Cu), silicon or conductive materials such as polycrystalline silicon.

[0646] like FIG. 62B As shown, electrode units 1311-1 (with its embedded portion 1311A-1) and 1311-2 (with its embedded portion 1311A-2) having a circular planar shape are arranged in a point-symmetric manner with the center point of the pixel set as the symmetric point.

[0647] An N+ semiconductor region 1312-1 serving as a charge detection unit is formed on the outer periphery (periphery) of the electrode unit 1311-1, and an insulating film 1313-1 and a hole concentration enhancement layer 1314-1 are inserted between the electrode unit 1311-1 and the N+ semiconductor region 1312-1.

[0648] Similarly, an N+ semiconductor region 1312-2 serving as a charge detection unit is formed on the outer periphery (periphery) of the electrode unit 1311-2, and an insulating film 1313-2 and a hole concentration enhancement layer 1314-2 are inserted between the electrode unit 1311-2 and the N+ semiconductor region 1312-2.

[0649] The electrode unit 1311-1 and the N+ semiconductor region 1312-1 constitute a signal extraction unit 65-1, and the electrode unit 1311-2 and the N+ semiconductor region 1312-2 constitute a signal extraction unit 65-2.

[0650] Inside the substrate 61, as shown in FIG. 13A, the electrode unit 1311-1 is covered with an insulating film 1313-1, and the insulating film 1313-1 is covered with a hole concentration enhancement layer 1314-1. The same applies to the relationship among the electrode unit 1311-2, the insulating film 1313-2, and the hole concentration enhancement layer 1314-2. FIG. 63A

[0651] For example, the insulating films 1313-1 and 1313-2 are composed of an oxide film (SiO2) and are formed in the same process as the insulating film 1322 formed on the first surface 1321 of the substrate 61. Note that the insulating film 1332 is also formed on the second surface 1331 of the substrate 61 opposite the first surface 1321.

[0652] The hole concentration enhancement layers 1314-1 and 1314-2 are composed of a P-type semiconductor region and can be formed, for example, by an ion implantation method, a solid phase diffusion method, a plasma doping method, or the like.

[0653] Hereinafter, without particularly distinguishing the electrode unit 1311-1 from the electrode unit 1311-2, these units are also simply referred to as the electrode unit 1311, and without particularly distinguishing the N+ semiconductor region 1312-1 from the N+ semiconductor region 1312-2, these regions are also simply referred to as the N+ semiconductor region 1312.

[0654] In addition, without particularly distinguishing the hole concentration enhancement layer 1314-1 from the hole concentration enhancement layer 1314-2, these layers are also simply referred to as the hole concentration enhancement layer 1314, and without particularly distinguishing the insulating film 1313-1 from the insulating film 1313-2, these layers are also simply referred to as the insulating film 1313.

[0655] ​The electrode unit 1311, the insulating film 1313, and the hole concentration enhancement layer 1314 can be formed in the following process. First, the P-type semiconductor region 1301 of the substrate 61 is etched from the first surface 1321 side to form a groove up to a predetermined depth. Next, the hole concentration enhancement layer 1314 is formed on the inner periphery of the formed groove by an ion implantation method, a solid phase diffusion method, a plasma doping method, or the like, and then the insulating film 1313 is formed. Next, a conductive material is embedded in the insulating film 1313 to form an embedded portion 1311A. Then, a conductive material such as a metal material is formed on the entire surface of the first surface 1321 of the substrate 61, and only the upper portion of the electrode unit 1311 is left by etching, thereby forming a protruding portion 1311B-1.

[0656] The depth of the electrode unit 1311 is set to be at least deeper than the N+ semiconductor region 1312 as the charge detection unit, and it is desirable to set the depth to be deeper than about half the thickness of the substrate 61.

[0657] The pixel 51 according to the first configuration example of the nineteenth embodiment forms a groove in the depth direction of the substrate 61, and embeds a conductive material in the groove to form the electrode unit 1311. Due to the electrode unit 1311, the charge distribution effect of the electric charge photoelectrically converted in a wide area in the depth direction of the substrate 61 is obtained, and thus it is possible to improve the charge separation efficiency Cmod with respect to long-wavelength light.

[0658] In addition, due to the structure in which the outer periphery portion of the electrode unit 1311 is covered with the insulating film 1313, the current flowing between the voltage application units is suppressed, and thus it is possible to reduce the current consumption. In addition, in the case of comparison with the same current consumption, it is possible to apply a high voltage to the voltage application units. In addition, even when the distance between the voltage application units is shortened, it is possible to suppress the current consumption, and thus it is possible to realize high resolution by reducing the pixel size and increasing the number of pixels.

[0659] Note that, in the first configuration example of the nineteenth embodiment, the protruding portion 1311B of the electrode unit 1311 can be omitted, but when the protruding portion 1311B is provided, the electric field in the direction perpendicular to the substrate 61 becomes strong, and thus it is easy to collect electric charges.

[0660] Further, in the case where it is desirable to improve the modulation degree by applying a voltage and to enhance the charge separation efficiency Cmod, the hole concentration enhancement layer 1314 can be omitted. In the case where the hole concentration enhancement layer 1314 is provided, it is possible to suppress the generation of electrons due to damage or contaminants when etching is performed to form a groove.

[0661] In the first configuration example of the nineteenth embodiment, the first surface 1321 or the second surface 1331 of the substrate 61 can be provided as a light incident surface, and can be either a back-illuminated type or a front-illuminated type, but the back-illuminated type is more desirable.

[0662] <Second configuration example of the nineteenth embodiment>

[0663] FIG. 63B is a plan view of a pixel according to the second configuration example of the nineteenth embodiment, and FIG. 63A is a cross-sectional view of a pixel according to the second configuration example of the nineteenth embodiment.

[0664] FIG. 63B is a plan view taken along the line B-B' in FIG. 63B , and FIG. 63A is a cross-sectional view taken along the line A-A' in FIG. 63A .

[0665] Note that, in the second configuration example in FIG. 63A and 63B , the same reference numerals are given to portions corresponding to FIG. 62, and the portions different from the first configuration example in FIGS. 62 and 63 will be mainly described, and the description of the same portions will be omitted as appropriate.

[0666] FIG. 11 and 63B , the difference is that the embedded portion 1311A of the electrode unit 1311 penetrates the substrate 61 that is a semiconductor layer, and the other configurations are the same. The embedded portion 1311A of the electrode unit 1311 is formed in a range from the first surface 1321 to the second surface 1331 of the substrate 61, and the insulating film 1313 and the hole concentration enhancement layer 1314 are also formed at the outer peripheral portion of the electrode unit 1311. As for the second surface 1331 at the side where the N+ semiconductor region 1312 that is a charge detection unit is not formed, the entire surface thereof is covered with the insulating film 1332.

[0667] As in the second configuration example, the embedded portion 1311A of the electrode unit 1311 that is a voltage application unit can be configured to penetrate the substrate 61. Even in this case, the charge distribution effect of the charges photoelectrically converted in a wide area in the depth direction of the substrate 61 is obtained, and thus the charge separation efficiency Cmod in the case of long-wavelength light can be improved.

[0668] In addition, since the outer peripheral portion of the electrode unit 1311 is covered with the insulating film 1313, the current flowing between the voltage application units is suppressed, and thus the current consumption can be reduced. In addition, in the case of comparison with the same current consumption, a high voltage can be applied to the voltage application units. In addition, even when the distance between the voltage application units is shortened, the current consumption can be suppressed, and thus high resolution can be achieved by reducing the pixel size and increasing the number of pixels.

[0669] In the second configuration example of the nineteenth embodiment, the first surface 1321 or the second surface 1331 of the substrate 61 can be provided as a light incident surface, and can be a back-illuminated type or a front-illuminated type, but the back-illuminated type is more desirable.

[0670] <Other examples of planar shape>

[0671] In the first and second configuration examples of the nineteenth embodiment, the planar shape of the electrode unit 1311 as the voltage application unit and the N+ semiconductor region 1312 as the charge detection unit is provided as a circular shape.

[0672] However, the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is not limited to a circular shape, and can be a shape such as an octagonal shape as shown in FIG. 12 , a rectangular shape as shown in FIG. 17 , and a square, and the like. In addition, the number of signal extraction units 65 (tapping portions) arranged in one pixel is not limited to two, and can be, for example, four as shown in FIG. 64A to 64C .

[0673] FIG. 62B is a plan view corresponding to the line B-B' in FIG. 64A , and shows an example in which the number of signal extraction units 65 is two and the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 constituting each signal extraction unit 65 is provided as a shape different from a circular shape.

[0674] FIG. 64A shows an example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a vertically elongated rectangular shape that is elongated in the vertical direction.

[0675] In FIG. 64BIn this configuration, electrode units 1311-1 and 1311-2 are arranged in a point-symmetrical manner, with the center point of the pixel set as the symmetrical point. Furthermore, electrode units 1311-1 and 1311-2 are arranged opposite each other. The shape and position of the insulating film 1313, hole concentration enhancement layer 1314, and N+ semiconductor region 1312 formed on the outer periphery of electrode unit 1311 are similar to those of electrode unit 1311.

[0676] FIG. 64C An example is shown in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is L-shaped.

[0677] FIG. 64B An example is shown in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is comb-shaped.

[0678] exist FIG. 65A to 65C and 64C In this configuration, electrode units 1311-1 and 1311-2 are arranged in a point-symmetrical manner, with the center point of the pixel set as the symmetrical point. Furthermore, electrode units 1311-1 and 1311-2 are arranged opposite each other. The shape and position of the insulating film 1313, hole concentration enhancement layer 1314, and N+ semiconductor region 1312 formed on the outer periphery of electrode unit 1311 are similar to those of electrode unit 1311.

[0679] FIG. 62B It corresponds to FIG. 65A The diagram shows a planar view of line B-B', and illustrates an example in which the number of signal extraction units 65 is four and the planar shape of the electrode unit 1311 and N+ semiconductor region 1312 constituting each signal extraction unit 65 is set to a shape other than a circle.

[0680] FIG. 65A An example is shown in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is an elongated vertical rectangle in the vertical direction.

[0681] exist FIG. 65A In the design, vertically elongated electrode units 1311-1 to 1311-4 are arranged at predetermined intervals in the horizontal direction and in a point-symmetric manner, wherein the center point of the pixel is set as the symmetry point. In addition, electrode units 1311-1 and 1311-2 and electrode units 1311-3 and 1311-4 are arranged opposite to each other.

[0682] The electrode unit 1311-1 and the electrode unit 1311-3 are electrically connected to each other through a wiring 1351, and constitute a voltage application unit to which a voltage MIX0 is applied, of a signal extraction unit 65-1 (first tapping portion TA), for example. The N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected to each other through a wiring 1352, and constitute a charge detection unit for detecting a signal charge DET1, of the signal extraction unit 65-1 (first tapping portion TA).

[0683] The electrode unit 1311-2 and the electrode unit 1311-4 are electrically connected to each other through a wiring 1353, and constitute a voltage application unit to which a voltage MIX1 is applied, of a signal extraction unit 65-2 (second tapping portion TB), for example. The N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected to each other through a wiring 1354, and constitute a charge detection unit for detecting a signal charge DET2, of the signal extraction unit 65-2 (second tapping portion TB).

[0684] Thus, in other words, in the arrangement of FIG. 65B the group of the voltage application unit and the charge detection unit of the signal extraction unit 65-1 having a rectangular planar shape and the group of the voltage application unit and the charge detection unit of the signal extraction unit 65-2 having a rectangular planar shape are alternately arranged in the horizontal direction.

[0685] The shape and positional relationship of the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are similar to the above-described shape and positional relationship.

[0686] FIG. 65B An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a square is shown.

[0687] In the arrangement of FIG. 65C the group of the voltage application unit and the charge detection unit of the signal extraction unit 65-1 having a square planar shape are arranged to face each other in a diagonal direction of the pixel 51, and the group of the voltage application unit and the charge detection unit of the signal extraction unit 65-2 having a square planar shape are arranged to face each other in a diagonal direction different from the diagonal direction in the signal extraction unit 65-1.

[0688] FIG. 65C An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a triangle is shown.

[0689] In the arrangement of FIG. 65BIn the arrangement, the group of voltage application units and charge detection units having a triangular planar shape of the signal extraction unit 65-1 is arranged opposite to each other in a first direction (horizontal direction) of the pixel 51, and the group of voltage application units and charge detection units having a triangular planar shape of the signal extraction unit 65-2 is arranged opposite to each other in a second direction (vertical direction) perpendicular to the first direction and different from the direction in the signal extraction unit 65-1.

[0690] Even in FIG. 65A and 65C where four electrode units 1311-1 to 1311-4 are arranged symmetrically in a point-symmetrical manner with the center point of the pixel set as a point of symmetry, where the electrode unit 1311-1 and the electrode unit 1311-3 are electrically connected to each other by the wiring 1351, where the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected to each other by the wiring 1352, where the electrode unit 1311-2 and the electrode unit 1311-4 are electrically connected to each other by the wiring 1353, and where the N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected to each other by the wiring 1354, the configuration is similar to that in FIG. 66A . The shape and positional relationship of the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are similar to those in the electrode unit 1311.

[0691] <Third Configuration Example of the Nineteenth Embodiment>

[0692] FIG. 66B is a plan view of a pixel according to the third configuration example of the nineteenth embodiment, and FIG. 66A is a cross-sectional view of a pixel according to the third configuration example of the nineteenth embodiment.

[0693] FIG. 66B is a plan view taken along the line B-B' in FIG. 66B , and FIG. 66A is a cross-sectional view taken along the line A-A' in FIG. 66A .

[0694] Note that, in the third configuration example in FIG. 66A and 66B , the same reference numerals are given to portions corresponding to the first configuration example in FIG. 62A and 66B , and the portions different from the first configuration example in FIG. 62A and 62B will be mainly described, and the description of the same portions will be omitted as appropriate.

[0695] In FIG. 63A and62B the first configuration example in FIG. 13A and FIG. 66A and 63B In the second configuration example in FIG. 13B, the electrode unit 1311 as the voltage application unit and the N+ semiconductor region 1312 as the charge detection unit are arranged on the same plane side of the substrate 61, that is, on the periphery (vicinity) of the first surface 1321 side.

[0696] In contrast, in the third configuration example in FIG. 13C and FIG. 66A and 66B In the third configuration example in FIG. 13C, the electrode unit 1311 as the voltage application unit is arranged on the plane side of the substrate 61 opposite to the first surface 1321 on which the N+ semiconductor region 1312 as the charge detection unit is formed, that is, on the second surface 1331 side. The protruding portion 131 IB of the electrode unit 1311 is formed on the upper portion of the second surface 1331 of the substrate 61.

[0697] In addition, the electrode unit 1311 is arranged so that the center position thereof overlaps the center position of the N+ semiconductor region 1312 in a plan view. FIG. 60 and 66B The example shown in FIG. 13C is an example in which the circular planar regions of the electrode unit 1311 and the N+ semiconductor region 1312 completely match each other. However, the planar regions do not necessarily completely match each other, and the planar regions on either side can be larger as long as the center positions thereof overlap each other. In addition, the center positions can not completely match each other, and can match each other to a certain extent that can be regarded as approximate matching.

[0698] The third configuration example is similar to the first configuration example except for the positional relationship between the electrode unit 1311 and the N+ semiconductor region 1312. As in the third configuration example, the embedded portion 1311A of the electrode unit 1311 as the voltage application unit is formed to a deep position in the vicinity of the N+ semiconductor region 1312 as the charge detection unit, which is formed in the first surface 1321 opposite to the second surface 1331 on which the electrode unit 1311 is formed. Even in this case, the charge distribution effect of the electric charges photoelectrically converted in a wide region in the depth direction of the substrate 61 is obtained, and thus the charge separation efficiency Cmod in the case of long-wavelength light can be improved.

[0699] In addition, due to the structure in which the outer peripheral portion of the electrode unit 1311 is covered with the insulating film 1313, the current flowing between the voltage application units is suppressed, and thus the current consumption can be reduced. In addition, in the case of comparison with the same current consumption, a high voltage can be applied to the voltage application units. In addition, even when the distance between the voltage application units is shortened, the current consumption can be suppressed, and thus high resolution can be achieved by reducing the pixel size and increasing the number of pixels.

[0700] In the third configuration example of the nineteenth embodiment, the first surface 1321 or the second surface 1331 of the substrate 61 can be provided as a light incident surface, and can be a backside illumination type or a frontside illumination type, but the backside illumination type is more desirable. For example, in a case where the third configuration example is configured as a backside illumination type, the second surface 1331 becomes the surface of the side on which the on-chip lens 62 is formed. For example, as shown in FIG. 11 The voltage supply line 1253 that supplies the electrode unit 1311 with an applied voltage is provided to be arranged in the vertical direction of the pixel array unit 20, and can be connected to the wiring on the front surface side through the through electrode that penetrates the substrate 61 at the periphery portion 1261 outside the pixel array unit 20.

[0701] <Other examples of planar shape>

[0702] In the third configuration example of the nineteenth embodiment, the planar shape of the electrode unit 1311 as the voltage application unit and the N+ semiconductor region 1312 as the charge detection unit is provided as a circular shape.

[0703] However, the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is not limited to a circular shape, and can be a shape such as an octagonal shape as shown in FIG. 12 a rectangular shape as shown in FIG. 17 a square, and the like. In addition, the number of signal extraction units 65 (tapping portions) arranged in one pixel is not limited to two, and can be four as shown in FIG. 67A to 67C and the like.

[0704] FIG. 66B is a plan view corresponding to the line B-B' in FIG. 67A , and shows an example in which the number of signal extraction units 65 is two and the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 that constitute each signal extraction unit 65 is provided as a shape different from a circular shape.

[0705] FIG. 67A shows an example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a vertically elongated rectangular shape that is elongated in the vertical direction.

[0706] In FIG. 67BIn the case of the pixel 1300, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 as the charge detection unit are arranged in a point-symmetrical manner with the center point of the pixel set as the point of symmetry. In addition, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 are arranged to face each other. The shape and positional relationship of the electrode unit 1311 arranged on the side of the second surface 1331 opposite to the surface on which the N+ semiconductor region 1312 is formed, or the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are also similar to the shape and positional relationship in the N+ semiconductor region 1312.

[0707] FIG. 67C An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is an L shape is shown.

[0708] FIG. 67B An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a comb shape is shown.

[0709] Even in the case of the pixel 1300, FIG. 68A to 68C and 67C , the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 are arranged in a point-symmetrical manner with the center point of the pixel set as the point of symmetry. In addition, the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-2 are arranged to face each other. The shape and positional relationship of the electrode unit 1311 arranged on the side of the second surface 1331 opposite to the surface on which the N+ semiconductor region 1312 is formed, or the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are also similar to the shape and positional relationship in the N+ semiconductor region 1312.

[0710] FIG. 66B is a plan view corresponding to the line B-B' in FIG. 68A , and shows an example in which the number of signal extraction units 65 is four and the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 constituting each signal extraction unit 65 is set to a shape different from a circular shape.

[0711] FIG. 68A An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a vertically elongated rectangular shape elongated in the vertical direction is shown.

[0712] In the case of the pixel 1300, FIG. 68AIn this case, the vertically elongated N+ semiconductor regions 1312-1 to 1312-4 are arranged at a predetermined interval in the horizontal direction, and are arranged in a point-symmetrical manner in a case where a center point of the pixel is set as a point of symmetry. In addition, the N+ semiconductor regions 1312-1 and 1312-2 are arranged to face each other, and the N+ semiconductor regions 1312-3 and 1312-4 are arranged to face each other.

[0713] The electrode unit 1311-1 and the electrode unit 1311-3 (not shown) formed on the second surface 1331 side are electrically connected to each other by the wiring 1351, and constitute a voltage application unit to which a voltage MIX0 is applied, for example, a signal extraction unit 65-1 (first tapping portion TA). The N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected to each other by the wiring 1352, and constitute a charge detection unit for detecting a signal charge DET1 of the signal extraction unit 65-1 (first tapping portion TA).

[0714] The electrode unit 1311-2 and the electrode unit 1311-4 (not shown) formed on the second surface 1331 side are electrically connected to each other by the wiring 1353, and constitute a voltage application unit to which a voltage MIX1 is applied, for example, a signal extraction unit 65-2 (second tapping portion TB). The N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected to each other by the wiring 1354, and constitute a charge detection unit for detecting a signal charge DET2 of the signal extraction unit 65-2 (second tapping portion TB).

[0715] Thus, in other words, in the arrangement of FIG. 68B In the arrangement of

[0716] The shape and positional relationship of the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are similar to the shape and positional relationship described above.

[0717] FIG. 68B An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a square is shown.

[0718] In the arrangement of FIG. 68CIn the arrangement of the pixel 51, the group of the voltage application unit and the charge detection unit having the square planar shape of the signal extraction unit 65-1 is arranged so as to face each other in a diagonal direction of the pixel 51, and the group of the voltage application unit and the charge detection unit having the square planar shape of the signal extraction unit 65-2 is arranged so as to face each other in a diagonal direction different from the diagonal direction in the signal extraction unit 65-1.

[0719] FIG. 68C An example in which the planar shape of the electrode unit 1311 and the N+ semiconductor region 1312 is a triangle is shown.

[0720] In the arrangement of the pixel 51, FIG. 68B In the arrangement of the pixel 51, the group of the voltage application unit and the charge detection unit having the square planar shape of the signal extraction unit 65-1 is arranged so as to face each other in a diagonal direction of the pixel 51, and the group of the voltage application unit and the charge detection unit having the square planar shape of the signal extraction unit 65-2 is arranged so as to face each other in a diagonal direction different from the diagonal direction in the signal extraction unit 65-1.

[0721] Even in the configuration in which the four electrode units 1311-1 to 1311-4 are arranged in a point-symmetrical manner with the center point of the pixel set as the point of symmetry in the pixel circuits in FIG. 31 and 68C , the configuration in which the electrode unit 1311-1 and the electrode unit 1311-3 are electrically connected to each other by the wiring 1351, the configuration in which the N+ semiconductor region 1312-1 and the N+ semiconductor region 1312-3 are electrically connected to each other by the wiring 1352, the configuration in which the electrode unit 1311-2 and the electrode unit 1311-4 are electrically connected to each other by the wiring 1353, and the configuration in which the N+ semiconductor region 1312-2 and the N+ semiconductor region 1312-4 are electrically connected to each other by the wiring 1354 are similar. The shape and positional relationship of the insulating film 1313 and the hole concentration enhancement layer 1314 formed at the outer periphery of the electrode unit 1311 are similar to the shape and positional relationship in the electrode unit 1311.

[0722] <Other Examples of Wiring Arrangement>

[0723] In the pixel circuit in FIG. 32 and FIG. 42A to 42C , or in the example of the metal film M3 of FIG. 69 , a configuration in which two vertical signal lines 29 are arranged in one pixel column in a manner corresponding to two signal extraction units 65 (two tapping portions TA and TB) is explained.

[0724] However, for example, a configuration can be employed in which four vertical signal lines 29 are arranged in one pixel column, and the pixel signals of a total of four taps of two pixels adjacent to each other in the vertical direction are simultaneously output.

[0725] FIG. 69 A circuit configuration example of the pixel array unit 20 in a case in which the pixel signals of a total of four taps of two pixels adjacent to each other in the vertical direction are simultaneously output is shown.

[0726] FIG. 69 A circuit configuration of four pixels (2 x 2) among the plurality of pixels 51 arranged in a matrix shape two-dimensionally in the pixel array unit 20 is shown. Note that in the case of distinguishing the four pixels 51 (2 x 2) in FIG. 32 , the pixels 51 are shown as pixels 511 to 514.

[0727] The circuit configuration of each of the pixels 51 is a circuit configuration including an additional capacitor 727 and a switching transistor 728 for controlling the connection of the additional capacitor 727 as described above with reference to FIG. 1 The repeated description of the circuit configuration is omitted.

[0728] In one pixel column of the pixel array unit 20, the voltage supply lines 30A and 30B are arranged in the vertical direction. A predetermined voltage MIX0 is supplied through the vertical supply line 30A to the first taps TA of the plurality of pixels 51 arranged in the vertical direction, and a predetermined voltage MIX1 is supplied through the voltage supply line 30B to the second taps TB.

[0729] In addition, in one pixel row of the pixel array unit 20, four vertical signal lines 29A to 29D are arranged in the vertical direction.

[0730] In the pixel column of the pixel 511 and the pixel 512, for example, the vertical signal line 29A transmits the pixel signal of the first tap TA of the pixel 511 to the column processing unit 23 FIG. 1 ), the vertical signal line 29B transmits the pixel signal of the second tap TB of the pixel 511 to the column processing unit 23, the vertical signal line 29C transmits the pixel signal of the first tap TA of the pixel 512 adjacent to the pixel 511 in the same column to the column processing unit 23, and the vertical signal line 29D transmits the pixel signal of the second tap TB of the pixel 512 to the column processing unit 23.

[0731] In the pixel column of the pixel 513 and the pixel 514, for example, the vertical signal line 29A transmits the pixel signal of the first tap TA of the pixel 513 to the column processing unit 23 FIG. 70), the vertical signal line 29B transfers the pixel signal of the second tapping portion TB of the pixel 513 to the column processing unit 23, the vertical signal line 29C transfers the pixel signal of the first tapping portion TA of the pixel 514 adjacent to the pixel 511 in the same column to the column processing unit 23, and the vertical signal line 29D transfers the pixel signal of the second tapping portion TB of the pixel 514 to the column processing unit 23.

[0732] On the other hand, in the horizontal direction of the pixel array unit 20, the control line 841 for transferring the drive signal RST to the reset transistor 723, the control line 842 for transferring the drive signal TRG to the transfer transistor 721, the control line 843 for transferring the drive signal FDG to the switching transistor 728, and the control line 844 for transferring the selection signal SEL to the selection transistor 725 are arranged in units of pixels.

[0733] As for the drive signal RST, the drive signal FDG, the drive signal TRG, and the selection signal SEL, the same signal is supplied from the vertical drive unit 22 to the respective pixels 51 in two rows adjacent to each other in the vertical direction.

[0734] As described above, in the pixel array unit 20, four vertical signal lines 29A to 29D are arranged in one pixel column, and thus it is possible to simultaneously read out the pixel signals in units of two rows.

[0735] FIG. 70 A layout of the third layer metal film M3 of the multi-layer wiring layer 811 in a case where four vertical signal lines 29A to 29D are arranged in one pixel column is shown.

[0736] In other words, FIG. 42C is FIG. 70 a modification example of the layout of the metal film M3 shown in

[0737] In FIG. 70 , four vertical signal lines 29A to 29D are arranged in one pixel column. In addition, four power supply lines 1401A to 1401D for supplying the power supply voltage VDD to one pixel column are arranged in one pixel column.

[0738] Note that, in FIG. 11 , the region of the pixel 51 and the regions of the signal extraction units 65-1 and 65-2 having an octagonal shape shown in FIG. 71 to FIG. 76 are indicated by broken lines for reference. The same applies to FIG. 70 .

[0739] In FIG. 70In the layout of the metal film M3 shown, the VSS wiring (ground wiring) 1411 having the GND potential is arranged near each of the vertical signal lines 29A to 29D and the power supply lines 1401A to 1401D. The VSS wiring 1411 includes the VSS wiring 1411B arranged near each of the vertical signal lines 29A to 29D and having a narrow line width, and the VSS wiring 1411A arranged at the pixel boundary portion between the vertical signal line 29B and the power supply line 1401C and between the vertical signal line 29C and the power supply line 1401D and having a wide line width.

[0740] To enhance the stability of the signal, it is effective to increase the power supply voltage VDD supplied to the power supply lines 1401 or to increase the voltages MIX0 and MIX1 supplied through the voltage supply lines 30A and 30B. However, on the one hand, the current increases, and the wiring reliability deteriorates. Here, as shown in FIG. 70 For one pixel column, the VSS wiring 1411A having a line width wider than that of the power supply line 1401 is provided for at least one VSS wiring 1411, so the current density decreases, and the wiring reliability can be improved. FIG. 70 An example in which two VSS wirings 1411A are symmetrically provided inside the pixel region for one pixel column is shown.

[0741] In addition, in the layout of FIG. 70 The VSS wiring 1411 (1411A or 1411B) is arranged near each of the vertical signal lines 29A to 29D. Therefore, the vertical signal lines 29 are less likely to be affected by potential fluctuations from the outside.

[0742] Note that the adjacent wirings of the signal lines, the power supply lines, and the control lines can be provided as the VSS wirings in the metal film of the other layer, without being limited to FIG. 42B the third layer metal film M3 of the multi-layer wiring layer shown. For example, for the control lines 841 to 844 of the second layer metal film M2 shown, the VSS wirings can be arranged on both sides of each of the control lines 841 to 844. Therefore, it is possible to reduce the influence of potential fluctuations from the outside on the control lines 841 to 844. FIG. 71

[0743] FIG. 71 A modification example 1 of the layout of the third layer metal film M3 of the multi-layer wiring layer 811 in the case where four vertical signal lines 29A to 29D are arranged in one pixel column is shown.

[0744] FIG. 70 The layout of the metal film M3 in FIG. 70 ​The layout of the metal film M3 shown differs in that the adjacent VSS wiring 1411 of each of the four vertical signal lines 29A to 29D is provided with the same line width.

[0745] More specifically, in FIG. 71 In the layout of the metal film M3 shown, the VSS wiring 1411A having a wide line width and the VSS wiring 1411B having a narrow line width are arranged on both sides of the vertical signal line 29C, and the VSS wiring 1411A having a wide line width and the VSS wiring 1411B having a narrow line width are also arranged on both sides of the vertical signal line 29B.

[0746] In contrast, in FIG. 72 In the layout of the metal film M3 shown, the VSS wiring 1411B having a narrow line width is arranged on both sides of the vertical signal line 29C, and the VSS wiring 1411B having a narrow line width is also arranged on both sides of the vertical signal line 29B. The VSS wiring 1411B having a narrow line width is also arranged on both sides of each of the other vertical signal lines 29A and 29D. The line widths of the VSS wiring 1411B on both sides of the four vertical signal lines 29A to 29D are all the same.

[0747] When the line widths of the VSS wiring 1411 on both sides of the vertical signal line 29 are provided with the same line width, the degree of influence of crosstalk can be made uniform, and the characteristic variation can be reduced.

[0748] FIG. 72 A modification example 2 of the layout of the third layer metal film M3 of the multi-layer wiring layer 811 in the case where the four vertical signal lines 29A to 29D are arranged in one pixel column is shown.

[0749] FIG. 70 The layout of the metal film M3 shown is the same as ​ The layout of the metal film M3 shown differs in that the VSS wiring 1411A having a wide line width is replaced with the VSS wiring 1411C in which a plurality of gaps 1421 are regularly provided on the inner side.

[0750] That is, the VSS wiring 1411C has a line width wider than the power supply line 1401, and in the VSS wiring 1411C, a plurality of gaps 1421 are arranged repeatedly in the vertical direction at a predetermined period. In FIG. 72 In the example of, the shape of each gap 1421 is a rectangular shape, but the shape thereof can be a circular shape or a polygonal shape, without being limited to a rectangular shape.

[0751] When a plurality of gaps 1421 are provided on the inner side of the wiring region, stability can be improved when forming (processing) the VSS wiring 1411C having a wide width.

[0752] Note that, FIG. 72 a layout in which FIG. 70 the VSS wiring 1411A of the metal film M3 shown is replaced with the VSS wiring 1411C, but FIG. 71 the VSS wiring 1411A of the metal film M3 shown can be replaced with the VSS wiring 1411C.

[0753] <Other layout examples of a pixel transistor>

[0754] Next, a description is given of FIG. 73A and 73B a modification example of the layout example of the pixel transistor shown. FIG. 44B

[0755] is a view showing FIG. 73A the layout of the pixel transistor shown. FIG. 44B On the other hand,

[0756] a modification example of the layout of the pixel transistor is shown. FIG. 73B As

[0757] and FIG. 73A shown, with respect to the center line (not shown) of the two signal extraction units 65-1 and 65-2, the reset transistors 723A and 723B, the transfer transistors 721A and 721B, the switch transistors 728A and 728B, the selection transistors 725A and 725B, and the amplification transistors 724A and 724B are formed in order from the side closer to the center line toward the outside. FIG. 44B In the case of the layout of the pixel transistor, the contact 1451 of the first power supply voltage VDD (VDD_1) is arranged between the reset transistors 723A and 723B, and the contacts 1452 and 1453 of the second power supply voltage VDD (VDD_2) are arranged outside the gate electrodes of the amplification transistors 724A and 724B, respectively.

[0758] Further, the contact 1461 of the first VSS wiring (VSS_A) is arranged between the gate electrodes of the selection transistor 725A and the switch transistor 728A, and the contact 1462 of the second VSS wiring (VSS_B) is arranged between the gate electrodes of the selection transistor 725B and the switch transistor 728B.

[0759] In the case of the layout of the pixel transistor, as

[0760] shown, four power supply lines 1401A to 1401D are required for one pixel column. FIGS. 70-72

[0761] On the other hand, in FIG. 73B ​In this case, with respect to the center lines (not shown) of the two signal extraction units 65-1 and 65-2, the gate electrodes of the switching transistors 728A and 728B, the transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B are formed in order from the side closer to the center line toward the outer side.

[0762] In the case of this pixel transistor arrangement, the contact 1471 having the first VSS wiring (VSS_1) is arranged between the switching transistors 728A and 728B, and the contacts 1472 and 1473 having the second VSS wiring (VSS_2) are arranged on the outer sides of the gate electrodes of the selection transistors 725A and 725B, respectively.

[0763] In addition, the contact 1481 of the first power supply voltage VDD (VDD_A) is arranged between the amplification transistor 724A and the gate electrode of the reset transistor 723A, and the contact 1482 of the second power supply voltage VDD (VDD_B) is arranged between the amplification transistor 724B and the gate electrode of the reset transistor 723B.

[0764] In the case of this pixel transistor arrangement, compared to the layout of the pixel transistors in FIG. 73A , the number of contacts of the power supply voltage can be further reduced, and thus the circuit can be simplified. In addition, the wiring of the power supply line 1401 in the pixel array unit 20 can also be reduced, and a power supply line 1401 having two wirings can be configured for one pixel column.

[0765] In addition, in the pixel transistor layout shown in FIG. 73B , the contact 1471 having the first VSS wiring (VSS_1) between the switching transistors 728A and 728B can be omitted. Thus, the density of the pixel transistors in the vertical direction can be reduced. In addition, since the number of contacts having the VSS wiring is reduced, the current flowing between the voltage supply line 741 FIG. 33A and 33B , and the VSS wiring for applying the voltage MIX0 or MIX1 can be reduced. FIG. 34A and 34B .

[0766] In the case where the contact 1471 having the first VSS wiring (VSS_1) is omitted, the amplification transistors 724A and 724B can be increased in the vertical direction. Thus, the noise of the pixel transistors can be reduced, and the signal deviation can be reduced.

[0767] In addition, in the pixel transistor layout shown in FIG. 73BIn the pixel transistor layout, contacts 1472 and 1473 with the second VSS wiring (VSS_2) can be omitted. Therefore, the pixel transistor density in the vertical direction can be reduced. Furthermore, since the number of contacts with the VSS wiring is reduced, the voltage supply line 741 for applying voltage MIX0 or MIX1 can be reduced. FIG. 33A and 33B as well as FIG. 34A and 34B The current flowing between the VSS wiring and the VSS wiring.

[0768] By omitting contacts 1472 and 1473 with the second VSS wiring (VSS_2), the amplification transistors 724A and 724B can be increased in the vertical direction. Therefore, the noise of the pixel transistors can be reduced, and signal deviation can be decreased.

[0769] FIG. 74 Show FIG. 73B The wiring layout of the pixel transistor Tr used to connect the metal film M1 in the pixel transistor layout. FIG. 74 Corresponding to the connection FIG. 44C The wiring for the pixel transistor Tr of the metal film M1 is shown. The wiring used to connect the pixel transistor Tr can be made while bypassing other wiring layers such as metal films M2 and M3.

[0770] FIG. 75 Shown in FIG. 73B The layout of the pixel transistors shown is the layout of the third metal film M3 of the multilayer wiring layer 811 in the case of two power lines 1401 arranged in a pixel column.

[0771] exist FIG. 75 In the accompanying drawings, the same reference numerals are given to those corresponding to... FIG. 70 The relevant parts should be omitted, and their descriptions should be appropriately omitted.

[0772] When comparing FIG. 75 The layout of the metal film M3 in the middle and FIG. 70 When laying out the metal film M3, in FIG. 70 Of the four power lines 1401A to 1401D, two power lines 1401C and 1401D are omitted, and the VSS wiring 1411A with a wide line width is replaced with VSS wiring 1411D with an even wider line width.

[0773] As mentioned above, when the area (line width) of VSS wiring 1411 is increased, the current density is further reduced, and the wiring reliability can be improved.

[0774] FIG. 76 Shown in FIG. 73BAnother layout of the third layer metal film M3 of the multilayer wiring layer 811 in a case where two power supply lines 1401 are arranged in one pixel column in the layout of the pixel transistor shown.

[0775] In FIG. 76 , the same reference numerals are given to portions corresponding to FIG. 70 , and the description thereof is appropriately omitted.

[0776] When the layout of the metal film M3 in FIG. 76 is compared with the layout of the metal film M3 in FIG. 70 , of the four power supply lines 1401A to 1401D in FIG. 70 , two power supply lines 1401A and 1401B are omitted, and VSS wiring 1411E having a wider line width is substituted therefor.

[0777] As described above, when the area (line width) of the VSS wiring 1411 is increased, the current density is further reduced, and the wiring reliability can be improved.

[0778] Note that FIG. 75 and FIG. 76 the layout of the metal film M3 shown in FIG. 70 is an example in which the layout of the metal film M3 shown in FIG. 71 and FIG. 72 is changed to two power supply lines 1401, but an example in which the layout of the metal film M3 shown in and

[0779] is changed to two power supply lines 1401 is also possible. FIG. 71 FIG. 72 That is, a configuration in which the number of power supply lines 1401 is changed to two is also applicable to the layout of the metal film M3 shown in (in which the VSS wiring 1411 adjacent to the four VSS wirings 1411, respectively, is provided to have the same line width) and the layout of the metal film M3 shown in

[0780] (in which the VSS wiring 1411C including a plurality of gaps 1421 is provided). FIG. 71 FIG. 72 Thus, as shown in , the degree of influence of crosstalk can be made uniform, and the characteristic variation can be reduced. In addition, as shown in

[0781] , when the VSS wiring 1411C having a wide width is formed, an effect capable of improving stability can be obtained.

[0782] FIG. 77 is a plan view showing an arrangement example of the VSS wiring in the multilayer wiring layer 811.

[0783] AsFIG. 77 As illustrated, in the multilayer wiring layer 811, the VSS wiring can be formed in a plurality of wiring layers, for example, in the first wiring layer 1521, the second wiring layer 1522, and the third wiring layer 1523.

[0784] In the first wiring layer 1521, for example, a plurality of vertical wirings 1511 extending in the vertical direction in the pixel array unit 20 are arranged at predetermined intervals in the horizontal direction. In the second wiring layer 1522, for example, a plurality of horizontal wirings 1512 extending in the horizontal direction in the pixel array unit 20 are arranged at predetermined intervals in the vertical direction. In the third wiring layer 1523, for example, wirings 1513 extending in the vertical direction or the horizontal direction to surround at least the outer side of the pixel array unit 20 are arranged to have a line width wider than the vertical wirings 1511 and the horizontal wirings 1512, and are connected to the GND potential. The wirings 1513 are also arranged within the pixel array unit 20 to connect a plurality of wirings 1513 opposite to each other in the outer peripheral portion.

[0785] The vertical wirings 1511 of the first wiring layer 1521 and the horizontal wirings 1512 of the second wiring layer 1522 are connected to each other by a via hole or the like at each overlapping portion 1531 where each of the vertical wirings 1511 and each of the horizontal wirings 1512 overlap each other in a plan view.

[0786] In addition, the vertical wirings 1511 of the first wiring layer 1521 and the wirings 1513 of the third wiring layer 1523 are connected to each other by a via hole or the like at each overlapping portion 1532 where each of the vertical wirings 1511 and each of the wirings 1513 overlap each other in a plan view.

[0787] In addition, the horizontal wirings 1512 of the second wiring layer 1522 and the wirings 1513 of the third wiring layer 1523 are connected to each other by a via hole or the like at each overlapping portion 1533 where each of the horizontal wirings 1512 and each of the wirings 1513 overlap each other in a plan view.

[0788] Note that, in FIG. 77 , with respect to the overlapping portions 1531 to 1533, reference numerals are given to only one position to prevent complication of the drawing.

[0789] As described above, the VSS wiring is formed in a plurality of wiring layers of the multilayer wiring layer 811, and the vertical wirings 1511 and the horizontal wirings 1512 can be formed in a lattice shape within the pixel array unit 20. Therefore, the propagation delay within the pixel array unit 20 is reduced, and it is possible to suppress characteristic variation.

[0790] FIG. 78is a plan view showing another wiring example of the VSS wiring in the multilayer wiring layer 811.

[0791] In FIG. 78 , the same reference numerals are given to portions corresponding to FIG. 77 , and the description thereof is appropriately omitted.

[0792] In FIG. 77 , the vertical wiring 1511 of the first wiring layer 1521 and the horizontal wiring 1512 of the second wiring layer 1522 are not formed outside the wiring 1513 arranged at the outer periphery of the pixel array unit 20. However, in FIG. 78 , the vertical wiring 1511 and the horizontal wiring 1512 are formed so as to extend outside the wiring 1513 formed at the outer periphery of the pixel array unit 20. Further, each of the vertical wirings 1511 is connected to the GND potential at the outer periphery portion 1542 of the substrate 1541 outside the pixel array unit 20, and each of the horizontal wirings 1512 is connected to the GND potential at the outer periphery portion 1543 of the substrate 1541 outside the pixel array unit 20.

[0793] In other words, in FIG. 77 , the vertical wiring 1511 of the first wiring layer 1521 and the horizontal wiring 1512 of the second wiring layer 1522 are connected to the GND potential through the wiring 1513 at the outer periphery. However, in FIG. 78 , the vertical wiring 1511 and the horizontal wiring 1512 are directly connected to the GND potential in addition to the connection through the wiring 1513. Note that the region in which the vertical wiring 1511 and the horizontal wiring 1512 are connected to the GND potential can be four sides (for example, the outer periphery portions 1542 and 1543 in FIG. 78 ) of the substrate 1541 or a predetermined one side, a predetermined two sides, or a predetermined three sides.

[0794] As described above, the VSS wiring is formed in a plurality of wiring layers of the multilayer wiring layer 811 and can be arranged in a lattice shape inside the pixel array unit 20 in a plan view. Therefore, the propagation delay within the pixel array unit 20 is reduced, and the characteristic variation can be suppressed.

[0795] Note that in FIG. 77 and FIG. 78 , the wiring example of the VSS wiring has been described, but the power supply line can be wired in a similar manner.

[0796] As with the VSS wiring and the power supply line shown in FIG. 77 and FIG. 78 , FIGS. 70-76 the VSS wiring 1411 and the power supply line 1401 described can be arranged in a plurality of wiring layers of the multilayer wiring layer 811.FIGS. 70-76 The VSS line 1411 and the power supply line 1401 described in the present specification are also applicable to any of the embodiments described in the present specification.

[0797] <First method of pupil correction>

[0798] Next, a first pupil correction method in the light receiving element 1 will be described.

[0799] As in an image sensor, the light receiving element 1 as a CAPD sensor can perform pupil correction in which the on-chip lens 62 or the inter-pixel light shielding film 63 is shifted toward the planar center of the pixel array unit 20 according to a difference in chief ray angle corresponding to an in-plane position of the pixel array unit 20.

[0800] Specifically, as shown in FIG. 17, in the pixel 51 at the position 1701-5 of the central portion of the pixel array unit 20 among the respective positions 1701-1 to 1701-9 of the pixel array unit 20, the on-chip lens 62 matches the center between the signal extraction units 65-1 and 65-2 formed in the substrate 61, but in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6 to 1701-9 of the peripheral portion of the pixel array unit 20, the center of the on-chip lens 62 is arranged to be shifted toward the planar center side of the pixel array unit 20. As with the on-chip lens 62, the inter-pixel light shielding films 63-1 and 63-2 are arranged to be shifted toward the planar center side of the pixel array unit 20. FIG. 79

[0801] In addition, as shown in FIG. 18, in the pixel 51, the DTIs 1711-1 and 1711-2 (in the DTI, a trench is formed to a predetermined depth in the substrate depth direction) are formed at the pixel boundary portion on the back surface side (the on-chip lens 62 side) of the substrate 61 to prevent the case where incident light is incident to an adjacent pixel, and in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6 to 1701-9 of the peripheral portion of the pixel array unit 20, in addition to the on-chip lens 62 and the inter-pixel light shielding films 63-1 and 63-2, the DTIs 1711-1 and 1711-2 are also arranged to be shifted toward the planar center side of the pixel array unit 20. FIG. 80

[0802] Alternatively, as shown in FIG. 19, in the pixel 51, the DTIs 1711-1 and 1711-2 are formed at the pixel boundary portion on the back surface side (the on-chip lens 62 side) of the substrate 61 to prevent the case where incident light is incident to an adjacent pixel, and in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6 to 1701-9 of the peripheral portion of the pixel array unit 20, in addition to the on-chip lens 62 and the inter-pixel light shielding films 63-1 and 63-2, the DTIs 1711-1 and 1711-2 are also arranged to be shifted toward the planar center side of the pixel array unit 20. FIG. 81 ​​As shown, in the pixel 51, at the pixel boundary portion on the front surface side of the substrate 61 (on the side of the multilayer configuration 811), the DTIs 1712-1 and 1712-2 (in the DTI, a trench is formed in the substrate depth direction to a predetermined depth) are formed to prevent the case where incident light is incident to the adjacent pixel, and in the pixels 51 at the positions 1701-1 to 1701-4, 1701-6 to 1701-9 located at the peripheral portion of the pixel array unit 20, in addition to the on-chip lens 62 and the inter-pixel light shielding film 63-1 and 63-2, the DTIs 1712-1 and 1712-2 are also arranged to be shifted toward the planar center side of the pixel array unit 20.

[0803] Note that, as the pixel isolation portion of the substrate 61 for isolating the adjacent pixels to prevent the incident light from being incident to the adjacent pixel, a configuration of a through-isolation portion that penetrates the substrate 61 and isolates the adjacent pixels can be employed instead of the DTIs 1711-1, 1711-2, 1712-1, and 1712-2. Even in this case, at the pixels 51 at the positions 1701-1 to 1701-4, 1701-6 to 1701-9 located at the peripheral portion of the pixel array unit 20, the through-isolation portion is arranged to be shifted toward the planar center side of the pixel array unit 20.

[0804] As shown, FIGS. 79-81 When the on-chip lens 62 is shifted toward the planar center side of the pixel array unit 20 in combination with the inter-pixel light shielding film 63 and the like, the main light beam can match the center of each pixel. However, in the light-receiving element 1 as a CAPD sensor, the optimum incident position in each pixel differs from each other by applying a voltage between the two signal extraction units 65 (tapping portions) to allow the current to flow, so that the optimum incident position in each pixel differs from each other. Therefore, in the light-receiving element 1, a pupil correction technique different from the optical pupil correction performed in the image sensor is required for the distance measurement.

[0805] The difference between the pupil correction performed in the light-receiving element 1 as a CAPD sensor and the pupil correction performed in the image sensor will be described with reference to FIGS. 82A-82C

[0806] Further, in FIGS. 82A-82C , nine pixels 51 (3 x 3) show the pixels 51 corresponding to the positions 1701-1 to 1701-9 of the pixel array unit 20 in FIGS. 79-81

[0807] FIG. 82A The positions of the on-chip lens 62 and the positions 1721 of the main light beam on the front surface side of the substrate in the case where the pupil correction is not performed are shown.

[0808] ​​In the pixel 51 at any of the positions 1701-1 to 1701-9 within the pixel array unit 20 without performing pupil correction, the center of the on-chip lens 62 is arranged to match the center between the two taps within the pixel, i.e., between the first tap TA (signal extraction unit 65-1) and the second tap TB (signal extraction unit 65-2). In this case, as shown in FIG. 17, the plurality of positions 1721 of the main light beam on the substrate front surface side become different from each other with the positions 1701-1 to 1701-9 within the pixel array unit 20. FIG. 82A

[0809] In the pupil correction performed in the image sensor, as shown in FIG. 18, the on-chip lens 62 is arranged such that each position 1721 of the main light beam matches the center between the first tap TA and the second tap TA in the pixel 51 at any of the positions 1701-1 to 1701-9 within the pixel array unit 20. More specifically, as shown in FIG. 18, the on-chip lens 62 is arranged to be displaced toward the planar center side of the pixel array unit 20. FIG. 82B FIGS. 79-81

[0810] In contrast, in the pupil correction performed in the light-receiving element 1, as shown in FIG. 19, the on-chip lens 62 is arranged to be displaced from the position of the on-chip lens 62 shown in FIG. 17, which makes the position 1721 of the main light beam a center position between the first tap TA and the second tap TB, toward the first tap TA side. FIG. 82C FIG. 82B FIG. 82B FIG. 82C The displacement amount of the position 1721 of the main light beam between the first tap TA and the second tap TB increases from the center position of the pixel array unit 20 to the outer peripheral portion.

[0811] FIG. 83 is a view showing the displacement amount of the on-chip lens 62 when the position 1721 of the main light beam is displaced toward the first tap TA side.

[0812] For example, the displacement amount LD between the position 1721c of the main light beam at the position 1701-5 of the center portion of the pixel array unit 20 and the position 1721x of the main light beam at the position 1701-4 of the peripheral portion of the pixel array unit 20 is the same as the relevant optical path difference LD of the pupil correction at the position 1701-4 of the peripheral portion of the pixel array unit 20.

[0813] In other words, the displacement from the center position between the first tap TA (signal extraction unit 65-1) and the second tap TB (signal extraction unit 65-2) toward the first tap TA side is such that the optical path length of the main light beam becomes the same in each pixel of the pixel array unit 20.

[0814] ​​​​​​Here, the shift toward the first tap TA side is performed because it is assumed that the following method is employed. In this method, the light-reception timing is set to four phases, and the phase shift (phase) corresponding to the delay time AT depending on the distance from the object is calculated by using only the output value of the first tap TA.

[0815] FIG. 84 is a timing chart showing a detection method using two phases (two-phase method) and a detection method using four phases (four-phase method) in a ToF sensor using an indirect ToF method.

[0816] The irradiation light modulated to repeat the irradiation ON / OFF in accordance with the irradiation time T (one cycle = 2T) is output from a predetermined light source, and in the light-reception element 1, the reflected light is received in a state of being delayed by a delay time AT, where the delay time AT corresponds to the distance from the object.

[0817] In the two-phase method, the light-reception element 1 receives light at the first tap TA and the second tap TB at the timing where the phases are shifted by 180°. The amount of phase shift θ corresponding to the delay time AT can be detected with the distribution ratio between the signal value q A received at the first tap TA and the signal value q B received at the second tap TB.

[0818] On the other hand, in the four-phase method, light is received at four timings of the same phase (phase 0) as the irradiation light, the phase (phase 90) shifted by 90° with respect to the irradiation light, the phase (phase 180) shifted by 180° with respect to the irradiation light, and the phase (phase 270) shifted by 270° with respect to the irradiation light. In this case, the signal value TA phase180 detected at the phase shifted by 180° is the same as the signal value q B received by the second tap TB in the two-phase method. Therefore, in the detection at the four phases, the signal value of only one of the first tap TA and the second tap TB can be utilized to detect the amount of phase shift θ corresponding to the delay time AT. In the four-phase method, the tap used for detecting the amount of phase shift θ is referred to as a phase-shift detection tap.

[0819] Here, in the case where the first tap TA between the first tap TA and the second tap TB is set as the phase-shift detection tap for detecting the amount of phase shift θ, in the pupil correction, the shift toward the first tap TA side is performed. Therefore, in each pixel of the pixel array unit 20, the optical path length of the main light beam becomes substantially the same.

[0820] When the signal values detected at the phase 0, the phase 90, the phase 180, and the phase 270 of the first tap TA in the four-phase method are set as q0A , q 1A , q 2A and q 3A When θ A is detected in the first tapping portion TA, the phase shift amount θ

[0821] [Math. 1]

[0822]

[0823] In addition, Cmod A in the four-phase method in the case where detection is performed in the first tapping portion TA is calculated according to the following expression (3).

[0824] [Math. 2]

[0825]

[0826] As shown in expression (3), Cmod A in the four-phase method is the larger value between (q 0A -q 2A ) / (q 0A +q 2A ) and (q 1A -q 3A ) / (q 1A +q 3A ).

[0827] As described above, the light-receiving element 1 performs pupil correction by changing the positions of the on-chip lens 62 and the light-blocking film 63 between the pixels, so that the optical path length of the chief ray in each pixel in the plane of the pixel array unit 20 becomes substantially the same. In other words, the light-receiving element 1 performs pupil correction so that the phase shift amount θ A of the first tapping portion TA as a phase shift detection tapping portion in each pixel in the plane of the pixel array unit 20 becomes substantially the same. Therefore, the chip dependence in the plane can be removed, and the distance measurement accuracy can be improved. Here, as described above, "substantially match" or "substantially the same" means "equivalent" within a predetermined range that can be considered the same other than "exactly match" or "exactly the same". The first method of pupil correction is applicable to any of the embodiments described in this specification.

[0828] [Second Method of Pupil Correction]

[0829] Next, a second method of pupil correction in the light-receiving element 1 will be described.

[0830] The first method for pupil correction is applicable when determining the signal of the first tap TA between the first tap TA and the second tap TB during phase shift calculation; however, it may be difficult to determine which tap to use. In this case, pupil correction can be performed using the following second method.

[0831] In the second method of pupil correction, the positions of the on-chip lens 62 and the inter-pixel light-shielding film 63 are set to be shifted towards the center of the plane, thereby increasing the DC contrast of the first tap-out portion TA. A DC contrast of the second tap TB B In each pixel of the pixel array unit 20, they become substantially the same. In the case where DTI 1711 is formed from the on-chip lens 62 side of the substrate 61 and DTI 1712 is formed from the front surface side, their positions are arranged to be shifted as in the first method.

[0832] The DC contrast ratio of the first tap TA is calculated according to the following expressions (4) and (5). A DC contrast of the second tap TB B .

[0833] [Mathematical Expression 3]

[0834]

[0835]

[0836] In expression (4), A H This indicates the signal value detected by the first tap TA after the light-receiving element 1 is directly irradiated with continuously emitted light without interruption, and B L This represents the signal value detected by the second tap TB, which is subjected to zero or negative voltage. In expression (5), B H This indicates the signal value detected in the second tap TB after the light-receiving element 1 is directly irradiated with continuously emitted light without interruption, and B L This indicates the signal value detected by the first tap TA when zero or negative voltage is applied.

[0837] The desired result is that the DC contrast ratio of the first junction TA is [missing information]. A DC contrast of the second tap TB B They are identical to each other, and the DC contrast of the first junction TA is DC. A DC contrast of the second tap TB B The pixels are roughly matched to each other at any position in the plane of the pixel array unit 20. However, the DC contrast of the first tap TA is...A DC contrast DC of the second tap portion TB B In a case where the DC contrast DC of the first tap portion TA and the DC contrast DC of the second tap portion TB differ from each other depending on the position in the plane of the pixel array unit 20, the position of the on-chip lens 62, the inter-pixel light shielding film 63, and the like is arranged to be shifted toward the center side of the plane so that the DC contrast DC of the first tap portion TA A In a case where the shift amount between the center portion and the outer peripheral portion of the pixel array unit 20 and the DC contrast DC of the second tap portion TB differ from each other B In a case where the shift amount between the center portion and the outer peripheral portion of the pixel array unit 20 and the DC contrast DC of the second tap portion TB differ from each other

[0838] As described above, the light-receiving element 1 performs pupil correction by changing the positions of the on-chip lens 62 and the inter-pixel light shielding film 63 so that the DC contrast DC of the first tap portion TA A DC contrast DC of the second tap portion TB B approximately match each other in each pixel in the plane of the pixel array unit 20. Thus, the chip dependence in the plane can be eliminated, and the distance measurement accuracy can be improved. Here, the "approximately match" or "approximately the same" as described above means "equivalent" within a predetermined range that can be regarded as the same other than "exactly match" or "exactly the same". The second method of pupil correction is applicable to any of the embodiments described in this specification.

[0839] Note that, as FIG. 84 indicated, the light-receiving timing of the first tap portion TA and the second tap portion TB is controlled by the voltage MIX0 and the voltage MIX1 supplied from the tap portion driving unit 21 through the voltage supply line 30. The voltage supply line 30 is arranged to be shared by one pixel column in the vertical direction of the pixel array unit 20, and thus a delay caused by an RC component occurs when the distance from the tap portion driving unit 21 is long.

[0840] Here, as FIG. 85 indicated, the resistance and the capacitance of the voltage supply line 30 are changed depending on the distance to the tap portion driving unit 21 so that the driving capability of each pixel 51 is approximately uniform. Thus, correction can be made so that the phase shift (phase) or the DC contrast DC becomes approximately uniform in the plane of the pixel array unit 20. Specifically, the voltage supply line 30 is arranged so that the line width is relatively widened in correspondence with the distance from the tap portion driving unit 21.

[0841] <Twentieth Embodiment>

[0842] In the twentieth to twenty-second embodiments described later, a configuration example of a light-receiving element 1 capable of acquiring auxiliary information other than the distance measurement information obtained from the distribution ratio of the signals between the first tap portion TA and the second tap portion TB will be described.

[0843] First, a configuration example of the light-receiving element 1 capable of acquiring phase difference information as auxiliary information in addition to the ranging information obtained from the distribution ratio of the signals between the first tapping portion TA and the second tapping portion TB will be described.

[0844] <First configuration example of the twentieth embodiment>

[0845] FIG. 86A is a cross-sectional view of a pixel according to the first configuration example of the twentieth embodiment, and FIG. 86B and 86C are plan views of the pixel according to the first configuration example of the twentieth embodiment.

[0846] In FIG. 86A , the same reference numerals are given to portions corresponding to the other embodiments described above, and the description thereof is appropriately omitted.

[0847] In FIGS. 86A-86C , in the partial pixels 51, a phase difference light-shield film 1801 for phase difference detection is newly provided on a portion of the upper surface of the surface of the substrate 61 on the side of the on-chip lens 62. For example, as shown in FIG. 86B and 86C , the phase difference light-shield film 1801 shields about half of the single-sided portion at one side between the first tapping portion TA side and the second tapping portion TB side of the pixel region. FIG. 86B is an example of the pixel 51 including the first tapping portion TA and the second tapping portion TB arranged in the up-down direction (vertical direction), and FIG. 86C is an example of the pixel 51 including the first tapping portion TA and the second tapping portion TB arranged in the left-right direction (horizontal direction).

[0848] The pixel 51 according to the first configuration example of the twentieth embodiment can be arranged in the pixel array unit 20 shown in any one of FIGS. 87A-87F .

[0849] FIG. 87A shows an arrangement example of the pixel 51 in which the pixel 51 including the first tapping portion TA and the second tapping portion TB arranged in the up-down direction is arranged in a matrix shape.

[0850] FIG. 87B shows an arrangement example of the pixel 51 in which the pixel 51 including the first tapping portion TA and the second tapping portion TB arranged in the left-right direction is arranged in a matrix shape.

[0851] FIG. 87CAn example of the arrangement of the pixels 51 in which the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the up-down direction are arranged in a matrix shape and the pixel positions of the adjacent columns are shifted by half a pixel in the up-down direction is shown.

[0852] FIG. 87D An example of the arrangement of the pixels 51 in which the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the left-right direction are arranged in a matrix shape and the pixel positions of the adjacent columns are shifted by half a pixel in the up-down direction is shown.

[0853] FIG. 87E An example of the arrangement of the pixels 51 in which the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the up-down direction and the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the left-right direction are alternately arranged in the row direction and the column direction is shown.

[0854] FIG. 87F An example of the arrangement of the pixels 51 in which the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the up-down direction and the pixels 51 including the first tap portion TA and the second tap portion TB arranged in the left-right direction are alternately arranged in the row direction and the column direction and the pixel positions of the adjacent columns are shifted by half a pixel in the up-down direction is shown.

[0855] FIGS. 86A-86C The pixels 51 in the FIGS. 87A-87F are arranged in any of the arrangements of FIG. 86B and 86C The pixels 51 having the half one-sided portion shielded at the first tap portion TA side and the pixels 51 having the half one-sided portion shielded at the second tap portion TB side are arranged at adjacent positions. In addition, a plurality of groups of the pixels 51 having the half one-sided portion shielded at the first tap portion TA side and the pixels 51 having the half one-sided portion shielded at the second tap portion TB side are dispersedly arranged in the pixel array unit 20.

[0856] For example, the first configuration example of the twentieth embodiment has a configuration similar to that of the first embodiment shown in FIG. 2 , the configuration of the fourteenth embodiment shown in FIG. 36 , or the configuration of the fifteenth embodiment, with the difference that the phase difference shielding film 1801 is provided in the partial pixels 51, but other configurations are shown in a simplified manner in FIGS. 86A-86C

[0857] When the first configuration example of the twentieth embodiment is briefly explained, the first configuration example of the twentieth embodiment is different from the first embodiment shown in FIGS. 86A-86C ​The configuration of the phase difference light shielding film 1801 is shown. Each pixel 51 includes a substrate 61 composed of a P-type semiconductor layer and an on-chip lens 62 formed on the substrate 61. An inter-pixel light shielding film 63 and the phase difference light shielding film 1801 are formed between the on-chip lens 62 and the substrate 61. In the pixel 51 in which the phase difference light shielding film 1801 is formed, the inter-pixel light shielding film 1801 adjacent to the phase difference light shielding film 63 is formed to be continuous (integral) with the phase difference light shielding film 1801. Although not shown in the drawing, as shown in FIG. 2 the fixed charge film 66 is also formed on the lower surface of the inter-pixel light shielding film 63 and the phase difference light shielding film 1801.

[0858] The first tapping portion TA and the second tapping portion TB are formed on the surface of the substrate 61 opposite to the light incident surface side on which the on-chip lens 62 is formed. The first tapping portion TA corresponds to the signal extraction unit 65-1, and the second tapping portion TB corresponds to the signal extraction unit 65-2. A predetermined voltage MIX0 is supplied to the first tapping portion TA from the tapping portion driving unit 21 (30A) through a voltage supply line 30A formed in the multilayer wiring layer 811, and a predetermined voltage MIX1 is supplied to the second tapping portion TB through a voltage supply line 30B. FIG. 1

[0859] FIG. 88 is a table that collects drive modes when the tapping portion driving unit 21 drives the first tapping portion TA and the second tapping portion TB in the first configuration example of the twentieth embodiment.

[0860] In the pixel 51 including the phase difference light shielding film 1801, the phase difference can be detected by five drive methods, modes 1 to 5, as shown in FIG. 88

[0861] The drive in mode 1 is the same as the drive in the pixel 51 not including the phase difference light shielding film 180. In mode 1, the tapping portion driving unit 21 applies a positive voltage (for example, 1.5 V) to the first tapping portion TA set as an active tapping portion and applies a 0 V voltage to the second tapping portion TB set as an inactive tapping portion in a predetermined light receiving period. In the next light receiving period, the tapping portion driving unit 21 applies a positive voltage (for example, 1.5 V) to the second tapping portion TB set as an active tapping portion and applies a 0 V voltage to the first tapping portion TA set as an inactive tapping portion. A 0 V (VSS potential) is applied to the pixel transistors Tr (for example, the transfer transistor 721 and the reset transistor 723), which are formed in the multilayer wiring layer 811 at the pixel boundary region of the substrate 61. FIG. 37

[0862] ​​​In Mode 1, the phase difference can be detected from the signal when the second tap portion TB is set as an active tap portion in the pixel 51 having the half of the single-sided portion shielded at the first tap portion TA side and the signal when the first tap portion TA is set as an active tap portion in the pixel 51 having the half of the single-sided portion shielded at the second tap portion TB side.

[0863] In Mode 2, the tap portion driving unit 21 applies a positive voltage (for example, 1.5 V) to the first tap portion TA and the second tap portion TB. 0 V (VSS potential) is applied to the pixel transistor Tr formed in the pixel boundary region of the substrate 61 in the multi-layer wiring layer 811.

[0864] In Mode 2, the signal can be detected uniformly at both sides of the first tap portion TA and the second tap portion TB, and thus the phase difference can be detected from the signal of the pixel 51 having the half of the single-sided portion shielded at the first tap portion TA side and the signal of the pixel 51 having the half of the single-sided portion shielded at the second tap portion TB side.

[0865] Mode 3 relates to driving in which weighting corresponding to the image height in the pixel array unit 20 is applied to the applied voltage of the first tap portion TA and the second tap portion TB in the driving of Mode 2. More specifically, when the image height (distance from the optical center) in the pixel array unit 20 increases, a potential difference is provided in the voltage applied to the first tap portion TA and the second tap portion TB. In other words, when the image height in the pixel array unit 20 increases, the driving is performed so that the applied voltage on the tap portion side of the inside (center portion side) of the pixel array unit 20 increases. Therefore, the pupil correction can be performed by the potential difference of the voltage applied to the tap portion.

[0866] Mode 4 is a mode in which a negative bias (for example, -1.5 V) is applied to the pixel transistor Tr formed in the pixel boundary region of the substrate 61 instead of 0 V (VSS potential) in the driving of Mode 2. When the negative bias is applied to the pixel transistor Tr formed in the pixel boundary region, the electric field from the pixel transistor Tr to the first tap portion TA and the second tap portion TB can be enhanced, and thus the electron as the signal charge can be easily injected into the tap portion.

[0867] Mode 5 is a mode in which a negative bias (for example, -1.5 V) is applied to the pixel transistor Tr formed in the pixel boundary region of the substrate 61 in place of 0 V (VSS potential) in the driving of Mode 3. When a negative bias is applied to the pixel transistor Tr formed in the pixel boundary region, an electric field from the pixel transistor Tr to the first tap TA and the second tap TB can be enhanced, and thus electrons as signal charges can be easily injected into the taps.

[0868] In any one of the five driving methods of Mode 1 to Mode 5, in the pixel 51 having the half one-side portion masked at the first tap TA side and in the pixel 51 having the half one-side portion masked at the second tap TB side, a phase difference (phase shift) occurs in the readout signal due to the difference in the light shielding region, and thus the phase difference can be detected.

[0869] According to the first configuration example of the twentieth embodiment as described above, in the light receiving element 1, the partial pixels 51 of the pixel array unit 20 in which the plurality of pixels 51 including the first tap TA and the second tap TB are arranged include the pixel 51 having the half one-side portion masked at the first tap TA side by the phase difference light shielding film 1801 and the pixel 51 having the half one-side portion masked at the second tap TB side by the phase difference light shielding film 1801. Therefore, it is able to acquire phase difference information as auxiliary information in addition to the ranging information obtained from the distribution ratio of the signals between the first tap TA and the second tap TB. Based on the detected phase difference information, the focal position can be calculated and the accuracy in the depth direction can be improved.

[0870] <Second configuration example of the twentieth embodiment>

[0871] FIG. 89 A cross-sectional view of a pixel according to the second configuration example of the twentieth embodiment is shown.

[0872] In FIG. 89 the cross-sectional view, the same reference numerals are given to the portions corresponding to the first configuration example of the twentieth embodiment, and the description thereof is appropriately omitted.

[0873] In FIGS. 86A-86C the first configuration example shown, the on-chip lens 62 is formed in one pixel unit, but in FIG. 89In the second configuration example of the second configuration example, one on-chip lens 1821 is formed for a plurality of pixels 51. In some of the pixels 51, a phase difference light-shield film 1811 for phase difference detection is newly provided on a portion of the upper surface of the substrate 61 on the side of the on-chip lens 1821. The phase difference light-shield film 1811 is formed in predetermined pixels 51 among the plurality of pixels 51 that share the same on-chip lens 1821. The inter-pixel light-shield film 63 adjacent to the phase difference light-shield film 1811 is formed so as to be continuous (integral) with the phase difference light-shield film 1811, similarly to the configuration in the first configuration example.

[0874] FIGS. 90A-90F is a plan view showing the arrangement of the phase difference light-shield film 1811 and the on-chip lens 1821 employed in the second configuration example of the twentieth embodiment.

[0875] FIG. 90A shows a first arrangement example of the phase difference light-shield film 1811 and the on-chip lens 1821.

[0876] FIG. 90A The pixel group 1831 shown includes two pixels 51 arranged in the up-down direction (vertical direction), and in the pixel group 1831, one on-chip lens 1821 is arranged for the two pixels 51 arranged in the up-down direction. In addition, the arrangement of the first tapping portion TA and the second tapping portion TB in the two pixels 51 that share one on-chip lens 1821 are the same as each other. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light-shield film 1811, the phase difference is detected by using the two pixels 51 in which the phase difference light-shield film 1811 is not formed.

[0877] FIG. 90B shows a second arrangement example of the phase difference light-shield film 1811 and the on-chip lens 1821.

[0878] FIG. 90B The pixel group 1831 shown includes two pixels 51 arranged in the up-down direction, and one on-chip lens 1821 is arranged for the two pixels 51 arranged in the up-down direction. In addition, the arrangement of the first tapping portion TA and the second tapping portion TB in the two pixels 51 that share one on-chip lens 1821 are opposite to each other. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light-shield film 1811, the phase difference is detected by using the two pixels 51 in which the phase difference light-shield film 1811 is not formed.

[0879] FIG. 90C shows a third arrangement example of the phase difference light-shield film 1811 and the on-chip lens 1821.

[0880] FIG. 90CThe pixel group 1831 illustrated includes two pixels 51 arranged in the left-right direction (horizontal direction), and one on-chip lens 1821 is provided for the two pixels 51 arranged in the left-right direction. Further, the arrangement of the first tapping portion TA and the second tapping portion TB in the two pixels 51 sharing one on-chip lens 1821 are the same as each other. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light shielding film 1811, the phase difference is detected by using the two pixels 51 for which the phase difference light shielding film 1811 is not formed.

[0881] FIG. 90D A fourth arrangement example of the phase difference light shielding film 1811 and the on-chip lens 1821 is illustrated.

[0882] FIG. 90D The pixel group 1831 illustrated includes two pixels 51 arranged in the left-right direction (horizontal direction), and one on-chip lens 1821 is provided for the two pixels 51 arranged in the left-right direction. Further, the arrangement of the first tapping portion TA and the second tapping portion TB in the two pixels 51 sharing one on-chip lens 1821 are opposite to each other. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light shielding film 1811, the phase difference is detected by using the two pixels 51 for which the phase difference light shielding film 1811 is not formed.

[0883] FIG. 90E A fifth arrangement example of the phase difference light shielding film 1811 and the on-chip lens 1821 is illustrated.

[0884] FIG. 90E The pixel group 1831 illustrated includes four pixels 51 arranged in 2 x 2, and one on-chip lens 1821 is provided for the four pixels 51. The arrangement of the first tapping portion TA and the second tapping portion TB in the four pixels 51 sharing one on-chip lens 1821 are the same as each other. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light shielding film 1811, the phase difference is detected by using the four pixels 51 for which the phase difference light shielding film 1811 is not formed.

[0885] FIG. 90F A sixth arrangement example of the phase difference light shielding film 1811 and the on-chip lens 1821 is illustrated.

[0886] FIG. 90F The pixel group 1831 illustrated includes four pixels 51 arranged in 2 x 2, and one on-chip lens 1821 is provided for the four pixels 51. The arrangement of the first tapping portion TA and the second tapping portion TB in the four pixels 51 sharing one on-chip lens 1821 are opposite to each other in the left and right pixels. In the two pixel groups 1831 symmetrical in the formation position of the phase difference light shielding film 1811, the phase difference is detected by using the four pixels 51 for which the phase difference light shielding film 1811 is not formed.

[0887] As described above, as the arrangement in the case where one on-chip lens 1821 is formed for a plurality of pixels 51, either of an arrangement in which one on-chip lens 1821 is arranged for two pixels or an arrangement in which one on-chip lens 1821 is arranged for four pixels can be employed. The phase difference light shielding film 1811 shields a plurality of pixels corresponding to a half of the single-sided portion below one on-chip lens 1821.

[0888] As the drive mode in the second configuration example, any of the five drive methods including the modes 1 to 5 described with reference to FIGS. 17A to 17E can be employed. FIG. 88

[0889] Therefore, according to the second configuration example of the twentieth embodiment, in the partial pixels 51 of the pixel array unit 20 in which the plurality of pixels 51 including the first tapping portion TA and the second tapping portion TB are arranged, two pixel groups 1831 in which the formation positions of the phase difference light shielding films 1811 are symmetrical are included. Therefore, phase difference information as auxiliary information in addition to the ranging information obtained by the distribution ratio of the signals between the first tapping portion TA and the second tapping portion TB can be acquired. Based on the detected phase difference information, the focal position can be calculated and the accuracy in the depth direction can be improved.

[0890] Note that, as the plurality of pixels 51 constituting the pixel array unit 20, the pixels 51 in the first configuration example of the twentieth embodiment and the pixels 51 in the second configuration example of the twentieth embodiment can be mixed.

[0891] <Modification Example Without Phase Difference Light Shielding Film>

[0892] In the first configuration example and the second configuration example of the twentieth embodiment, the configuration in which the phase difference light shielding film 1801 or 1811 is provided between the on-chip lens 62 and the substrate 61 has been described.

[0893] However, even in the pixels 51 not including the phase difference light shielding film 1801 or 1811, the phase difference information can be obtained at the time of driving in the modes 2 to 5 in which the positive voltage is simultaneously applied to the first tapping portion TA and the second tapping portion TB among the five drive methods in the modes 1 to 5. For example, the phase difference information can be acquired by driving a half of the single-sided pixels 51 among the plurality of pixels below one on-chip lens 1821 in the modes 2 to 5. Even in the configuration in which one on-chip lens 62 is provided for one pixel, the phase difference information can be acquired by driving the pixel in the modes 2 to 5.

[0894] ​Thus, in the pixel 51 that does not include the phase difference shading film 1801 or 1811, the phase difference information can be acquired by performing the driving in the modes 2 to 5. Even in this case, the focal position can be calculated based on the detected phase difference information, and the accuracy in the depth direction can be improved.

[0895] Note that, in the pixel 51 that does not include the phase difference shading film 1801 or 1811, in a case where it is desired to acquire the phase difference information by using the driving in the mode 1, the phase difference information can be acquired when the irradiation light emitted from the light source is set to continuous light that is continuously emitted without interruption.

[0896] <Twenty-First Embodiment>

[0897] Next, a configuration example of the light-receiving element 1 capable of acquiring polarization degree information as auxiliary information in addition to the distance measurement information obtained in accordance with the distribution ratio of the signals between the first tapping portion TA and the second tapping portion TB will be described.

[0898] FIG. 91 A cross-sectional view of the pixel according to the twenty-first embodiment is shown.

[0899] In FIG. 91 , the same reference numerals are given to portions corresponding to the twentieth embodiment, and the description thereof is appropriately omitted.

[0900] In FIG. 91 , the twenty-first embodiment, the polarization filter 1841 is provided between the on-chip lens 62 and the substrate 61. For example, the pixel 51 according to the twenty-first embodiment has a configuration similar to that of the first embodiment shown in FIG. 2 , the fourteenth embodiment shown in FIG. 36 , or the fifteenth embodiment, but differs in that the polarization filter 1841 is provided.

[0901] The polarization filter 1841, the on-chip lens 62, the first tapping portion TA, and the second tapping portion TB are arranged in any one of the arrangements in FIG. 92A or FIG. 92B .

[0902] FIG. 92A is a plan view showing a first arrangement example of the polarization filter 1841, the on-chip lens 62, the first tapping portion TA, and the second tapping portion TB in the twenty-first embodiment.

[0903] As shown in FIG. 92A , the polarization filter 1841 has any one of polarization directions between 0°, 45°, 90°, and 135°, and four kinds of polarization filters 1841 having polarization directions that differ by 45° are formed in a unit of four pixels (2 x 2) in predetermined pixels 51 of the pixel array unit 20.

[0904] The on-chip lens 62 is arranged in units of pixels, and the positional relationship between the first tapping portion TA and the second tapping portion TB is the same as each other throughout the pixels.

[0905] FIG. 92B is a plan view showing a second arrangement example of the polarizer filter 1841, the on-chip lens 62, the first tapping portion TA, and the second tapping portion TB in the twenty-first embodiment.

[0906] As FIG. 92B indicated, the polarization filter 1841 has any one of polarization directions between 0°, 45°, 90°, and 135°, and four kinds of polarization filters 1841 having polarization directions differing by 45° are formed in units of four pixels (2 x 2) in predetermined pixels 51 of the pixel array unit 20.

[0907] The on-chip lens 62 is arranged in units of pixels, and the positional relationship between the first tapping portion TA and the second tapping portion TB is opposite to each other between adjacent pixels in the horizontal direction. In other words, pixel columns in which the arrangement of the first tapping portion TA and the second tapping portion TB are opposite to each other are alternately arranged in the horizontal direction.

[0908] As the driving method of the pixel 51 including the polarization filter 1841, five kinds of driving methods in Mode 1 to Mode 5 explained with reference to FIG. 88 in the twentieth embodiment are possible.

[0909] In the twenty-first embodiment, among the plurality of pixels 51 arranged in the pixel array unit 20, a plurality of partial pixels 51 include the polarization filter 1841 as FIG. 91 and FIG. 92A and FIG. 92B indicated.

[0910] When the pixel 51 including the polarization filter 1841 is driven by any one of Mode 1 to Mode 5, polarization degree information can be acquired. Based on the acquired polarization degree information, information related to the surface state (unevenness) and the relative distance difference of the object surface as a subject can be acquired, the reflection direction can be calculated, or ranging information of a transparent object such as glass and ranging information to an object in front of...

Claims

1. A light-receiving element comprising: an on-chip lens; a wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer, wherein the semiconductor layer includes: a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit disposed at a periphery of the first voltage application unit, a second charge detection unit disposed at a periphery of the second voltage application unit, and a charge discharge region provided outside an effective pixel region, wherein the charge discharge region includes a light-shielded pixel that is driven.

2. The light-receiving element according to claim 1, wherein the wiring layer includes at least one layer including a reflecting member, and the reflecting member is disposed so as to overlap the first charge detection unit and / or the second charge detection unit in a plan view.

3. The light-receiving element according to claim 1, wherein the wiring layer includes at least one layer including a light-shielded member, and the light-shielded member is disposed so as to overlap the first charge detection unit and / or the second charge detection unit in a plan view.

4. The light-receiving element according to claim 1, wherein the charge discharge region includes an open pixel that is driven.

5. The light-receiving element according to claim 1, wherein the charge discharge region includes a high-concentration N-type region to which zero voltage or positive voltage is applied.

6. The light-receiving element according to claim 1, further comprising: a P-well region at a boundary portion of a pixel that contacts an insulating film at a periphery of the first charge detection unit and the second charge detection unit.

7. The light-receiving element according to claim 6, wherein an impurity concentration of the P-well region is higher than an impurity concentration of a photoelectric conversion region.

8. The light-receiving element according to claim 1, further comprising: an N-type diffusion layer in a gap region between an insulating film at a periphery of the first charge detection unit and the second charge detection unit and a P-well region in which a pixel transistor is formed, to which zero voltage or positive voltage is applied.

9. The light-receiving element according to claim 8, wherein the N-type diffusion layer is disposed to be shared by a column of pixels inside the effective pixel region.

10. The light-receiving element according to claim 8, wherein the N-type diffusion layer is disposed in a pixel outside the effective pixel region.

11. The light-receiving element according to claim 8, wherein the N-type diffusion layer is disposed in each pixel inside the effective pixel region.

12. The light-receiving element according to any one of claims 1 to 11, wherein the first voltage application unit and the second voltage application unit are constituted by a first P-type semiconductor region and a second P-type semiconductor region formed in the semiconductor layer, respectively.

13. The light-receiving element according to any one of claims 1 to 11, wherein the first voltage application unit and the second voltage application unit are constituted by a first transfer transistor and a second transfer transistor formed in the semiconductor layer, respectively.

14. A distance measuring module comprising: The light-receiving element according to any one of claims 1 to 13; a light source that emits irradiation light having a luminance that fluctuates periodically; and a light emission control unit that controls an irradiation timing of the irradiation light.

Images