Solid state drive and method for metadata access

Abstract

A solid-state drive and a method for metadata access are provided. The solid-state drive includes a first memory and a second memory of different kinds and a memory controller that controls the first memory and the second memory, wherein the memory controller receives a metadata access request from a host and includes a condition checker that determines a condition of the first memory and a condition of the second memory in response to the metadata access request and selects at least one of the first memory and the second memory, and the memory controller accesses the memory selected by the condition checker.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0085788 filed on Jul. 24, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a solid state drive and a method for accessing metadata for a solid state drive. Background Art

[0004] A solid-state drive (SSD) is a storage device that stores information in semiconductor memory (usually NAND flash memory). SSDs have advantages over mechanical hard disk drives (HDDs), including high speed, less mechanical delay, lower failure rate, reduced heat generation, less noise, and can be made smaller and lighter than hard disk drives. In particular, since there is no physical drive device in an SSD, there is no noise and the data processing speed is very fast.

[0005] A new solid-state drive has been developed for forming a composite solution by adding a memory of a different kind from NAND flash memory to a conventional solid-state drive having NAND flash memory. This composite solution device may have better operating performance according to the characteristics of the different memories. Summary of the invention

[0006] Aspects of the present invention provide solid state drives that can exhibit improved operating performance.

[0007] Aspects of the present invention provide a metadata access method for a solid state drive that can exhibit improved operating performance.

[0008] Aspects of the present invention are not limited to those mentioned above and another aspect not mentioned which can be clearly understood by those skilled in the art from the following description.

[0009] According to one aspect of the inventive concept, a solid-state drive is provided. The solid-state drive includes a first memory and a second memory of different types from each other, and a memory controller that controls the first memory and the second memory, wherein the memory controller receives a metadata access request from a host and includes a condition checker, the condition checker determines conditions of the first memory and the second memory in response to the metadata access request, and selects at least one of the first memory and the second memory based on at least one of the conditions of the first memory and the conditions of the second memory, and the memory controller accesses the selected memory by the condition checker.

[0010] According to another exemplary embodiment of the present invention, a solid-state drive is provided. The solid-state drive includes a first memory storing first metadata, a second memory storing second metadata identical to the first metadata and different from the first memory type, and a memory controller controlling the first memory and the second memory, and includes a condition checker configured to determine a condition of the first memory and a condition of the second memory and select one of the first memory and the second memory with a better condition, wherein the memory controller receives a metadata read request from a host, and reads one of the first metadata and the second metadata stored in the first memory and the second memory selected by the condition checker in response to the metadata read request.

[0011] According to another aspect of the present invention, a metadata access method of a solid state drive (SSD) is provided, which includes at least a first memory and a second memory of different types from each other. The method includes receiving a metadata read request from a host, determining a condition of the first memory and a condition of the second memory to select one of the first memory and the second memory, and reading metadata of the selected memory in the first memory and the second memory.

[0012] According to another aspect of the present invention, there is provided a device, comprising: a first memory configured to store therein first metadata; a second memory configured to store therein second metadata, wherein the second memory is of a different type from the first memory; and a memory controller configured to control memory access operations for the first memory and the second memory. The memory controller includes a condition checker. The memory controller is configured to receive a metadata access request from outside the device, and the condition checker is configured to determine a first condition of the first memory device and determine a second condition of the second memory device in response to the metadata access request, and is configured to select at least one of the first memory and the second memory based on the first condition and the second condition. The memory controller is configured to perform a metadata access operation for at least one of the selected first memory and the second memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the attached drawings.

[0014] Figure 1 is a block diagram illustrating an example embodiment of a solid state drive system.

[0015] Figure 2 It is shown Figure 1 A block diagram of an example embodiment of a solid state drive.

[0016] Figure 3 It is shown in detail Figure 2 A block diagram of an embodiment of a memory controller and a memory.

[0017] Figure 4 It is shown in detail Figure 3 An exemplary view of a table of characteristics of the operation of a condition checker.

[0018] Figure 5 From the interface perspective Figure 3 A block diagram of an example embodiment of a memory controller.

[0019] Figure 6 It is shown in detail Figure 3 A block diagram of the structure of the second memory.

[0020] Figure 7 yes Figure 6 FIG. 1 is an exemplary equivalent circuit diagram of a memory block of a second memory.

[0021] Figure 8 yes Figure 6 FIG. 1 is an exemplary perspective view of a memory block of a second memory.

[0022] Fig. 9 is an exemplary perspective view of a memory block of a second memory of an exemplary embodiment of a solid state drive.

[0023] Fig.10 is a timing diagram illustrating a programming operation of an example embodiment of a solid state drive.

[0024] Fig.11 is a block diagram illustrating an example embodiment of a solid state drive.

[0025] Fig.12 is a block diagram illustrating another example embodiment of a solid state drive.

[0026] Fig.13 is a block diagram illustrating yet another example embodiment of a solid state drive.

[0027] Fig.14 is a timing diagram illustrating an example embodiment of a programming operation of a solid state drive.

[0028] Fig.15 is a timing diagram illustrating another example embodiment of a programming operation of a solid state drive.

[0029] Fig.16 is a timing diagram illustrating yet another example embodiment of a programming operation of a solid state drive.

[0030] Fig.17 is a flow chart illustrating an example embodiment of a metadata access method for a solid state drive.

[0031] Fig.18 is a flow chart illustrating another example embodiment of a metadata access method for a solid state drive. DETAILED DESCRIPTION

[0032] In the following, reference will be made to Figures 1 to 10 Semiconductor devices according to some embodiments of the present invention are described.

[0033] Figure 1 is a block diagram illustrating an example embodiment of a solid state drive system.

[0034] refer to Figure 1 The solid state drive system includes a host 10 and a solid state drive 20.

[0035] The host 10 may be coupled to the solid state drive 20 from the outside of the solid state drive 20. The host 10 may be connected to the solid state drive 20 via a host interface (I / F). The host 10 may control data processing operations (e.g., programming operations, erasing operations, and reading operations) of the solid state drive 20.

[0036] The host 10 may be implemented as a host processor, an integrated circuit (IC), a motherboard, a system on chip (SoC), an application processor (AP), a mobile AP, a network server, a data server, or a database server, but is not limited thereto.

[0037] The solid state drive 20 may send commands and / or data to and receive commands and / or data from the host 10 via the host interface. The solid state drive 20 may be implemented as a flash memory-based memory, but is not limited thereto. For example, the solid state drive 20 may be implemented as a solid state drive (SSD) or an embedded SSD (eSSD), but is not limited thereto.

[0038] The host 10 and the solid-state drive 20 may be connected to each other to implement a single data processing system. The data processing system may be implemented as, for example, a PC (personal computer), a workstation, a data center, an Internet data center (IDC), a DAS (direct attached storage) system, a SAN (storage area network) system, a NAS (network attached storage) system, a RAID (redundant array of inexpensive disks or redundant array of independent disks) system, or a mobile device, but is not limited thereto.

[0039] In addition, the mobile device may be implemented as, for example, a laptop, a mobile phone, a smart phone, a tablet PC, a PDA (Personal Digital Assistant), an EDA (Enterprise Digital Assistant), a digital camera, a digital video camera, a PMP (Portable Multimedia Player), a PND (Personal Navigation Device or Portable Navigation Device), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, or an e-book, but is not limited thereto.

[0040] Figure 2 It is shown Figure 1 A block diagram of an example embodiment of a solid state drive.

[0041] refer to Figure 2 , the solid state drive includes a host interface 300 , a processing core 100 , a volatile memory 200 , a power control module 400 , a memory controller 500 , and a non-volatile memory 600 .

[0042] The host interface 300 may be a transmission path for commands and / or data between the host 10 and the solid state drive 20. According to various embodiments, the host interface 300 may be implemented as a SATA (Serial Advanced Technology Attachment) interface, a SATAe (SATA Express) interface, a SAS (Serial Attached Small Computer System Interface (SCSI)) interface, a PCIe (Peripheral Component Interconnect Express) interface, an NVMe (Non-Volatile Memory Express) interface, an AHCI (Advanced Host Controller Interface) interface, or a Multimedia Card (MMC) interface, but is not limited thereto.

[0043] According to various embodiments, the host 300 may transmit an electrical signal or an optical signal.

[0044] The processing core 100 may perform operations of the solid state drive 20. Specifically, an operation of a data processing command transmitted by the host 10 and a refresh operation of the nonvolatile memory 600, etc. may be performed.

[0045] The processing core 100 may include a first core 101 and a second core 102. The first core 101 and the second core 102 may be the same type of cores or may be different types of cores from each other. The first core 101 and the second core 102 may respectively perform different operations.

[0046] exist Figure 2 In the embodiment, although the processing core 100 is shown as two cores of the first core 101 and the second core 102, the embodiment is not limited thereto. In some embodiments, the number of the processing cores may be one or three or more.

[0047] The processing core 100 may perform operations on data processing commands and refresh operations of the nonvolatile memory 600 together with the volatile memory 200. The volatile memory 200 may be, for example, a DRAM (Dynamic Random Access Memory). The volatile memory 200 may perform the role of a buffer memory to perform the above operations.

[0048] The power control module 400 can control the power supplied to the solid state drive 20. The power control module 400 can be controlled from the host ( Figure 110) receives power supply and controls the power. Alternatively or additionally, the power control module 400 may receive power supply from a battery located therein.

[0049] The memory controller 500 may control the nonvolatile memory 600. Figure 1 When a host 10 of the memory controller 500 receives a request, the memory controller 500 may access the nonvolatile memory 600. Therefore, the memory controller 500 may control the transmission or processing of a command to the nonvolatile memory 600 and data to / from the nonvolatile memory 600.

[0050] Specifically, the memory controller 500 may perform a program operation, a read operation, and an erase operation on the nonvolatile memory 600. The memory controller 500 will be described in more detail later.

[0051] The nonvolatile memory 600 may internally program or store data according to a request from a host, or read data stored therein. The nonvolatile memory 600 may include a first memory 610 and a second memory 620.

[0052] The first memory 610 and the second memory 620 may be memory devices of different kinds or types from each other. Here, the "type" of the memory device refers to the type of technology used to store data in the memory device. For example, each of the first memory 610 and the second memory 620 may be one of PRAM (phase change random access memory), RRAM (resistive random access memory), MRAM (magnetic random access memory) and NAND flash memory. For convenience, it is assumed below that the first memory 610 is PRAM and the second memory 620 is NAND flash memory.

[0053] exist Figure 2 In the embodiment, the first memory 610 may be connected to the first channel Ch1, and the plurality of second memories 620 may be connected to the second channel Ch2, the third channel Ch3, and the fourth channel Ch4. That is, the second memory 620 may include a first channel memory 621 connected to the second channel Ch2, a second channel memory 622 connected to the third channel Ch3, and a third channel memory 623 connected to the fourth channel Ch4.

[0054] at this time, Figure 2 The configuration is only an example, and the memory may be arranged in any other form. That is, a plurality of first memories 610 may be connected to a plurality of channels, and a single second memory 620 may be connected to one channel. Moreover, the total number of memories is not limited.

[0055] As described above, the second memory 620 may include a three-dimensional NAND flash memory array. The second memory 620 may be monolithically formed on one or more physical levels of a memory cell array having an active region disposed above a silicon substrate and circuits associated with the operation of the memory cells. The circuits associated with the operation of the memory cells may be located within or above the substrate. The term "monolithically" means that the layers of each level of the three-dimensional array are deposited directly on the layers of the lower levels of the three-dimensional array.

[0056] In an exemplary embodiment, a three-dimensional memory array has a vertical directionality and includes a vertical NAND string in which at least one memory cell is located above another memory cell. At least one memory cell includes a charge trapping layer. Each vertical NAND string may include at least one selection transistor located above the memory cell. At least one selection transistor has the same structure as the memory cell and may be formed monolithically with the memory cell. This will be described in more detail later.

[0057] The system bus 700 may connect the host interface 300, the volatile memory 200, the processing core 100, the memory controller 500 connected to the nonvolatile memory 600, and the power control module 400. That is, movement of data and requests may be performed via the system bus 700.

[0058] Figure 3 It is shown in detail Figure 2 A block diagram of an embodiment of a memory controller and a memory, and Figure 4 It is shown in detail Figure 3 Example of a table of properties for the condition checker's actions.

[0059] refer to Figure 3 , the memory controller 500 may include a flash translation layer (FTL) 510 , a condition checker 520 , and a property table 530 .

[0060] In response to a request from the host (e.g. Figure 1 In response to a data access request from a host 10), the flash translation layer 510 may convert a logical address received from the host into a physical address and provide the physical address to the nonvolatile memory 600.

[0061] In addition, the flash translation layer 510 may perform management operations of various unit areas (eg, chip unit, block unit, page unit, etc.) of the nonvolatile memory 600. For example, garbage collection and bad block management operations of multiple blocks of the nonvolatile memory 600 may be performed.

[0062] In addition, the flash translation layer 510 may perform wear leveling. Wear leveling refers to the dispersion of memory operations between cells of the NAND flash memory. If the cells of the NAND flash memory undergo programming and erasing processes too frequently, the cells of the NAND flash memory may be in an unstable state (wear). Therefore, the memory operations between the cells of the NAND flash memory are dispersed so that each block reaches the limit of the program / erase (P / E) cycle at the same time or almost at the same time.

[0063] The condition checker 520 may check the conditions of each memory. That is, the first memory 610 may have an associated first condition that may change over time, and the second memory 620 may have an associated second condition that may change over time, and the first condition and the second condition may be different from each other at any given point in time. The condition checker 520 may determine what the current conditions of the first memory 610 and the second memory 620 are.

[0064] The first memory 610 and the second memory 620 may each contain the same metadata. That is, the first memory 610 may store the first metadata MD1 and the second memory 620 may store the second metadata MD2, wherein the first metadata MD1 and the second metadata MD2 may be mirror data having the same content.

[0065] The metadata may be important data for initial driving of the solid state drive 20. That is, the metadata may include data for security authentication, data for initial driving of firmware, and data for firmware debugging.

[0066] Solid-state drive 20 according to some embodiments may prepare for corruption of metadata by mirroring such metadata and storing it in a different class or type of storage.

[0067] When there is an access request for metadata (ie, a read request for metadata) from the host 10, the memory controller 500 receives the access request for metadata, and the condition checker 520 may determine which memory of the first memory 610 and the second memory 620 has a better condition.

[0068] The condition checker 520 may determine a current condition of the first memory 610 and may determine a current condition of the second memory 620. The condition checker 520 may compare the condition of the first memory 610 with the condition of the second memory 620 to select a memory having a better condition.

[0069] The memory condition comparison method of the condition checker 520 can be various. For example, the condition checker 520 can refer to the characteristic table 530. Figure 35. The characteristic table 530 is shown as being located outside the condition checker 520, but the embodiment is not limited thereto. That is, the characteristic table 530 may be located inside the condition checker 520 or may be completely stored in another memory outside the memory controller 500. That is, the location of the characteristic table 530 may not be limited except that it may be accessed by the condition checker 520.

[0070] The characteristic table 530 may include a characteristic table of the first memory 610 and a characteristic table of the second memory 620. The characteristic table 530 may include condition scores corresponding to the state values.

[0071] The state value may be a value of the current memory state. The state value may be, for example, at least one of temperature, P / E cycle, program retention time, and erase retention time. However, the embodiment is not limited thereto, and a condition score of another state value may be stored in the characteristic table 530.

[0072] In the case of temperature, at high temperatures, the condition of the NAND flash memory may be better than that of the PRAM. If the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, the condition checker 520 may give a high score to the second memory 620 at high temperatures.

[0073] For example, the state value of the first memory 610 may be t2 among t1 to t4, and its condition score may be a2. In contrast, the state value of the second memory 620 may be t3, and its condition score may be b3 among b1 to b4. At this time, b1 to b4 may be values ​​different from a1 to a4. This may be attributed to the characteristic difference between PRAM and NAND flash memory.

[0074] In the case of P / E cycles, since the reliability of the NAND flash memory decreases as the number of P / E cycles increases, a score reflecting this decrease may be stored in the characteristic table 530. The program retention time indicates the time left unattended after being last programmed, and the erase retention time may indicate the time left unattended after being last erased. As the program retention time and the erase retention time increase, the NAND flash memory threshold voltage distribution may be widened by the action of electrons / holes in the cells of the NAND flash memory. That is, as the program retention time or the erase retention time increases, the reliability of the second memory 620 as the NAND flash memory may decrease.

[0075] The characteristic table 530 may store a condition score corresponding to each of the above-mentioned state values ​​reflecting the above-mentioned characteristics. The condition checker 520 may receive current state information from the first memory 610 and the second memory 620, respectively. At this time, the current state information may include a state value.

[0076] A plurality of status values ​​may be applied. For example, when all temperatures and P / E cycles are considered, the condition scores of the first memory 610 and the second memory 620 may be compared by adding the condition score according to temperature and adding the condition score according to P / E cycle.

[0077] The condition checker 520 may select a memory having a higher condition score among the first memory 610 and the second memory 620. That is, the condition checker 520 may select a memory having a better condition among memories of different kinds or types.

[0078] The memory controller 500 may respond to a host (eg, Figure 1 The memory controller 500 reads metadata of the memory selected by the condition checker 520 in response to a metadata read request of the host 10). That is, when the condition checker 520 selects the first memory 610, the memory controller 500 reads the first metadata MD1 of the first memory 610, and conversely, when the condition checker 520 selects the second memory 620, the memory controller 500 may read the second metadata MD2 of the second memory 620.

[0079] In this embodiment, since metadata in a better condition can be accessed through the above process, the operation performance and reliability of the solid state drive 20 can be greatly improved.

[0080] Figure 5 From the interface perspective Figure 3 A block diagram of an embodiment of a memory controller.

[0081] refer to Figure 5 , the memory controller 500 may include a volume interface (Volume interface) 501. The volume interface 501 may include a secure volume 502, a firmware (F / W) volume 503, a debug volume 504, and a user volume 505.

[0082] The secure volume 502 may be an area for security authentication of the solid state drive 20. The firmware volume 503 may be an area for a firmware driver of the solid state drive 20. The debug volume 504 may be an area for debugging the solid state drive 20. The user volume 505 may be an area for direct access by a user.

[0083] These areas need to be accessed to one of the first memory 610 and the second memory 620 eventually, and one of the first memory 610 and the second memory 620 can be selected and accessed by the dynamic selector 506. The dynamic selector 506 can be selected according to Figure 3 The operation of the condition checker 520 allows selective access.

[0084] Since the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, there may be a PRAM interface 507 for accessing the first memory 610 and a NAND interface 508 for accessing the second memory 620 .

[0085] The PRAM interface 507 may allow access to the first memory 610 , and the NAND interface 508 may allow access to the second memory 620 .

[0086] In the following, reference will be made to Figures 6 to 8 The structure of a NAND flash memory constituting the second memory 620 of the solid state drive 20 according to some embodiments is described in detail.

[0087] Figure 6 It is shown in detail Figure 3 A block diagram of the structure of the second memory, and Figure 7 yes Figure 6 FIG. 1 is an exemplary equivalent circuit diagram of a memory block of a second memory. Figure 8 yes Figure 6 FIG. 1 is an exemplary perspective view of a memory block of a second memory.

[0088] For convenience, Figure 6 Only the first channel memory 621 of the second memory 620 is shown. The second channel memory 622 and the third channel memory 623 may also have the same or similar structure as the first channel memory 621.

[0089] refer to Figure 6 The first channel memory 621 includes a plurality of memory blocks (BLK1 to BLKz, z is an integer of 2 or more). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of pages (page 1 to page m, m is an integer of 2 or more).

[0090] refer to Figure 7 , the memory block BLK includes strings connected to a plurality of bit lines (BL1 to BLn, n is an integer of 2 or more). Here, each string includes at least one string selection transistor SST connected in series between the bit line and a common source line CSL, a plurality of memory cells (MC1 to MCm, m is an integer of 2 or more), and at least one ground selection transistor GST.

[0091] Each of the memory cells (MC1 to MCm) may store at least one bit or more of data. Although not shown, each string may include at least one dummy cell between the string selection transistor SST and the memory cells (MC1 to MCM), and at least one dummy cell between the memory cells (MC1 to MCM) and the ground selection transistor GST.

[0092] refer to Figure 8 , four sub-blocks are formed on the substrate. Each sub-block is formed by stacking at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL between word line cutouts (WL cutouts) on the substrate in the form of a plate. Here, at least one string selection line SSL is separated by a string selection line cutout (string cutout). Figure 8 There is a string selection line cut in the memory block BLKa, but the embodiment is not limited thereto. That is, the memory block BLKa may be implemented so that there is no string selection line cut.

[0093] The first direction (1st) and the second direction (2nd) may intersect each other, and the third direction (3rd) may intersect the first direction (1st) and the second direction (2nd). For example, the first direction (1st), the second direction (2nd), and the third direction (3rd) may be orthogonal directions relative to each other.

[0094] The ground selection lines GSL, word lines WL, and string selection lines SSL extend in the second direction and may be spaced apart from each other in the first direction by word line cuts and string selection line cuts. In addition, the ground selection lines GSL, word lines WL, and string selection lines SSL may be sequentially stacked in the third direction.

[0095] In some embodiments, at least one dummy word line may be stacked in the form of a plate between the ground selection line GSL and the word line WL, or at least one dummy word line may be stacked in the form of a plate between the word line WL and the string selection line SSL.

[0096] Although not shown, each word line cutout includes a common source line CSL. In an embodiment, the common source line CSL included in each word line cutout is connected in common. The pillar connected to the bit line penetrates at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL to form a string.

[0097] exist Figure 8 In FIG. 1 , the targets between the word line cuts are shown as sub-blocks, but the embodiments are not necessarily limited thereto. Figure 8 In the embodiment of the present invention, the target between the word line cut and the string selection line cut may be referred to as a sub-block.

[0098] The block BLKa may be implemented as a structure in which two word lines are merged into one (in other words, a merged word line structure).

[0099] Fig. 9 is an exemplary perspective view of a memory block of a second memory of an exemplary embodiment of a solid state drive.

[0100] Fig. 9 The structure of the block BLKb may be different from Figure 8 Block BLKa structure.

[0101] refer to Fig. 9 For ease of explanation, the number of word line layers in the memory block BLKb is limited to four, but the embodiment is not limited thereto. The memory block BLKb may be implemented as a pipe-shaped bit costscalable (pBiCS) structure in which lower ends of adjacent memory cells are connected in series through pipes.

[0102] The memory block BLKb includes m×n (m and n are natural numbers) strings (NS). Fig. 9 In FIG. 1 , an example in which m=6 and n=2 is shown, which has 12 strings NS. Each string NS includes memory cells (MC1 to MC8) connected in series. Here, the first upper end of the memory cell (MC1 to MC8) is connected to the string selection transistor SST, and the second upper end of the memory cell (MC1 to MC8) is connected to the ground selection transistor (GST), and the lower end of the memory cell (MC1 to MC8) is connected through a transistor.

[0103] The word lines (WL1 to WL8) extend in a first direction (1st), and the strings NS may extend in a third direction (3rd). The word lines (WL1 to WL8) and the strings NS may be spaced apart from each other in a second direction (2nd).

[0104] The memory cells constituting the string NS are formed by stacking on a plurality of semiconductor layers. Each string NS includes a first column P11, a second column P12, and a column connection portion P13 for connecting the first column P11 and the second column P12 to each other. The first column P11 is connected to a bit line (e.g., BL1) and the column connection portion P13, and is formed by penetrating a string selection line SSL and a word line (WL5 to WL8). The second column P12 is connected to a common source line CSL and a column connection portion P13, and is formed by penetrating a ground selection line GSL and a word line (WL1 to WL4). Fig. 9 As shown, the string NS is realized in the form of a U-shaped column.

[0105] At this time, the first pillar P11 and the second pillar P12 extend in the third direction, and the pillar connection portion P13 may be connected in the second direction.

[0106] In some embodiments of the present invention, the back gate BG is formed on the substrate, and the pillar connection portion P13 may be implemented inside the back gate BG. In an embodiment, the back gate BG may generally exist in the block BLKb. The back gate BG may have a structure separated from the back gate of another block.

[0107] Fig.10 is a timing diagram illustrating a programming operation of an example embodiment of a solid state drive.

[0108] refer to Figure 3 and Fig.10 , the method for programming the solid state drive 20 according to some embodiments may be different from the reading method.

[0109] The memory controller 500 receives data from the host ( Figure 1 10) receiving a metadata programming request. When the memory controller 500 receives the metadata programming request, the condition checker 520 checks the conditions of the first memory 610 and the second memory 620.

[0110] Similar to the above-described manner, the condition checker 520 may select a memory having a better condition between the first memory 610 and the second memory 620. As a result, the memory controller 500 may program metadata in the memory selected by the condition checker 520 first.

[0111] Assuming that the condition checker 520 has selected the first memory 610 , the memory controller 500 may program the first metadata MD1 in the first memory 610 at the first time t1 .

[0112] The memory controller 500 may program the second metadata MD2 in the second memory 620 which is not selected by the condition checker 520 immediately without programming the first metadata MD1 .

[0113] The condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and when the condition of the second memory 620 becomes better than the condition of the first memory 610 at the first time t1, the second metadata MD2 may be programmed in the second memory 620 at the second time t2. The second time t2 may be a time after the first time t1.

[0114] Here, the time when the condition of the second memory 620 becomes better may mean the time when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is greater than or equal to a preset specific value or threshold.

[0115] Although the time is different, the first metadata MD1 and the second metadata MD2 may be data of the same content mirroring each other. This may be for the purpose of repeatedly storing metadata so that the metadata can be read from a storage with better conditions at a later metadata reading time.

[0116] In the following, reference will be made to Fig.11 An embodiment of a solid state drive is described. Repeated parts of the above description will be omitted or simplified.

[0117] Fig.11 is a block diagram illustrating an example embodiment of a solid state drive.

[0118] exist Fig.11 In the solid-state drive of FIG. 6 , the mirror metadata may exist not only in the first channel memory 621 but also in each of the second channel memory 622 and the third channel memory 623 .

[0119] Specifically, the third metadata MD3 is stored in the second channel memory 622 connected to the third channel Ch3, and the fourth metadata MD4 may be stored in the third channel memory 623 connected to the fourth channel Ch4.

[0120] As a result, the condition checker 520 may compare the first memory 610 , the first channel memory 621 , the second channel memory 622 , and the third channel memory 623 together to select any one of them, rather than simply comparing the condition scores of the first memory 610 and the second memory 620 .

[0121] Here, the first metadata MD1, the second metadata MD2, the third metadata MD3, and the fourth metadata MD4 are all metadata mirrors having the same content.

[0122] In the embodiment of the solid-state drive 20, even in memories of the same kind or type in different channels, state values ​​such as temperature, P / E cycle, program retention time, and erase retention time may be different. Therefore, it is possible to select a memory of the best condition among memories of the same kind or type and read metadata therefrom.

[0123] Therefore, since the metadata is read without damaging the metadata, the overall operational performance of the solid state drive 20 can be greatly improved.

[0124] In the following, reference will be made to Fig.12 Another exemplary embodiment of a solid state drive is described. Repeated portions of the above description will be omitted or simplified.

[0125] Fig.12 is a block diagram illustrating another example embodiment of a solid state drive.

[0126] refer to Fig.12 , the memory controller 500 of the solid state drive may include characteristic parameters 531.

[0127] The characteristic parameter 531 may include a characteristic parameter of the first memory 610 and a characteristic parameter of the second memory 620. The characteristic parameter 531 may be a parameter multiplied by a state value.

[0128] For example, a condition checker may use a condition such as y=a 1 X 1 +a 2 X 2 +a 3X 3 Here, y is the conditional score, X 1 , X 2 and X 3 The state values ​​of temperature, P / E cycle and programming retention time can be respectively. 1 、a 2 and a 3 Can be X 1 , X 2 and X 3 parameters and can be stored in feature parameters 531.

[0129] The above parameters are stored for each memory and are available to the condition checker 520 to derive a condition score for each memory.

[0130] In this case, the formula may be a high-order polynomial rather than a linear expression as described above. This may be appropriately modified or changed in consideration of the characteristics of the memory. For example, a first-order term may be used for a specific state value, while a second-order term may be used for another state value.

[0131] In the following, reference will be made to Fig.13 Another exemplary embodiment of a solid state drive is described. Repeated parts of the above description will be omitted or simplified.

[0132] Fig.13 is a block diagram illustrating yet another example embodiment of a solid state drive.

[0133] refer to Fig.13 , the solid state drive may further include a third memory 630 .

[0134] The third memory 630 may be a memory of a different kind or type than the first memory 610 and the second memory 620. For example, if the first memory 610 is a PRAM and the second memory 620 is a NAND flash memory, the third memory 630 may be an RRAM.

[0135] The third memory 630 may be connected to the memory controller 500 via a fifth channel Ch5. The third memory 630 may include fifth metadata MD5, wherein the first metadata MD1, the second metadata MD2, and the fifth metadata MD5 are mirror images of each other. That is, the fifth metadata MD5 may be metadata having the same content as the first metadata MD1 and the second metadata MD2.

[0136] The condition checker 520 may derive condition scores of the first memory 610 , the second memory 620 , and the third memory 630 , respectively.

[0137] The condition checker 520 may refer to the characteristic table 530. The characteristic table 530 may include characteristic tables of the first memory 610, the second memory 620, and the third memory 630, respectively.

[0138] The condition checker 520 may compare the condition scores of each of the first memory 610 , the second memory 620 , and the third memory 630 , and select a memory having the best condition.

[0139] As a result, the memory controller 500 may read metadata of the memory selected by the condition checker 520 .

[0140] The solid state drive according to the present embodiment can compare the conditions of each of the three different kinds or types of memory and read the metadata of the best memory. Therefore, a more stable and reliable solid state drive can be provided.

[0141] exist Fig.13 3 kinds or types of memories are shown in FIG. 3 , but the embodiment is not limited thereto. That is, the solid state drive according to some embodiments may include four or more kinds or types of memories, their respective conditions may be determined, and a memory with the best condition may be selected.

[0142] In the following, reference will be made to Figure 1 , Fig.13 and Fig.14 A solid state drive according to some embodiments is described. Repeated parts of the above description will be omitted or simplified.

[0143] Fig.14 is a timing diagram illustrating an example embodiment of a programming operation of a solid state drive.

[0144] refer to Figure 1 , Fig.13 and Fig.14 , a method for programming a solid state drive according to some embodiments may first program all memories except for a memory having the worst condition.

[0145] The memory controller 500 receives a metadata program request from the host 10 , and the condition checker 520 checks conditions of the first memory 610 , the second memory 620 , and the third memory 630 .

[0146] Similar to the above-described manner, the condition checker 520 may select a memory having a better condition among the first memory 610, the second memory 620, and the third memory 630. However, the condition checker 520 may select a plurality of memories instead of only one memory.

[0147] Specifically, the condition checker 520 may select the remaining memories, ie, two memories except for the memory having the worst condition among the total three memories. Therefore, the memory controller 500 may first program the metadata in the memory selected by the condition checker 520.

[0148] Assuming that the condition checker 520 selects the first memory 610 and the third memory 630 , the memory controller 500 may program the first metadata MD1 in the first memory 610 at the first time t1 , and may program the fifth metadata MD5 in the third memory 630 at the same first time t1 .

[0149] The memory controller 500 may program the second metadata MD2 in the second memory 620 which is not selected by the condition checker 520 immediately without programming the first metadata MD1 and the fifth metadata MD5 .

[0150] The condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and when the condition of the second memory 620 is better than the conditions of the first memory 610 and the third memory 630 at the first time t1, the second metadata MD2 may be programmed in the second memory 620 at the second time t2. The second time t2 may be a time after the first time t1.

[0151] Here, the time when the condition of the second memory 620 is better may mean the time when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is greater than or equal to a preset specific value or threshold.

[0152] Although the programming time is different, the first metadata MD1, the fifth metadata MD5 and the second metadata MD2 may be data having the same content mirroring each other. This may be for the purpose of repeatedly storing metadata so that the metadata can be read later from a memory with better conditions.

[0153] In this embodiment, metadata is not immediately programmed into memory in poor condition, and by allowing the metadata to be programmed later when conditions become better, corruption of the metadata may be prevented.

[0154] In the following, reference will be made to Figure 1 , Fig.13 and Fig.15 A solid state drive according to some embodiments is described. Repeated parts of the above description will be omitted or simplified.

[0155] Fig.15 is a timing diagram illustrating another example embodiment of a programming operation of a solid state drive.

[0156] refer to Figure 1 , Fig.13 and Fig.15 , a method for programming a solid state drive according to some embodiments may first program a memory having an optimal condition, and thereafter may sequentially program the remaining memories.

[0157] Similar to the above method, the condition checker 520 may select a memory having the best condition from among the first memory 610 , the second memory 620 , and the third memory 630 .

[0158] Specifically, the condition checker 520 may select a memory having the best condition among a total of three memories. As a result, the memory controller 500 may first program metadata in the memory selected by the condition checker 520.

[0159] Assuming that the condition checker 520 has selected the first memory 610 , the memory controller 500 may program the first metadata MD1 in the first memory 610 at the first time t1 .

[0160] The memory controller 500 may program each of the second metadata MD2 and the fifth metadata MD5 in the second memory 620 and the third memory 630 , which are not selected by the condition checker 520 , respectively, immediately without programming the first metadata MD1 .

[0161] The condition checker 520 may dynamically check the conditions of the second memory 620 and the third memory 630 that are not selected by the condition checker 520. Subsequently, when the condition of the third memory 630 becomes better than the condition of the first memory 610 at the first time t1, the fifth metadata MD5 may be programmed in the third memory 630 at the second time t2. The second time t2 may be a time after the first time t1.

[0162] Likewise, the condition checker 520 may further check the condition of the second memory 620 that is not dynamically programmed. Subsequently, when the condition of the second memory 620 at the third time t3 becomes better than the condition of the first memory 610 at the first time t1 and the condition of the third memory 630 at the second time t2, the second metadata MD2 may be programmed in the second memory 620 at the third time t3. The third time t3 may be a time after the first time t1 and the second time t2.

[0163] At this time, the time when the condition becomes better may mean the time when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is greater than or equal to a preset specific value or threshold.

[0164] Although the time is different, the first metadata MD1, the fifth metadata MD5, and the second metadata MD2 may be data having the same content that are mirrored to each other.

[0165] In this embodiment, by making each memory program metadata when the condition is good, it is easier to prevent the metadata from being damaged. In other words, because each memory is programmed when the condition is good, the reliability of all metadata can be very high.

[0166] In the following, reference will be made to Figure 1 , Fig.13 and Fig.16 A solid state drive according to some embodiments is described. Repeated parts of the above description will be omitted or simplified.

[0167] Fig.16 is a timing diagram illustrating yet another embodiment of a programming operation of a solid state drive.

[0168] refer to Figure 1 , Fig.13 and Fig.16 , the method for programming a solid-state drive according to some embodiments of the present invention can program memories other than the worst-condition memories.

[0169] In the same manner as the above-described method, the condition checker 520 may select the remaining memories except for the memory having the worst condition among the first memory 610 , the second memory 620 , and the third memory 630 .

[0170] Specifically, the condition checker 520 may select two memories except for the memory having the worst condition among the total three memories. As a result, the memory controller 500 may first program metadata in the memory selected by the condition checker 520 .

[0171] Assuming that the condition checker 520 has selected the first memory 610 and the third memory 630 , the memory controller 500 may program the first metadata MD1 in the first memory 610 at the first time t1 , and may program the fifth metadata MD5 in the third memory 630 at the first time t1 .

[0172] The memory controller 500 may not program metadata in the second memory 620 that is not selected by the condition checker 520. Of course, the first metadata MD1 and the fifth metadata MD5 may be data having the same contents that are mirrored to each other.

[0173] In this embodiment, even if only one of the multiple memories is excluded, since metadata is repeatedly stored, an operation of intentionally performing programming on the memory with the worst condition can be excluded under the condition that the reliability of the metadata can be sufficiently improved.

[0174] The operation of continuously and dynamically checking the condition of the second memory 620 that is not selected by the condition checker 520 after the first time t1, and the operation of dynamically checking the metadata in the second memory 620 consume a lot of resources. Therefore, in this embodiment, the operation performance of the solid-state drive can be maintained at a high level by excluding the above-mentioned operation and saving the resources that will be consumed in such operation. At the same time, since the solid-state drive of this embodiment programs metadata in each of the two memories, the reliability of the metadata can also be maintained at a high level.

[0175] In the following, reference will be made to Figure 1 , Figure 3 and Fig.17 A metadata access method of a solid state drive according to some embodiments is described. The repeated parts of the above description will be omitted or simplified.

[0176] Fig.17 is a flow chart illustrating an example embodiment of a metadata access method for a solid state drive.

[0177] refer to Fig.17 , in operation S100 , a metadata read request is received.

[0178] Specifically, refer to Figure 1 and Figure 3 , when there is a read request for metadata from the host 10, the memory controller 500 may receive the read request.

[0179] Reference again Fig.17 , in operation S200, memory conditions of different memories are determined and a memory is selected.

[0180] Specifically, refer to Figure 1 and Figure 3 , the condition checker 520 may determine the current condition of the first memory 610 and may determine the current condition of the second memory 620. The condition checker 520 may compare the condition of the first memory 610 with the condition of the second memory 620 and select the memory with the better condition. For example, the condition checker 520 may determine the conditions of the first memory 610 and the second memory 620 with reference to the characteristic table 530.

[0181] Reference again Fig.17 , when the first memory is selected, in operation S300, the first metadata is read.

[0182] Specifically, refer to Figure 1 and Figure 3 , since the first memory 610 has a better condition than the second memory 620 , the first metadata MD1 in the first memory 610 may have higher reliability than the second metadata MD2 in the second memory 620 .

[0183] Reference again Fig.17 , if the second memory is selected, the second metadata is read in operation S400 (S400).

[0184] Specifically, refer to Figure 1 and Figure 3 , since the second memory 620 is in a better condition, the second metadata MD2 may have higher reliability.

[0185] The metadata access method of the solid state drive according to some embodiments stores the mirror metadata to different kinds or types of memories and reads the metadata from the memory with better conditions, thereby improving the reliability of the solid state drive.

[0186] In the following, reference will be made to Figure 1 , Figure 3 , Fig.10 and Fig.18 A metadata access method of a solid state drive according to some embodiments is described. The repeated parts of the above description will be omitted or simplified.

[0187] Fig.18 is a flow chart illustrating another example embodiment of a metadata access method for a solid state drive.

[0188] refer to Fig.18 , in operation S1100, a metadata programming request is received.

[0189] Specifically, refer to Figure 1 , Figure 3 and Fig.10 , when there is a program request for metadata from the host 10, the memory controller 500 may receive the program request.

[0190] Reference again Fig.18 , determine the memory conditions of various memories of the SSD and select a memory (S1200).

[0191] Specifically, refer to Figure 1 , Figure 3 and Fig.10 , when the memory controller 500 receives the metadata program request, the condition checker 520 checks the conditions of the first memory 610 and the second memory 620. Similar to the above method, the condition checker 520 may select a memory with a better condition between the first memory 610 and the second memory 620.

[0192] Reference again Fig.18 , when the first memory is selected, metadata is programmed in the first memory in operation S1300.

[0193] Specifically, refer to Figure 1 , Figure 3 and Fig.10 , since the first memory 610 has a better condition than the second memory 620, in order to prevent the possibility of metadata corruption, metadata may be programmed only in the first memory 610. At this time, when metadata is programmed in the first memory 610, metadata programmed into the memory having a bad condition may be corrupted.

[0194] Reference again Fig.18 , in operation S1500, a condition of the second memory is determined.

[0195] Specifically, refer to Figure 1 , Figure 3 and Fig.10 , since the metadata has been programmed in the first memory 610, the condition checker 520 may dynamically check the condition of the second memory 620 in which the metadata is not programmed.

[0196] If the condition of the second memory 620 is not good, it is possible to wait without programming the metadata until the condition of the second memory 620 becomes better.

[0197] Reference again Fig.18 , if the condition of the second memory becomes better, metadata is programmed in the second memory in operation S1700.

[0198] That is, the condition checker 520 dynamically checks the condition of the second memory 620 that is not selected by the condition checker 520, and when the condition of the second memory 620 becomes better than the condition of the first memory 610 at the first time t1, the second metadata MD2 may be programmed in the second memory 620 at the second time t2. The second time t2 may be a time after the first time t1.

[0199] At this time, the time when the condition of the second memory 620 becomes better may mean the time when the condition score derived by the condition checker 520 with reference to the characteristic table 530 is greater than or equal to a preset specific value or threshold.

[0200] Reference again Fig.18 , if the second memory 620 is selected, metadata is programmed in the second memory 620 in operation S1400, a condition of the unselected first memory 610 is determined in operation S1600, and metadata is programmed in the first memory 610 at a time when the condition of the first memory 610 becomes better in operation S1800.

[0201] In the above description, the metadata in each memory may be mirror data, that is, data including the same content. As a result, the metadata may be read from the memory with better conditions in future metadata reading operations.

[0202] In this embodiment, when the condition of a specific memory is not good, the metadata is not immediately programmed into the memory, but is programmed into the memory when the condition of the memory becomes better. Therefore, damage to the mirror metadata can be prevented.

[0203] In the above embodiment, only two kinds or types of memories are shown, but this is only an example, and the metadata access method of the solid-state drive according to the present embodiment can also be applied to a solid-state drive including three or more kinds or types of memories. In this case, in step S1200, at least one memory may be selected instead of selecting only one memory.

[0204] At the end of the specific implementation, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the preferred embodiments disclosed in the present invention are used only in a general and descriptive sense, and not for the purpose of limitation.

[0205] Although the inventive concept has been specifically shown and described with reference to its exemplary embodiments, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the inventive concept as defined by the appended claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the invention.

Claims

1. A solid state drive, include: A first memory and a second memory that are different types from each other; as well as a memory controller configured to control the first memory and the second memory, wherein the memory controller is configured to receive a metadata access request from a host and includes a condition checker configured to determine a condition of the first memory and a condition of the second memory in response to the metadata access request and select at least one of the first memory and the second memory based on at least one of the condition of the first memory and the condition of the second memory, wherein the memory controller is configured to access the at least one of the first memory and the second memory selected by the condition checker, wherein when the metadata access request is a metadata programming request, the memory controller is configured to program metadata in a selected memory of the first memory and the second memory, wherein the metadata programmed in the first memory and the metadata programmed in the second memory are the same, wherein the memory controller is configured to first program the metadata in the memory selected by the condition checker among the first memory and the second memory, and When the condition of a memory not selected by the condition checker among the first memory and the second memory becomes better, the metadata is programmed in the memory not selected by the condition checker.

2. The solid-state drive of claim 1 , wherein the condition checker is configured to determine the condition of the first memory and the condition of the second memory in consideration of at least one of temperature, the number of program / erase cycles, a program retention time, and an erase retention time. 3 . The solid-state drive according to claim 1 , wherein each of the first memory and the second memory is one of a NAND flash memory, a PRAM, a RRAM, and an MRAM.

4. The solid state drive according to claim 1, in, The metadata access request is a metadata read request, wherein each of the first memory and the second memory stores metadata identical to each other, wherein the condition checker is configured to select one of the first memory and the second memory in response to the metadata read request, and The memory controller is configured to read the metadata in the memory selected by the condition checker in the first memory and the second memory. 5 . The solid-state drive of claim 1 , wherein the second memory comprises a first channel memory and a second channel memory connected to the memory controller via different channels.

6. The solid-state drive of claim 5 , wherein the condition checker is configured to determine the condition of each of the first memory, the first channel memory, and the second channel memory in response to the metadata access request, and is configured to select one of the first memory, the first channel memory, and the second channel memory.

7. The solid state drive according to claim 1, further comprising: include: a third memory of a different type than the first memory and the second memory, wherein the condition checker is configured to select at least one of the first memory, the second memory, and the third memory in response to the metadata access request, and The memory controller is configured to access the memory selected by the condition checker.

8. The solid state drive according to claim 7, in, The metadata access request is a metadata programming request, The condition checker is configured to select remaining memories other than the selected at least one of the first memory and the second memory and the third memory, and The memory controller is configured to program the metadata in the memory selected by the condition checker.

9. The solid state drive according to claim 8, in, The memory controller is configured to first program the metadata in the memory selected by the condition checker among the first memory, the second memory, and the third memory, and When the condition of a memory not selected by the condition checker among the first memory, the second memory, and the third memory becomes better, the memory controller programs the metadata in the memory not selected by the condition checker.

10. The solid state drive according to claim 1, in, The metadata includes at least one of security metadata, firmware metadata, and debug metadata.

11. A solid state drive, include: a first memory configured to store first metadata; a second memory configured to store second metadata identical to the first metadata, wherein the second memory is of a different type than the first memory; and a memory controller configured to control the first memory and the second memory and comprising a condition checker configured to determine a condition of the first memory and a condition of the second memory and select one of the first memory and the second memory having a better condition, wherein the condition checker is configured to compare a first condition score obtained by summing a plurality of condition scores corresponding to a plurality of state values ​​of the first memory based on a characteristic of the first memory with a second condition score obtained by summing a plurality of condition scores corresponding to a plurality of state values ​​of the second memory based on a characteristic of the second memory, and The memory controller is configured to receive a metadata read request from a host, and read one of the first metadata and the second metadata stored in the memory selected by the condition checker in response to the metadata read request.

12. The solid-state drive according to claim 11, wherein the condition checker is configured to receive current state information of the first memory and the second memory to determine a condition of the first memory and a condition of the second memory based on the current state information, and The current state information includes at least one of a temperature of the first memory and the second memory, a number of program / erase cycles, a program retention time, and an erase retention time. 13 . The solid-state drive of claim 12 , wherein the condition checker comprises a characteristic table configured to store characteristic values ​​corresponding to the current state information for each of the first memory and the second memory.

14. The solid state drive of claim 12, wherein the condition checker includes characteristic parameters corresponding to the current state information for each of the first memory and the second memory.

15. A method for metadata access, wherein include: A solid-state drive receives a metadata read request from a host, wherein the solid-state drive includes at least a first memory and a second memory of different types from each other; The condition of the first memory and the condition of the second memory are determined by the following steps to select one of the first memory and the second memory: comparing a first condition score obtained by summing a plurality of condition scores corresponding to a plurality of state values ​​of the first memory based on a characteristic of the first memory with a second condition score obtained by summing a plurality of condition scores corresponding to a plurality of state values ​​of the second memory based on a characteristic of the second memory; as well as reading metadata of a selected memory from among the first memory and the second memory, The metadata of the first storage device is the same as the metadata of the second storage device.

16. The method according to claim 15, further comprising: include: receiving a metadata programming request from the host; determining a condition of each of the first memory and the second memory to select at least one of the first memory and the second memory; as well as programming the metadata in a selected one of the first memory and the second memory, The metadata programmed in the first memory is the same as the metadata programmed in the second memory.

17. The method according to claim 15, further comprising: include: After programming the metadata in the selected memory among the first memory and the second memory, when the condition of the first memory and the unselected memory among the second memory becomes better, programming the metadata in the unselected memory among the first memory and the second memory.

18. The method according to claim 15, wherein the second memory comprises a first channel memory and a second channel memory having different channels, and in, Determining a condition of the first memory and a condition of the second memory and selecting one of the first memory and the second memory includes: A condition of each of the first memory, the first channel memory, and the second channel memory is determined, and one of the first memory, the first channel memory, and the second channel memory is selected.

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