Storage device, method and system for operating storage device

Abstract

A storage device, a method for operating the storage device, and a system are provided. The storage device includes a storage cell array and a processor in memory (PIM) that performs an internal processing operation. In an internal processing mode, the storage device performs an internal processing operation through the PIM based on internal processing information stored in the storage cell array. When the internal processing information is an internal processing operation command indicating the type of the internal processing operation, the storage device outputs an internal processing operation command including an internal processing read command and an internal processing write command to a host device. The host device issues a priority command determined from a data transaction command and an internal processing operation command to the storage device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0088682 filed on July 30, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to a storage device that performs an internal processing operation, a method of operating the storage device, and a storage system including the storage device. Background Art

[0004] Various systems such as computer graphics, servers, supercomputers, and networks that require high performance and low power consumption are under development. These systems include storage devices that store data or instructions used by a host included in the system or perform computing operations.

[0005] Dynamic random access memory (DRAM) is a storage device with high response speed and high operation speed characteristics. The system usually uses DRAM as the working memory or main memory of the system. General DRAM writes data or reads written data under the control of the host. When performing a computing operation, the host retrieves instructions and / or data from the DRAM and uses the data to execute instructions and / or perform a computing operation. When there is a result of the computing operation, the host writes the result of the computing operation back to the DRAM.

[0006] Because the operation of retrieving instructions and / or data from DRAM and writing them back to DRAM is relatively slow, while the computing operations performed by the host are quite fast, system performance may be slowed. In addition, in the case of data-intensive systems, system performance may be reduced due to the memory bandwidth limitations of DRAM.

[0007] In order to improve system performance, storage devices including internal processors have been developed to perform some computing operations of the host through internal processing. Due to the internal processing of the storage device, the computing workload of the host can be reduced.

[0008] However, in order to prevent conflicts between the internal processing and the processing of the host, the storage device may need to perform an arbitration function to determine the priority of the internal processing and the processing of the host. In addition, the storage device may perform read and write operations in the storage device through internal processing. In this case, when the data stored in the cache of the host is changed in the storage device, since the data in the cache is not the latest data, there may be limitations in the consistency of the cache data. Therefore, the storage device may need to perform virtual storage management functions such as virtual memory address conversion across the host and the storage device.

[0009] Executing the arbitration function and the virtual storage management function in a storage device that performs internal processing may have limitations because hardware configuration and / or implementation of the storage device is complex and difficult.

[0010] The information disclosed in this background technology section was known to the inventor before the disclosure of this application, or is technical information obtained in the process of implementing this disclosure. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0011] Exemplary embodiments of the inventive concept provide a storage device that performs internal processing operations by delegating an arbitration function and a virtual storage management function to a host, a method of operating the storage device, and a system including the storage device.

[0012] According to one aspect of the inventive concept, there is provided a storage device comprising: a storage cell array configured to store internal processing information; and a processor in memory (PIM), the PIM configured to perform an internal processing operation based on the internal processing information in an internal processing mode, wherein when the internal processing information includes an internal processing operation command indicating a type of the internal processing operation, the PIM outputs the internal processing operation command to an external device.

[0013] According to one aspect of the inventive concept, there is provided a method for operating a storage device, the storage device comprising a storage cell array and a processor in memory (PIM) configured to perform an internal processing operation, the method comprising: entering an internal processing mode under the control of an external device; performing the internal processing operation based on internal processing information stored in the storage cell array by the PIM in the internal processing mode; and when the internal processing information includes an internal processing operation command indicating a type of the internal processing operation, outputting the internal processing operation command to the external device.

[0014] According to one aspect of the inventive concept, a host device is provided, comprising: a host processor configured to perform a computing operation and issue a storage request command according to the computing operation; and a storage controller configured to receive the storage request command, issue a data transaction command for accessing a storage device according to the storage request command, and control an internal processing mode of the storage device, wherein the storage controller is further configured to receive an internal processing operation command generated during an internal processing operation in the internal processing mode from the storage device, and issue a priority command determined from the data transaction command and the internal processing operation command to the storage device.

[0015] According to one aspect of the inventive concept, there is provided a method for operating a host device including a host processor and a storage controller, the method comprising: the host processor issuing a storage request command according to a computing operation; the storage controller issuing a data transaction command for accessing a storage device according to the storage request command; the storage controller controlling the storage device to enter an internal processing mode; the storage controller receiving an internal processing operation command generated during an internal processing operation in the internal processing mode from the storage device; and the storage controller issuing a priority command determined from the data transaction command and the internal processing operation command to the storage device.

[0016] According to one aspect of the present invention, there is provided a system comprising: a host device for performing a computing operation; and a storage device, wherein the storage device, under the control of the host device, performs a storage request operation according to the computing operation and performs an internal processing operation based on internal processing information stored in a storage cell array included in the storage device, wherein the internal processing information comprises an internal processing operation command sent by the storage device to the host device, wherein, according to the internal processing operation command, the host device controls the storage device to perform the internal processing operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Exemplary embodiments of the present inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a block diagram illustrating a system including a storage device that performs internal processing operations according to an embodiment of the inventive concept;

[0019] Figure 2 It shows Figure 1 A diagram of the operation of the system;

[0020] Figure 3 is a block diagram illustrating a storage device according to an embodiment of the inventive concept;

[0021] Figure 4 is a flowchart illustrating a method of operating a storage device according to an embodiment of the inventive concept;

[0022] Figure 5 is a flowchart illustrating a method of operating a host device according to an embodiment of the inventive concept;

[0023] Figure 6 is a block diagram illustrating a system including a storage device that performs internal processing operations according to another embodiment of the inventive concept;

[0024] Figure 7is a block diagram illustrating a server system to which a system including a storage device that performs internal processing operations according to an embodiment of the inventive concept can be applied; and

[0025] Figure 8 is a block diagram illustrating a data center of a system including a storage device that performs internal processing operations according to an embodiment of the inventive concept to which can be applied. DETAILED DESCRIPTION

[0026] The embodiments described below are all exemplary, therefore, the inventive concept is not limited to the embodiments disclosed below, and can be implemented in various other forms. The embodiments provided in the following description do not exclude association with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the inventive concept. For example, even if the content described in a specific example is not described in an example different from it, it can also be understood that these contents are related to different examples or combined with different examples, unless otherwise mentioned in the description of the different examples.

[0027] Figure 1 is a block diagram illustrating a system including a memory device that performs internal processing operations according to an embodiment of the inventive concept.

[0028] Reference Figure 1 , the system 100 may include a host device 110 and a storage device 120. The host device 110 may be communicatively connected to the storage device 120 through channels CH1 and CH2. The storage device 120 may operate in any one of a normal mode for performing data transaction operations and an internal processing mode for performing internal processing operations. The data transaction operations of the storage device 120 may include write operations to / read operations from a storage cell array 122. The storage device 120 may be a storage device of a processor-in-memory (PIM) type that includes a processor-in-memory that performs internal processing operations.

[0029] The host device 110 may be, for example, a computing system, such as a computer, a notebook computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device. Alternatively, the host device 110 may be some components included in the computing system, such as a graphics card.

[0030] The host device 110 may include a host processor 112, a memory controller 114, and a PIM agent 116. The host processor 112, the memory controller 114, and the PIM agent 116 may be interconnected via a bus 118 including at least one or more signal lines.

[0031] The host processor 112 may be a functional block that performs general computing operations in the system 100, and may correspond to a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP). The host processor 112 may issue a storage request command MEMREQ CMD associated with a storage request for a computing operation. The host processor 112 may include a memory management unit (MMU). When the MMU issues a storage request command MEMREQ CMD to the storage device 120, the MMU may perform a virtual storage management function such as virtual storage address conversion.

[0032] The storage controller 114 may access the storage device 120 according to the storage request command MEMREQ CMD of the host processor 112. The storage controller 114 may prioritize the storage request command MEMREQ CMD and issue a data transaction command generated according to the storage request command MEMREQ CMD to the storage device 120.

[0033] The memory controller 114 may control the memory device 120 to write data into the memory device 120 or read data written into the memory device 120. The memory controller 114 may control the write or read operation to the memory device 120 by providing a command CMD and an address ADDR to the memory device 120. In addition, write data DQ and read data DQ may be exchanged between the memory controller 114 and the memory device 120. The data transaction operation may be performed through a first channel CH1 executing a predetermined protocol (e.g., a DDR protocol) between the host device 110 and the memory device 120. The first channel CH1 may include a bus or a signal line for transmitting a command CMD, an address ADDR, and data DQ.

[0034] The PIM agent 116 may control the storage device 120 to operate in the internal processing mode. The PIM agent 116 may generate an internal processing mode signal IPM and send it to the storage device 120. The storage device 120 may perform an internal processing operation in response to the internal processing mode signal IPM. The internal processing mode signal IPM may be a specific dedicated signal. In this case, the internal processing mode signal IPM may be sent to the storage device 120 via a bus and / or a signal line of a second channel CH2 between the host device 110 and the storage device 120.

[0035] According to one embodiment, the PIM agent 116 may activate the internal processing mode signal IPM and transmit it to the storage device 120. The internal processing mode signal IPM may be transmitted to the storage device 120 as a combination of several signals (e.g., a command combination, a mode register set (MRS), or an address combination). In this case, the internal processing mode signal IPM may be transmitted to the storage device 120 through a bus and / or a signal line of a first channel CH1 between the host device 110 and the storage device 120.

[0036] The internal processing mode signal IPM may allow the memory device 120 to operate in the internal processing mode. In the internal processing mode, the internal processing operation may include accessing the memory cell array 122 to perform a processing operation on data stored in the memory cell array 122.

[0037] For example, the internal processing operation may be a processing operation on the data stored in the memory cell array 122, such as data inversion, data shift, data exchange, data comparison, logic operation (AND, XOR, etc.) or mathematical operation (addition, subtraction, etc.). The storage device 120 may send an internal processing operation command IPCMD indicating the type of the internal processing operation to the host device 110. In this case, the internal processing operation command IPCMD may be sent to the PIM agent 116 via a bus and / or a signal line of the second channel CH2 between the host device 110 and the storage device 120. The internal processing operation command IPCMD may include an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE.

[0038] The PIM agent 116 may receive an internal process operation command IPCMD generated when the storage device 120 operates in the internal process mode from the storage device 120. The PIM agent 116 may transmit the received internal process operation command IPCMD to the storage controller 114 through the bus 118. The storage controller 114 may receive the internal process operation command IPCMD and transmit the received internal process operation command IPCMD as a command CMD to the storage device 120. The storage controller 114 may transmit an internal process read command PIM_READ and / or an internal process write command PIM_WRITE constituting the internal process operation command IPCMD as the command CMD to the storage device 120. In this case, the internal process operation command IPCMD may be transmitted to the storage device 120 through a command (CMD) bus and / or a signal line of a first channel CH1 between the host device 110 and the storage device 120.

[0039] When the internal processing operation is completed according to the internal processing information IPI stored in the memory cell array 122 in the storage device 120, the storage device 120 may send a completion signal DONE indicating the completion of the internal processing operation to the host device 110. When the PIM agent 116 of the host device 110 receives the completion signal DONE, the storage device 120 may exit the internal processing mode. In this case, the completion signal DONE may be sent to the PIM agent 116 via a bus and / or a signal line of the second channel CH2 between the host device 110 and the storage device 120.

[0040] The storage controller 114 may receive a storage request command MEMREQCMD of the host processor 112, and generate a data transaction command according to the storage request command MEMREQ CMD to perform a data transaction operation. The storage controller 114 may issue a data transaction command to the storage device 120 according to the data transaction operation, and the storage device 120 may operate in a normal mode according to the data transaction command. The storage controller 114 may issue an internal processing operation command IPCMD to the storage device 120, and the storage device 120 may operate in an internal processing mode.

[0041] When issuing data transaction commands and internal processing operation commands IPCMD to the storage device 120, the storage controller 114 may prioritize these commands and issue these commands to the storage device 120. The storage controller 114 may perform an arbitration function to determine or select a priority command to be processed preferentially from the data transaction commands and the internal processing operation commands IPCMD, and issue the priority command to the storage device 120. The storage controller 114 may issue the priority command to the storage device 120 via a CMD bus and / or a CMD signal line of a first channel CH1 between the host device 110 and the storage device 120.

[0042] The storage device 120 may write data or read data under the control of the storage controller 114. For example, the storage device 120 may include a dynamic random access memory (DRAM). However, the inventive concept is not limited thereto, and the storage device 120 may include any one of volatile storage devices such as static RAM (SRAM), DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate (LPDDR) SDRAM, wide I / O DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC). According to one embodiment, the storage device 120 may include any one of non-volatile storage devices such as a flash memory device, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

[0043] The memory device 120 may include a memory cell array 122 and a PIM 124. The memory cell array 122 and the PIM 124 may be interconnected through at least one or more signal lines 126.

[0044] The memory cell array 122 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines, respectively. The memory cell array 122 may store internal processing information IPI under the control of the host device 110. The internal processing information IPI may be information for an internal processing operation performed by the PIM 124, and may include information such as an internal processing operation command IPCMD and internal processing data. The internal processing data may include specific address information according to the internal processing operation command IPCMD such as data exchange.

[0045] The PIM 124 may perform an internal processing operation under the control of the host device 110. The PIM 124 may receive an internal processing mode signal IPM from the host device 110 and enter an internal processing mode in response to the received internal processing mode signal IPM. The PIM 124 may perform an internal processing operation in the internal processing mode based on the internal processing information IPI stored in the memory cell array 122. For example, the internal processing operation may refer to a processing operation on data stored in the memory cell array 122, such as data inversion, data shift, data exchange, data comparison, logic operation, or mathematical operation.

[0046] After completing the internal processing operation according to the internal processing information IPI stored in the memory cell array 122, the PIM 124 may generate a completion signal DONE and transmit it to the host device 110. The completion signal DONE may be transmitted to the PIM agent 116 via a bus and / or signal line of the second channel CH2 between the host device 110 and the memory device 120.

[0047] Similar to the host processor 112, the PIM 124 included in the storage device 120 may be hardware having a processing function. When the PIM 124 is referred to as an internal processor, the term "internal" may mean that it is in the storage device 120. Therefore, a processor "external" to the storage device 120 may refer to the host processor 112, for example.

[0048] The storage device 120 may operate in a normal mode of performing a data transaction operation or in an internal processing mode of performing an internal processing operation under the control of the host device 110 .

[0049] In normal mode, the storage device 120 may perform a data transaction operation through the first channel CH1 under the control of the host device 110. The data transaction operation may refer to performing a write operation and / or a read operation according to a predetermined Joint Electron Device Engineering Council (JEDEC) timing specification such as a DDR protocol. In normal mode, the write operation and / or the read operation of the storage device 120 may be performed by the memory controller 114 of the host device 110. In normal mode, a command CMD, an address ADDR, and / or data DQ for a write operation and / or a read operation of the storage device 120 may be sent to the storage device 120 through a bus and / or a signal line of the first channel CH1 between the host device 110 and the storage device 120.

[0050] In the internal processing mode, the storage device 120 may perform an internal processing operation through the first channel CH1 or the second channel CH2 under the control of the host device 110. The host device 110 may activate and transmit an internal processing mode signal IPM to the storage device 120 so that the storage device 120 enters the internal processing mode. The internal processing mode signal IPM may be transmitted through a bus and / or a signal line of the first channel CH1 or the second channel CH2 between the host device 110 and the storage device 120.

[0051] The storage device 120 may enter the internal processing mode in response to the internal processing mode signal IPM. When entering the internal processing mode, the internal processing information IPI may be written or uploaded to the storage cell array 122 under the control of the host device 110. The write operation of the internal processing information IPI may be performed by a write command CMD of the storage device 120. The internal processing information IPI may be sent through a bus and / or a signal line of a first channel CH1 between the host device 110 and the storage device 120.

[0052] In the internal processing mode, when the internal processing information IPI is previously written or uploaded to the storage cell array 122, the write operation of the internal processing information IPI may be skipped. For example, when the system 100 is powered on, information stored in a separate storage medium (e.g., a solid state drive (SSD)) included in the system 100 may be preloaded and stored in the storage cell array 122. In the internal processing mode, the storage device 120 may read the internal processing information IPI written to the storage cell array 122. The PIM 124 may read the internal processing information IPI. When the read internal processing information IPI includes or is an internal processing operation command IPCMD indicating a type of internal processing operation (e.g., data inversion, data shift, data exchange, data comparison, logical operation, or mathematical operation), the PIM 124 may send an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE constituting the internal processing operation command IPCMD to the host device 110. The internal process operation command IPCMD may be transmitted to the PIM agent 116 through a bus and / or a signal line of the second channel CH2 between the host device 110 and the storage device 120 .

[0053] As described above, the storage controller 114 of the host device 110 can perform an arbitration function to prioritize the data transaction command and the internal processing operation command IPCMD and send them to the storage device 120. Therefore, the storage device 120 may not need to perform an additional arbitration function. In addition, when the storage controller 114 issues the internal processing operation command IPCMD to the storage device 120, the MMU of the host processor 112 can perform virtual storage management functions such as virtual storage address conversion according to the internal processing operation command IPCMD. Therefore, the storage device 120 may not need to perform the virtual storage management function associated with the internal processing operation. That is, since the arbitration function and the virtual storage management function are delegated to the host device 110, the storage device 120 can simply and easily perform the internal processing operation without complex hardware configuration and / or implementation.

[0054] Figure 2 It shows Figure 1 1 is a diagram of the operation of system 100.

[0055] Combination Figure 1 Reference Figure 2In operation S210, the host device 110 may instruct the storage device 120 to enter the internal processing mode. The PIM agent 116 of the host device 110 may activate and transmit an internal processing mode signal IPM including a combination of various signals (e.g., a dedicated signal or command combination, an MRS, or an address combination) to the storage device 120. The internal processing mode signal IPM may be transmitted through a bus and / or a signal line of the first channel CH1 or the second channel CH2 between the host device 110 and the storage device 120.

[0056] In operation S220 , the memory device 120 may enter an internal processing mode in response to the internal processing mode signal IPM and perform an internal processing operation.

[0057] When the storage device 120 enters the internal processing mode, the host device 110 may control the storage device 120 so that internal processing information IPI for an internal processing operation to be performed by the PIM 124 may be written or uploaded to the storage cell array 122. The write operation of the internal processing information IPI may be performed through a bus and / or a signal line of a first channel CH1 between the host device 110 and the storage device 120. The PIM 124 may detect whether the internal processing information IPI includes an internal processing operation command.

[0058] In operation S230 , the storage device 120 may transmit, to the host device 110 , an internal process operation command IPCMD detected while operating in the internal process mode.

[0059] In the internal processing mode, the PIM 124 of the storage device 120 may perform an internal processing operation based on the internal processing information IPI stored in the storage cell array 122. The PIM 124 may read the internal processing information IPI stored in the storage cell array 122. When the read internal processing information IPI includes or is an internal processing operation command IPCMD indicating the type of the internal processing operation (e.g., data inversion, data shift, data exchange, data comparison, logical operation, or mathematical operation), the PIM 124 may send an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE constituting the internal processing operation command IPCMD to the host device 110. The internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE may be sent to the PIM agent 116 through the bus and / or signal line of the second channel CH2 between the host device 110 and the storage device 120.

[0060] In operation S240 , the host device 110 may issue the internal processing operation command IPCMD received from the storage device 120 to the storage device 120 .

[0061] The PIM agent 116 of the host device 110 may receive an internal processing operation command IPCMD including an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE from the PIM 124, and send the received internal processing operation command IPCMD to the memory controller 114 through the bus 118. The memory controller 114 may determine or select a priority command to be processed preferentially from the received internal processing operation command IPCMD and a data transaction command to be sent to the memory device 120.

[0062] In this embodiment, when the priority command is an internal processing operation command IPCMD, the storage controller 114 may issue the internal processing operation command IPCMD to the storage device 120. The storage controller 114 may issue the internal processing operation command IPCMD to the storage device 120 via a CMD bus and / or a CMD signal line of a first channel CH1 between the host device 110 and the storage device 120. In another embodiment, when the priority command is a data transaction command, the storage controller 114 may issue the data transaction command to the storage device 120 via a CMD bus and / or a CMD signal line of a first channel CH1 between the host device 110 and the storage device 120.

[0063] In operation S250 , the memory device 120 may perform an internal processing operation through the signal line 126 between the PIM 124 and the memory cell array 122 according to the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE issued from the memory controller 114 .

[0064] Some or most of the internal processing operations may be data communication operations performed by the internal processing operation command IPCMD. The data communication operation may include an operation of reading the internal processing data (e.g., reference data, source data, destination data, or target data used in the internal processing operation) from the memory cell array 122 and an operation of writing the processing result of the internal processing operation to the memory cell array 122. For example, it is assumed that the PIM 124 may perform data search, data transmission, data addition, or data exchange according to the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE.

[0065] When the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE is a command for data search, the PIM 124 may determine whether the internal processing data is stored in the memory cell array 122 according to the internal processing read command PIM_READ. The PIM 124 may output hit / miss or address information as a processing result of the data search operation. The PIM 124 may write the hit / miss or address information according to the data search operation into the memory cell array 122 according to the internal processing write command PIM_WRITE.

[0066] When the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE is a command for data transmission, the PIM 124 may transfer data corresponding to the reference address information to the target area according to the internal processing read command PIM_READ and the internal processing write command PIM_WRITE. The PIM 124 may output address information about the target area as a processing result of the data transmission operation. The operation of transmitting data and writing address information of the target area through the PIM 124 may be performed in the memory cell array 122.

[0067] When the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE is a command for data addition, the PIM 124 may read data corresponding to the reference address information from the memory cell array 122 according to the internal processing read command PIM_READ, and may add the internal processing data to the read data according to the internal processing write command PIM_WRITE and store the addition result in the memory cell array 122. The PIM 124 may output address information about an area storing the addition result data as a processing result of the data addition operation. The operation of adding data and writing address information about an area storing the addition result data by the PIM 124 may be performed in the memory cell array 122.

[0068] When the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE is a command for data exchange, the PIM 124 may read first data and second data corresponding to the first reference address information and the second reference address information, respectively, from the memory cell array 122 according to the internal processing read command PIM_READ, exchange the read first data and second data, and store the exchanged first data and second data, respectively, in memory cells corresponding to the first reference address information and the second reference address information about the memory cell array 122 according to the internal processing write command PIM_WRITE. The data exchange operation by the PIM 124 may be performed in the memory cell array 122.

[0069] The above operations S220 to S250 may be repeatedly performed until the PIM 124 processes all the internal processing information IPI stored in the memory cell array 122 .

[0070] In operation S260, the storage device 120 may complete the internal processing operation according to the internal processing information IPI and exit the internal processing mode.

[0071] After completing the internal processing operation according to the internal processing information IPI stored in the memory cell array 122, the PIM 124 may transmit a completion signal DONE to the host device 110. The completion signal DONE may be transmitted to the PIM agent 116 via a bus and / or signal line of the second channel CH2 between the host device 110 and the memory device 120.

[0072] Figure 3 1 is a block diagram illustrating a memory device according to an embodiment of the inventive concept. In the present embodiment, it is assumed that the memory device 120 is a DRAM; however, the scope of the inventive concept is not limited thereto.

[0073] Reference Figure 1 and Figure 3 , the memory device 120 may include a memory cell array 122, a PIM 124, a command / address buffer 310, a row / column decoder 312, a sense amplifier / write driver (SA / WD) 314, a switch circuit 316, and a data input / output (IO) buffer 318.

[0074] The memory cell array 122 may include a plurality of memory cells arranged in a matrix form arranged in rows and columns. The memory cell array 122 may include a plurality of word lines and a plurality of bit lines connected to the memory cells. The plurality of word lines may be connected to the rows of the memory cells, and the plurality of bit lines may be connected to the columns of the memory cells.

[0075] The command / address buffer 310 may receive a control signal corresponding to a command CMD from the memory controller 114 through the first channel CH1. The control signal may include, for example, a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, and / or a chip select signal / CS, and the command CMD may include, for example, an activation command, a read command, a write command, and / or a precharge command.

[0076] The command / address buffer 310 may receive an address ADDR from the memory controller 114 through the first channel CH1. The address ADDR may include a row address for addressing a row of the memory cell array 122 and a column address for addressing a column of the memory cell array 122. The command / address buffer 310 may send the row address and the column address to the row / column decoder 312.

[0077] The row / column decoder 312 may select any one of a plurality of word lines connected to the memory cell array 122. The row / column decoder 312 may decode a row address received from the command / address buffer 310, select one word line corresponding to the row address, and activate the selected word line.

[0078] The row / column decoder 312 may select one of a plurality of bit lines connected to the memory cell array 122. The row / column decoder 312 may decode a column address received from the command / address buffer 310 and select certain bit lines corresponding to the column address.

[0079] The sense amplifier / write driver 314 can sense a voltage change of the bit line selected by the row / column decoder 312, and provide output data based on the sense-amplified voltage to the switch circuit 316. In addition, the sense amplifier / write driver 314 can receive data from the switch circuit 316 and write the received data to the memory cell connected to the bit line selected by the row / column decoder 312.

[0080] The data input / output buffer 318 may receive data from the memory controller 114 through the first channel CH1 and provide the received data to the switch circuit 316. In addition, the data input / output buffer 318 may receive data from the switch circuit 316 through the data DQ bus and / or the data DQ signal line of the first channel CH1 and provide the received data to the memory controller 114.

[0081] The switch circuit 316 may be selectively controlled so that the memory device 120 performs data transaction operations according to a normal mode of the memory device 120 and performs internal processing operations according to an internal processing mode of the memory device 120 .

[0082] In a normal mode read operation, the switch circuit 316 may transmit data received from the memory cell array 122 and the sense amplifier / write driver 314 to the data input / output buffer 318. The data input / output buffer 318 may provide the data received from the switch circuit 316 to the memory controller 114 through the first channel CH1.

[0083] In a normal mode write operation, the switch circuit 316 may transmit data received from the data input / output buffer 318 to the sense amplifier / write driver 314. The sense amplifier / write driver 314 may write the data received from the switch circuit 316 into a memory cell connected to a word line and a bit line selected by the row / column decoder 312.

[0084] In the internal processing mode, the switch circuit 316 may receive the internal processing information IPI from the data input / output buffer 318, and write or upload the received internal processing information IPI into the memory cell array 122 through the sense amplifier / write driver 314. Thereafter, the internal processing information IPI written into the memory cell array 122 may be accessed or read by the PIM 124.

[0085] In the internal processing mode, the switch circuit 316 may receive the internal processing information IPI read from the memory cell array 122 through the sense amplifier / write driver 314 and transmit the received internal processing information IPI to the PIM 124 .

[0086] PIM 124 may be implemented as a computationally intensive core, a GPU accelerator, or a field programmable gate array (FPGA). Alternatively, PIM 124 may be implemented as a neural processing unit (NPU) that performs parallel computing, data reuse, locality of data values, or deep neural networks. PIM 124 may include an internal processor 320, a control circuit 322, a command queue 324, and a command detector 326.

[0087] The internal processor 320 may perform an internal processing operation based on the internal processing information IPI. The internal processor 320 may receive an internal processing mode signal IPM from the host device 110, and enter an internal processing mode in response to the received internal processing mode signal IPM. In the internal processing mode, the internal processor 320 may read the internal processing information IPI from the memory cell array 122, and perform an internal processing operation based on the read internal processing information IPI. After completing the internal processing operation according to the internal processing information IPI, the internal processor 320 may generate a completion signal DONE and send it to the PIM agent 116.

[0088] According to the normal mode or the internal processing mode of the memory device 120 , the control circuit 322 may control the switch circuit 316 to configure the data path.

[0089] In the normal mode, the control circuit 322 may control the switch circuit 316 to configure a normal data path connecting the first channel CH1, the data input / output buffer 318, the switch circuit 316, the sense amplifier / write driver 314, and the memory cell array 122. Data transaction operations may be performed through the normal data path.

[0090] In the internal processing mode, the control circuit 322 can control the switch circuit 316 to write or upload the internal processing information IPI into the memory cell array 122. In this case, the control circuit 322 can configure a normal data path connecting the first channel CH1, the data input / output buffer 318, the switch circuit 316, the sense amplifier / write driver 314 and the memory cell array 122, and can write the internal processing information IPI sent through the normal data path into the memory cell array 122.

[0091] In the internal processing mode, the control circuit 322 may control the switch circuit 316 to configure an internal operation data path connecting the PIM 124, the switch circuit 316, the sense amplifier / write driver 314, and the memory cell array 122. The internal processing information IPI read from the memory cell array 122 through the internal operation data path may be transmitted to the internal processor 320 of the PIM 124. In addition, the processing result of the internal processing operation performed in the internal processor 320 according to the internal processing information IPI may be written back to the memory cell array 122 through the internal operation data path.

[0092] When the internal processing information IPI read from the memory cell array 122 includes or is an internal processing operation command IPCMD indicating the type of the internal processing operation, the internal processor 320 may store the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE constituting the internal processing operation command IPCMD in the command queue 324. The command queue 324 may store the internal processing operation command IPCMD including at least one of the internal processing read command PIM_READ and the internal processing write command PIM_WRITE.

[0093] The internal processing operation command IPCMD of the command queue 324 may be transmitted to the PIM agent 116 through the second channel CH2, and the PIM agent 116 may transmit the internal processing operation command IPCMD received from the command queue 324 to the memory controller 114 through the bus 118 in the host device 110. The memory controller 114 may transmit the internal processing operation command IPCMD including the received internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE as a command CMD to the command / address buffer 310 of the memory device 120 through the first channel CH1.

[0094] The command detector 326 may determine whether the command CMD received by the command / address buffer 310 includes or is an internal processing operation command IPCMD. When it is determined that the received command CMD includes or is an internal processing operation command IPCMD, the command detector 326 may send the internal processing operation command IPCMD to the internal processor 320. The internal processor 320 may perform an internal processing operation according to the internal processing operation command IPCMD including the internal processing read command PIM_READ and / or the internal processing write command PIM_WRITE.

[0095] Figure 4 is a flowchart illustrating a method of operating a memory device according to an embodiment of the inventive concept.

[0096] Reference Figure 3 and Figure 4 In operation S410, the PIM 124 may receive the internal processing mode signal IPM and enter the internal processing mode in response to the internal processing mode signal IPM.

[0097] In operation S412 , the PIM 124 may perform an internal processing operation based on the internal processing information IPI stored in the memory cell array 122 .

[0098] In operation S414, the PIM 124 may transmit an internal process operation command IPCMD generated during operation in the internal process mode to the PIM agent 116 of the host device 110. The PIM 124 may read the internal process information IPI from the memory cell array 122. When the read internal process information IPI includes or is the internal process operation command IPCMD, the PIM 124 may transmit an internal process read command PIM_READ and / or an internal process write command PIM_WRITE constituting the internal process operation command IPCMD to the PIM agent 116.

[0099] In operation S416 , the command / address buffer 310 may receive a command CMD from the memory controller 114 of the host device 110 .

[0100] In operation S420, the command detector 326 may determine whether the command CMD received from the storage controller 114 includes or is an internal processing operation command IPCMD. As a result of the determination, when the command CMD received from the storage controller 114 includes or is an internal processing operation command IPCMD, the method may proceed to operation S422, and when the received command CMD does not include or is not an internal processing operation command IPCMD, the method may proceed to operation S430.

[0101] In operation S422, the PIM 124 may perform an internal processing operation with the memory cell array 122 according to the internal processing operation command IPCMD. That is, internal processing data used in the internal processing operation according to the internal processing operation command IPCMD may be read from the memory cell array 122, or a processing result of the internal processing operation may be written into the memory cell array 122.

[0102] In operation S424, the PIM 124 may determine whether the internal processing operation is completed based on the internal processing information IPI stored in the memory cell array 122. For example, the PIM 124 may determine whether there is still any internal processing information IPI in the memory cell array 122. As a result of the determination, when the internal processing operation is completed, the method may proceed to operation S426. When there is still an internal processing operation to be performed based on the internal processing information IPI, the method may proceed to operation S412, and perform the internal processing operation based on the remaining internal processing information IPI.

[0103] In operation S426, the PIM 124 may transmit a completion signal DONE of the internal processing operation to the PIM agent 116 of the host device 110 and exit the internal processing operation mode.

[0104] As a result of the determination in operation S420, when the command CMD received from the storage controller 114 does not include or is not an internal processing operation command IPCMD, that is, when the command CMD includes or is a data transaction command, a data transaction operation such as a data communication operation can be performed between the storage controller 114 and the storage cell array 122 according to the data transaction command (operation S430).

[0105] Figure 5 is a flowchart illustrating a method of operating a host device according to an embodiment of the inventive concept.

[0106] Reference Figure 1 and Figure 5In operation S510, the host processor 112 may issue a storage request command MEMREQ CMD for a computing operation to the storage controller 114, and the storage controller 114 generates a data transaction command according to the storage request command MEMREQ CMD to perform a data transaction operation.

[0107] In operation S512, the PIM agent 116 may transmit an internal processing mode signal IPM to the PIM 124 of the storage device 120. The PIM 124 may enter an internal processing mode and perform an internal processing operation in response to the internal processing mode signal IPM.

[0108] In operation S514, the PIM agent 116 may receive an internal process operation command IPCMD including an internal process read command PIM_READ and / or an internal process write command PIM_WRITE generated during an internal process operation of the PIM 124. The PIM agent 116 may transmit the received internal process operation command IPCMD to the memory controller 114.

[0109] In operation S516, the storage controller 114 may perform an arbitration function between the data transaction command and the internal processing operation command IPCMD to determine their priorities. As a result of the determination, when the priority command is the internal processing operation command IPCMD, the method may proceed to operation S520, and when the priority command is a data transaction command for a computing operation, the method may proceed to operation S530.

[0110] In operation S520, the memory controller 114 may issue an internal processing operation command IPCMD to the memory device 120 through the CMD bus and / or the CMD signal line of the first channel CH1. In this case, the memory controller 114 may perform a virtual storage management function such as virtual storage address conversion associated with the internal processing operation command IPCMD, and issue the internal processing operation command IPCMD to the memory device 120.

[0111] In operation S522 , the PIM 124 may perform an internal processing operation such as a data communication operation with the memory cell array 122 according to the internal processing operation command IPCMD.

[0112] In operation S524 , when the PIM 124 completes the internal processing operation according to the internal processing information IPI, the PIM agent 116 may receive a completion signal DONE of the internal processing operation from the PIM 124 .

[0113] In operation S530, the memory controller 114 may issue a data transaction command for a computing operation to the memory device 120 through the CMD bus and / or the CMD signal line of the first channel CH1. In this case, the memory controller 114 may issue the data transaction command to the memory device 120 by performing a virtual memory management function such as virtual memory address conversion associated with the data transaction command.

[0114] In operation S532 , the memory controller 114 may perform a data communication operation with the memory cell array 122 according to a data transaction command associated with the memory request.

[0115] Figure 6 is a block diagram illustrating a system including a memory device that performs internal processing operations according to another embodiment of the inventive concept.

[0116] Figure 6 The system 600 may include a host device 110a and a storage device 120. Figure 1 Unlike the host device 110 of the system 100 shown in FIG. 1 , the host device 110 a may include a host processor 112 and a storage controller 114 a , and may not include a PIM agent 116 . Other components may be different from those in FIG. Figure 1 In the following, the components of Figure 1 The difference.

[0117] Reference Figure 6 , the storage controller 114a may be configured to include Figure 1 . The storage controller 114a may control the storage device 120 to operate in the internal processing mode. The storage controller 114a may activate the internal processing mode signal IPM and transmit it to the storage device 120 through the first channel CH1 or the second channel CH2. The storage controller 114a may receive an internal processing operation command IPCMD including an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE generated when the storage device 120 operates in the internal processing mode from the storage device 120 through the second channel CH2. The storage controller 114a may receive a completion signal DONE indicating completion of the internal processing operation from the storage device 120 through the second channel CH2.

[0118] The system 600 may include a host device 110a and a storage device 120 for performing a computing operation. Under the control of the host device 110a, the storage device 120 may perform a storage request operation according to the computing operation and perform an internal processing operation based on the internal processing information IPI stored in the storage cell array 122. When the internal processing information IPI includes or is an internal processing operation command IPCMD indicating the type of the internal processing operation, the storage device 120 may send the internal processing operation command IPCMD to the host device 110a. The host device 110a may issue a data transaction command for the storage request operation to the storage device 120. The host device 110a may issue a priority command to the storage device 120 by arbitrating between the data transaction command and the internal processing operation command IPCMD received from the storage device 120. When issuing the priority command to the storage device 120, the host device 110a may perform a virtual storage management function associated with the priority command including virtual storage address conversion. The storage device 120 may generate a completion signal indicating that the internal processing operation performed based on the internal processing information IPI is completed, and transmit the completion signal to the host device 110a.

[0119] Figure 7 is a block diagram illustrating a server system to which a system including a storage device that performs an internal processing operation according to an embodiment of the inventive concept can be applied.

[0120] Reference Figure 7 , the server system 700 may include multiple servers 100_1, 100_2, ..., 100_N. Multiple servers 100_1, 100_2, ..., 100_N may include storage devices connected to the PCIe bus. Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard designed to replace the PCI, PCI-X and Accelerated Graphics Port (AGP) bus standards. PCIe may include higher maximum system bus throughput, fewer I / O pins, smaller physical footprint, good bus device performance expansion and more detailed error detection and reporting mechanisms. Multiple servers 100_1, 100_2, ..., 100_N may be connected to the manager 710. Multiple servers 100_1, 100_2, ..., 100_N may include the above reference Figures 1 to 6 The system 100 described above may be Figures 1 to 6 The system 100 described is the same or similar.

[0121] Each of the plurality of servers 100_1, 100_2, ..., 100_N may include a host device and a storage device for performing a computing operation. Under the control of the host device, the storage device may perform a storage request operation according to the computing operation and perform an internal processing operation based on the internal processing information IMI stored in the storage cell array. When the internal processing information IMI includes or indicates an internal processing operation command IPCMD of the type of the internal processing operation, the storage device may send an internal processing operation command IPCMD including an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE to the host device. The host device may issue a data transaction command for a storage request operation to the storage device. The host device may issue a priority command to the storage device by arbitrating between the data transaction command and the internal processing operation command IPCMD received from the storage device. When issuing a priority command to the storage device, the host device may execute a virtual storage management function associated with the priority command including a virtual storage address conversion. The storage device may generate a completion signal indicating that the internal processing operation performed based on the internal processing information IMI is completed, and send the completion signal to the host device.

[0122] Figure 8 is a block diagram illustrating a data center of a system including a storage device that performs internal processing operations according to an embodiment of the inventive concept to which can be applied.

[0123] Reference Figure 8 , the data center 800 may include a plurality of server systems 700_1, 700_2, ..., 700_N. Each of the plurality of server systems 700_1, 700_2, ..., 700_N may be connected to Figure 7 810_1, 810_2, ..., 810_M. Although network 830 is shown as a separate single network, it can also be any type of network that can be generally understood by those of ordinary skill in the art. Network 830 can be a personal or public network, a wired or wireless network, or a whole or part of a network. According to one embodiment, network 830 can be a global network, a wide area network (WAN) or a local area network (LAN) such as the Internet or the World Wide Web ("Web" for short). Nodes 810_1, 810_2, ..., 810_M can include any one of client computers, other servers, remote data centers, and storage systems.

[0124] Each of the plurality of server systems 700_1, 700_2, ..., 700_N and / or nodes 810_1, 810_2, ..., 810_M may include a host device and a storage device for performing a computing operation. Under the control of the host device, the storage device may perform a storage request operation according to the computing operation and perform an internal processing operation based on the internal processing information IMI stored in the storage cell array. When the internal processing information IMI includes or indicates an internal processing operation command IPCMD of the type of the internal processing operation, the storage device may send an internal processing operation command IPCMD including an internal processing read command PIM_READ and / or an internal processing write command PIM_WRITE to the host device. The host device may issue a data transaction command for a storage request operation to the storage device. The host device may issue a priority command to the storage device by arbitrating between the data transaction command and the internal processing operation command IPCMD received from the storage device. When issuing a priority command to the storage device, the host device may execute a virtual storage management function including virtual storage address conversion associated with the priority command. The storage device may generate a completion signal indicating completion of an internal processing operation performed based on the internal processing information IMI, and transmit the completion signal to the host device.

[0125] Although the present invention has been described with reference to the embodiments shown in the accompanying drawings, this is only an example, and it will be appreciated by those skilled in the art that various modifications and other equivalent embodiments may be derived therefrom. Therefore, the spirit and scope of the present invention should be defined by the appended claims.

[0126] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a memory cell array configured to store internal processing information; as well as an in-memory processor configured to perform internal processing operations based on the internal processing information in an internal processing mode, wherein, in response to the in-memory processor determining that the internal processing information includes an internal processing operation command indicating a type of the internal processing operation, the in-memory processor requests the internal processing operation from an external device via a dedicated pin, and then receives the internal processing operation command from the external device based on the request, wherein the internal processing operation command is generated during execution of the internal processing operation by the processor in the memory based on the internal processing information, and the internal processing operation command includes an internal processing read command and an internal processing write command associated with the internal processing operation, and The in-memory processor includes a command queue configured to store and output at least one of the internal processing read command and the internal processing write command to the external device.

2. The storage device according to claim 1, further comprising a command / address buffer configured to receive a command issued from the external device, in, The in-memory processor includes a command detector configured to determine whether a received command includes the internal processing operation command.

3. The storage device according to claim 2, wherein: In response to determining that the received command includes the internal processing operation command, the in-memory processor performs a data communication operation with the memory cell array according to the internal processing operation command.

4. The storage device according to claim 1, wherein: The in-memory processor is configured to receive an internal processing mode signal from the external device indicating entry into the internal processing mode.

5. The storage device according to claim 4, wherein: The in-memory processor is configured to receive the internal processing mode signal from the external device through a signal line of a first channel executing a predetermined protocol between the external device and the memory device.

6. The storage device according to claim 4, wherein: The in-memory processor is configured to receive the internal processing mode signal from the external device through a dedicated signal line of a second channel between the external device and the memory device.

7. The storage device according to claim 1, wherein: The in-memory processor is configured to request the internal processing operation command from the external device through a dedicated signal line of a second channel between the external device and the memory device.

8. The storage device according to claim 1, wherein: The in-memory processor is further configured to generate a completion signal indicating completion of the internal processing operation, and send the completion signal to the external device to exit the internal processing mode.

9. The storage device according to claim 8, wherein: The internal processing operation includes at least one of an operation of reading internal processing data and an operation of writing a result of another internal processing operation into the memory cell array, the internal processing data including at least one of reference data, source data, destination data and target data.

10. The storage device according to claim 8, wherein: The internal processing operation includes performing at least one of data search, data transmission, data addition, and data exchange on the storage cell array according to the internal processing operation command received from the external device.

11. The storage device according to claim 1, wherein: The memory device is configured to receive a data transaction command from the external device through a signal line of a first channel executing a predetermined protocol between the external device and the memory device in a normal mode, and perform a data communication operation between the external device and the memory cell array according to the received data transaction command.

12. A method of operating a memory device, the memory device comprising a memory cell array and an in-memory processor configured to perform internal processing operations, the method comprising: Entering internal processing mode under the control of external devices; In the internal processing mode, the internal processing operation is performed by the in-memory processor based on the internal processing information stored in the memory cell array; as well as requesting the internal processing operation from the external device via a dedicated pin, and then receiving the internal processing operation command from the external device based on the request, in response to the in-memory processor determining that the internal processing information includes an internal processing operation command indicating a type of the internal processing operation, wherein the internal processing operation command is generated during execution of the internal processing operation by the processor in the memory based on the internal processing information, and the internal processing operation command includes an internal processing read command and an internal processing write command associated with the internal processing operation, and The in-memory processor includes a command queue configured to store and output at least one of the internal processing read command and the internal processing write command to the external device.

13. The method according to claim 12, further comprising: receiving a command from the external device; detecting whether the received command includes the internal processing operation command; as well as In response to determining that the received command includes the internal processing operation command, a data communication operation is performed between the memory cell array and the in-memory processor according to the internal processing operation command.

14. The method according to claim 12, wherein: Entering the internal processing mode under the control of the external device includes: receiving an internal processing mode signal from the external device indicating entering the internal processing mode.

15. The method according to claim 14, wherein: The internal processing mode signal is received through a signal line of a first channel executing a predetermined protocol between the external device and the storage device.

16. The method according to claim 14, wherein: The internal processing mode signal is received through a dedicated signal line of a second channel between the external device and the memory device.

17. The method according to claim 12, further comprising: generating a completion signal indicating completion of the internal processing operation performed; as well as The completion signal is sent to the external device through a dedicated signal line of a second channel between the external device and the storage device.

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