Additively manufactured programmable resistor jumper

Abstract

The present application discloses an additively manufactured programmable resistor jumper. A first conductive wiring structure (220) is electrically connected to a first electronic component (208). A second conductive wiring structure (220) is electrically connected to a second electronic component (210). An additive deposition process deposits a material (224) over a surface of a processed wafer (200) to form a conductive or resistive structure extending from a portion of the first conductive wiring structure (220) to a portion of the second conductive wiring structure (220) to configure a circuit including first and second electronic components (208, 210).

Description

Background Art

[0001] Analog and digital circuits can be adjusted during manufacturing to set circuit performance parameters and / or change circuit configurations. Fuses, electrically erasable programmable read-only memories (EEPROMs), and one-time programmable (OTP) memories can be used for different product options that are trimmed and / or programmed during microelectronic device manufacturing. However, these memory elements and / or fuses typically require additional mask steps and more die area, cost, and complexity, which limits product flexibility and reliability, and / or require precise special multi-pass testing and programming procedures to ensure reliability. Summary of the invention

[0002] The first conductive wiring structure is electrically connected to the first electronic component. The second conductive wiring structure is electrically connected to the second electronic component. The additive deposition process deposits material over the surface of the processed wafer to form a conductive or resistive structure that extends from an exposed portion of the first conductive wiring structure to an exposed portion of the second conductive wiring structure to configure a circuit including the first electronic component and the second electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a flow chart of a method of manufacturing a microelectronic device.

[0004] Figure 2 is a partial side view of a processed wafer having conductive material deposited to connect metallization features to configure the circuitry of the wafer.

[0005] Figure 3 A circuit system is schematically shown. Figure 2 A partial top view of the wafer.

[0006] Figure 4 is a partial side view of a processed wafer having resistive material deposited to provide resistors between metallization features to configure circuitry of the wafer.

[0007] Figure 5 is a partial side view of a processed wafer having semiconductor material deposited to connect metallization features to configure the circuitry of the wafer.

[0008] Figure 6 is a partial top view showing several die areas of a processed wafer prior to additive deposition.

[0009] Figure 7 FIG. 1 is a diagram showing additively deposited conductive, resistive, and semiconductor structures formed between metallization features to configure Figure 6A partial top view of the circuit system of the wafer.

[0010] Figure 8 It is shown Figure 6 and Figure 7 A partial top view of a singulated die of a wafer. DETAILED DESCRIPTION

[0011] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Moreover, in this specification, the term "coupled" or "coupled" includes indirect or direct electrical or mechanical connections, or a combination thereof. For example, if a first device is coupled to or coupled with a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intermediate devices and connections.

[0012] Figure 1 A method 100 of manufacturing and configuring a microelectronic device, such as a microelectronic device having an integrated circuit (IC), is shown. Unlike fuses, EEPROM, or OTP memory, the method 100 uses a printing or other additive deposition process to form a conductive or resistive material structure above a first surface (e.g., a top surface) of a processed wafer, such as a silicon wafer or a silicon-on-insulator ("SOI") wafer, to configure the circuitry of the electronic components of the wafer. The described examples facilitate trimming analog circuits, as well as programming digital and analog circuits to set or modify circuit configurations after wafer processing, prior to singulation and packaging during microelectronic device fabrication. The method 100 includes fabricating a wafer at 102, and configuring the circuitry of the electronic components of the processed wafer at 103 prior to final assembly and packaging. The wafer fabrication at 102 includes forming the electronic components on or in a semiconductor substrate, and a metallization process to form metallization structures above the substrate. The metallization process includes forming one or more dielectric layers, wherein the conductive wiring structure is connected to one or more electronic components to provide a processed wafer having a top surface that exposes two or more conductive wiring structures. The top surface of the metallization structure does not need to be planar. In some examples, the top surface exposes the conductive wiring structure of the uppermost metallization layer and also exposes the conductive wiring structure of a different (e.g., lower) metallization layer. Wafer manufacturing at 102 includes forming a passivation layer over a selected portion of the first surface of the wafer. When in use, the passivation layer forms a selected portion covering the top surface and exposes a portion of the conductive wiring structure.

[0013] The exemplary manufacturing method 100 includes a circuit configuration method 103. The processing at 103 includes using additive deposition to configure the circuit system of the electronic components of the processed wafer. The configuration processing at 103 includes performing a first wafer probe test at 104, which measures the parameters of the circuit system of the electronic components. The processed wafer includes a plurality of die regions that will eventually be singulated into individual integrated circuit dies for subsequent packaging to form microelectronic devices. In this example, each die region includes: (a) one or more electronic components formed on or in a corresponding portion of the die region of the semiconductor substrate of the processed wafer; and (b) a conductive wiring structure of a metallization structure for providing an external path for electrical interconnection by a probe machine. The first wafer probe test at 104 may include: (a) applying a probe signal to one or more probed electrical connections; and (b) measuring one or more parameters associated with the circuit system of the electronic components of the processed wafer. The probe test at 104 identifies the operability and performance parameters of the die region and its associated circuit system. The probe test can identify any faulty circuits. If the corresponding circuitry of the die region includes features for self-repair (e.g., spare memory cells), the die region may be identified for subsequent self-repair via additive deposition, as further described below. For each die region of the processed wafer, the first probe test 104 collects corresponding trim or configuration data to identify locations for subsequent additive deposition to set or modify the circuit configuration of the wafer.

[0014] At 106, method 100 also includes depositing material onto the top surface of the wafer from the exposed portion of the first conductive wiring structure to the exposed portion of the second conductive wiring structure to configure the circuit system of the electronic component. The position and / or material used in the deposition at 106 is determined at least in part according to (e.g., in response to or based on) one or more parameters measured during any wafer probe processing portion of 104. In this way, the circuit conditions of the measured processed wafer are selectively adjusted or set according to the wafer probe results. The additive deposition at 106 provides controlled formation of one or more structures connected between two or more exposed conductive wiring structures of the wafer metallization structure. The deposited structure operates as a jumper and / or resistor to modify or set the circuit configuration in the die. The additively deposited material forms an ohmic contact with the exposed portion of the conductive wiring structure of one or more metallization layers. The additively deposited material is tailored to produce an ohmic contact of a controlled metal-metal interface with the material (e.g., aluminum, copper, etc.) of the conductive wiring structure without producing a Schottky diode.

[0015] The deposition at 106 includes depositing a first conductive material to form a conductive jumper between an exposed portion of a first conductive wiring structure and an exposed portion of a second conductive wiring structure. The deposition at 106 includes depositing a resistive material to form a resistor or a fuse between an exposed portion of a first conductive wiring structure and an exposed portion of a second conductive wiring structure. The deposition at 106 includes depositing a semiconductor material to form a semiconductor structure between an exposed portion of a first conductive wiring structure and an exposed portion of a second conductive wiring structure. The deposition at 105 includes performing a printing process or other additive deposition process to form a material. The printing process at 106 is an inkjet process. In another example, the printing process at 106 is an electrostatic spray process. In another example, the printing process at 106 is a jet dispensing process. In another example, the printing process at 106 is a laser assisted deposition process. In another example, the printing process at 106 is a spraying process. In another example, the printing process at 106 is a screen printing process. A plurality of printing processes are performed at 106.

[0016] exist Figure 1 In the example method 100 of , a curing process is performed at 108 to cure the material deposited at 106. The processing at 108 includes pre-baking the wafer and exposing the deposited material to ultraviolet (UV) light to promote drying and establish the desired material properties of the first deposited material. In other embodiments, the optional curing process at 108 can be omitted.

[0017] Figure 1 The example method 100 includes performing a second wafer probe test at 110 after the additive deposition process at 106. The second wafer probe test at 110 measures one or more circuit parameters tested in the first wafer probe at 104. According to (e.g., in response to or based on) the results of the second wafer probe test at 110, further additive deposition may be performed along any curing process portions of 106 and 108. In other examples, the second wafer probe process at 110 may be omitted.

[0018] At 112, the exemplary method 100 also includes applying a voltage signal or a current signal to the deposited material to disconnect the first conductive wiring structure from the second conductive wiring structure. The material printed at 106 creates an electrical fuse at the following locations: (a) between the two conductive wiring structures; and (b) therefore between the electrical components connected to the two conductive wiring structures, respectively. The fuse material can be resistive to operate as a jumper for resistive interconnection of associated electrical components, or the fuse material can be disconnected (e.g., blown) at 112 by providing a voltage or current signal between the conductive wiring structures or between other externally accessible conductive features of the wafer. In another example, the material printed at 106 creates a resistor at the following locations: (a) between the two conductive wiring structures; and (b) therefore between the electrical components connected to the two conductive wiring structures, respectively. All or part of the resistive material can be removed, for example, by laser trimming at 112, to adjust the circuit system of the electronic component. For example, the resistive material may be additively deposited at an initial width at 106, and laser trimming may thereafter be used at 112 to narrow the deposited resistive material, thereby increasing resistance. This helps to fine-tune and trim circuit performance parameters before or after IC packaging to correct any changes in the performance of the circuit introduced by mechanical stresses from assembly and packaging of the IC. In the example shown, the desired one or more fuses are blown at 112 before assembly and packaging at 114. In other examples, a current or voltage signal is applied after the assembly process at 114. In yet another example, the signal application process at 112 may be omitted. The initial wafer probe operation at 104 and / or the subsequent wafer probe process at 110 include an optical probe to identify topographical features of the top surface 219 of the processed wafer 200, and the additive deposition process at 106 is adjusted to preferentially deposit material structures (e.g., conductive materials, resistive materials, semiconductor materials, etc.) in valleys or low-lying areas of the identified top surface 219. Thus, some manufacturing processes at 102 include planarizing the top surface 219, and other wafer manufacturing processes at 102 omit the top surface planarization process, leaving high and low topographic features on the top surface 219. In some embodiments, the additive deposition at 106 preferentially deposits material in the low areas between steps on the top surface 219. In one embodiment, the low areas are identified by optical wafer probing at 104 and / or 110. One example embodiment includes detecting characteristics of the surface at 110 and modifying the additive process at 106 to adjust for differences in the surface between dies for specific areas of the wafer to be modified.

[0019] The configuration process at 103 (eg, Figure 1After steps 104-112 in ), the exemplary manufacturing method 100 includes an assembly process at 114. The assembly process includes one or more of: back grinding the processed wafer; sawing or laser cutting the wafer to singulate the wafer into individual tube cores including corresponding circuits formed by electronic components; a tube core attach process to attach each tube core to a corresponding lead frame; wire bonding to attach bonding wires to the tube core and lead frame features; a cleaning process, such as a plasma cleaning step (e.g., Ar / O2); and a molding operation to form a completed microelectronic device (e.g., a microelectronic device with an integrated circuit). At 116, a final test is performed to verify the operation of the completed microelectronic device. The assembly process at 114 includes forming a passivation layer (e.g., Figure 2 230 in ) to cover all or at least a portion of the additively deposited material formed at 106. In the case where the deposited material includes silver, the additional passivation layer formed over the additively deposited silver helps prevent or mitigate silver migration. The subsequently formed passivation material can be deposited using any suitable process, including additive deposition (e.g., printing), chemical vapor deposition (CVD) to deposit nitride or oxynitride passivation materials, etc.

[0020] Figure 2 An example microelectronic device during fabrication according to example method 100 is shown. Figure 2 , a processed wafer 200 is shown, which includes an example die portion or die region 201. As described above, the wafer 200 is processed into an integral structure, including an example additive deposition process (e.g., Figure 1 106 ), and the wafer 200 is subsequently singulated into individual dies 201 . Figure 2 The device in the embodiment includes a semiconductor substrate 202 (e.g., a silicon wafer, an SOI wafer, etc.), and a number of electronic components are formed on or in the substrate 202. In the example shown, a polysilicon structure 204 is formed above the upper surface of the substrate 202, and an isolation structure 206 (e.g., a field oxide structure, a shallow trench isolation (STI) structure, etc.) is formed to isolate selected areas or regions of the substrate 202. Using conventional semiconductor processing techniques and equipment, one or more portions of the substrate 202 and / or one or more portions of the polysilicon structure 204 are selectively implanted with p-type or n-type impurities or dopants to form one or more electronic components. Some of the polysilicon structures 204 provide polysilicon resistors 208, and the example shown also includes a number of field effect transistors (e.g., MOSFETs) 210 formed on or in the substrate 202. Figure 2Example labels for some polysilicon resistors are shown, including resistor R1, resistor R2, resistor R3, and resistor R4. Other types and forms of electronic components may be formed on or in the substrate and / or subsequently formed metallization structures, such as inductors, capacitors, etc.

[0021] A first metallization layer 212 is formed over the upper surface of the substrate 202, the polysilicon structure 204, and the isolation structure 206. The first metallization layer or level 212 is referred to as a pre-metallization dielectric (PMD) layer and can be any suitable dielectric material, such as silicon dioxide (SiO2). Conductive contacts 214 are formed through the PMD layer 212 from a suitable conductive material (e.g., tungsten (W), copper (Cu), etc.) to form ohmic conductive contacts to select portions of the electronic components 208, 210. One or more additional metallization layers, referred to as interlayer dielectric (ILD) layers, are formed over the PMD layer 212 to provide a single or multilayer structure 216. The metallization structures 212, 216 include a final or uppermost ILD dielectric layer 218 having a top surface or upper surface 209. The ILD layer 216 includes conductive wiring structures to form interconnections through associated PMD layer contacts 214 to interconnect the various electronic components of the wafer 200 to each other and to provide external connections to various electronic component features of the electronic component features. The conductive wiring structures 220 (e.g., copper) have an upper surface exposed through a top surface or upper surface 219 of the final ILD layer 218. The illustrated example includes a passivation layer 222 (e.g., an oxide, an oxynitride, a polyamide, a nitride material, etc.) formed over selected portions of the top ILD layer 218. The passivation layer 222 exposes portions of the tops of the conductive wiring structures 220 shown.

[0022] exist Figure 2 In the example of , the metallization structures 212, 216 include first and second conductive wiring structures 220 electrically connected to specific resistors in the resistors 208, including: (a) a first (leftmost) conductive wiring structure 220 connected to a node joining resistors R2 and R4; and (b) a second conductive wiring structure 220 connected to a first end of resistor R3. The conductive, resistive, or semi-conductive connection of the first and second conductive wiring structures 220 to each other is made by additive deposition of material 224 to electrically connect the first end of resistor R3 to the node joining resistors R2 and R4. Figure 2In the example of , the processing at 106 is used to form a conductive material 224 between the conductive wiring structures 220 to provide an ohmic contact between the first end of the resistor R3 and the node joining R2 and R4. Examples of suitable deposited conductive materials 224 include nanoparticle materials, sol-gel, metal-salt decomposition, etc. This electrically connects R3 in parallel with the series combination of R1 and R2, and thus changes the circuit configuration of the resistor component 208. The example shown also includes a conductive wiring structure 220 electrically connected to the gate of the example transistor 210. In addition, a particular conductive wiring structure 220 is connected to a reference voltage node (e.g., Figure 2 marked as GND in the figure) and connected to the supply voltage node (for example, Figure 2 marked as VCC in the figure). Although Figure 2 The example shows the formation of structure 224 between exposed portions in the topmost metallization layer 218, but the additive deposition process at 106 is used in other examples to form structures (e.g., conductive structure 224) that are connected to conductive wiring structures in different layers of the multilayer metallization structure 216, such as where the top or first surface 219 of the metallization structure 212, 216 includes openings that expose portions of such conductive wiring structures of various metallization layers.

[0023] The processing at 106 produces a conductive material 224 that connects the gate of one of the transistor components 210 to the ground reference GND, and forms a second structure 224 that connects the gate of the other transistor 210 to the power supply voltage VCC. In this manner, the selective additive deposition of the material structure 224 over the top surface 219 of the metallization structures 212, 216 sets or adjusts the circuit configuration of the electronic components in the illustrated die area 201 of the wafer 200. Figure 2 Also shown is the use of a spraying or printing process using a print head or nozzle 226 during the creation of one of the conductive material structures 224. In this example, the deposition system is arranged along Figure 2 The print head or nozzle 226 is translated from left to right in direction 228 in order to deposit material 224 extending between selected conductive wiring structures 220 . Figure 2 Also shown is an example second passivation structure 230 formed over one of the additively deposited conductive material structures 224 .

[0024] Figure 3 Shown along Figure 2 A partial top view of the wafer 200 taken along line 3 - 3 includes an upper portion of the conductive wiring structure 220 exposed through the passivation layer 222 . Figure 3 Also shown are deposited conductive material structures 224 that join selected pairs of conductive wiring structures 220. Figure 3Circuit connections provided by conductive structures 224 are schematically illustrated to configure analog circuit 300 and digital circuit 310 .

[0025] Figure 3 The analog (eg, resistor) circuit 300 in Figure 3 The series connection of resistor components 208, labeled R1, R2, R4, R5, and R6 in the schematic diagram of FIG. 3 is formed. Resistor R1 and resistor R2 are connected between circuit nodes 302 and 304, and resistors R4-R6 are connected in series with each other between node 304 and another node 306. The bottom terminals or branches of resistors R1 and R3 are at Figure 2 302 to form the circuit node 302 shown. The additive deposition of structure 224 between the first conductive wiring structure 220 (connected to the upper terminal of R3) and the second conductive wiring structure 220 (connected to the node joining R2 and R4) connects resistor R3 in parallel with the series combination of R1 and R2. This sets or modifies the resistance in the circuit between node 302 and node 306. In contrast, the omission of the additively deposited structure 224 provides a different resistance between node 302 and node 306.

[0026] Figure 3 The digital circuit 310 in includes two or more inverters 312 that include transistor components 210. The inverters 312 include outputs that provide Boolean signals (e.g., having a first state or a different second state) that can be used to program or configure larger digital circuits and / or analog circuits. The input of the first inverter 312 is connected to the first conductive wiring structure 220, and the example deposited material structure 224 provides an ohmic electrical connection of the inverter input to the conductive wiring structure 220 connected to a reference voltage node (GND). After manufacturing, a microelectronic device formed using the example of the die will be programmed by a high signal at the output of the inverter 312 due to the additive deposition of the conductive material structure 224 during manufacturing. The second inverter 314 shown includes an input (e.g., a voltage at which the inverter 312 is electrically connected to the corresponding conductive wiring structure 220 through the metallization structures 212, 216). Figure 2 The gate of one of the transistor components 210 in FIG. Figure 3 The additively deposited conductive material structure 224 in provides an ohmic electrical contact between the input of the inverter 314 and the supply voltage conductive wiring structure 220. In operation of the resulting microelectronic device, the output of the inverter 314 will provide a low electrical signal.

[0027] Figure 4 Another example of a processed wafer 200 is shown, generally as described above in conjunction with Figure 2 In this example, Figure 1The additive deposition process at 106 forms a conductive material structure 224 to configure the above combined Figure 2 and Figure 3 The digital circuit 310. In this example, Figure 1 The additive deposition process at 106 of the method 100 deposits a conductive wiring structure 220 (connected to the Figure 3 304 in FIG. 304) to a resistive material 400 of the second conductive wiring structure 220 (connected to node 302). Examples of suitable resistor materials 400 include carbon-based materials and all their allotropes, polymers filled with carbon / conductive particles, solution deposited metals, etc. This creates a new resistor R7 in series with R3, and this series combination is connected in parallel with the series combination of R1 and R2 (at Figure 3 302 and 304 in FIG. 1 ). This example provides a method for performing a multi-threaded operation on a node 302 and a multi-threaded operation on a node 304. Figure 2 and Figure 3 The additively printed conductive material structures 224 shown have different resistances. Figure 1 The processing at 106 may include the performance of multiple additive deposition processes, such as: (a) a first additive deposition of conductive material 224 to configure digital circuit 310 ; and (b) a second additive deposition of resistive material 400 to configure analog circuit 300 .

[0028] Figure 5 Another example of a processed wafer 200 is shown, generally as described above in conjunction with Figure 2 In this further example, the additive deposition process at 106 forms the conductive material structure 224 to configure the digital circuit 310, and also deposits the conductive wiring structure 220 (connected to the first conductive wiring structure 220). Figure 3 The semiconductor material 500 extends from the node 304 in the resistor R3 to the second conductive wiring structure 220 (connected to the node 302). Examples of suitable semiconductor materials 500 include silicon and solid or liquid solutions containing silicon. This example is at the upper terminal of the resistor R3 and Figure 3 Two different semiconductor depositions are performed to produce the illustrated structure 500 to produce a diode between the first and second conductive wiring structures 220 in the analog circuit 300.

[0029] Figure 6 Shows Figure 1 2 is a top view of several die regions 201 of a processed wafer 200 after wafer fabrication at 102 and before additive deposition processing at 106. At this stage of the fabrication process, the top of the conductive wiring structure 220 is exposed through an opening in any passivation layer at the top surface 219 of the uppermost metallization structure dielectric layer 218, as generally described above in conjunction with Figure 2 In this example, Figure 1 The additive deposition process at 106 forms a conductive material structure 224 to configure the digital circuit 310, as described above in conjunction with Figure 2 and Figure 3 In this example, Figure 1 The additive deposition process at 106 of the method 100 deposits a conductive wiring structure 220 (connected to the Figure 3 304 in FIG. 304) to the resistive material 400 of the second conductive wiring structure 220 (connected to node 302). This creates a new resistor R7 in series with R3, and this series combination is combined with the series combination of R1 and R2 (in Figure 3 This example provides a parallel connection between node 302 and node 304. Figure 2 and Figure 3 The additively printed conductive material structures 224 shown have different resistances. Figure 1 The processing at 106 may include the performance of multiple additive deposition processes, such as: (a) a first additive deposition of conductive material 224 to configure digital circuit 310 ; and (b) a second additive deposition of resistive material 400 to configure analog circuit 300 .

[0030] Based on the wafer probe test at 104 or a predetermined manufacturing process, Figure 1 An additive deposition process is performed at 106 to provide Figure 7 200. In this example, various different material structures 224, 400 and 500 have been additively deposited over the metallization structure to provide conductive, resistive and / or semiconductor interconnects between pairs of exposed conductive wiring structures 220. In addition, as shown in this example, some digital circuits are programmed differently for different die regions 201. This example illustrates the flexibility of the described process 100 to allow some die to be configured in one way and other die to be configured differently with respect to the programming of the digital circuits 310. This example also illustrates that the analog circuits 300 of different die 201 can be configured differently on a single wafer 200. Figure 8 Shows Figure 6 and Figure 7 An example of a wafer 200 with singulated dies 201 is shown.

[0031] The described examples provide significant advantages over other analog and digital circuit trimming or programming techniques. For example, the described examples do not require significant die space, particularly compared to EEPROM, OTP and / or polysilicon fuse methods. In addition, the described methods do not require complex interconnection of circuit components or associated additional metallization structure layers compared to other circuit trimming or programming techniques. The described examples can be used for any suitable trimming or programming tasks during the manufacture of integrated circuits or microelectronic devices, such as configuration of temperature measurement circuits, reference voltage circuits, current measurement circuits, timing (e.g., clock) reference circuits, etc. In addition, the described examples can be used to create different products from a single IC design by configuring specific functions such as output stage topologies or specifications (e.g., regulated output voltages or detection thresholds). The examples use printed metal, conductive polymers, or other conductive / semiconductor / resistive materials 224, 400, 500 to create jumpers in place of traditional non-volatile memory for wafer-level trimming or other circuit configurations. The described examples also provide flexibility to allow unique configuration of each die on a wafer based on probe level measurements and / or according to a predetermined production plan. The described examples also provide enhanced circuit reliability by using additive deposition. Compared to polysilicon fuse technology (wherein polysilicon structures are fabricated during wafer processing and thereafter subjected to high current or laser cutting to "blow" or open fuses), the described examples do not suffer from the possibility of regrowth of fuses or laser links. The described examples also provide wide tolerances for changes in resistance / impedance of specific connections. Moreover, the described examples provide flexibility for a variety of different trimming and / or programming functions at very low cost without the need for additional mask layers to create new components. Example embodiments also help to accelerate manufacturing, where various spraying or printing additive deposition embodiments can print a 300mm wafer 200 with a unique pattern for each die 201 in less than five minutes.

[0032] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A method for manufacturing an integrated circuit, the method comprising: manufacturing a wafer including a surface exposing portions of a first conductive wiring structure and a second conductive wiring structure, wherein the first conductive wiring structure is electrically connected to a first electronic component and the second conductive wiring structure is electrically connected to a second electronic component; performing a wafer probe test to measure parameters of the circuit system; after performing the wafer probe test, additively depositing a material onto the surface of the wafer from an exposed portion of the first conductive wiring structure to an exposed portion of the second conductive wiring structure to configure the circuit system including the first electronic component and the second electronic component, wherein additively depositing the material includes depositing the material according to the parameter to configure the circuit system; as well as The wafer is singulated into individual dies, including a die containing the circuitry.

2. The method according to claim 1, further comprising: Prior to additively depositing the material, a passivation layer is formed over selected portions of the surface of the wafer.

3. The method according to claim 1, wherein the wafer probe test is a first wafer probe test, and the method further comprises: After additively depositing the material, a second wafer probe test is performed that measures the parameter. 4 . The method of claim 1 , wherein additively depositing the material comprises performing a printing process to deposit a conductive material to form a conductive jumper between the exposed portion of the first conductive wiring structure and the exposed portion of the second conductive wiring structure.

5. The method according to claim 4, wherein the printing process is selected from the group consisting of an inkjet process, an electrostatic jet process, a jet dispensing process, a laser assisted deposition process, a spray coating process and a screen printing process. 6 . The method of claim 1 , wherein additively depositing the material comprises performing a printing process to deposit a resistive material to form a resistor or a fuse between the exposed portion of the first conductive wiring structure and the exposed portion of the second conductive wiring structure.

7. The method according to claim 6, wherein the printing process is selected from the group consisting of an inkjet process, an electrostatic jet process, a jet dispensing process, a laser assisted deposition process, a spray coating process and a screen printing process.

8. The method of claim 6, further comprising at least one of the following: After additively depositing the material, applying a voltage signal or a current signal to the deposited material to disconnect the first conductive wiring structure from the second conductive wiring structure; and After additively depositing the material, a portion of the deposited material is removed to adjust the circuitry. 9 . The method of claim 1 , wherein additively depositing the material comprises performing a printing process to deposit a semiconductor material to form a semiconductor structure between the exposed portion of the first conductive wiring structure and the exposed portion of the second conductive wiring structure.

10. The method according to claim 9, wherein the printing process is selected from the group consisting of an inkjet process, an electrostatic jet process, a jet dispensing process, a laser assisted deposition process, a spray coating process and a screen printing process.

11. The method of claim 1 , wherein fabricating the wafer comprises: forming the first electronic component and the second electronic component on or in a semiconductor substrate; as well as A metallization structure is formed that exposes the portions of the first conductive wiring structure and the second conductive wiring structure, the metallization structure being formed over the substrate and comprising a dielectric layer.

12. The method according to claim 1, further comprising: After additively depositing the material, a passivation layer is formed over at least a portion of the material.

13. A method of manufacturing an integrated circuit, the method comprising: manufacturing a wafer including a surface exposing portions of a first conductive wiring structure and a second conductive wiring structure, wherein the first conductive wiring structure is electrically connected to a first electronic component and the second conductive wiring structure is electrically connected to a second electronic component; additively depositing material onto the surface of the wafer from an exposed portion of the first conductive wiring structure to an exposed portion of the second conductive wiring structure to configure a circuit system including the first electronic component and the second electronic component; singulating the wafer into individual dies, the dies including a die containing the circuitry; detecting characteristics of the surface; as well as Additive deposition of the material on the surface is modified to adjust for differences in the surface between dies for specific areas of the wafer.

14. A method of configuring a circuit system of an integrated circuit, the method comprising: Providing a processed wafer, the processed wafer comprising: a semiconductor substrate having electronic components; and a metallization structure including a dielectric layer; performing wafer probe testing to measure parameters of the circuit system; and After performing the wafer probe test, an additive deposition process is performed, wherein the additive deposition process deposits material above the dielectric layer to form a conductive or resistive structure extending from an exposed portion of a first conductive wiring structure to an exposed portion of a second conductive wiring structure to configure the circuit system, wherein the first conductive wiring structure is electrically connected to a first electronic component among the electronic components, the second conductive wiring structure is electrically connected to a second electronic component among the electronic components, and the circuit system includes the first electronic component and the second electronic component, and wherein performing the additive deposition process includes performing the additive deposition process according to the parameters to configure the circuit system.

15. The method of claim 14, wherein the wafer probe test is a first wafer probe test, and the method further comprises: After performing the additive deposition process, a second wafer probe test is performed to measure the parameter.

16. The method of claim 15, further comprising at least one of the following: After performing the second wafer probe test, applying a voltage signal or a current signal to the deposited material to disconnect the first conductive wiring structure from the second conductive wiring structure; and After depositing the material, a portion of the deposited material is removed to adjust the circuitry.

17. The method of claim 14, wherein the additive deposition process is selected from the group consisting of an inkjet process, an electrostatic spray process, a jet dispensing process, a laser assisted deposition process, a spray coating process, and a screen printing process.

18. The method of claim 14, further comprising at least one of the following: After depositing the material, applying a voltage signal or a current signal to the deposited material to disconnect the first conductive wiring structure from the second conductive wiring structure; and After depositing the material, a portion of the deposited material is removed to adjust the circuitry.

19. The method of claim 14, wherein the additive deposition process deposits a semiconductor material to form a semiconductor structure between the exposed portion of the first conductive wiring structure and the exposed portion of the second conductive wiring structure.

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