Complementary metal oxide semiconductor standard cell and computer readable medium

Abstract

The present invention discloses a complementary metal oxide semiconductor (MOS) CMOS standard cell circuit using metal lines in a first metal layer for routing and related methods. In one aspect, a CMOS standard cell circuit includes a first supply rail, a second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell, so that the metal line has a cut edge corresponding to the first cell boundary and the second cell boundary. Metal lines that are not cut corresponding to the first cell boundary and the second cell boundary can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing to reduce routing in other metal layers so that fewer vias and metal lines are disposed above the first metal layer.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application No. 15 / 487,222, filed on April 13, 2017, and entitled “COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (MOS) (CMOS) STANDARD CELL CIRCUITS EMPLOYING METAL LINES IN AFIRST METAL LAYER USED FOR ROUTING, AND RELATED METHODS,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technology of the present disclosure relates generally to complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits, and more particularly to the fabrication of CMOS standard cell circuits with increased performance and reduced power consumption. Background Art

[0004] A processor-based computer system may include a large number of integrated circuit (IC) arrays. Each IC has a complex layout design including multiple IC devices. Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits are often used to assist in making the design of ICs less complex and more manageable. In detail, CMOS standard cell circuits provide designers with default cell counts corresponding to commonly used IC devices that conform to specific design rules for selecting technologies. As a non-limiting example, a CMOS standard cell circuit (i.e., a standard cell circuit that includes both P-type dopant and N-type dopant semiconductor material diffusion regions to form P-type MOS (P-type MOS, PMOS) and N-type MOS (N-type MOS, NMOS) devices) may include a gate, an inverter, a multiplexer, and an adder. Compared to custom designing each circuit, using CMOS standard cell circuits enables designers to create ICs with a consistent layout design, thereby creating a more uniform and less complex layout design across multiple ICs.

[0005] Conventional CMOS standard cell circuits are manufactured using process technologies that form device elements with predefined technology node sizes. For example, a conventional CMOS standard cell circuit may employ process technologies to manufacture device elements with a width of ten (10) nanometers (nm) or seven (7) nm. CMOS standard cell circuits designed to have technology node sizes of ten (10) nm and below conventionally employ local interconnect wiring layers to obtain connections between multiple device nodes so that the CMOS standard cell circuits implement specific functions. For example, a CMOS standard cell circuit may employ a metal zero layer (M0) as a local interconnect wiring layer to interconnect the source, drain, and / or gate of a transistor to other device nodes in the CMOS standard cell circuit using vertical interconnect accesses (vias) and wiring in additional metal layers, such as metal one (M1) and metal two (M2).

[0006] As technology nodes and other lithographic feature sizes continue to decrease, a higher number of devices, such as transistors, can be fabricated in a smaller area within a die. Although CMOS standard cell circuits can be designed to have higher device densities, design rules for a given manufacturing technology, such as the spacing between specific nodes, need to be met to ensure that the CMOS standard cell circuits function in the desired manner. For example, one technique for achieving higher device density while complying with design rules regarding element spacing includes printing individual shapes (e.g., M0) of an interconnect wiring layer and cutting the interconnect wiring layer into multiple portions (i.e., multiple wires). Cutting the interconnect wiring layer (M0) in this manner results in multiple wires being separated by a width corresponding to the cut, wherein such separation is smaller than that which can be achieved by printing separate wires in the interconnect wiring layer. As a result, adjacent CMOS standard cells in a CMOS standard cell circuit may be placed closer together using the printing and cutting methods described above.

[0007] However, printing and cutting shapes in the interconnect wiring layer (M0) in the plurality of CMOS standard cells as described above results in additional vias and wires in the metal layer other than the interconnect wiring layer to interconnect the device nodes of the plurality of CMOS standard cells. The capacitance of such vias and wires increases the switching power of the CMOS standard cell circuit, thereby increasing the corresponding power consumption. In addition, the resistance of such vias combined with the increased resistance and capacitance of the additional metal wiring increases the delay of the CMOS standard cell circuit, which reduces the corresponding performance. Summary of the invention

[0008] Aspects disclosed in the embodiments include complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits that employ metal lines in a first metal layer for routing, and related methods thereof. In one aspect, the CMOS standard cell circuit includes a first supply rail (e.g., a voltage rail) and a second supply rail (e.g., a ground rail) disposed in the first metal layer. In addition, the CMOS standard cell circuit includes metal lines disposed in the first metal layer. The voltage rail and the ground rail are not cut during manufacturing, so that the voltage rail and the ground rail can be shared by adjacent CMOS standard cells in the corresponding CMOS standard cell circuit. One or more of the metal lines are dynamically cut during manufacturing, so that the metal lines have cut edges corresponding to first cell boundaries and second cell boundaries of the corresponding CMOS standard cell. In addition, one or more metal lines are not cut corresponding to the first and / or second cell boundaries (i.e., have uncut edges corresponding to at least one of the first cell boundary and the second cell boundary), wherein such metal lines can be used to interconnect nodes of a CMOS standard cell to nodes in an adjacent CMOS standard cell. In this way, the metal lines are dynamically cut so that the corresponding CMOS standard cell circuit can achieve a desired figure of merit (FOM) by using the metal lines in the first metal layer to interconnect nodes in adjacent CMOS standard cell circuits. In other words, dynamically cutting the metal lines in the first metal layer allows the first metal layer to be used for routing in the CMOS standard cell circuit, which reduces the amount of routing in other metal layers, so that fewer vertical interconnect accesses (vias) and metal lines are disposed above the first metal layer. Reducing the number of vias and metal lines disposed above the first metal layer reduces the resistance and capacitance of the CMOS standard cell circuit compared to conventional CMOS standard cell circuits, which results in increased performance and reduced power consumption.

[0009] In this regard, in one aspect, a CMOS standard cell is provided. The CMOS standard cell includes a first supply rail disposed in a direction in a first metal layer, a second supply rail disposed in the first metal layer in the direction, and a plurality of metal wires disposed in the first metal layer in the direction. Each metal wire of the plurality of metal wires corresponds to a track in a plurality of tracks. One or more metal wires of the plurality of metal wires have a cut edge corresponding to a first cell boundary of the CMOS standard cell. One or more metal wires of the plurality of metal wires have a cut edge corresponding to a second cell boundary of the CMOS standard cell, wherein the second cell boundary is on an opposite side of the CMOS standard cell compared to the first cell boundary. One or more metal wires of the plurality of metal wires have an uncut edge corresponding to at least one of the first cell boundary and the second cell boundary.

[0010] In another aspect, a CMOS standard cell circuit is provided. The CMOS standard cell circuit includes a plurality of CMOS standard cells. Each CMOS standard cell includes a first supply rail disposed in a direction in a first metal layer, a second supply rail disposed in the direction in the first metal layer, and a plurality of metal wires disposed in the direction in the first metal layer. Each metal wire of the plurality of metal wires corresponds to a track in a plurality of tracks. One or more metal wires of the plurality of metal wires have a cutting edge corresponding to a first cell boundary of a corresponding CMOS standard cell. One or more metal wires of the plurality of metal wires have a cutting edge corresponding to a second cell boundary of the corresponding CMOS standard cell, wherein the second cell boundary is on an opposite side of the corresponding CMOS standard cell compared to the first cell boundary. One or more metal wires of the plurality of metal wires have an uncut edge corresponding to at least one of the first cell boundary and the second cell boundary. One or more CMOS standard cells of the plurality of CMOS standard cells are disposed so that the second cell boundary of the one or more CMOS standard cells is substantially adjacent to the first cell boundary of one or more other CMOS standard cells. The one or more metal lines of two or more CMOS standard cells form a single continuous metal line spanning the corresponding tracks of the two or more CMOS standard cells.

[0011] In another aspect, a method for manufacturing a CMOS standard cell circuit by dynamically cutting metal lines in a first metal layer is provided. The method includes determining the placement of a plurality of metal lines and interconnects disposed above a first metal layer in one or more CMOS standard cells. The method also includes determining whether a first metal layer layout optimizer is available. The method also includes determining a layout of a plurality of instances of the one or more CMOS standard cells in response to determining that the first metal layer layout optimizer is available. The placement of the plurality of metal lines disposed in the first metal layer in the layout of each instance of the one or more CMOS standard cells is based on an optimized placement layout of the plurality of metal lines disposed in the first metal layer using orientation and adjacency variables of the one or more CMOS standard cells and a plurality of cell variation templates defining physical properties of each layout. The method also includes providing a layout of the plurality of instances of the one or more CMOS standard cells in response to determining that the first metal layer layout optimizer is not available. The placement of the plurality of metal lines disposed in the first metal layer in the layout of each instance of the one or more CMOS standard cells corresponds to the placement of the plurality of metal lines disposed in the first metal layer in the plurality of cell variation templates. The method also includes determining a plurality of corresponding design costs for each layout of each of the plurality of instances of the one or more CMOS standard cells. The method also includes building one or more first metal layer cost-based trees based on one or more corresponding variation seeds. Each first metal layer cost-based tree includes the plurality of design costs corresponding to a combination of the layouts of the one or more CMOS standard cells associated with the corresponding variation seeds. The method also includes determining the first metal layer cost-based tree including the plurality of design costs corresponding to merits. The method also includes placing and cutting the plurality of metal lines in the first metal layer according to the layout of each of the one or more CMOS standard cells of the determined first metal layer cost-based tree.

[0012] In another aspect, a non-transitory computer-readable medium is provided on which computer data is stored that, when used by a manufacturing system, allows the manufacturing system to manufacture a CMOS standard cell circuit. The CMOS standard cell circuit includes a plurality of CMOS standard cells. Each CMOS standard cell includes a first supply rail disposed in a direction in a first metal layer, a second supply rail disposed in the direction in the first metal layer, and a plurality of metal wires disposed in the direction in the first metal layer. Each metal wire of the plurality of metal wires corresponds to a track in a plurality of tracks. One or more metal wires of the plurality of metal wires have a cut edge corresponding to a first cell boundary of the corresponding CMOS standard cell. One or more metal wires of the plurality of metal wires have a cut edge corresponding to a second cell boundary of the corresponding CMOS standard cell, wherein the second cell boundary is on an opposite side of the corresponding CMOS standard cell compared to the first cell boundary. One or more metal wires of the plurality of metal wires have an uncut edge corresponding to at least one of the first cell boundary and the second cell boundary. One or more CMOS standard cells of the plurality of CMOS standard cells are disposed so that the second cell boundary of the one or more CMOS standard cells is substantially adjacent to the first cell boundary of one or more other CMOS standard cells. The one or more metal lines of two or more CMOS standard cells form a single continuous metal line spanning the corresponding tracks of the two or more CMOS standard cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a top view of an exemplary layout of an exemplary conventional complementary metal oxide semiconductor (MOS) (CMOS) standard cell fabricated by a conventional process of cutting all metal lines in a first metal layer at a first cell boundary and a second cell boundary of a conventional CMOS standard cell;

[0014] Figure 2 Is Figure 1 A top view of an exemplary layout of an exemplary conventional CMOS standard cell circuit formed by two (2) instances of a conventional CMOS standard cell, wherein the metal line in the first metal layer of each conventional CMOS standard cell is cut so that the metal line of each CMOS standard cell does not cross the boundary of the corresponding CMOS standard cell;

[0015] Figure 3 is a top view of an exemplary layout of an exemplary CMOS standard cell employing metal lines in a first metal layer for routing in order to increase performance and reduce power consumption;

[0016] Figure 4 Is Figure 3a top view of an exemplary layout of an exemplary CMOS standard cell circuit formed by two (2) instances of a CMOS standard cell of the present invention, wherein a metal line in a first metal layer of each CMOS standard cell has a cut edge corresponding to a first cell boundary, a second cell boundary and / or between the first cell boundary and the second cell boundary of each CMOS standard cell;

[0017] Figure 5 is a flow chart illustrating an exemplary process for fabricating a CMOS standard cell circuit that employs metal lines in a first metal layer for routing to increase performance and reduce power consumption;

[0018] Figure 6 is Figure 5 Illustration of an exemplary unit variation template used in the process of

[0019] Figure 7 yes Figure 5 An illustration of an exemplary first metal layer based cost tree generated during a process of;

[0020] Fig. 8A is a logic diagram of an exemplary buffer;

[0021] Figure 8B is used Figure 5 The manufacturing process is formed Fig. 8A A top view of an exemplary layout of a buffer;

[0022] Figure 8C is used Figure 5 The manufacturing process is formed Fig. 8A Alternative top view of an exemplary layout of a buffer of the layout;

[0023] Fig.8D is used Figure 5 The manufacturing process is formed Fig. 8A Another alternative top view of an exemplary layout of a buffer of the layout;

[0024] Fig. 9 is formed using conventional manufacturing processes that do not dynamically cut metal lines in the first metal layer Fig. 8A Alternative top view of an exemplary layout of a buffer of the layout;

[0025] Fig.10 is a block diagram of an exemplary processor-based system that may include Figure 4 CMOS standard cell circuits that employ metal lines in a first metal layer for routing to increase performance and reduce power consumption; and

[0026] Fig.11is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component formed in an integrated circuit (IC), wherein the RF component may include a Figure 4 A CMOS standard cell circuit that employs metal lines in the first metal layer for routing to increase performance and reduce power consumption. DETAILED DESCRIPTION

[0027] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be considered preferred or advantageous over other aspects. In addition, although power and ground connections are not illustrated in the drawings, any aspect described herein employs any power and ground connections necessary for operation as understood by a person of ordinary skill in the art.

[0028] exist Figure 3 Before beginning to discuss the details of an exemplary complementary metal oxide semiconductor (MOS) (CMOS) standard cell (i.e., a standard cell that includes both P-type dopant and N-type dopant semiconductor material diffusion regions to form both P-type MOS (PMOS) and N-type MOS (NMOS) devices) using metal lines in the first metal layer for routing, an exemplary conventional CMOS standard cell manufactured by a conventional process that does not use metal lines in the first metal layer for routing is first described.

[0029] At this point, Figure 1 1 is a top view of an exemplary layout 100 of an exemplary conventional CMOS standard cell 102. In detail, the CMOS standard cell 102 includes a first supply rail 104 (eg, voltage rail 104) and a second supply rail 106 (eg, ground rail 106) disposed in a first metal layer. The voltage rail 104 corresponds to the voltage rail T V , and the ground rail 106 corresponds to the ground rail T G. In addition, metal lines 108(1) to 108(6) for interconnecting nodes within the CMOS standard cell 102 are disposed in the first metal layer, wherein each metal line 108(1) to 108(6) corresponds to a track T(1) to T(6). Although the metal lines 108(1) to 108(6) are disposed between the voltage rail 104 and the ground rail 106 in this example, other examples may include the voltage rail 104 and the ground rail 106 disposed between the metal lines 108(1) to 108(6). The CMOS standard cell 102 also includes a P-type dopant semiconductor material diffusion region (P region) 110, an N-type dopant semiconductor material diffusion region (N region) 112, and gates 114(1) to 114(3) for forming one or more transistors in the CMOS standard cell 102. As a non-limiting example, the first metal layer may be a metal zero layer (e.g., M0) such that voltage rail 104, ground rail 106, and metal lines 108(1)-108(6) are disposed over P region 110, N region 112, and gates 114(1)-114(3).

[0030] Continue to view Figure 1, metal lines 108(1) to 108(6) are cut corresponding to the first cell boundary 116(1) and the second cell boundary 116(2) of the CMOS standard cell 102, so that the metal lines 108(1) to 108(6) are not electrically coupled to the metal lines on the first metal layer in the adjacent CMOS standard cell when they are disposed in the CMOS standard cell circuit. More specifically, the conventional process for manufacturing the CMOS standard cell 102 uses cutting masks 118(1), 118(2) to cut the metal lines 108(1) to 108(6) corresponding to the first cell boundary 116(1) and the second cell boundary 116(2), respectively. The cutting masks 118(1), 118(2) are not used to cut the voltage rail 104 and the ground rail 106, so that the voltage rail 104 and the ground rail 106 can be shared by adjacent CMOS standard cells in the corresponding CMOS standard cell circuit. In this example, the cutting masks 118(1), 118(2) can be single-patterned or multi-patterned. For example, in a single patterning process, one cut mask (e.g., cut mask 118(1)) corresponds to the first cell boundary 116(1), and one cut mask (e.g., cut mask 118(2)) corresponds to the second cell boundary 116(2). In this way, the single patterning process limits the vertical separation between the individual cut masks, thereby limiting which metal lines 108(1) to 108(6) can be cut. In a multiple patterning process, multiple cut masks (e.g., cut mask 118(1) divided into multiple cut masks) correspond to the first cell boundary 116(1), and multiple cut masks (e.g., cut mask 118(2) divided into multiple cut masks) correspond to the second cell boundary 116(2). In this way, the multiple patterning process reduces the vertical space between the cut masks and reduces or removes the limitation on which metal lines 108(1) to 108(6) can be cut. For example, if the metal lines 108(1)-108(6) are double patterned, the odd numbered tracks 108(1), 108(3), and 108(5) should have a different cut mask than the even numbered tracks 108(2), 108(4), and 108(6). Cutting the metal lines 108(1)-108(6) allows the CMOS standard cells 102 to have smaller separation from adjacent CMOS standard cells than can be achieved by printing the metal lines 108(1)-108(6) in the first metal layer for each corresponding CMOS standard cell. However, statically cutting the metal lines 108(1)-108(6) at the first cell boundary 116(1) and the second cell boundary 116(2) limits the metal lines 108(1)-108(6) from interconnecting nodes inside the CMOS standard cells 102.

[0031] At this point, Figure 2 is used Figure 1FIG. 2 is a top view of an exemplary layout 200 of an exemplary conventional CMOS standard cell circuit 202 (i.e., a standard cell circuit including both P-type dopant and N-type dopant semiconductor material diffusion regions to form both PMOS and NMOS devices) formed by two (2) instances of a conventional CMOS standard cell 102, referred to herein as CMOS standard cells 102(1), 102(2). Each CMOS standard cell 102(1), 102(2) includes Figure 1 The CMOS standard cell 102 has certain components in common, such as through Figure 1 and 2 The common element numbers between the embodiments are shown and therefore will not be repeated in this article.

[0032] Continue to view Figure 2 , the CMOS standard cell 102(1) includes a first supply rail 104(1) (e.g., voltage rail 104(1)), a second supply rail 106(1) (e.g., ground rail 106(1)), and metal lines 108(1)(1) to 108(1)(6) disposed in a first metal layer. The CMOS standard cell 102(1) also includes gates 114(1)(1) to 114(1)(3). Similarly, the CMOS standard cell 102(2) includes a first supply rail 104(2) (e.g., voltage rail 104(2)), a second supply rail 106(2) (e.g., ground rail 106(2)), and metal lines 108(2)(1) to 108(2)(6) disposed in a first metal layer. The CMOS standard cell 102(2) also includes gates 114(2)(1) to 114(2)(3). The voltage rails 104(1), 104(2) are connected using a gate that corresponds to the voltage rails T V The single metal line of 106(1) and 106(2) is formed so that the supply voltage can be shared between the CMOS standard cells 102(1) and 102(2). The ground rails 106(1) and 106(2) also use a single metal line corresponding to the ground rail T GThe CMOS standard cells 102(1) and 102(2) are formed by using a single metal line so that the CMOS standard cells 102(1) and 102(2) can share a ground voltage source. In addition, each of the corresponding metal lines 108(1)(1) to 108(1)(6) and 108(2)(1) to 108(2)(6) is initially formed using a single metal line corresponding to each track T(1) to T(6). However, the cutting mask 204(1) is used to cut the metal lines 108(1)(1) to 108(1)(6) corresponding to the first cell boundary 116(1)(1) of the CMOS standard cell 102(1), and the cutting mask 204(2) is used to cut the metal lines 108(2)(1) to 108(2)(6) corresponding to the second cell boundary 116(2)(2) of the CMOS standard cell 102(2). In addition, the cutting mask 204(3) is arranged corresponding to the second cell boundary 116(1)(2) of the CMOS standard cell 102(1) and the first cell boundary 116(2)(1) of the CMOS standard cell 102(2) so that each single metal line corresponding to the tracks T(1) to T(6) is cut to produce a distance DS between the metal lines 108(1)(1) to 108(1)(6) and the corresponding metal lines 108(2)(1) to 108(2)(6).

[0033] Continue to view Figure 2 , metal lines 108(1)(1) to 108(1)(6) are limited to interconnecting nodes within CMOS standard cell 102(1), while metal lines 108(2)(1) to 108(2)(6) are limited to interconnecting nodes within CMOS standard cell 102(2). Therefore, in order to interconnect nodes of CMOS standard cell 102(1) with nodes of CMOS standard cell 102(2), CMOS standard cell circuit 202 must employ vertical interconnect accesses (vias) and metal lines in metal layers other than the first metal layer. For example, if the first metal layer is M0, then additional metal lines in metal layer one (M1) and metal layer two (M2) may be used to interconnect nodes between CMOS standard cells 102(1), 102(2), wherein vias are used to interconnect metal lines between M0, M1, and M2. However, the capacitance of such vias and metal lines in M1 and M2 increases the switching power of CMOS standard cell circuit 202, thereby increasing the corresponding power consumption. Additionally, the resistance of such vias combined with the increased resistance and capacitance of the additional metal lines in M1 and M2 may increase the delay of the CMOS standard cell circuit 202, which reduces the corresponding performance.

[0034] At this point, Figure 33 is a top view of an exemplary layout 300 of an exemplary CMOS standard cell 302 that employs metal lines 304(1) to 304(6) in a first metal layer for routing in order to increase performance and reduce power consumption. In detail, the CMOS standard cell 302 includes a first supply rail 306 (e.g., voltage rail 306) and a second supply rail 308 (e.g., ground rail 308) disposed in a direction D and in the first metal layer. The voltage rail 306 corresponds to the voltage rail T V , and the ground rail 308 corresponds to the ground rail T G . In addition, metal lines 304(1)-304(6) are disposed in direction D and in the first metal layer, wherein each metal line 304(1)-304(6) corresponds to a track T(1)-T(6). Although in this example metal lines 304(1)-304(6) are disposed between voltage rail 306 and ground rail 308, other examples may include voltage rail 306 and ground rail 308 disposed between the metal lines 304(1)-304(6). CMOS standard cell 302 also includes a P region 310, an N region 312, and gates 314(1)-314(3) for forming one or more transistors in CMOS standard cell 302. As a non-limiting example, the first metal layer may be M0 such that voltage rail 306, ground rail 308, and metal lines 304(1)-304(6) are disposed over P region 310, N region 312, and gates 314(1)-314(3).

[0035] Continue to refer Figure 3 ,and Figure 1 Similar to the CMOS standard cell 102 of FIG. 1 , the voltage rail 306 and the ground rail 308 are not cut so that the voltage rail 306 and the ground rail 308 can be shared by adjacent CMOS standard cells in the corresponding CMOS standard cell circuit. However, as discussed in more detail below, the metal lines 304(1)-304(6) in this aspect are dynamically cut rather than being cut as in FIG. Figure 1For example, metal lines 304(1) to 304(3), 304(5), 304(6) are cut corresponding to the first cell boundary 316(1) of the CMOS standard cell 302, so that metal lines 304(1) to 304(3), 304(5), 304(6) have corresponding cut edges C(1) to C(5) corresponding to the first cell boundary 316(1). However, metal line 304(4) is not cut corresponding to the first cell boundary 316(1), so that metal line 304(4) has an uncut edge UC(1) corresponding to the first cell boundary 316(1). More specifically, an exemplary process for fabricating the CMOS standard cell 302 employs a cut mask 318(1)(1) to cut metal lines 304(1)-304(3) corresponding to a first cell boundary 316(1), and employs a cut mask 318(1)(2) to cut metal lines 304(5), 304(6) corresponding to the first cell boundary 316(1), while leaving metal line 304(4) uncut. Although the cut masks 318(1)(1), 318(1)(2) are each illustrated as a single shape, each cut mask 318(1)(1), 318(1)(2) may be employed using several masks depending on the type of patterning process used (e.g., single patterning, double patterning, triple patterning, etc.). In this manner, the metal line 304(4) may be used to interconnect nodes of the CMOS standard cell 302 to nodes in a CMOS standard cell disposed adjacent to the first cell boundary 316(1). In addition, the voltage rail 306 and the ground rail 308 have corresponding uncut edges UC_V(1), UC_V(2) and UC_G(1), UC_G(2) corresponding to the first cell boundary 316(1) and the second cell boundary 316(2), respectively, so that the voltage rail 306 and the ground rail 308 can be shared by adjacent CMOS standard cells.

[0036] Continue to refer Figure 3, metal lines 304(1), 304(2), 304(4) to 304(6) are cut corresponding to a second cell boundary 316(2) of the CMOS standard cell 302, the second cell boundary 316(2) being on an opposite side of the CMOS standard cell 302 compared to the first cell boundary 316(1). In this way, metal lines 304(1), 304(2), 304(4) to 304(6) have corresponding cut edges C(6) to C(10) corresponding to the second cell boundary 316(2). However, metal line 304(3) is not cut corresponding to the second cell boundary 316(2), so that metal line 304(3) has an uncut edge UC(2) corresponding to the second cell boundary 316(2). In detail, an exemplary process for fabricating the CMOS standard cell 302 employs a cut mask 318(2)(1) to cut metal lines 304(1), 304(2) corresponding to the second cell boundary 316(2), and employs a cut mask 318(2)(2) to cut metal lines 304(4) to 304(6) corresponding to the second cell boundary 316(2), while leaving the metal line 304(3) uncut. Although the cut masks 318(2)(1), 318(2)(2) are each illustrated as a single shape, each cut mask 318(2)(1), 318(2)(2) may be employed using a plurality of masks depending on the type of patterning process used (e.g., single patterning, double patterning, triple patterning, etc.). Thus, the metal line 304(3) may be used to interconnect nodes of the CMOS standard cell 302 to nodes in a CMOS standard cell disposed adjacent to the second cell boundary 316(2). In this manner, metal lines 304(1)-304(6) are cut dynamically (i.e., selectively) rather than statically to achieve a particular metric for a corresponding CMOS standard cell circuit by using metal lines 304(3), 304(4) in a first metal layer (e.g., M0) to interconnect nodes in a CMOS standard cell adjacent to CMOS standard cell 302. While this aspect includes uncut edges UC(1), UC(2) corresponding to metal lines 304(4), 304(3), respectively, other aspects may include uncut edges on any combination of metal lines 304(1)-304(6), wherein one or more of metal lines 304(1)-304(6) has an uncut edge on at least one of a first cell boundary 316(1) and a second cell boundary 316(2).

[0037] At this point, Figure 4 is used Figure 3FIG. 4 is a top view of an exemplary layout 400 of an exemplary CMOS standard cell circuit 402 formed by two (2) instances of a CMOS standard cell 302, referred to herein as CMOS standard cells 302(1), 302(2). Each CMOS standard cell 302(1), 302(2) includes Figure 3 The CMOS standard cell 302 has certain components in common, such as through Figure 3 and 4 The common element numbers between the embodiments are shown and therefore will not be repeated in this article.

[0038] Continue to refer Figure 4 , the CMOS standard cell 302(1) includes metal lines 304(1)(1) to 304(1)(6) disposed in a direction D and in a first metal layer, a first supply rail 306(1) (e.g., a voltage rail 306(1)), and a second supply rail 308(1) (e.g., a ground rail 308(1)). The CMOS standard cell 302(1) also includes a P region 310(1), an N region 312(1), and gates 314(1)(1) to 314(1)(3). In addition, a first cell boundary 316(1)(1) of the CMOS standard cell 302(1) is on an opposite side of the CMOS standard cell 302(1) than a second cell boundary 316(1)(2) of the CMOS standard cell 302(1). Similarly, the CMOS standard cell 302(2) includes metal lines 304(2)(1) to 304(2)(6) disposed in a direction D and in a first metal layer, a first supply rail 306(2) (e.g., a voltage rail 306(2)), and a second supply rail 308(2) (e.g., a ground rail 308(2)). The CMOS standard cell 302(2) also includes a P region 310(2), an N region 312(2), and gates 314(2)(1) to 314(2)(3). In addition, a first cell boundary 316(2)(1) of the CMOS standard cell 302(2) is on an opposite side of the CMOS standard cell 302(2) than a second cell boundary 316(2)(2) of the CMOS standard cell 302(2). The voltage rails 306(1), 306(2) are connected using a circuit corresponding to the voltage rails T. V The single metal line of 306(1) and 306(2) is formed so that the supply voltage can be shared between the CMOS standard cells 302(1) and 302(2). In other words, the voltage rails 306(1) and 306(2) are not cut, so that the voltage rails 306(1) and 306(2) include uncut edges UC_V(1)(1), UC_V(1)(2), UC_V(2)(1) and UC_V(2)(2). The ground rails 308(1) and 308(2) also use the ground rails T corresponding to the ground rails T. GThe single metal line of the CMOS standard cells 302(1) and 302(2) is formed so that the CMOS standard cells 302(1) and 302(2) may share a ground voltage. In other words, the ground rails 308(1) and 308(2) are not cut, so that the ground rails 308(1) and 308(2) include uncut edges UC_G(1)(1), UC_G(1)(2), UC_G(2)(1) and UC_G(2)(2).

[0039] Continue to refer Figure 4, each of the corresponding metal lines 304(1)(1) to 304(1)(6), 304(2)(1) to 304(2)(6) is initially formed using a single metal line corresponding to each track T(1) to T(6). However, a cutting mask 404(1)(1) is used to cut the metal lines 304(1)(1) to 304(1)(3) corresponding to the first cell boundary 316(1)(1), and a cutting mask 404(1)(2) is used to cut the metal lines 304(1)(5), 304(1)(6) corresponding to the first cell boundary 316(1)(1). Therefore, the CMOS standard cell 302(1) has corresponding cut edges C(1)(1) to C(1)(5), and an uncut edge UC(1)(1) corresponding to the first cell boundary 316(1)(1). The cutting mask 404(2) is used to cut the metal lines 304(2)(1) to 304(2)(6) corresponding to the second cell boundary 316(2)(2), so that the CMOS standard cell 302(2) has cutting edges C(2)(1) to C(2)(6) corresponding to the second cell boundary 316(2)(2). In addition, the cutting masks 404(3)(1) and 404(3)(2) are arranged corresponding to the second cell boundary 316(1)(2) of the CMOS standard cell 302(1) and the first cell boundary 316(2)(1) of the CMOS standard cell 302(2), wherein the second cell boundary 316(1)(2) is substantially adjacent to the first cell boundary 316(2)(1). Although the cutting masks 404(1)(1), 404(1)(2), 404(2), 404(3)(1), 404(3)(2) are each illustrated as a single shape, each cutting mask 404(1)(1), 404(1)(2), 404(2), 404(3)(1), 404(3)(2) may be employed using multiple masks depending on the type of patterning process used (e.g., single patterning, double patterning, triple patterning, etc.). In this manner, cutting masks 404(3)(1), 404(3)(2) produce metal lines 304(1)(1), 304(1)(2), 304(1)(4) to 304(1)(6) having cutting edges C(1)(6) to C(1)(10), and metal lines 304(2)(1), 304(2)(2), 304(2)(4) to 304(2)(6) having cutting edges C(2)(7) to C(2)(11). In addition, this results in metal lines 304(1)(1), 304(1)(2), 304(1)(4) to 304(1)(6) being separated from corresponding metal lines 304(2)(1), 304(2)(2), 304(2)(4) to 304(2)(6) by a distance DS.However, the cutting masks 404(3)(1) and 403(3)(2) respectively cause the metal lines 304(1)(3) and 304(2)(3) to have uncut edges UC(1)(2) and UC(2)(1) (i.e., have no corresponding cutting edges), so that a single continuous metal line is arranged across the corresponding tracks T(3) of the CMOS standard cells 302(1) and 302(2). In this way, a single continuous metal line corresponding to the metal lines 304(1)(3) and 304(2)(3) can be used to interconnect the nodes between the CMOS standard cells 302(1) and 302(2).

[0040] Continue to refer Figure 4 As a non-limiting example, if the first metal layer is M0, then the number of additional metal lines and corresponding vias in M1 and M2 can be reduced because the interconnection / routing of nodes between CMOS standard cells 302(1), 302(2) can be achieved using metal lines 304(1)(3), 304(2)(3) corresponding to track T(3) in M0. As used herein, M1 and M2 are metal layers disposed above the M0 metal layer. The reduced number of vias and metal lines disposed above the first metal layer is comparable to conventional CMOS standard cells, such as Figure 1 The CMOS standard cell 102 reduces the resistance and capacitance of the CMOS standard cells 302(1) and 302(2). The reduced resistance and capacitance in the CMOS standard cells 302(1) and 302(2) results in the CMOS standard cell circuit 402 being smaller than that of the CMOS standard cell circuit 402. Figure 2 The CMOS standard cell circuit 202 has increased performance and reduced power consumption.

[0041] Figure 5 An exemplary process 500 for CMOS standard cell circuit 402 is described by employing metal lines 304(1)(1)-304(1)(6) and 304(2)(1)-304(2)(6) in a first metal layer (e.g., M0) for routing in order to increase performance and reduce power consumption. In detail, process 500 represents an optimized method for placing and routing metal lines in a first metal layer while also complying with design rules for a corresponding manufacturing technology. In addition, process 500 as described herein may be used as a separate pre-processing step prior to using existing placement and routing tools, or integrated into existing placement and routing tools as an enhancement feature.

[0042] At this point, continue to refer to Figure 5, process 500 includes determining placement of metal lines and interconnects disposed above a first metal layer (e.g., M0) in CMOS standard cells 302(1), 302(2) (block 502). Process 500 also includes determining whether a first metal layer layout optimizer is available (block 504). If the first metal layer layout optimizer is available, process 500 includes determining a layout for each instance of CMOS standard cells 302(1), 302(2). More specifically, determining each layout includes placing metal lines 304(1)(1)-304(1)(6) and 304(2)(1)-304(2)(6) disposed in the first metal layer in the layout for each instance of CMOS standard cells 302(1), 302(2) based on optimized placement of metal lines 304(1)(1)-304(1)(6) and 304(2)(1)-304(2)(6) in combination with data from a cell variation template (block 506). For example, the first metal layer layout optimizer may optimize the placement of metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) based on adjacency and orientation variables corresponding to the CMOS standard cells 302(1), 302(2). Such adjacency and orientation variables may indicate how the CMOS standard cells 302(1), 302(2) should be oriented with respect to each other in the CMOS standard cell circuit 402. Additionally, the cell variation templates may include a data structure stored in a memory, wherein the cell variation templates describe each possible variation in the physical properties of the first metal layer usage for each instance of each CMOS standard cell 302(1), 302(2). For example, as discussed in more detail below, each cell variation template may include, for example, whether particular metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) may be cut on corresponding cell boundaries, and which tracks T V , T G and T(1) to T(6) may be used for routing. Additionally, if a first metal layer layout optimizer is not available, process 500 includes providing a layout for each instance of CMOS standard cells 302(1), 302(2), wherein placement of metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) disposed in the first metal layer in the layout for each instance of CMOS standard cells 302(1), 302(2) corresponds to placement of metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) disposed in the first metal layer (M0) in the cell variation template (block 508).

[0043] Continue to refer Figure 5, process 500 further includes determining, for each layout of each instance of CMOS standard cell 302(1), 302(2), a corresponding design cost (block 510). For example, block 510 may include determining a power cost, a performance cost, and / or an area cost for each layout variation based on metal-first layer (M0) usage. Based on the design costs determined in block 510, process 500 includes building a metal-first layer cost-based tree based on one or more corresponding variation seeds (block 512). As discussed in more detail below, each metal-first layer cost-based tree includes a design cost corresponding to a combination of layouts of CMOS standard cells 302(1), 302(2) associated with the corresponding variation seed. More specifically, variation seeds may be defined to control the total number of first metal layer cost-based trees that are built, wherein each variation seed may correspond to a particular set of permutations of the arrangement and physical properties of the CMOS standard cell circuit 402 (e.g., which metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) are cut or not cut, the order in which the CMOS standard cells 302(1), 302(2) are arranged / placed, etc.). In detail, a plurality of first metal layer cost-based trees are built to take into account the number of permutations that may be used to form the CMOS standard cell circuit 402 using the CMOS standard cells 302(1), 302(2).

[0044] Continue to refer Figure 5, process 500 includes determining a first metal layer cost-based tree including design costs corresponding to a figure of merit (FOM) (block 514). For example, the FOM may be determined to ensure that the corresponding layout 400 of the CMOS standard cell circuit 402 achieves desired power, performance, and area metrics by maximizing routing on the first metal layer (M0) to minimize routing on additional metal layers. Additionally, process 500 includes placing and cutting metal lines 304(1)(1)-304(1)(6) and 304(2)(1)-304(2)(6) in the first metal layer (e.g., M0) according to the layout of each of the CMOS standard cells 302(1), 302(2) corresponding to the determined first metal layer cost-based tree (block 516). For example, placing and cutting metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) in box 516 may include placing metal lines 304(1)(1) to 304(1)(6) and 304(2)(1) to 304(2)(6) and using cutting masks 404(1)(1), 404(1)(2), 404(2), 404(3)(1), and 404(3)(2) to form cut edges C(1)(1) to C(1)(10) and C(2)(1) to C(2)(11), and uncut edges UC(1)(1), UC(1)(2), and UC(2)(1). After placing and cutting metal lines 304(1)(1)-304(1)(6) and 304(2)(1)-304(2)(6), process 500 may include placing interconnects and metal lines over the first metal layer according to the layout (e.g., placing metal lines in M1 and M2). In this manner, using process 500 provides a layout of CMOS standard cell circuit 402 that achieves a desired FOM by optimizing routing in the first metal layer (M0) while reducing the amount of routing in additional metal layers, such as M1 and M2.

[0045] Figure 6 Description Figure 5 6. An exemplary cell variation template 600 for use with the process 500 of FIG. 6. In this aspect, the cell variation template 600 corresponds to a CMOS standard cell circuit, such as the CMOS standard cell circuit 402, which is used as an inverter and includes columns 602(1), 602(2) divided into rows 604(1) to 604(6). Column 602(1) corresponds to a specific attribute of the inverter, while column 602(2) includes a track T within the inverter to which the attribute in column 602(1) is applied. V , T Gand T(1) to T(6). For example, column 602(1), row 604(1) corresponds to the input of the inverter, where column 602(2), row 604(1) indicates that the input of the inverter can be accessed using the metal line in the first metal layer (M0) corresponding to track 3 (i.e., T(3)). Similarly, column 602(1), row 604(2) corresponds to the output of the inverter, where column 602(2), row 604(2) indicates that the output of the inverter can be accessed using the metal lines in the first metal layer (M0) corresponding to tracks 1 and 6 (i.e., T(1) and T(6)). In addition, column 602(1), row 604(3) corresponds to open tracks within the inverter, where column 602(2), row 604(3) indicates that the metal lines in the first metal layer (M0) corresponding to tracks 2, 4, and 5 (i.e., T(2), T(4), T(5)) are open.

[0046] Continue to refer Figure 6 , column 602(1), row 604(4) define an attribute indicating that the corresponding track in the first metal layer (M0) cannot be used on any boundary of the inverter, where column 602(2), row 604(4) indicates that tracks 0 and 7 (i.e., T V and T G ) has this attribute. In addition, column 602(1), row 604(5) defines an attribute indicating that the corresponding track in the first metal layer (M0) cannot be used on the left boundary of the inverter, wherein column 602(2), row 604(5) indicates that no track has this attribute. Column 602(1), row 604(6) defines an attribute indicating that the corresponding track in the first metal layer (M0) cannot be used on the right boundary of the inverter, wherein column 602(2), row 604(6) indicates that no track has this attribute. It is worth noting that other aspects of the cell variation template 600 can include various attributes in addition to the attributes listed in the cell variation template 600. By using a cell variation template, such as the data provided in the cell variation template 600, the process 500 can compare the design costs of various instances of each CMOS standard cell 302(1), 302(2) to determine an optimized utilization of the first metal layer (M0).

[0047] Figure 7 yes Figure 5FIG. 7 is an illustration of an exemplary first metal layer cost-based tree 700 generated during process 500 of FIG. 7 . In this aspect, the first metal layer cost-based tree 700 represents possible combinations of CMOS standard cells A(1), B(1)-B(2), and C(1)-C(3) that form a CMOS standard cell circuit. Additionally, each instance of each CMOS standard cell A(1), B(1)-B(2), and C(1)-C(3) has a corresponding FOM. For example, the first metal layer cost-based tree 700 has a root node corresponding to CMOS standard cell A(1) having a FOM of four (4). CMOS standard cell A(1) may be combined with CMOS standard cell B(1) having a FOM of two (2). If CMOS standard cell A(1) is combined with CMOS standard cell B(1), then the combination may be combined with CMOS standard cell C(1) having a FOM of three (3) or CMOS standard cell C(2) having a FOM of two (2). In this manner, the combination of CMOS standard cells A(1), B(1) and C(1) has a total FOM of nine (9) (i.e., 4+2+3=9), while the combination of CMOS standard cells A(1), B(1) and C(2) has a total FOM of eight (8) (i.e., 4+2+2=8). Alternatively, CMOS standard cell A(1) may be combined with CMOS standard cell B(2) having a FOM of one (1) and CMOS standard cell C(3) having a FOM of nine (9). In this manner, the combination of CMOS standard cells A(1), B(2) and C(3) has a total FOM of fourteen (14) (i.e., 4+1+9=14). In this aspect, the FOM is proportional to the M0 utilization, and therefore, the combination of CMOS standard cells A(1), B(2) and C(3) having a highest FOM of fourteen (14) corresponds to the most favorable design of the CMOS standard cell circuit.

[0048] To provide further clarification of the aspects provided herein, Figures 8A to 8D Description: You can use Figure 5 An exemplary buffer 800 manufactured by the process 500 is shown. Fig. 8A A logic diagram illustrating buffer 800, Figure 8B A top view illustrating an exemplary layout 802 of a buffer 800 is shown, and Figure 8C and 8D An alternative top view of a layout 802 of a buffer 800 is shown. The components of the buffer 800 are shown in FIG. Figures 8A to 8D are referenced by common component numbers. Figures 8A to 8D Buffer 800 is illustrated, but other devices, such as but not limited to AND-based gates (eg, NAND gates) and cross-coupled latches may also be used. Figure 5 The process 500 is manufactured as a CMOS standard unit circuit.

[0049] Continue to refer Figures 8A to 8D Buffer 800 includes inverters 804(1) and 804(2). Specifically, inverter 804(1) has an input node 806 and an output node 808, and inverter 804(2) has an input node 810 and an output node 812. The output node 808 of inverter 804(1) is electrically coupled to the input node 810 of inverter 804(2). Figure 8B , inverter 804(1) includes a voltage rail corresponding to T V and a first supply rail 814(1) (e.g., voltage rail 814(1)) having uncut edges UC_V(1)(1), UC_V(1)(2), wherein the voltage rail 814(1) is disposed in a first direction D1 in a first metal layer (e.g., M0). The inverter 804(1) also includes a ground rail T G and a second supply rail 816(1) (e.g., a ground rail 816(1)) having uncut edges UC_G(1)(1), UC_G(1)(2), wherein the ground rail 816(1) is disposed in a first direction D1 in a first metal layer (M0). The inverter 804(1) also includes metal lines 818(1)(1) to 818(1)(6) corresponding to rails T(1) to T(6) disposed in the first direction D1 and in the first metal layer (M0), cut edges C(1)(1) to C(1)(11), uncut edges UC(1)(1), a P region 820(1), an N region 822(1), and gates 824(1)(1) to 824(1)(3). In addition, the inverter 804(2) includes a voltage rail T corresponding to the voltage rail T V and a first supply rail 814(2) (e.g., voltage rail 814(2)) having uncut edges UC_V(2)(1), UC_V(2)(2), wherein the voltage rail 814(2) is disposed in a first direction D1 in a first metal layer (M0). The inverter 804(2) also includes a ground rail T corresponding to the ground rail T Gand a second supply rail 816(2) (e.g., ground rail 816(2)) having uncut edges UC_G(2)(1), UC_G(2)(2), wherein ground rail 816(2) is disposed in a first direction D1 and in a first metal layer (M0). Inverter 804(2) includes metal lines 818(2)(1) to 818(2)(6) corresponding to tracks T(1) to T(6) disposed in a first direction D1 and in a first metal layer (M0), cut edges C(2)(1) to C(2)(9), uncut edges UC(2)(1) to UC(2)(3), P regions 820(2), N regions 822(2), and gates 824(2)(1) to 824(2)(3). In this manner, voltage rails 814(1), 814(2) are connected using voltage rails T(1) to T(6). V The ground rails 816(1) and 816(2) are formed by a single metal line corresponding to the ground rail T G A single metal wire is formed.

[0050] Continue to refer Figure 8B , the input is provided to the gate 824(1)(2) (i.e., the input node 806), which is electrically coupled to the metal line 818(1)(3) by means of a via 826(1) (e.g., M0 via 826(1)). The metal line 818(1)(3) is electrically coupled to the metal line 828(1) by means of a via 830(1) (e.g., zero-level via V0 830(1)), wherein the metal line 828(1) is disposed in a second metal layer (e.g., M1) and in a second direction D2 orthogonal to the first direction D1. The P region 820(1) is electrically coupled to the metal line 818(1)(2) by means of a metal-to-diffusion (MD) line 832(1) and a via 834(1) (e.g., M0 via 834(1)). Similarly, N region 822(1) is electrically coupled to metal line 818(1)(5) by means of MD line 832(2) and via 834(2) (e.g., M0 via 834(2)). In addition, metal lines 818(1)(2), 818(1)(5) are electrically coupled to metal line 828(2) disposed in the second metal layer (M1) using respective vias 830(2), 830(3) (e.g., zero-level vias V0 830(2), 830(3)). Metal line 828(2) is electrically coupled to metal line 818(1)(4) using via 830(4) (e.g., zero-level via V0 830(4)) to form output node 808.

[0051] Continue to refer Figure 8B, buffer 800 is formed such that no cut corresponding to track T(4) is performed, so that metal lines 818(1)(4), 818(2)(4) form a single continuous metal line across track T(4) of inverters 804(1), 804(2), rather than using an additional metal layer, such as M2, to route output node 808 to input node 810. In this way, the output node 808 is interconnected to input node 810 using the first metal layer (M0). In detail, the single metal line corresponding to metal lines 818(1)(4), 818(2)(4) is electrically coupled to metal line 828(3) disposed in the second metal layer (e.g., M1) by means of vias 830(5) (e.g., zero-level via V0 830(5)). Via 830(6) (e.g., zero-level via V0 830(6)) electrically couples metal line 828(3) to metal line 818(2)(3), wherein metal line 818(2)(3) is electrically coupled to gate 824(2)(2) by means of via 826(2) (e.g., M0 via 826(2)). P region 820(2) is electrically coupled to metal line 818(2)(2) by means of MD line 832(3) and via 834(3) (e.g., M0 via 834(3)). Similarly, N region 822(2) is electrically coupled to metal line 818(2)(5) by means of MD line 832(4) and via 834(4) (e.g., M0 via 834(4)). Additionally, metal lines 818(2)(2), 818(2)(5) are electrically coupled to metal line 828(4) disposed in the second metal layer (M1) using respective vias 830(7), 830(8) (eg, V0 830(7), 830(8)).

[0052] In this way, continue to refer to Figure 8B , output node 808 is electrically coupled to input node 810 using metal lines 818(1)(4), 818(2)(4) corresponding to track T(4) in M0, thereby avoiding additional metal layers, such as additional vias and metal lines in M2. The reduced number of vias and metal lines disposed above the first metal layer reduces the resistance and capacitance of buffer 800 compared to conventional buffers, resulting in increased performance and reduced power consumption of buffer 800. In addition, other aspects of buffer 800 may be achieved by configuring process 500 to combine specific elements, such as floating gates, to achieve reduced area consumption. For example, process 500 may be configured to combine gates 824(1)(3), 824(2)(1) into a single floating gate so that the overall width of buffer 800 is reduced, thereby reducing area consumption.

[0053] Especially refer to Figure 8C, the alternative top view illustrates the use of a single metal line represented by metal lines 818(1)(4), 818(2)(4) corresponding to track T(4) to interconnect output node 808 to input node 810. Figure 8C The orientation of the inverters 804(1), 804(2) described in the above Figure 5 However, buffer 800 may be designed with alternative orientations of inverters 804(1), 804(2) to achieve different FOMs. For example, Fig.8D Another alternative top view of the layout 802 of the buffer 800 is illustrated. In detail, Fig.8D Including inverters 804(1) and 804(2), which are compared with Figure 8C Inverters 804(1) and 804(2) in are oriented as mirror images. In this way, Fig.8D The orientation in the embodiment results in the output node 808 being interconnected to the input node 810 by means of a single metal line represented by metal lines 818(1)(2), 818(2)(2) corresponding to track T(2), rather than using a single metal line represented by metal lines 818(1)(4), 818(2)(4) corresponding to track T(4) to interconnect the output node 808 to the input node 810. It is noteworthy that in this aspect, metal line 818(1)(2) has a cut edge C(1) and metal line 818(2)(2) has a cut edge C(2), so that the single metal line corresponding to track T(2) is limited to electrically coupling the output node 808 and the input node 810.

[0054] As a point of comparison, Fig. 9 Description and Fig. 8A An alternative top view of a layout 900 of a buffer 800 ′ similar to the buffer 800 is formed using conventional manufacturing procedures that do not dynamically cut metal lines in the first metal layer. Fig. 9 As described in FIG. 1 , if the first metal layer (e.g., M0) cannot be used to interconnect the output node 808' of the inverter 804'(1) to the input node 810' of the inverter 804'(2), then the metal line 902 in the additional metal layer (e.g., M2) is used to make the interconnection. However, in addition to the metal line 902, associated vias 904(1), 904(2) (e.g., M1 vias 904(1), 904(2)) are also used to electrically couple the metal line 902 and the metal lines 828'(2), 828'(3), respectively. The metal line 902 and the vias 904(1), 904(2) are more convenient than the metal line 902. Figures 8B to 8D The layout 802 in FIG. 8 increases the resistance and capacitance of the buffer 800 ′, resulting in higher power consumption and reduced performance of the buffer 800 ′.

[0055] CMOS standard cell circuits employing metal lines in a first metal layer for routing according to aspects disclosed herein, and related methods thereof, may be provided in or integrated into any processor-based device. Examples, but not limitation, include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet computer, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, goggles, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0056] At this point, Fig.10 An example of a processor-based system 1000 is described, which may include an Figure 4 Elements of a CMOS standard cell circuit 402 that employs metal lines in the first metal layer for routing in order to increase performance and reduce power consumption. In this example, a processor-based system 1000 includes one or more central processing units (CPUs) 1002, each of which includes one or more processors 1004. The one or more CPUs 1002 may have a cache memory 1006 coupled to the processor 1004 for quick access to temporarily stored data. The CPU 1002 is coupled to a system bus 1008 and may couple a master device and a controlled device included in the processor-based system 1000 to each other. As is well known, the CPU 1002 communicates with these other devices by exchanging address, control, and data information via the system bus 1008. For example, the CPU 1002 may communicate a bus change request to a memory controller 1010, which is an example of a controlled device. Although Fig.10 Although not illustrated, multiple system buses 1008 may be provided, wherein each system bus 1008 forms a different mesh architecture.

[0057] Other master devices and controlled devices can be connected to the system bus 1008. Fig.10, as illustrated in , these devices may include a memory system 1012, one or more input devices 1014, one or more output devices 1016, one or more network interface devices 1018, and one or more display controllers 1020, as examples. The input device 1014 may include any type of input device, including (but not limited to) input keys, switches, voice processors, etc. The output device 1016 may include any type of output device, including (but not limited to) audio, video, other visual indicators, etc. The network interface device 1018 may be any device configured to allow data to be exchanged to and from the network 1022. The network 1022 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM The network interface device 1018 may be configured to support any type of desired communication protocol. The memory system 1012 may include one or more memory units 1024(0)-1024(N).

[0058] The CPU 1002 may also be configured to access a display controller 1020 via the system bus 1008 to control information sent to one or more displays 1026. The display controller 1020 sends information to the display 1026 to be displayed via one or more video processors 1028, which process the information to be displayed into a format suitable for the display 1026. The display 1026 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0059] Fig.11 An exemplary wireless communication device 1100 is illustrated, which includes radio frequency (RF) components formed in an integrated circuit (IC) 1102, wherein the RF components may include a Figure 4 The wireless communication device 1100 may include or be provided in any of the above reference devices. Fig.11, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include a memory for storing data and program code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 that support bidirectional communication. In general, the wireless communication device 1100 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver 1104 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0060] The transmitter or receiver may be implemented with a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, for example, from RF frequency to an intermediate frequency (IF) in one stage, and then from IF frequency to baseband in another stage for the receiver. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.11 In the wireless communication device 1100 in FIG. 1 , the transmitter 1108 and the receiver 1110 are implemented using a direct conversion architecture.

[0061] In the transmit path, the data processor 1106 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog-converters (DACs) 1112(1), 1112(2) to convert the digital signals generated by the data processor 1106 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0062] Within the transmitter 1108, low pass filters 1114(1), 1114(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital to analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from the low pass filters 1114(1), 1114(2), respectively, and provide I and Q baseband signals. An up-converter 1118 up-converts the I and Q baseband signals, and I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 1122 via mixers 1120(1), 1120(2) to provide an up-converted signal 1124. A filter 1126 filters the up-converted signal 1124 to remove undesired signals caused by the up-conversion and noise in the receive band. A power amplifier (PA) 1128 amplifies the up-converted signal 1124 from the filter 1126 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.

[0063] In the receive path, antenna 1132 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134. The duplexer or switch 1130 is designed to operate with a specific receive (RX) to TX duplexer frequency separation so that the RX signal is separated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Down-converting mixers 1138(1), 1138(2) mix the output of filter 1136 and the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to produce I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers (AMPs) 1142(1), 1142(2) and further filtered by low-pass filters 1144(1), 1144(2) to obtain I and Q analog input signals, which are provided to the data processor 1106. In this example, the data processor 1106 includes analog-to-digital-converters (ADCs) 1146(1), 1146(2) to convert the analog input signals into digital signals to be further processed by the data processor 1106.

[0064] exist Fig.11In the wireless communication device 1100 of the embodiment, the TX LO signal generator 1122 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific basic frequency. The TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1122. Similarly, the RX phase-locked loop (PLL) circuit 1150 receives timing information from the data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1140.

[0065] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As a non-limiting example, the aspects disclosed herein may include a non-transitory computer-readable medium having stored thereon instructions that, when used by a manufacturing system, allow the manufacturing system to manufacture, for example, Figure 4 The computer data of the CMOS standard cell circuit 402 of the CMOS standard cell circuit in . As an example, the master control device and the controlled device described herein can be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been described above generally in terms of their functionality. How to implement this functionality depends on the specific application, design options and / or design constraints imposed on the entire system. A technician in the field can implement the described functionality in a varying manner for each specific application, but these implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0066] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The processor may be a microprocessor, but in an alternative example, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0067] The aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0068] It should also be noted that the operational steps described in any exemplary aspect herein are described to provide examples and discussion. The described operations may be performed in many different sequences that are different from the described sequence. In addition, the operations described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that the operational steps illustrated in the flow chart may be subject to many different modifications, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0069] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A complementary metal oxide semiconductor (CMOS) standard cell, comprising: a first supply rail disposed in a first metal layer in a direction; a second supply rail disposed in the first metal layer in the direction; and A plurality of metal lines arranged in the first metal layer in the direction, wherein: Each metal wire of the plurality of metal wires corresponds to a track of the plurality of tracks; One or more of the plurality of metal lines has a cut edge corresponding to a first cell boundary in the CMOS standard cell; One or more of the plurality of metal lines has a cut edge corresponding to a second cell boundary of the CMOS standard cell, wherein the second cell boundary is on an opposite side of the CMOS standard cell compared to the first cell boundary; and One or more of the plurality of metal lines has an uncut edge corresponding to at least one of the first cell boundary and the second cell boundary, further comprising one or more metal lines disposed in a second metal layer and in a second direction, the second direction being substantially orthogonal to a direction of one or more vertical interconnect access vias disposed between the first metal layer and the second metal layer, wherein the one or more vias electrically couple the one or more metal lines in the second metal layer and the one or more metal lines in the first metal layer, and wherein: The first metal layer includes a metal zero layer M0; The second metal layer includes a metal layer M1 disposed above the first metal layer; and The one or more through-vias include one or more zero-level through-vias V0. 2 . The CMOS standard cell of claim 1 , wherein the plurality of metal lines in the first metal layer are disposed between the first supply rail and the second supply rail.

3. The CMOS standard cell according to claim 1, wherein: The first supply rail is disposed between the plurality of metal lines in the first metal layer; and The second supply rail is disposed between the plurality of metal lines in the first metal layer.

4. The CMOS standard cell according to claim 1, which is integrated into an integrated circuit IC.

5. The CMOS standard cell of claim 1 integrated into a device selected from the group consisting of: an entertainment unit; a communication device; a fixed location data unit; a mobile location data unit; a tablet; a computer; a monitor; a tuner; and a vehicle component.

6. A complementary metal oxide semiconductor (CMOS) standard unit circuit, comprising: A plurality of CMOS standard cells according to any one of claims 1 to 5, in: One or more of the plurality of CMOS standard cells are arranged such that the second cell boundary of the one or more CMOS standard cells is substantially adjacent to the first cell boundary of one or more other CMOS standard cells; and The one or more metal lines of two or more CMOS standard cells form a single continuous metal line spanning the corresponding tracks of the two or more CMOS standard cells. 7 . The CMOS standard cell circuit of claim 6 , wherein the plurality of metal lines in the first metal layer of each CMOS standard cell are disposed between the first supply rail and the second supply rail.

8. The CMOS standard unit circuit according to claim 6, wherein: The first supply rail of each CMOS standard cell is disposed between the plurality of metal lines in the first metal layer; and The second supply rail of each CMOS standard cell is disposed between the plurality of metal lines in the first metal layer.

9. A non-transitory computer readable medium having stored thereon computer data which, when used by a manufacturing system, allows the manufacturing system to manufacture the CMOS standard cell circuit according to any one of claims 6 to 8.

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