Substrate with embedded traces

Abstract

The present disclosure relates to substrates with embedded traces. Provided herein is an embodiment of a substrate with one or more embedded traces and a method for manufacturing one or more embedded traces. The method includes: forming a bump on a first major surface of the substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace, the trace including a lower trace portion in direct contact with the first major surface, a sidewall trace portion in direct contact with at least one sidewall of the bump, and an upper trace portion in direct contact with the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Description

Technical Field

[0001] The present disclosure relates generally to microelectronic packaging and, more particularly, to substrates having embedded traces. Background Art

[0002] Electronic components, such as semiconductor dies, are typically attached to a substrate, which is typically a board made of a non-conductive material that includes conductive structures to form electrical connections between the electronic components and external conductive structures. The substrate can be flexible or rigid and provides adequate mechanical support for the attached electronic components. Summary of the invention

[0003] According to a first aspect of the present invention, there is provided a method for manufacturing one or more embedded traces, the method comprising:

[0004] forming a bump on the first major surface of the substrate, the bump having a height measured from the first major surface to a top surface of the bump;

[0005] forming a trace, the trace comprising:

[0006] a lower trace portion in direct contact with the first major surface,

[0007] a sidewall trace portion in direct contact with at least one sidewall of the bump, and

[0008] an upper trace portion in direct contact with the top surface of the bump;

[0009] depositing a blanket dielectric layer over the traces; and

[0010] A top portion of the blanket dielectric layer is etched away to expose a top surface of the upper trace portion.

[0011] In one or more embodiments, the top surface of the upper trace portion is coplanar with a top surface of a remainder of the blanket dielectric layer.

[0012] In one or more embodiments, the top surface of the upper trace portion extends beyond a top surface of a remainder of the blanket dielectric layer.

[0013] In one or more embodiments, the first major surface of the substrate includes a dielectric material.

[0014] In one or more embodiments, the substrate comprises a metal-clad dielectric core board covered by a dielectric material.

[0015] In one or more embodiments, the bump includes a dielectric bump.

[0016] In one or more embodiments, the bump includes a metal bump.

[0017] In one or more embodiments, forming the bump includes:

[0018] depositing a base dielectric layer over and in direct contact with the first major surface of the substrate;

[0019] depositing a photoresist mask on the base dielectric layer and patterning the photoresist mask to define areas where the dielectric bumps are to be formed;

[0020] removing portions of the base dielectric layer outside the photoresist mask to form the dielectric bumps in the regions; and

[0021] The photoresist mask is removed.

[0022] In one or more embodiments, forming the bump includes:

[0023] depositing a base dielectric layer over and in direct contact with the first major surface of the substrate, wherein the base dielectric layer is photoimageable;

[0024] photoimaging portions of the base dielectric layer to define areas where the dielectric bumps are to be formed; and

[0025] Non-photoimaged portions of the base dielectric layer are removed to form the dielectric bumps in the regions.

[0026] In one or more embodiments, forming the bump includes:

[0027] depositing a blanket seed layer over and in direct contact with the first major surface of the substrate;

[0028] depositing a photoresist mask on the blanket seed layer and patterning the photoresist mask to define areas where the metal bumps are to be formed;

[0029] plating exposed portions of the blanket seed layer to form the metal bumps in the regions; and

[0030] The photoresist mask and any portion of the blanket seed layer underlying the photoresist mask are removed.

[0031] In one or more embodiments, forming the trace includes:

[0032] depositing a blanket seed layer over the first major surface of the substrate, including over the bump, wherein the blanket seed layer is in direct contact with the first major surface, at least one sidewall of the bump, and the top surface of the bump;

[0033] depositing a photoresist mask on the blanket seed layer and patterning the photoresist mask to define areas including the bumps where the traces are to be formed;

[0034] plating exposed portions of the blanket seed layer to form the traces in the regions; and

[0035] The photoresist mask and any portion of the blanket seed layer underlying the photoresist mask are removed.

[0036] In one or more embodiments, the method further comprises:

[0037] One or more columns of metal-filled vias are formed over the bumps, wherein the bumps comprise metal bumps.

[0038] In one or more embodiments, each of the one or more metal-filled vias is formed by:

[0039] depositing and patterning a photoresist mask on a top surface of the substrate, the photoresist mask having openings aligned with an underlying metal surface;

[0040] plating the underlying metal surface to form a metal-filled via within the opening;

[0041] removing the photoresist mask;

[0042] depositing a second blanket dielectric layer over the metal-filled via; and

[0043] A top portion of the second blanket dielectric layer is etched away to expose a top surface of the metal-filled via.

[0044] In one or more embodiments, the underlying metal surface is one of a group including the top surface of the upper trace portion and a top surface of an underlying metal-filled via.

[0045] In one or more embodiments, the method further comprises:

[0046] A second trace is formed in contact with a top surface of the top metal-filled via of the one or more via columns, the top surface being exposed in the top dielectric layer of the substrate.

[0047] In one or more embodiments, the method further comprises:

[0048] A second metal bump is formed in contact with a top surface of the top metal-filled via of the one or more via columns, the top surface being exposed in the top dielectric layer of the substrate.

[0049] In one or more embodiments, the method further comprises:

[0050] forming a second trace, the second trace being over and in contact with the second metal bump, wherein the second trace comprises:

[0051] a lower trace portion in direct contact with the top dielectric layer,

[0052] a sidewall trace portion in direct contact with at least one sidewall of the second metal bump, and

[0053] An upper trace portion is in direct contact with the top surface of the second metal bump.

[0054] In one or more embodiments, the method further comprises:

[0055] depositing a second blanket dielectric layer over the second trace; and

[0056] A top portion of the second blanket dielectric layer is etched away to expose a top surface of the upper trace portion to form a bondable surface.

[0057] In one or more embodiments, the method further comprises:

[0058] Before forming the bumps, cross-directional traces are formed directly on the first major surface, wherein

[0059] The cross-direction traces extend in a first direction,

[0060] The trace including the lower trace portion, the sidewall trace portion and the upper trace portion extends in a second direction perpendicular to the first direction, and

[0061] The bumps include dielectric bumps formed over and in direct contact with top surfaces and sidewalls of the cross-directional traces.

[0062] In one or more embodiments, the cross-direction trace has a first height measured from the first major surface to the top surface of the cross-direction trace,

[0063] The dielectric bump has a second height measured from the first major surface to a top surface of the dielectric bump, the second height being greater than the first height, and

[0064] The upper trace portion is in direct contact with the top surface of the dielectric bump and has a third height measured from the first major surface to the top surface of the upper trace portion, the third height being greater than the second height.

[0065] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0067] Figures 1A to 1K is a block diagram depicting an exemplary embedded trace manufacturing process flow according to some embodiments of the present disclosure.

[0068] Figures 2A to 2D is a block diagram depicting exemplary alternative embedded trace fabrication process steps according to some embodiments of the present disclosure.

[0069] Figures 3A to 3J is a block diagram depicting another exemplary embedded trace manufacturing process flow according to some embodiments of the present disclosure.

[0070] Figures 4A to 4E is a block diagram depicting an exemplary stacked via manufacturing process flow according to some embodiments of the present disclosure.

[0071] Figures 5A to 5J is a block diagram depicting an additional exemplary embedded trace manufacturing process flow according to some embodiments of the present disclosure.

[0072] Figure 6 , 7A 7D and 8A to 8E are block diagrams depicting an exemplary cross-direction embedded trace manufacturing process flow according to some embodiments of the present disclosure.

[0073] The present invention is illustrated by way of example and not limited by the accompanying drawings, in which like reference numerals designate similar elements unless otherwise indicated. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale. DETAILED DESCRIPTION

[0074] The following sets forth a detailed description of various embodiments that is intended to illustrate the present invention and should not be construed as limiting.

[0075] Overview

[0076] Manufacturing the substrate can be expensive depending on the technology used. For example, some technologies use a disposable carrier on which layers are built using additive methods, which is generally more expensive than using a copper clad core and using conventional build-up layer processes. In addition, as technology develops, the need for a large number of interconnects on the substrate becomes greater.

[0077] The present disclosure provides a method for manufacturing a substrate having one or more embedded traces. An embedded trace is a trace formed above a bump, which may be a dielectric bump or a metal bump formed on a major surface of a substrate. The trace extends along the major surface, along at least one sidewall of the bump, and along the top surface of the bump. The trace can be formed using photolithography and plating. The trace is embedded in a dielectric material, and the top surface of the portion of the trace located on the top of the bump is exposed by the dielectric material. The top surface acts as a bondable surface to which an electrical component or an external conductive structure (such as a wire bond or a solder ball) can be attached. The underlying bump provides mechanical support for attachment to the external conductive structure, wherein the embedded properties of the underlying bump and the trace are also used to anchor the bondable surface without shifting during attachment. The bondable surface may be coplanar with the surrounding dielectric material, or may extend beyond the surrounding dielectric material to improve attachment.

[0078] The present disclosure also provides a method for manufacturing a substrate having one or more metal-filled vias, which can be formed using photolithography and plating. The metal-filled vias can be stacked to form a column of metal-filled vias with a smooth vertical profile compared to micro-vias made using conventional methods. The present disclosure also provides a method for manufacturing a substrate having cross-directional traces, wherein one trace can extend along the main surface of the substrate, a dielectric bump is formed above the trace to act as a "bridge", and another trace is formed above the dielectric bump to cross the underlying trace.

[0079] The substrates disclosed herein provide mechanical support and electrically connect electronic components using conductive structures, which may include any number of embedded traces, bondable surfaces, metal-filled vias, and cross-directional traces, as discussed herein.

[0080] Exemplary Embodiments

[0081] Figures 1A to 1KA cross-sectional view of various process steps in an exemplary embedded trace manufacturing process flow including forming a dielectric bump is shown. The embedded trace manufacturing process can be implemented as part of a built-in process, wherein a plurality of built-in layers (such as conductive layers and dielectric layers) are formed on a core board (such as a coated or uncoated core board) forming a substrate, or formed on a board that provides mechanical support and uses a conductive structure to electrically connect electronic components, as discussed below. The embedded trace manufacturing process can be implemented at various points during such a built-in process, such as during the initial stages of the built-in process to form a bump on or near the main surface of the core board, or during a later stage of the built-in process to form a bump near the outermost surface of the resulting substrate, or at any point therebetween to form a bump in the built-in layer of the substrate. The built-in layer includes a conductive material layer, a dielectric material layer, or both built above the top side, bottom side, or both of the top side and bottom side of the core board forming the substrate.

[0082] Figure 1A A cross-sectional view of a substrate 100 having a top surface 102 and a bottom surface 104 is shown. In some embodiments, the substrate 100 may be a bare or uncoated dielectric core board made of a dielectric core material having a top dielectric surface 102 and a bottom dielectric surface 104. In other embodiments, the substrate 100 may be a metal-coated dielectric core board made of a dielectric core material having a metal layer, the metal layer being laminated, coated, or bonded to the top surface of the dielectric core material to provide a top metal surface. Similarly, the metal layer may be laminated, coated, or bonded to the bottom surface of the dielectric core material to provide a bottom metal surface. The top metal surface and the bottom metal surface are also covered by a dielectric material (completely or partially) to provide a top dielectric surface 102 and a bottom dielectric surface 104. In some embodiments, the substrate 100 may also include one or more build-up layers formed on both sides of the substrate 100, wherein the outermost top build-up layer and the outermost bottom build-up layer of the dielectric material on the substrate 100 provide a top dielectric surface 102 and a bottom dielectric surface 104, respectively. The example of dielectric core material may include but is not limited to one or more of the following: glass, fiberglass, FR4, BT resin, ceramic, polyimide and the like. The example of coating or metal layer may include but is not limited to metal foil, such as copper foil or aluminum foil, which may be laminated on one side or both sides of dielectric core board material. The example of dielectric material includes but is not limited to silicon oxide, silicon nitride, silicon dioxide, silicon oxynitride, polyimide, other suitable materials (including oxide, nitride) and the like. The example of conductive material includes but is not limited to copper, gold, aluminum or other suitable conductive materials or an alloy consisting of one or more suitable metals.

[0083] Figure 1AAlso shown is a dielectric material that is deposited over the top surface 102 and the bottom surface 104 to form a layer 106 that is in direct contact with the top surface 102 and a layer 106 that is in direct contact with the bottom surface 104, wherein each layer 106 has an outer surface 108. Examples of deposited materials (such as dielectric material layer 106 or other materials, such as photoresist materials) include, but are not limited to, growth, oxidation, sputtering, and conformal deposition. It should be noted that the surfaces 102 and 104 of the embodiments described herein may also be referred to as major surfaces, such as a first major surface and a second major surface. Layer 106 acts as a base dielectric layer 106, and one or more dielectric bumps are formed from the base dielectric layer 106, as discussed further below. In the following figures, only half of the substrate 100 is shown for simplicity purposes. For example, Figure 1B One side of a substrate 100 is shown having a major surface 110, which can be considered as a top side of the substrate 100 including a top surface 102 or a bottom side of the substrate 100 including a bottom surface 104, wherein a base dielectric layer 106 is formed directly on the major surface 110. It should also be noted that the process steps described herein can be applied to the top side, the bottom side, or both sides of the substrate 100 in a sequential manner or in a parallel manner.

[0084] Figure 1C A layer of photoresist material is shown deposited over the side of substrate 100 and patterned into a photoresist mask 114, which directly contacts the outer surface 108 of the base dielectric layer 106. A photoresist mask (such as photoresist mask 114) can be patterned using ultraviolet (UV) light applied to the photoresist material through a photomask to develop portions of the photoresist material into the photoresist mask (or to cause the photoresist material to undergo a photochemical reaction), and then remove portions of the undeveloped photoresist material to retain the patterned photoresist mask. Examples of photoresist materials include, but are not limited to, photosensitive polymers or combinations of components that undergo a photochemical reaction when exposed to UV light through a photomask, such as polymethyl methacrylate (PMMA), combinations of phenolic resin matrices and sensitizers, and the like.

[0085] The patterned photoresist mask 114 includes a plurality of portions that each define an area 116 of the underlying base dielectric layer 106 where a dielectric bump is to be formed. The location of each portion of the photoresist mask 114 defines the location of a corresponding dielectric bump, and the perimeter shape of each portion of the photoresist mask 114 corresponds to the perimeter shape of the corresponding dielectric bump. Each dielectric bump may have one of a plurality of shapes such as a square shape, a rectangular shape, a curved shape (such as a circular shape or an elliptical shape), a polygonal or multi-pointed shape (such as an L-shape or an H-shape), and the like, as viewed from a top-down perspective. In some embodiments, the location of each area 116 of the base dielectric layer 106 corresponds to a target location of a bondable surface or bonding pad to be formed above the resulting dielectric bump, as discussed further below.

[0086] Figure 1D An etching step 118 is shown applied to the substrate 100, which removes exposed portions of the base dielectric layer 106 not covered by the photoresist mask 114 without substantially removing the underlying dielectric material at the major surface 110 of the substrate 100. The etching step 118 may be performed using an etchant that selectively etches the dielectric material of the base dielectric layer 106, which may be a different dielectric material than the dielectric material at the major surface 110 of the substrate 100, or the etching step 118 may be limited to a predetermined amount of time to prevent substantial removal of the underlying dielectric material at the major surface 110. Examples of etching steps such as etching step 118 may include, but are not limited to, using wet or dry etchant techniques.

[0087] Figure 1E The resulting dielectric bumps 120 are shown formed after the etching step 118 has removed the exposed portions of the base dielectric layer 106 and after removing the remaining portions of the photoresist mask 114. Each dielectric bump 120 has a height 126 as measured from the major surface 110 that substantially corresponds to the height of the base dielectric layer 106. Each dielectric bump 120 also has a plurality of sidewalls 124 (e.g., four sidewalls if the perimeter of the bump 120 is square or rectangular) and a top (planar) surface 122.

[0088] Figure 1F A seed layer 130 is shown, which is deposited over the sides of the substrate 100, including being deposited over the major surface 110 and over each dielectric bump 120. The seed layer 130 is in direct contact with the major surface 110, the sidewalls 124 of the dielectric bump 120, and the top surface 122 of the dielectric bump 120. The seed layer 130 is a conductive material, examples of which include, but are not limited to, copper, gold, aluminum, and the like. Examples of depositing a seed layer such as the seed layer 130 may include, but are not limited to, sputtering, conformal deposition, and similar methods.

[0089] Figure 1G A layer of photoresist material is shown deposited over the side of substrate 100 and patterned into a photoresist mask 132 that directly contacts seed layer 130. Patterned photoresist mask 132 includes a plurality of openings 129 that each define an area 131 where traces are to be formed, wherein area 131 includes dielectric bumps. The location of each opening 129 defines the location of a corresponding trace, and the perimeter shape of each opening 129 corresponds to the perimeter of the corresponding trace.

[0090] Figure 1H A plating step 134 is shown applied to the substrate 100 to plate the exposed portions of the seed layer 130 within each opening 129. Portions of the seed layer 130 that remain under the photoresist mask 132 are not plated. Examples of plating steps such as plating step 134 may include, but are not limited to, using electroplating or electroless plating techniques, which may be performed for a predetermined amount of time to achieve a target thickness of the resulting plated conductive material.

[0091] Fig. 1I The resulting traces 136 are shown after removing portions of the photoresist mask 132 and the underlying remaining portions of the seed layer 130, such as by using one or more additional etching steps. Each trace 136 includes a lower trace portion 133 in direct contact with the major surface 110, a sidewall trace portion 135 in direct contact with at least one sidewall of the dielectric bump 120, and an upper trace portion 137 in direct contact with the top surface 122 of the dielectric bump 120. In some embodiments, traces 136 may include sidewall trace portions 135 in direct contact with up to and including the sidewalls of all of the dielectric bumps 120. Figure 1K 1 , each trace 136 generally has a uniform thickness, shown as height 143, corresponding to the combined thickness or height of the seed layer 130 and the conductive material plated onto the seed layer 130. In some embodiments, the height 126 of the dielectric bump 120 is greater than the height 143 of the trace 136. In this manner, the trace 136 can extend in three dimensions, including in an xy plane parallel to the major surface 110 and in a z direction orthogonal to the major surface 110.

[0092] Figure 1J A dielectric material is shown deposited over the sides of substrate 100 to form layer 138, including over trace 136 and its underlying bump 120. Layer 138 directly contacts trace 136 and exposed portions of major surface 110 to embed trace 136 in the dielectric material. In the illustrated embodiment, dielectric material layer 138 has an outer surface 140 that covers the entire trace 136, including over upper trace portion 137 of trace 136.

[0093] Figure 1K The resulting embedded traces 136 are shown after performing an etching step 142 that removes the outermost portion of the dielectric material layer 138 to form a new outer surface 146. The upper trace portion 137 of each trace 136 has a top surface 144 exposed by the dielectric material layer 138 as a result of the etching step 142. In some embodiments, the top surface 144 acts as a bondable surface or bonding pad to which an electronic component or external conductive structure can be attached. For example, a wire can be bonded to or a solder ball can be bonded to a bondable surface such as the top surface 144 to form an external conductive structure. The combination of the dielectric bump 120 and the plated trace 136 having the exposed surface 144 may also be referred to as a capture pad 144. The underlying dielectric bump 120 provides mechanical support for such bonded wires or solder balls and is sufficient to withstand thermal ultrasonic stresses or mechanical stresses during attachment of the wires or solder balls. In some embodiments, Figure 1K The resulting substrate 100 shown in can be a finished substrate to which one or more electronic components can be attached. Traces, such as traces 136, are exemplary conductive structures that provide electrical connections, such as between a die or other electronic component attached to one set of bondable surfaces and an external conductive structure attached to another set of bondable surfaces. In addition, bondable surfaces, such as top surface 144, can be located on both sides of the substrate, wherein the electrical connections formed by the conductive structures, including the traces, can pass through the substrate using one or more perforations that can electrically connect electronic components and external conductive structures located on one or both sides of the substrate.

[0094] exist Figure 1K , top surface 144 is coplanar with exterior surface 146 of the remainder of dielectric material layer 138. The remainder of dielectric layer 138 has a height 147 measured from major surface 110 to exterior surface 146. Height 145 is measured from major surface 110 to top surface 144. In the illustrated embodiment, height 147 is equal to height 145, where top surface 144 is coplanar with exterior surface 146. In other embodiments (such as Figure 3J ), top surface 144 extends beyond outer surface 146, wherein height 147 of layer 138 is shorter than height 145 to top surface 144 (in Figure 3J144). In such embodiments, lateral edges (e.g., outer inflection points and edges) of upper trace portion 137 are also exposed by layer 138. In some embodiments, top portions of sidewall trace portions 135 may additionally be exposed by layer 138, which may provide improved wetting for solder ball applications under sidewall trace portions 135. As described above, lower trace portions 133 each have a height 143 that corresponds to the thickness of the resulting conductive material forming trace 136, where height 143 is measured from major surface 110 to top surface 141 of lower trace portion 133. Additional plating or deposition steps may also be performed to coat bondable surfaces (e.g., top surface 144) with a conductive material that improves wettability and adhesion of external conductive structures, such as one or more conductive metals, examples of which include, but are not limited to, nickel, gold, copper, aluminum, titanium, tungsten, chromium, palladium, or other suitable conductive metals or alloys composed of one or more suitable conductive metals.

[0095] Figures 2A to 2D Cross-sectional views showing some exemplary alternative process steps in an exemplary embedded trace fabrication process flow including forming dielectric bumps. Figure 2A A photoimageable dielectric material is shown deposited over major surface 110 to form a layer 206 having an exterior surface 108 in direct contact with major surface 110. Layer 206 serves as a base dielectric layer from which one or more dielectric bumps are formed, as discussed below. Examples of photoimageable dielectric materials include, but are not limited to, photoimageable polyimides, photoimageable epoxy-based polymers, and the like.

[0096] Figure 2B A photolithography step 214 is shown where UV light is applied to substrate 100 through a photomask. The photomask defines a plurality of regions 216 (shown in dashed outline), where each region 216 defines a location where a dielectric bump will be formed. UV light is applied to regions 216 through the photomask, which develops regions 216 within photoimageable layer 206 into hardened dielectric material (or causes the photoresist material to undergo a photochemical reaction). The perimeter shape of regions 216 in the photomask corresponds to the perimeter shape of a corresponding dielectric bump.

[0097] Figure 2C An etching step 218 is shown applied to substrate 100 to remove undeveloped portions of layer 206 outside of region 216 without substantially removing the underlying dielectric material at major surface 110 of substrate 100. Etching 218 may be performed using an etchant that selectively etches the undeveloped photoimageable dielectric material of layer 206, which may be distinct from the dielectric material at major surface 110, or etching step 218 may be limited to a predetermined amount of time to prevent substantial removal of the underlying dielectric material at major surface 110.

[0098] Figure 2D The resulting dielectric bumps 120 are shown after the etching step 218 has removed the undeveloped portions of the layer 206. Each dielectric bump 120 has the above Figure 1E In some embodiments, the manufacturing process can be performed from Figure 2D Continue until Figure 1F , as discussed above.

[0099] Figures 3A to 3J Cross-sectional views showing various process steps in an exemplary embedded trace fabrication process flow including forming metal bumps. Figure 3A A dielectric material is shown deposited over the sides of substrate 100 to form a layer 106 that is in direct contact with a surface of substrate 100, such as top surface 102. In the illustrated embodiment, layer 106 may be one of a plurality of build-up layers formed on substrate 100 and forms a new outermost surface of substrate 100, also referred to as major surface 110 of substrate 100. Layer 106 may cover an underlying metal surface, such as an exposed portion of a metal surface of a metal clad core board. In some embodiments, layer 106 may provide an insulating layer of dielectric material that covers any conductive material exposed at underlying surface 102 (e.g., layer 106 may directly contact an exposed portion of an underlying conductive trace (not shown) formed during a previous step of a build-up process).

[0100] Figure 3B A seed layer 130 is shown deposited over the sides of the substrate 100 , including deposited over and directly on the major surface 110 . Figure 3C A layer of photoresist material of a photoresist mask 312 is shown deposited over the side of the substrate 100 and patterned to be in direct contact with the seed layer 130. The patterned photoresist mask 312 includes a plurality of openings 314 that each define an area 316 in which a metal bump will be formed. The location of each opening 314 defines the location of a corresponding metal bump, and the perimeter shape of each opening 314 corresponds to the perimeter of the corresponding metal bump.

[0101] Figure 3D A plating step 318 is shown applied to the substrate 100 to plate the exposed portions of the seed layer 130 within each opening 314 with a conductive material. The portions of the seed layer 130 that remain under the photoresist mask 312 are not plated. Figure 3EThe resulting metal bumps 320 are shown formed after removing the photoresist mask 312 and the underlying portions of the seed layer 130, such as by using one or more additional etching steps. Each metal bump 320 has a height 326 that substantially corresponds to the height of the plated conductive material measured from the underlying major surface 110, which is the combined thickness or height of the seed layer 130 and the conductive material plated onto the seed layer 130. Each metal bump 320 has a plurality of sidewalls 324 and a top (planar) surface 322.

[0102] Figure 3F Seed layer 330 is shown deposited over the sides of substrate 100, including over underlying major surface 110 and over each metal bump 320. Seed layer 330 is in direct contact with underlying major surface 110, sidewalls 324 of metal bumps 320, and top surfaces 322 of the metal bumps.

[0103] Figure 3G A layer of photoresist material of a photoresist mask 332 is shown deposited over the side of the substrate 100 and patterned to be in direct contact with the seed layer 130. The photoresist mask 332 includes a plurality of openings 329 that each define a region 331 where a trace is to be formed, wherein the region 331 includes the metal bump 320. The location and perimeter shape of each opening 329 defines the location and perimeter shape of a corresponding trace. Figure 3G Also shown is a plating step 334 applied to the substrate 100 that plates the exposed portions of the seed layer 130 within each opening 329. The portions of the seed layer 130 that remain under the photoresist mask 332 are not plated.

[0104] Figure 3H The resulting traces 336 are shown after removing portions of the photoresist mask 332 and the underlying remaining portions of the seed layer 130, such as by using one or more additional etching steps. Each trace 336 includes a lower trace portion 333 in direct contact with the major surface 110, a sidewall trace portion 335 in direct contact with at least one sidewall of the metal bump 320, and an upper trace portion 337 in direct contact with the top surface 322 of the metal bump 320.

[0105] Fig. 3I A dielectric material is shown deposited over the sides of substrate 100 to form layer 338, including over trace 336 and its underlying bump 320. Layer 338 directly contacts trace 336 and exposed portions of major surface 110 to embed trace 336 in the dielectric material. In the illustrated embodiment, layer 338 has an outer surface 340 that covers the entire trace 336, including over upper trace portion 337.

[0106] Figure 3JThe resulting embedded traces 336 are shown after performing an etching step 342 to remove the outermost portion of layer 338 to form a new outer surface 346. The upper trace portion 337 of each trace 336 has a top surface 344 exposed through layer 338 as a result of etching step 342. In some embodiments, top surface 344 acts as a bondable surface or bonding pad. The combination of metal bump 320 and plated trace 336 having exposed surface 344 may also be referred to as capture pad 344. In some embodiments, metal bump 320 may provide additional mechanical support to withstand the stress involved in bonding a wire to or attaching a solder ball to the top surface of the upper trace portion compared to dielectric bump 120. In the illustrated embodiment, top surface 344 is exposed through outer surface 346 and extends beyond outer surface 346, wherein the remainder of layer 338 has a height 347 measured from main surface 110 to outer surface 346. Height 347 is less than height 345 measured from major surface 110 to top surface 344 of upper trace portion 337. As also shown, lateral edges of upper trace portion 337 are exposed through layer 138. In some embodiments, top portions of sidewall trace portions 335 may additionally be exposed for improved wetting.

[0107] Each trace 336 generally has a uniform thickness shown as height 343, which corresponds to the combined thickness or height of seed layer 330 and the conductive material plated onto seed layer 130. Height 343 is measured from major surface 110 to top surface 341 of lower trace portion 333. In some embodiments, height 326 of metal bump 320 is greater than height 343 of trace 336. In this manner, trace 336 can extend in three dimensions, including in an xy plane parallel to major surface 110 and in a z direction orthogonal to major surface 110.

[0108] Figures 4A to 4E A cross-sectional view showing various process steps in an exemplary stacked via manufacturing process flow. In the illustrated embodiment, Figure 4A from Figure 3J In some embodiments, the underlying metal bump 320 may provide improved mechanical support to withstand the stresses involved in forming stacked vias over the metal bump 320 compared to the dielectric bump 120. Figure 4A An embedded trace having a top surface 344 is shown extending beyond an exterior surface 346 of layer 338 , but an embedded trace having a top surface 344 that is coplanar with exterior surface 346 of layer 338 may also be used.

[0109] Figure 4BA layer of photoresist material is shown deposited over the sides of substrate 100 and patterned into a photoresist mask 448 that includes a plurality of openings 450 aligned with upper trace portions 334. Top surface 344 is exposed within openings 450 of photoresist mask 448.

[0110] Figure 4C A plating step 452 applied to substrate 100 is shown plating the exposed top surface 344 within each opening 450 with a conductive material, which forms a metal-filled via 454 in direct contact with the top surface 344. Metal-filled vias 454 may also be referred to as being stacked on top of upper trace portion 337 and metal bump 320.

[0111] Figure 4D The resulting metal filled via 454 is shown after removal of the photoresist mask 448 . Figure 4E A dielectric material is shown deposited over the sides of substrate 100 to form layer 456, which is in direct contact with the outer surface 346 of the underlying dielectric layer 338 and the sidewalls of the metal-filled via 454. In some embodiments, layer 456 may cover a top surface 460 of metal-filled via 454. In such embodiments, an etching step may be applied to remove the outermost portion of layer 456 to form a new surface 462 and expose the top surface 460 of metal-filled via 454 through layer 456. In the illustrated embodiment, top surface 460 is coplanar with outer surface 462 of layer 456. In other embodiments, top surface 460 may be non-coplanar, such as extending beyond outer surface 462.

[0112] Figures 4A to 4E The steps shown in the figure can be repeated several times to form multiple metal-filled vias 454 stacked on top of each other. For example, the top surface 460 of the metal-filled via 454 acts as a contact with the Figure 4A A photoresist mask may then be formed on the top surface 344 of the substrate. Figure 4E 4. The substrate 100 shown in FIG. 4 is shown in FIG. 4, wherein the openings 450 are aligned with the top surface 460 to plate additional metal-filled vias within each opening 450. The photoresist mask may then be removed and another dielectric layer deposited to surround the additional metal-filled vias.

[0113] Since the openings in the photoresist mask are aligned to the outer perimeter of the underlying metal surface within an acceptable tolerance (e.g., + / - 12 microns), the alignment of each metal-filled via stacked on top of each other is also within an acceptable tolerance (e.g., + / - 10 microns). For example, each metal-filled via has a substantially similar lateral width (e.g., 80 microns), where the alignment tolerance allows the plurality of stacked metal-filled vias to have a smoother vertical profile similar to a column profile, which provides a more compact lateral footprint compared to stacks of known microvias. Known microvias have a "lip" extending away from the sidewalls of the microvia at the top portion of the microvia, where the sidewalls slope inward toward the bottom portion of the microvia due to the manner in which the microvia is manufactured. The tolerance of such laser-drilled stacked microvias is greater than the acceptable tolerance provided by the present disclosure (e.g., + / - 20 microns). The smoother column profile of the stacked metal-filled vias of the present disclosure can be further seen in the following discussion. Figures 5A to 5J It should also be noted that the metal bumps 320 may each have a substantially similar lateral width (e.g., 50 microns), and the plated traces 336 may each have a substantially similar consistent thickness (e.g., 15 microns) that adds a similar amount to the lateral width of the resulting capture liner 344 (e.g., 80 microns), which may be substantially similar to the lateral width of the metal-filled via.

[0114] Figures 5A to 5J Shown in Figures 4A to 4D 2 is a cross-sectional view of various process steps in another exemplary embedded trace manufacturing process flow performed after the stacked via manufacturing process flow shown in . Figure 5A A second metal-filled via 554 is shown stacked on top of metal-filled via 454, surrounded by a dielectric layer 556 having an exterior surface 562. Metal-filled vias 554 each have a top surface 560 exposed through layer 556. Surfaces 560 and 562 may or may not be coplanar for similar reasons discussed above.

[0115] Figure 5B A layer of photoresist material is shown deposited over the sides of substrate 100 and patterned into a photoresist mask 514 that includes a plurality of openings 516 aligned with the top surface 560 of the underlying metal-filled via 554. In the illustrated embodiment, at least a portion of the top surface 560 is exposed within the openings 516 of the photoresist mask 514. In some embodiments, the openings 516 may be large enough to form a suitably sized metal bump relative to a larger opening that may form a suitably sized metal-filled via. In some embodiments, the resulting metal bump may be smaller than the resulting metal-filled via because the metal bump will be plated over to form a trace.

[0116] Figure 5C A plating step 518 applied to substrate 100 is shown plating the exposed top surface 560 within each opening 516 with a conductive material, which forms a metal bump 520 in direct contact with top surface 344. Metal bump 520 may also be referred to as being stacked on top of underlying metal-filled via 554.

[0117] Figure 5D The resulting metal bumps 520 are shown after removal of the photoresist mask 514 , wherein each bump 520 has a height 526 measured from an underlying surface 560 , sidewalls 524 , and a top surface 522 . Figure 5E Seed layer 530 is shown deposited over the sides of substrate 100 , making direct contact with underlying dielectric surface 562 , sidewalls of metal bump 520 , and top surface 522 of metal bump 520 .

[0118] Fig. 5F A layer of photoresist material is shown deposited over the sides of substrate 100 and patterned into a photoresist mask 532 that includes a plurality of openings 529 that each define a region 531 where traces are to be formed, wherein region 531 includes metal bumps 520 . Figure 5G A plating step 534 is shown applied to the substrate 100 , which plates the exposed portions of the seed layer 530 within each opening 529 .

[0119] Figure 5H The resulting traces 536 are shown after removing portions of the photoresist mask 532 and the underlying remaining portions of the seed layer 530. Each trace 536 includes a lower trace portion 533, a sidewall trace portion 535 in direct contact with at least one sidewall of the metal bump 520, and an upper trace portion 537 in direct contact with the top surface 522 of the metal bump 520.

[0120] Fig.5I A dielectric material is shown deposited over the sides of substrate 100 to form layer 538, which buries trace 536. In the illustrated embodiment, layer 538 has an outer surface 540 that covers trace 136. Figure 5J The resulting embedded trace 536 is shown after performing an etching step 542 that removes the outermost portion of layer 538 to form a new exterior surface 546 and exposes a top surface 544 of upper trace portion 537 through layer 538. In the illustrated embodiment, top surface 544 is coplanar with exterior surface 546 of layer 538. In other embodiments, top surface 544 may be non-coplanar, such as extending beyond exterior surface 546.

[0121] Figure 6 A perspective view of embedded traces extending in a vertical direction on one side of a substrate is shown. Trace 602 extends in a first direction or x-direction, and trace 604 extends in a second direction or y-direction perpendicular to the first direction. A portion of trace 604 is formed above a dielectric bump 620 that raises trace 604 in a third orthogonal direction or z-direction. The raised portion of trace 604 is separated from trace 602 and crosses over trace 602 without contacting trace 602, wherein dielectric bump 620 acts as an insulator between traces 602 and 604. Trace 604 includes one or more lower trace portions 606 (shown extending outwardly on both sides of bump 620) in direct contact with the underlying dielectric surface, one or more sidewall trace portions 608 (shown on opposite sidewalls 624 of bump 620) in direct contact with the sidewalls of dielectric bump 620, and an upper trace portion 610 in direct contact with a top surface 622 of bump 620. Trace 602 (also referred to as a cross-direction trace) is shown extending through opposite sidewalls 628 of bump 620, which are perpendicular to sidewalls 624 with sidewall trace portions 608 of trace 604. Although not shown for simplicity, traces 602 and 604 are both covered by a dielectric material.

[0122] Figures 7A to 7D 8A to 8E show cross-sectional views of various process steps in an exemplary cross-direction embedded trace fabrication process flow, wherein Figures 7A to 7D Involving a planar trace (such as trace 602) under a dielectric bump and Figures 8A to 8E Elevated traces (such as trace 606) over dielectric bumps are involved.

[0123] Fig. 7A A seed layer 770 is shown deposited over the side of the substrate 100 , wherein the seed layer 770 is in direct contact with the major surface 110 of the dielectric layer 106 of the substrate 100 . Figure 7B A layer of photoresist material is shown deposited over the sides of substrate 100 and patterned into a photoresist mask 772 in direct contact with seed layer 770. Patterned photoresist mask 772 includes at least one opening 774 in which a planar trace is to be formed. Figure 7C A plating step 776 is shown that plates the exposed portions of the seed layer 770 within the opening 774 to form a planar trace, or a trace (or portion of a trace) that remains in direct contact with the underlying major surface 110 . Fig.7D The resulting trace 602 is shown after the photoresist mask 772 and underlying portions of the seed layer 770 have been removed. The trace 602 has a consistent thickness shown as height 143 measured from the major surface 110 to the top surface 141 of the trace.

[0124] Fig. 8A from Fig.7D Continuing, where a dielectric bump 620 is formed over a portion of the planar trace 602. The dielectric bump 620 may be formed using the various steps described above. The dielectric bump 620 extends a width 630 on both sides of the trace 602 to provide adequate insulation. Figure 8B Seed layer 790 is shown deposited over sides of substrate 100 , including over and directly on major surface 110 , sidewalls 624 of bumps 620 , and top surfaces 622 of bumps 620 . Figure 8C A layer of photoresist material is shown deposited over the sides of substrate 100 and patterned into a photoresist mask 792 that is in direct contact with seed layer 790. Patterned photoresist mask 792 includes at least one opening 794 where elevated traces are formed over bumps 620. Fig.8D A plating step 796 is shown that plates the exposed portion of the seed layer 790 to form an elevated trace, or a trace (or portion of a trace) that is in direct contact with at least one sidewall 624 and the top surface 622 of the bump 620 . Fig. 8E The resulting trace 604 is shown after the photoresist mask 792 and any underlying portions of the seed layer 790 have been removed. The trace 604 has one or more lower trace portions 606, one or more sidewall trace portions 608, and an upper trace portion 610. The trace 604 has a consistent thickness, shown as height 143 of the lower trace portion 606, which is measured from the major surface 110 to the top surface 141 and is substantially equal to the height 143 of the trace 602. In the illustrated embodiment, the height 626 of the dielectric bump 620 is greater than the height 143. Although not shown, a layer of dielectric material is subsequently deposited over the traces 602 and 604 such that the traces 602 and 604 are embedded in the dielectric material.

[0125] It should be noted that other variations of embodiments may exist. For example, in some embodiments, Figure 5J The substrate 100 shown in FIG. 1 may have a flat embedded trace (eg, Fig.7D In another example, the trace 602 shown in FIG. 5 is provided as a bondable surface for an external conductive structure, rather than the trace 536 shown. Figure 4E The top surface 460 of the metal filled via 454 shown in FIG. Figure 5A The top surface 560 of the topmost metal-filled via 554 shown in FIG. 5 may provide a bondable surface for external conductive structures, rather than forming another embedded trace or another metal-filled via on top.

[0126] The substrates described herein may be used to support semiconductor dies or integrated circuit dies, which may include any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon on insulator (SOI), silicon, single crystal silicon, the like, and combinations thereof.

[0127] It should now be appreciated that a method for manufacturing a substrate having one or more embedded traces has been provided, the one or more embedded traces comprising a trace formed over a dielectric bump or a metal bump formed on a major surface of the substrate. The trace extends along the major surface, along at least one sidewall of the bump, and along a top surface of the bump, wherein the top surface of the portion of the trace located on top of the bump is exposed by the dielectric material and provides a bondable surface.

[0128] In one embodiment of the present disclosure, a method for manufacturing one or more embedded traces is provided, the method comprising: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace, the trace comprising a lower trace portion in direct contact with the first major surface, a sidewall trace portion in direct contact with at least one sidewall of the bump, and an upper trace portion in direct contact with the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

[0129] One aspect of the above-described embodiment provides that a top surface of the upper trace portion is coplanar with a top surface of a remainder of the blanket dielectric layer.

[0130] Another aspect of the above embodiment provides that a top surface of the upper trace portion extends beyond a top surface of a remainder of the blanket dielectric layer.

[0131] Another aspect of the above embodiment provides that the first major surface of the substrate includes a dielectric material.

[0132] Another aspect of the above embodiment provides that the substrate includes a metal clad dielectric core board covered by a dielectric material.

[0133] Another aspect of the above embodiment provides that the bump includes a dielectric bump.

[0134] Another aspect of the above embodiment provides that the bump comprises a metal bump.

[0135] Another aspect of the above-mentioned embodiment provides that forming a bump includes: depositing a base dielectric layer, wherein the base dielectric layer is above the first major surface of the substrate and is in direct contact with the first major surface of the substrate; depositing a photoresist mask on the base dielectric layer and patterning the photoresist mask to define an area in which a dielectric bump will be formed; removing a portion of the base dielectric layer outside the photoresist mask to form a dielectric bump within the area; and removing the photoresist mask.

[0136] Another aspect of the above-mentioned embodiment provides that forming the bump includes: depositing a base dielectric layer, wherein the base dielectric layer is above the first major surface of the substrate and in direct contact with the first major surface of the substrate, wherein the base dielectric layer is photoimageable; photoimaging a portion of the base dielectric layer to define an area in which the dielectric bump will be formed; and removing a non-photoimaged portion of the base dielectric layer to form a dielectric bump in the area.

[0137] Another aspect of the above-mentioned embodiment provides that forming the bump includes: depositing a blanket seed layer, wherein the blanket seed layer is above the first major surface of the substrate and is in direct contact with the first major surface of the substrate; depositing a photoresist mask on the blanket seed layer and patterning the photoresist mask to define an area in which a metal bump will be formed; plating exposed portions of the blanket seed layer to form a metal bump within the area; and removing the photoresist mask and any portion of the blanket seed layer underlying the photoresist mask.

[0138] Another aspect of the above embodiment provides that forming the trace includes: depositing a blanket seed layer over the first major surface of the substrate, including over the bump, wherein the blanket seed layer directly contacts the first major surface, at least one sidewall of the bump, and the top surface of the bump; depositing a photoresist mask on the blanket seed layer and patterning the photoresist mask to define an area including the bump where the trace will be formed; plating exposed portions of the blanket seed layer to form the trace within the area; and removing the photoresist mask and any portion of the blanket seed layer underlying the photoresist mask.

[0139] Another aspect of the above embodiment further includes: forming one or more metal-filled via columns over the bumps, wherein the bumps include metal bumps.

[0140] Another aspect of the above-described embodiment provides that each of the one or more metal-filled vias is formed by: depositing a photoresist mask on a top surface of the substrate and patterning the photoresist mask, the photoresist mask having an opening aligned with an underlying metal surface; plating the underlying metal surface to form a metal-filled via within the opening; removing the photoresist mask; depositing a second blanket dielectric layer over the metal-filled via; and etching away a top portion of the second blanket dielectric layer to expose a top surface of the metal-filled via.

[0141] Yet another aspect of the above embodiment provides that the underlying metal surface is one of a group including a top surface of an upper trace portion and a top surface of an underlying metal-filled via.

[0142] Yet another aspect of the above embodiment additionally includes forming a second trace in contact with top surfaces of top metal-filled vias of the one or more via columns, the top surfaces being exposed in the top dielectric layer of the substrate.

[0143] Yet another aspect of the above embodiment further includes forming a second metal bump in contact with a top surface of the top metal-filled vias of the one or more via columns, the top surface being exposed in the top dielectric layer of the substrate.

[0144] Yet another aspect of the above embodiment further includes: forming a second trace, which is above the second metal bump and in contact with the second metal bump, wherein the second trace includes: a lower trace portion directly in contact with the top dielectric layer, a sidewall trace portion directly in contact with at least one sidewall of the second metal bump, and an upper trace portion directly in contact with the top surface of the second metal bump.

[0145] Yet another aspect of the above embodiment further includes: depositing a second blanket dielectric layer over the second trace; and etching away a top portion of the second blanket dielectric layer to expose a top surface of the upper trace portion to form a bondable surface.

[0146] Another aspect of the above embodiment further includes: before forming the bump, directly forming a cross-direction trace on the first major surface, wherein the cross-direction trace extends in a first direction, the trace including a lower trace portion, a sidewall trace portion and an upper trace portion extends in a second direction perpendicular to the first direction, and the bump includes a dielectric bump, which is formed above the top surface and sidewall of the cross-direction trace and directly contacts the top surface and sidewall of the cross-direction trace.

[0147] Another aspect of the above embodiment provides that the cross-direction trace has a first height measured from the first major surface to the top surface of the cross-direction trace, the dielectric bump has a second height measured from the first major surface to the top surface of the dielectric bump, the second height is greater than the first height, and the upper trace portion directly contacts the top surface of the dielectric bump and has a third height measured from the first major surface to the top surface of the upper trace portion, the third height is greater than the second height.

[0148] Since the apparatus implementing the present invention is largely composed of electronic components and circuits known to those skilled in the art, in order to understand and appreciate the basic concepts of the present invention and in order not to confuse or deviate from the teachings of the present invention, the circuit details will not be explained to any greater extent than is deemed necessary as shown above.

[0149] Furthermore, the terms "front," "back," "top," "bottom," "above," "below," and the like, if any, in the specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0150] As used herein, the terms "substantial" and "substantially" mean sufficient to achieve the stated purpose or value in a practicable manner, taking into account any minor imperfections or deviations (if any) caused by common and expected process anomalies that may occur during manufacturing process steps, which minor imperfections or deviations are not significant for the stated purpose or value.

[0151] Although the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Figure 1K Additional or fewer embedded traces may be implemented in the embodiment. Therefore, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any advantages, advantages, or solutions to problems described herein with respect to specific embodiments be construed as a critical, required, or essential feature or element of any or all the claims.

[0152] Furthermore, as used herein, the terms "a" and "an" are defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "an". The same applies to the use of definite articles.

[0153] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal priority or other priority of these elements.

Claims

1. A method for manufacturing one or more embedded traces, characterized in that The method comprises: forming a bump on the first major surface of the substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace, the trace comprising: a lower trace portion in direct contact with the first major surface, a sidewall trace portion in direct contact with at least one sidewall of the bump, and an upper trace portion in direct contact with the top surface of the bump; depositing a blanket dielectric layer over the traces; and A top portion of the blanket dielectric layer is etched away to expose a top surface of the upper trace portion.

2. The method according to claim 1, characterized in that: The top surface of the upper trace portion is coplanar with a top surface of a remainder of the blanket dielectric layer.

3. The method according to claim 1, characterized in that The top surface of the upper trace portion extends beyond a top surface of a remainder of the blanket dielectric layer.

4. The method according to claim 1, characterized in that: The first major surface of the substrate includes a dielectric material.

5. The method according to claim 1, characterized in that The substrate includes a metal-clad dielectric core board covered by a dielectric material.

6. The method according to claim 1, characterized in that The bumps include dielectric bumps.

7. The method according to claim 1, characterized in that The bumps include metal bumps.

8. The method according to claim 1, characterized in that The forming of the trace comprises: depositing a blanket seed layer over the first major surface of the substrate, including over the bump, wherein the blanket seed layer is in direct contact with the first major surface, at least one sidewall of the bump, and the top surface of the bump; depositing a photoresist mask on the blanket seed layer and patterning the photoresist mask to define areas including the bumps where the traces are to be formed; plating exposed portions of the blanket seed layer to form the traces in the regions; and The photoresist mask and any portion of the blanket seed layer underlying the photoresist mask are removed.

9. The method according to claim 1, characterized in that: Further including: One or more columns of metal-filled vias are formed over the bumps, wherein the bumps comprise metal bumps.

10. The method according to claim 1, characterized in that Further including: Before forming the bumps, cross-directional traces are formed directly on the first major surface, wherein The cross-directional traces extend in a first direction, The trace including the lower trace portion, the sidewall trace portion and the upper trace portion extends in a second direction perpendicular to the first direction, and The bumps include dielectric bumps formed over and in direct contact with top surfaces and sidewalls of the cross-directional traces.

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