Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a first set of at least one solder ball disposed on a side surface of the first semiconductor chip, an interposer disposed on the first semiconductor chip and the first substrate and in contact with the first set of at least one solder ball, and an adhesive layer disposed between the first semiconductor chip and the interposer and configured to expose at least a portion of an upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first set of at least one solder ball.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0090286, filed on August 2, 2018, and all benefits derived therefrom, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor packaging. Background Technology

[0004] With the development of the electronics industry, the demand for higher performance, faster operation, and / or miniaturization of electronic components is increasing. In response to this trend, methods for stacking and filling multiple semiconductor chips on a single package substrate or methods for stacking one package on another can be used. For example, package-in-package (PIP) or package-on-package (POP) type semiconductor packages can be used. Summary of the Invention

[0005] Some example embodiments provide a POP-type semiconductor package that may include an interposer for electrical connection between an upper package and a lower package. The interposer may facilitate the connection between the upper and lower packages and reduce or prevent warpage of the upper and lower packages.

[0006] Some example embodiments provide semiconductor packages with enhanced reliability by using the restoring force of an interposer to reduce or prevent deformation.

[0007] According to some example embodiments, a semiconductor package is provided, the semiconductor package including a first substrate, a first semiconductor chip on the first substrate, a first set of at least one solder ball on a side surface of the first semiconductor chip, an interposer layer on the first semiconductor chip and the first substrate and in contact with the first set of at least one solder ball, and an adhesive layer between the first semiconductor chip and the interposer layer and configured to expose at least a portion of the upper surface of the first semiconductor chip, wherein a first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first set of at least one solder ball.

[0008] According to some example embodiments, there is provided a semiconductor package including: a first package including a first substrate and a first semiconductor chip on the first substrate and protruding in a direction in which the first substrate is positioned; a second package on the first package and including a second substrate and a second semiconductor chip on the second substrate; an interposer between the first package and the second package; and a first set of at least one solder ball on a side surface of the first semiconductor chip and configured to electrically connect the first substrate and the interposer, wherein a first height from an upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height of the first set of at least one solder ball.

[0009] According to some example embodiments, there is provided a semiconductor package including: a first substrate protruding in a direction in which a lower surface of the first substrate is positioned; a first semiconductor chip on an upper surface of the first substrate and including an upper surface having a first width; an interposer on the upper surface of the first semiconductor chip, a height of the interposer from the upper surface of the first substrate becoming smaller as moving away from a center of the first substrate; an adhesive layer between the first semiconductor chip and the interposer and including a lower surface having a second width smaller than the first width of the upper surface of the first semiconductor chip; and a molding layer at least partially surrounding a side surface of the adhesive layer between the first substrate and the interposer and the first semiconductor chip.

[0010] The objectives addressed by the present disclosure are not limited to the above-mentioned objectives, and other objectives not mentioned above will become apparent to those skilled in the art from the following provided description. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other objects, features and advantages of the present disclosure will become more apparent to one of ordinary skill in the art by describing example embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 is a view provided to explain a semiconductor package according to some example embodiments;

[0013] Figures 2 to 6 is a view showing an intermediate stage of manufacturing, provided to explain a method of manufacturing a semiconductor package according to some example embodiments;

[0014] Figure 7 is a view provided to explain a semiconductor package according to some other example embodiments;

[0015] Figure 8 is a view provided to explain a semiconductor package according to some other example embodiments;

[0016] Figure 9 is provided to explain a view of a semiconductor package according to some other example embodiments;

[0017] Figure 10 is provided to explain a view of a semiconductor package according to some other example embodiments;

[0018] Figure 11 is provided to explain a view of a semiconductor package according to some other example embodiments. DETAILED DESCRIPTION

[0019] In the present specification, a semiconductor package of a POP type will be described hereinafter; however, the present disclosure is not limited thereto.

[0020] Hereinafter, a semiconductor package according to some example embodiments will be described with reference to Figure 1

[0021] Figure 1 is provided to explain a view of a semiconductor package according to some example embodiments.

[0022] With reference to Figure 1 , a semiconductor package according to some example embodiments includes a first package 10, an interposer 150, and / or a second package 20.

[0023] The first package 10 can include a first substrate 110, a first set of at least one solder ball 111, a second set of at least one solder ball 112, a third set of at least one solder ball 113, a first semiconductor chip 120, an adhesive layer 130, and / or a first molding layer 140.

[0024] The first substrate 110 can be, for example, a printed circuit board (PCB) or a ceramic substrate. However, the present disclosure is not limited thereto.

[0025] When the first substrate 110 is a PCB, the first substrate 110 can include at least one material selected from a phenol resin, an epoxy resin, and a polyimide. For example, the first substrate 110 can include at least one material selected from FR4, a tetrafunctional epoxy resin, a polyphenylene ether, an epoxy / polyphenylene ether, a bismaleimide triazine BT, a polyamide short fiber base material, a cyanate ester, a polyimide, and a liquid crystal polymer. A surface of the first substrate 110 can be covered by a solder resist, but the present disclosure is not limited thereto.

[0026] The first substrate 110 can include a lower surface 110a and an upper surface 110b opposite to each other. The first substrate 110 can be formed to be convex in a first direction DR1 in which the lower surface 110a of the first substrate 110 is positioned. The first substrate 110 can have a first thickness t1 in the first direction DR1.

[0027] ​At least one set of solder balls 111 may be located on the lower surface 110a of the first substrate 110. The first set of at least one set of solder balls 111 may contact a conductive socket disposed on the lower surface of the first substrate 110. The first set of at least one set of solder balls 111 may convexly protrude from the lower surface 110a of the first substrate 110 in a first direction DR1. The first set of at least one set of solder balls 111 may be a component for electrically connecting the first substrate 110 to another external component.

[0028] The first group of at least one solder ball 111 may include, for example, at least one of tin Sn, lead Pb, nickel Ni, gold Au, silver Ag, copper Cu, bismuth Bi, and combinations thereof, but this disclosure is not limited thereto.

[0029] The first semiconductor chip 120 can be disposed on the upper surface 110b of the first substrate 110. The first semiconductor chip 120 can be a logic semiconductor chip used as a microprocessor. The first semiconductor chip 120 can be, for example, a central processing unit (CPU), a controller, or an application-specific integrated circuit (ASIC).

[0030] The first semiconductor chip 120 may be formed to protrude in the first direction DR1. The first semiconductor chip 120 may be arranged parallel to the first substrate 110. However, this disclosure is not limited thereto. That is, according to some other example embodiments, the first semiconductor chip 120 may be arranged flat without bending.

[0031] Despite Figure 1 The illustration shows only one semiconductor chip formed on the first substrate 110, but this disclosure is not limited thereto. That is, according to some other example embodiments, multiple semiconductor chips can be stacked on the first substrate 110.

[0032] The second set of at least one solder ball 112 can be disposed on the upper surface 110b of the first substrate 110. For example, the second set of at least one solder ball 112 can be disposed between the upper surface 110b of the first substrate 110 and the first semiconductor chip 120.

[0033] The second set of at least one solder ball 112 can contact a conductive groove disposed on the upper surface 110b of the first substrate 110. Furthermore, the second set of at least one solder ball 112 can contact a conductive groove disposed on the lower surface of the first semiconductor chip 120. The second set of at least one solder ball 112 can electrically connect the first substrate 110 and the first semiconductor chip 120.

[0034] The second group of at least one solder ball 112 may include, for example, at least one of tin Sn, indium In, bismuth Bi, antimony Sb, copper Cu, silver Ag, zinc Zn, lead Pb, and combinations thereof, but this disclosure is not limited thereto.

[0035] The third group of at least one solder ball 113 can be disposed on the side surface of the first semiconductor chip 120. For example, the third group of at least one solder ball 113 can be disposed between the upper surface 110b of the first substrate 110 and the lower surface 150a of the interposer 150 so as to be displaced (e.g., displaced in the third direction DR3) with respect to the side surface of the first semiconductor chip 120.

[0036] The third group of at least one solder ball 113 can be in contact with the conductive trench disposed on the upper surface 110b of the first substrate 110. Also, the third group of at least one solder ball 113 can be in contact with the conductive trench disposed on the lower surface 150a of the interposer 150. The third group of at least one solder ball 113 can electrically connect the first substrate 110 and the interposer 150.

[0037] A first height h1 from the upper surface 110b of the first substrate 110 to the upper surface 120b of the first semiconductor chip 120 can be formed to be greater than a second height h2 of the third group of at least one solder ball 113.

[0038] The above relates to forming the interposer 150 in a convex shape in the second direction DR2 by applying pressure to the edge of the interposer 150 during a process of stacking the interposer 150 on the first package 10. This will be described in more detail below.

[0039] The third group of at least one solder ball 113 can include, for example, at least one of tin Sn, indium In, bismuth Bi, antimony Sb, copper Cu, silver Ag, zinc Zn, lead Pb, and combinations thereof, but the present disclosure is not limited thereto.

[0040] The adhesive layer 130 can be disposed between the upper surface 120b of the first semiconductor chip 120 and the lower surface 150a of the interposer 150.

[0041] The adhesive layer 130 can expose at least a portion of the upper surface 120b of the first semiconductor chip 120. For example, the adhesive layer 130 can be disposed on the upper surface 120b of the first semiconductor chip 120 such that the upper surface 120b of the first semiconductor chip 120 is exposed at an edge portion. A first width w1 of the upper surface 120b of the first semiconductor chip 120 can be formed to be greater than a second width w2 of the lower surface 130a of the adhesive layer 130.

[0042] The adhesive layer 130 can perform a function of bonding the interposer 150 on the first semiconductor chip 120. The adhesive layer 130 can include, for example, at least one organic resin of an epoxy resin, an acrylic resin, a polyester resin, and a polycarbonate, but the present disclosure is not limited thereto.

[0043] The first molding layer 140 can be disposed between the upper surface 110b of the first substrate 110 and the lower surface 150a of the interposer 150.

[0044] For example, the first molding layer 140 can be disposed to cover the upper surface 110b of the first substrate 110, side surfaces of the second group of at least one solder ball 112, side surfaces of the third group of at least one solder ball 113, the first semiconductor chip 120, side surfaces of the adhesive layer 130, and / or the lower surface 150a of the interposer 150 on the first substrate 110.

[0045] That is, the first molding layer 140 can be disposed on the upper surface 120b of the first semiconductor chip 120 exposed in the side surface of the adhesive layer 130.

[0046] The first molding layer 140 can be formed of, for example, a silicon-based material, a thermosetting material, a thermoplastic material, a UV processing material, or the like. Furthermore, the first molding layer 140 can be formed of a polymer such as resin (e.g., epoxy molding compound (EMC)).

[0047] The interposer 150 can be disposed on the first package 10. For example, the interposer 150 can be disposed on the first semiconductor chip 120 and the first substrate 110, and can be bonded on the first semiconductor chip 120 through the adhesive layer 130. The interposer 150 can be displaced and disposed with respect to the first semiconductor chip 120.

[0048] The lower surface 150a of the interposer 150 can be in contact with the third group of at least one solder ball 113. The interposer 150 can be electrically connected with the first substrate 110 through the third group of at least one solder ball 113.

[0049] The interposer 150 can be formed to be convex in a second direction DR2 in which the upper surface 150b of the interposer 150 is positioned. However, the disclosure is not limited thereto. That is, according to some other example embodiments, the interposer 150 can be formed to be convex in the first direction DR1 with an initial shape and a restoring force of the interposer 150 in a manufacturing process.

[0050] The interposer 150 can be formed such that a height from the upper surface 110b of the first substrate 110 to the lower surface 150a of the interposer 150 becomes smaller as it is farther away from the center of the first substrate 110.

[0051] The interposer 150 can have a second thickness t2 in the first direction DR1. The second thickness t2 of the interposer 150 can be formed to be greater than the first thickness t1 of the first substrate 110. When the second thickness t2 of the interposer 150 is formed to be greater than the first thickness t1 of the first substrate 110, a restoring force of the interposer 150 can be increased, and thus, deformation of the semiconductor package can be reduced or prevented.

[0052] The interposer 150 can include at least one of silicon, glass, ceramic, and plastic. However, the disclosure is not limited thereto.

[0053] The second package 20 can be disposed on the upper surface 150b of the interposer 150. The second package 20 can be formed to protrude in the second direction DR2. However, the disclosure is not limited thereto.

[0054] The second package 20 can include a second substrate 160, a fourth group of at least one solder ball 161, a fifth group of at least one solder ball 162, a second semiconductor chip 170, and / or a second molding layer 180.

[0055] The second substrate 160 can be disposed to be parallel to the interposer 150 on the upper surface 150b of the interposer 150. The second substrate 160 can be, for example, a printed circuit board (PCB) or a ceramic substrate. However, the disclosure is not limited thereto.

[0056] A surface of the second substrate 160 can be covered by a solder resist, but the disclosure is not limited thereto.

[0057] The second substrate 160 can include a lower surface 160a facing the upper surface 150b of the interposer 150 and an upper surface 160b opposite the lower surface 160a. The second substrate 160 can be formed to protrude in the second direction DR2.

[0058] The fourth group of at least one solder ball 161 can be disposed on the lower surface 160a of the second substrate 160. For example, the fourth group of at least one solder ball 161 can be disposed between the lower surface 160a of the second substrate 160 and the upper surface 150b of the interposer 150.

[0059] The fourth group of at least one solder ball 161 can be in contact with a conductive slot disposed on the lower surface 160a of the second substrate 160. In addition, the fourth group of at least one solder ball 161 can be in contact with a conductive slot disposed on the upper surface 150b of the interposer 150. The fourth group of at least one solder ball 161 can electrically connect the second substrate 160 and the interposer 150.

[0060] The fourth group of at least one solder ball 161 can include, for example, at least one of tin Sn, lead Pb, nickel Ni, gold Au, silver Ag, copper Cu, bismuth Bi, and a combination thereof, but the disclosure is not limited thereto.

[0061] The second semiconductor chip 170 can be disposed on the upper surface 160b of the second substrate 160. The second semiconductor chip 170 can be, for example, a semiconductor memory chip. The second semiconductor chip 170 can be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). However, the present disclosure is not limited thereto.

[0062] The second semiconductor chip 170 can be formed to protrude in the second direction DR2. The second semiconductor chip 170 can be disposed to be parallel to the second substrate 160. However, the present disclosure is not limited thereto. That is, according to some other example embodiments, the second semiconductor chip 170 can be disposed to be flat without being bent.

[0063] Although it is shown in Figure 1 that only one semiconductor chip is formed on the second substrate 160, the present disclosure is not limited thereto. That is, according to some other example embodiments, a plurality of semiconductor chips can be stacked on the second substrate 160.

[0064] The fifth group of at least one solder ball 162 can be disposed on the upper surface 160b of the second substrate 160. For example, the fifth group of at least one solder ball 162 can be disposed between the upper surface 160b of the second substrate 160 and the second semiconductor chip 170.

[0065] The fifth group of at least one solder ball 162 can be in contact with a conductive groove disposed on the upper surface 160b of the second substrate 160. In addition, the fifth group of at least one solder ball 162 can be in contact with a conductive groove disposed on the lower surface of the second semiconductor chip 170. The fifth group of at least one solder ball 162 can electrically connect the second substrate 160 and the second semiconductor chip 170.

[0066] The fifth group of at least one solder ball 162 can include, for example, at least one of tin Sn, indium In, bismuth Bi, antimony Sb, copper Cu, silver Ag, zinc Zn, lead Pb, and combinations thereof, but the present disclosure is not limited thereto.

[0067] Although it is shown in Figure 1 that the second semiconductor chip 170 is electrically connected to the second substrate 160 through the fifth group of at least one solder ball 162, the present disclosure is not limited thereto. That is, according to some other example embodiments, the second semiconductor chip 170 can be electrically connected to the second substrate 160 through a wire bond.

[0068] The second molding layer 180 can be disposed on the upper surface 160b of the second substrate 160. For example, the second molding layer 180 can be disposed to cover the upper surface 160b of the second substrate 160, the side surface of the fifth group of at least one solder ball 162, and the second semiconductor chip 170 on the second substrate 160.

[0069] The second molding layer 180 can be formed of, for example, a silicon-based material, a thermosetting material, a thermoplastic material, a UV processing material, or the like. Also, the second molding layer 180 can be formed of a polymer such as resin (e.g., epoxy molding compound (EMC)).

[0070] The semiconductor package according to some example embodiments can enhance the reliability of the semiconductor package by reducing or preventing deformation of the semiconductor package using the restoring force of the interposer 150.

[0071] For example, the semiconductor package according to some example embodiments can fix the interposer 150 with the first semiconductor chip 120 using the adhesive layer 130 and modify the first package 10 disposed on the lower portion of the interposer 150 into a smile shape (a shape protruding downward) by the restoring force, which results in reducing or preventing deformation in the semiconductor package.

[0072] For the above effect, the second width w2 of the adhesive layer 130 can be formed to be smaller than the first width w1 of the first semiconductor chip 120. Also, the height between the first substrate 110 and the interposer 150 can be formed to be smaller as it is farther from the center of the first substrate 110. That is, the first height h1 from the upper surface 110b of the first substrate 110 to the upper surface 120b of the first semiconductor chip 120 can be formed to be greater than the second height h2 of the third group of at least one solder ball 113.

[0073] Hereinafter, a method of manufacturing a semiconductor package according to some example embodiments will be described with reference to the accompanying drawings. Figures 1 to 6 A method of manufacturing a semiconductor package according to some example embodiments will be described.

[0074] Figures 2 to 6 are views showing intermediate stages of manufacturing, provided to explain a method of manufacturing a semiconductor package according to some example embodiments.

[0075] Referring to Figure 2 The first semiconductor chip 120 formed with the second group of at least one solder ball 112 can be formed on the upper surface 110b of the first substrate 110.

[0076] Referring to Figure 3 The adhesive layer 130 can be formed on the upper surface 120b of the first semiconductor chip 120. The adhesive layer 130 can be formed to expose the edges of the upper surface 120b of the first semiconductor chip 120.

[0077] Next, the interposer 150 can be bonded to the adhesive layer 130.

[0078] In some example embodiments, the third set of at least one solder ball 113 can be formed on the lower surface 150a of the interposer 150. For example, the third set of at least one solder ball 113 can be formed to protrude in the first direction DR1 on an edge of the lower surface 150a of the interposer 150 that does not overlap the first semiconductor chip 120.

[0079] However, the present disclosure is not limited thereto. That is, according to some other example embodiments, the third set of at least one solder ball 113 can be formed to protrude in the second direction DR2 on an edge of the upper surface 110b of the first substrate 110 that does not overlap the first semiconductor chip 120.

[0080] Referring to Figure 4 The third set of at least one solder ball 113 can be connected with the first substrate 110 by performing a compression process P1 in the first direction DR1 on an edge of the lower surface 150a of the interposer 150 that does not overlap the first semiconductor chip 120.

[0081] Through the compression process P1, the interposer 150 can be formed to protrude in the second direction DR2.

[0082] Referring to Figure 5 The first molding layer 140 can be formed between the upper surface 110b of the first substrate 110 and the lower surface 150a of the interposer 150.

[0083] For example, the first molding layer 140 can be formed to cover the upper surface 110b of the first substrate 110, side surfaces of the second set of at least one solder ball 112, side surfaces of the third set of at least one solder ball 113, the first semiconductor chip 120, side surfaces of the adhesive layer 130, and the lower surface 150a of the interposer 150.

[0084] Next, the first set of at least one solder ball 111 can be formed on the lower surface 110a of the first substrate 110. The first set of at least one solder ball 111 can be formed to protrude convexly from the lower surface 110a of the first substrate 110 in the first direction DR1.

[0085] Referring to Figure 6 Due to the strength of the interposer 150, the edge of the interposer 150 and the edge of the first substrate 110 can move in the second direction DR2 with a restoring force P2. In some example embodiments, the adhesive layer 130 formed on the first semiconductor chip 120 can support the center of the interposer 150.

[0086] The first substrate 110 can have a convex shape in the first direction DR1 using the restoring force P2 of the interposer 150. The interposer 150 can have a convex shape in the second direction DR2.

[0087] In some example embodiments, the first semiconductor chip 120 can be formed to be convex in the first direction DR1. However, the present disclosure is not limited thereto. That is, according to some other example embodiments, the first semiconductor chip 120 can be formed to be flat without being curved.

[0088] Although it is shown in Figure 6 that the convexity of the first substrate 110 is greater than that of the interposer 150, the present disclosure is not limited thereto. That is, according to some other example embodiments, the convexity of the interposer 150 can be formed to be greater than that of the first substrate 110 as the strength of the restoring force P2 of the interposer 150.

[0089] Referring to Figure 1 , the second package 20 can be formed on the upper surface 150b of the interposer 150.

[0090] For example, the second package 20 including the second substrate 160, the second semiconductor chip 170 formed on the second substrate 160, and the second molding layer 180 formed to cover the second substrate 160 and the second semiconductor chip 170 can be formed on the upper surface 150b of the interposer 150.

[0091] In some example embodiments, the lower surface 160a of the second substrate 160 can be connected with the upper surface 150b of the interposer 150 by the fourth set of at least one solder ball 161.

[0092] Although it is shown in Figure 1 that the second semiconductor chip 170 is electrically connected with the second substrate 160 by the fifth set of at least one solder ball 162, the present disclosure is not limited thereto. That is, according to some other example embodiments, the second semiconductor chip 170 can be electrically connected with the second substrate 160 by a wire bond.

[0093] Although not shown in Figure 1 , a molding layer or an insulating layer can be additionally formed so as to at least partially surround the side surface of the fourth set of at least one solder ball 161 between the lower surface 160a of the second substrate 160 and the upper surface 150b of the interposer 150.

[0094] The semiconductor package according to some example embodiments can be manufactured by the manufacturing method described above.

[0095] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 7 . Attention will be mainly paid to differences from Figure 1The differences from the semiconductor package shown in FIG. 1 will be described.

[0096] Figure 7 are provided to explain a semiconductor package according to some other example embodiments.

[0097] Referring to Figure 7 , the underfill material 290 can be formed to at least partially surround side surfaces of the second set of at least one solder ball 112 between the first substrate 110 and the first semiconductor chip 120. The first molding layer 140 can be formed to at least partially surround side surfaces of the underfill material 290 without being in direct contact with the second set of at least one solder ball 112.

[0098] The underfill material 290 can be formed to further protrude laterally from the side surfaces of the first semiconductor chip 120, but the present disclosure is not limited thereto.

[0099] Although not shown in Figure 7 , according to some other example embodiments, the underfill material can be formed to at least partially surround side surfaces of a fifth set of at least one solder ball 162 between the second substrate 160 and the second semiconductor chip 170.

[0100] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 8 . The differences from the semiconductor package shown in FIG. 1 will be mainly described. Figure 1

[0101] Figure 8 are provided to explain a semiconductor package according to some other example embodiments.

[0102] Referring to Figure 8 , the insulating layer 330 can be disposed between the upper surface 120b of the first semiconductor chip 120 and the lower surface 150a of the interposer 150.

[0103] Like the adhesive layer 130 shown in Figure 1 , the insulating layer 330 can be disposed on the upper surface 120b of the first semiconductor chip 120 so as to expose edges of the upper surface 120b of the first semiconductor chip 120. The first molding layer 140 can at least partially surround side surfaces of the insulating layer 330.

[0104] The insulating layer 330 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0105] ​For example, the low-k dielectric material can include a flowable oxide (FOX), a tonen silazane (TOSZ), an undoped silicon glass (USG), a boron silicon glass (BSG), a phosphor silicon glass (PSG), a boron phosphor silicon glass (BPSG), a plasma enhanced tetraethyl orthosilicate (PETEOS), a fluorosilicate glass (FSG), a carbon doped silicon oxide (CDO), a xerogel, an aerogel, amorphous carbon fluoride, an organosilicate glass (OSG), a poly(p-xylylene), a bisbenzocyclobutene (BCB), SiLK, a polyimide, a porous polymer material, or a combination thereof, but is not limited thereto.

[0106] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 9 A semiconductor package according to some other example embodiments will be described with reference to Figure 1 described with reference to the semiconductor package shown in FIG. 1.

[0107] Figure 9 is provided to explain a view of a semiconductor package according to some other example embodiments.

[0108] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 9 The insulating layer 430 can be disposed between the upper surface 120b of the first semiconductor chip 120 and the lower surface 150a of the interposer 150. The insulating layer 430 can expose at least a portion of the upper surface 120b of the first semiconductor chip 120.

[0109] The insulating layer 430 can include a first sub-insulating layer 431, a second sub-insulating layer 432, and / or a third sub-insulating layer 433 which are displaced from each other in the third direction DR3. However, the present disclosure is not limited thereto. That is, according to some other example embodiments, the insulating layer 430 can include two sub-insulating layers which are displaced from each other in the third direction DR3 or four or more sub-insulating layers which are displaced from each other in the third direction DR3.

[0110] The first molding layer 140 can at least partially surround the side surface of the first sub-insulating layer 431, the side surface of the second sub-insulating layer 432, and the side surface of the third sub-insulating layer 433, respectively. That is, the first molding layer 140 can be disposed between the first sub-insulating layer 431 and the second sub-insulating layer 432 and between the second sub-insulating layer 432 and the third sub-insulating layer 433.

[0111] The insulating layer 430 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0112] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 10 A semiconductor package according to some other example embodiments will be described with reference to Figure 1The differences from the illustrated semiconductor package are described.

[0113] Figure 10 are provided to explain views of a semiconductor package according to some other example embodiments.

[0114] Referring to Figure 10 , the interposer 550 and the second package 20 can be sequentially stacked to be flat without a curvature on the first package 10.

[0115] For example, the interposer 550 can be arranged to extend without a curvature on the first package 10 in the third direction DR3. That is, the lower surface 550a and the upper surface 550b of the interposer 550 can be formed to extend in the third direction DR3.

[0116] The second substrate 560 can be formed such that the lower surface 560a and the upper surface 560b of the second substrate 560 extend in the third direction DR3 to be parallel with the interposer 550. The second semiconductor chip 570 and the second molding layer 580 covering the second semiconductor chip 570 can be formed on the second substrate 560.

[0117] Hereinafter, a semiconductor package according to some other example embodiments will be described with reference to Figure 11 The differences from the illustrated semiconductor package are described. Figure 1

[0118] Figure 11 are provided to explain views of a semiconductor package according to some other example embodiments.

[0119] Referring to Figure 11 , the interposer 650 and the second package 20 can be sequentially stacked to be convex in the first direction DR1 on the first package 10.

[0120] For example, the interposer 650 and the second substrate 660 can be sequentially stacked to be convex in the first direction DR1, and the second semiconductor chip 670 and the second molding layer 680 covering the second semiconductor chip 670 can be formed on the second substrate 660.

[0121] The convexity of the interposer 650 can be less than the convexity of the first substrate 110. Also, the convexity of the second package 20 can be less than the convexity of the first substrate 110.

[0122] In some example embodiments, the convexity of the interposer 650 can be the same as the convexity of the second package 20. That is, each of the lower surface 650a of the interposer 650, the upper surface 650b of the interposer 650, the lower surface 660a of the second substrate 660, and the upper surface 660b of the second substrate 660 can be formed to be parallel.​

[0123] The example embodiments according to the present disclosure are explained above with reference to the accompanying drawings, but it is understood that the present disclosure is not limited to the foregoing example embodiments, but can have various different forms, and can be implemented in other specific forms by those skilled in the art without changing the technical idea or essential characteristics of the present disclosure. Therefore, it will be understood that the above-described example embodiments are merely illustrative, and should not be construed as limiting.

Claims

1. A semiconductor package comprising: a first substrate; a first semiconductor chip on the first substrate; a first set of at least one solder ball; an interposer on the first semiconductor chip and the first substrate and in contact with the first set of at least one solder ball; and an adhesive layer between the first semiconductor chip and the interposer and configured to expose at least a portion of an upper surface of the first semiconductor chip, the adhesive layer in contact with each of an upper surface of the first semiconductor chip and a lower surface of the interposer, wherein a first height from an upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height of the first set of at least one solder ball, wherein a thickness of the adhesive layer decreases as a distance from a center of the first semiconductor chip increases, and wherein the first set of at least one solder ball is disposed between the upper surface of the first substrate and the lower surface of the interposer so as to be displaced relative to a side surface of the first semiconductor chip.

2. The semiconductor package of claim 1, wherein the first substrate is convex in a direction in which a lower surface of the first substrate is located, and the interposer is convex in a direction in which an upper surface of the interposer is located.

3. The semiconductor package of claim 1, wherein a first width of the upper surface of the first semiconductor chip is greater than a second width of a lower surface of the adhesive layer.

4. The semiconductor package of claim 1, wherein a height of the interposer from the upper surface of the first substrate decreases as a distance from a center of the first substrate increases.

5. The semiconductor package of claim 1, further comprising: a second substrate on an upper surface of the interposer; and a second semiconductor chip on an upper surface of the second substrate.

6. The semiconductor package of claim 1, further comprising a molding layer at least partially surrounding a side surface of the adhesive layer and the first semiconductor chip between the first substrate and the interposer.

7. The semiconductor package of claim 1, further comprising a second set of at least one solder ball between the first substrate and the first semiconductor chip and configured to electrically connect the first substrate and the first semiconductor chip.

8. The semiconductor package of claim 7, further comprising: an underfill material at least partially surrounding a side surface of the second set of at least one solder ball between the first substrate and the first semiconductor chip; and a molding layer at least partially surrounding a side surface of the adhesive layer, a side surface of the underfill material, and the first semiconductor chip between the first substrate and the interposer.

9. A semiconductor package comprising: a first package including a first substrate and a first semiconductor chip on the first substrate and convex in a direction in which the first substrate is located; a second package on the first package and including a second substrate and a second semiconductor chip on the second substrate; an interposer between the first package and the second package. ​ ​ ​ a first set of at least one solder ball disposed between the upper surface of the first substrate and the lower surface of the interposer so as to be displaced with respect to the side surface of the first semiconductor chip and configured to electrically connect the first substrate and the interposer, and an adhesive layer between the first semiconductor chip and the interposer and configured to expose at least a portion of the upper surface of the first semiconductor chip, the adhesive layer being in contact with each of the upper surface of the first semiconductor chip and the lower surface of the interposer, wherein a first height from the upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first set of at least one solder ball, and wherein a thickness of the adhesive layer decreases as it moves away from a center of the first semiconductor chip.

10. The semiconductor package of claim 9, wherein a second width of a lower surface of the adhesive layer is less than a first width of the upper surface of the first semiconductor chip, and the adhesive layer is configured to join the first semiconductor chip and the interposer.

11. The semiconductor package of claim 9, further comprising a molding layer at least partially surrounding a side surface of the adhesive layer and the first semiconductor chip between the first substrate and the interposer.

12. The semiconductor package of claim 9, wherein the interposer is convex in a direction of the second package positioning.

13. A semiconductor package, comprising: a first substrate convex in a direction of a lower surface of the first substrate being positioned; a first semiconductor chip on an upper surface of the first substrate and including an upper surface having a first width; an interposer on the upper surface of the first semiconductor chip and decreasing in height from the upper surface of the first substrate as it moves away from a center of the first substrate; an adhesive layer between the first semiconductor chip and the interposer and including a lower surface having a second width that is less than the first width of the upper surface of the first semiconductor chip, the adhesive layer being in contact with each of an upper surface of the first semiconductor chip and a lower surface of the interposer; and a molding layer at least partially surrounding a side surface of the adhesive layer and the first semiconductor chip between the first substrate and the interposer, wherein a thickness of the adhesive layer decreases as it moves away from a center of the first semiconductor chip.

14. The semiconductor package of claim 13, wherein the interposer is convex in a direction of an upper surface of the interposer being positioned.

15. The semiconductor package of claim 14, further comprising: a second substrate parallel to the interposer on the upper surface of the interposer; and a second semiconductor chip on an upper surface of the second substrate.

16. The semiconductor package of claim 15, wherein the second substrate is convex in a direction of the upper surface of the second substrate being positioned. ​ 16. The semiconductor package of claim 13, further comprising a set of at least one solder ball disposed between an upper surface of the first substrate and a lower surface of the interposer so as to be displaced relative to a side surface of the first semiconductor die and configured to electrically connect the first substrate and the interposer, wherein a first height from the upper surface of the first substrate to the upper surface of the first semiconductor die is greater than a second height of the set of at least one solder ball.

17. The semiconductor package of claim 13, wherein a second thickness of the interposer is greater than a first thickness of the first substrate.

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