Semiconductor memory device

Abstract

A semiconductor device can include a stack structure including a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes vertically extending to penetrate the stack structure. Each of the plurality of layers can include a plurality of semiconductor patterns extending in parallel along a first direction, a bit line electrically connected to the semiconductor patterns and extending along a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0090647, filed on August 3, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device. For example, at least some exemplary embodiments relate to a three-dimensional semiconductor memory device with increased integration. Background Technology

[0004] Semiconductor devices have become highly integrated to meet customers' demands for high performance and low manufacturing costs. Since the integration level of semiconductor devices is a significant factor determining product price, the demand for highly integrated semiconductor devices is steadily increasing. The integration level of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a single memory cell, making it highly susceptible to the technological level required to form intricate patterns. However, the extremely expensive processing equipment required to increase pattern refinement can practically limit the increase in integration level of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide three-dimensional semiconductor memory devices with improved electrical characteristics.

[0006] According to some exemplary embodiments of the present invention, a semiconductor device may include a plurality of gate electrodes; and a stacked structure comprising a plurality of layers vertically stacked on a substrate. The plurality of gate electrodes extend vertically such that the plurality of gate electrodes penetrate the stacked structure. Each of the plurality of layers may include: a plurality of semiconductor patterns extending parallel to a first direction; a bit line electrically connected to the semiconductor patterns and extending in a second direction, the second direction intersecting the first direction; a first air gap between the bit lines of the first layer and the bit lines of the second layer; and a data storage element electrically connected to a corresponding one of the semiconductor patterns.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device may include: a stacked structure comprising a plurality of layers vertically stacked on a substrate, each of the plurality of layers including a plurality of semiconductor patterns extending parallel to a first direction, a bit line electrically connected to the semiconductor patterns and extending in a second direction (the first direction intersects the second direction), and a data storage element electrically connected to a corresponding one of the semiconductor patterns; a plurality of gate electrodes extending vertically to penetrate the stacked structure; and a structure located between a bit line of a first layer of the plurality of layers and a bit line of a second layer of the plurality of layers adjacent to the first layer, such that the structure reduces the coupling capacitance between adjacent bit lines, the structure including one of a first air gap and a first shielding line.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device may include: a stacked structure comprising a plurality of layers vertically stacked on a substrate, the plurality of layers including a first semiconductor pattern and a second semiconductor pattern extending parallel to a first direction, a bit line electrically connected to the first semiconductor pattern and the second semiconductor pattern (the bit line extending in a second direction intersecting the first direction), and a data storage element electrically connected to a corresponding one of the first semiconductor pattern and the second semiconductor pattern; a first gate electrode and a second gate electrode extending vertically in a hole penetrating the stacked structure, the first gate electrode and the second gate electrode being adjacent to the first semiconductor pattern and the second semiconductor pattern, respectively; and a structure located between the first gate electrode and the second gate electrode such that the structure reduces the coupling capacitance between the first gate electrode and the second gate electrode, the structure including one of a first air gap and a first shielding line. Attached Figure Description

[0009] Figure 1 A simplified circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown.

[0010] Figure 2 A perspective view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown.

[0011] Figure 3 A perspective view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown.

[0012] Figure 4 Examples are shown Figure 3 A plan view of a three-dimensional semiconductor memory device.

[0013] Figure 5A , Figure 5B and Figure 5C Examples are given along the respective Figure 4The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0014] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 A plan view illustrating a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown.

[0015] Figure 7 , Figure 9 , Figure 11A , Figure 13A , Figure 15A , Figure 17A , Figure 19A and Figure 21A Examples are given along the respective Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 A cross-sectional view taken from line A-A'.

[0016] Figure 11B , 13B , Figure 15B , Figure 17B , Figure 19B and Figure 21B Examples are given along the respective Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 The cross-sectional view taken by line B-B'.

[0017] Figure 15C , Figure 17C , Figure 19C and Figure 21C Examples are given along the respective Figure 14 , Figure 16 , Figure 18 and Figure 20 The cross-sectional view taken from line C-C'.

[0018] Figure 22 Examples of three-dimensional semiconductor memory devices illustrating some exemplary embodiments of the concept according to the present invention are shown. Figure 4 The cross-sectional view taken from line C-C'.

[0019] Figure 23Examples of three-dimensional semiconductor memory devices illustrating some exemplary embodiments of the concept according to the present invention are shown. Figure 4 The cross-sectional view taken from line C-C'.

[0020] Figure 24 A plan view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown.

[0021] Figure 25 Examples along Figure 24 A cross-sectional view taken from line A-A'. Detailed Implementation

[0022] Figure 1 A simplified circuit diagram illustrating a cell array of a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown.

[0023] Reference Figure 1 A three-dimensional semiconductor memory device according to some exemplary embodiments of the present invention may include a cell array consisting of a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along a second direction D2.

[0024] Each subcell array (SCA) may include multiple bit lines (BL), multiple word lines (WL), and multiple memory cell transistors (MCTs). A memory cell transistor (MCT) can be placed between a word line (WL) and a bit line (BL).

[0025] Bit lines BL can be conductive patterns (e.g., metal lines) spaced apart from and disposed on the substrate. Bit lines BL can extend in a first direction D1. Bit lines BL in a subcell array SCA can be spaced apart from each other in a vertical direction (e.g., a third direction D3).

[0026] Word lines WL can be conductive patterns (e.g., metal lines) extending in a direction perpendicular to the substrate (e.g., third direction D3). Word lines WL in a subcell array SCA can be spaced apart from each other in a first direction D1.

[0027] The gate of a memory cell transistor (MCT) can be connected to the word line WL, and the source of the MCT can be connected to the bit line BL. Each of the memory cell transistors (MCTs) may include a data storage element DS. For example, the data storage element DS may be a capacitor, and the drain of the memory cell transistor (MCT) may be connected to the capacitor.

[0028] Figure 2 A perspective view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown.

[0029] Reference Figure 1 and Figure 2 A reference may be provided on the substrate 100. Figure 1 One of the multiple sub-cell arrays (SCAs) discussed. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0030] For example, a stacked structure SS comprising a first layer L1, a second layer L2, and a third layer L3 may be disposed on the substrate 100. The first layer L1, the second layer L2, and the third layer L3 of the stacked structure SS may be spaced apart and stacked in a vertical direction (e.g., third direction D3). Each of the first layer L1, the second layer L2, and the third layer L3 may include a plurality of semiconductor patterns SP, a plurality of data storage elements DS, and a bit line BL.

[0031] The semiconductor pattern SP can have a linear, strip, or columnar shape extending in the second direction D2. For example, the semiconductor pattern SP can include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). Each of the semiconductor patterns SP can include a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH can be interposed between the first impurity region SD1 and the second impurity region SD2. The channel region CH can correspond to a reference. Figure 1 The channel of the memory cell transistor (MCT) under discussion. The first impurity region SD1 and the second impurity region SD2 can correspond to a reference. Figure 1 The source and drain of the memory cell transistor (MCT) are discussed.

[0032] The first impurity region SD1 and the second impurity region SD2 can be regions of the semiconductor pattern SP that are doped with impurities. The first impurity region SD1 and the second impurity region SD2 can have n-type or p-type conductivity. The first impurity region SD1 can be formed on the upper part of the semiconductor pattern SP.

[0033] Data storage element DS can be connected to a corresponding terminal of semiconductor pattern SP. Data storage element DS can be connected to a corresponding second impurity region SD2 of semiconductor pattern SP. Data storage element DS can be a memory element capable of storing data. Each data storage element DS can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and a variable resistor structure including a phase change material. For example, each of the data storage elements DS can be a capacitor.

[0034] Bit lines BL can have a linear or strip shape extending in a first direction D1. Bit lines BL can be spaced apart from each other and stacked along a third direction D3. Bit lines BL can include a conductive material. For example, the conductive material can include one or more of doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitride materials (titanium nitride, tantalum nitride, etc.), metallic materials (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). Bit lines BL can be referenced. Figure 1 The bitline BL is under discussion.

[0035] Of the first layer L1, the second layer L2, and the third layer L3, the first layer L1 will be described in detail below. The semiconductor patterns SP of the first layer L1 can be arranged spaced apart from each other in a first direction D1. The semiconductor patterns SP of the first layer L1 can be located at the same first horizontal height. A bit line BL of the first layer L1 can be disposed on the semiconductor patterns SP of the first layer L1. The bit line BL can be disposed on the top surface of the semiconductor patterns SP. The bit line BL can be disposed on the top surface of the first impurity region SD1 of the semiconductor patterns SP. For example, the bit line BL can be directly connected to the first impurity region SD1. Alternatively, the bit line BL can be electrically connected to the first impurity region SD1 via a metal silicide. The above detailed description of the first layer L1 is also substantially applicable to the second layer L2 and the third layer L3.

[0036] A gate electrode GE penetrating the stacked structure SS may be disposed on the substrate 100. The gate electrode GE may have a linear or strip shape extending in a third direction D3. The gate electrode GE may be arranged in a first direction D1. When viewed in a plan view, each of the gate electrodes GE may be disposed between a pair of adjacent semiconductor patterns SP. Each of the gate electrodes GE may extend vertically on the sidewall of a plurality of vertically stacked semiconductor patterns SP.

[0037] For example, one of the gate electrodes GE can be adjacent to the first semiconductor pattern SP of the first layer L1, the first semiconductor pattern SP of the second layer L2, and the first semiconductor pattern SP of the third layer L3. The other gate electrode GE can be adjacent to the second semiconductor pattern SP of the first layer L1, the second semiconductor pattern SP of the second layer L2, and the second semiconductor pattern SP of the third layer L3.

[0038] The gate electrode GE may be adjacent to the channel region CH of the semiconductor pattern SP. The gate electrode GE may be disposed on the sidewall of the channel region CH and may extend in the third direction D3. The gate dielectric layer GI may be inserted between the gate electrode GE and the channel region CH. The gate dielectric layer GI may include a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the high-k dielectric layer may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0039] The gate electrode GE may include a conductive material, which may be one of a doped semiconductor material, a conductive metal nitride material, a metal material, and a metal-semiconductor compound. The gate electrode GE may be a reference... Figure 1 The word line WL is under discussion.

[0040] A dielectric structure ISS may be disposed on the substrate 100, the dielectric structure ISS extending along one side surface of the stacked structure SS in a first direction D1. The dielectric structure ISS may be coupled to the other end of the semiconductor pattern SP. The dielectric structure ISS may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0041] Although not shown, dielectric material may fill empty spaces within the stacked structure SS. For example, the dielectric material may include one or more of silicon oxide, silicon nitride, and silicon oxynitride layers.

[0042] Figure 3 A perspective view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown. Figure 4 Examples are shown Figure 3 A plan view of a three-dimensional semiconductor memory device. Figure 5A , Figure 5B and Figure 5C Examples are given along the respective Figure 4 The cross-sectional views taken from lines A-A', B-B', and C-C' are shown. In the example embodiments below, the views referenced above will be omitted. Figure 1 and Figure 2 The technical features discussed will be described in detail, and their differences will be discussed in detail.

[0043] Reference Figure 3 , Figure 4 and Figures 5A to 5CMultiple stacked structures SS1 and SS2 can be disposed on the substrate 100. Stacked structures SS1 and SS2 may include a first stacked structure SS1 and a second stacked structure SS2. The first stacked structure SS1 and the second stacked structure SS2 may extend in a first direction D1. The first stacked structure SS1 and the second stacked structure SS2 may be arranged spaced apart from each other in a second direction D2.

[0044] Each of the first stacked structure SS1 and the second stacked structure SS2 may have a dielectric structure ISS disposed on its opposite side. The dielectric structure ISS may extend along the first stacked structure SS1 and the second stacked structure SS2 in a first direction D1. A single dielectric structure ISS may be inserted between the first stacked structure SS1 and the second stacked structure SS2. The dielectric structure ISS may insulate the first stacked structure SS1 and the second stacked structure SS2 from each other.

[0045] Each of the first stacked structure SS1 and the second stacked structure SS2 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 sequentially stacked on the substrate 100. Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a first dielectric layer ILD1, a semiconductor layer SL, and a second dielectric layer ILD2. The first dielectric layer ILD1, the semiconductor layer SL, and the second dielectric layer ILD2 may be sequentially stacked. The first dielectric layer ILD1 and the second dielectric layer ILD2 may vertically separate the semiconductor layer SL between them from other semiconductor layers SL.

[0046] Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may further include a bit line BL extending in the first direction D1. For example, each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include two bit lines BL spaced apart from each other in the second direction D2. The bit lines BL may be disposed in the second dielectric layer ILD2. The bit lines BL may be located at the same horizontal height as the second dielectric layer ILD2. The second dielectric layer ILD2 may cover the sidewalls of the bit lines BL. The bit lines BL may be disposed on the top surface of the semiconductor layer SL. The bit lines BL may be disposed adjacent to the dielectric structure ISS. The bit lines BL may be a reference. Figure 1 The bitline BL is under discussion.

[0047] Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may further include a first air gap AG1 defined when the first dielectric layer ILD1 is recessed. For example, each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include two first air gaps AG1 spaced apart from each other in the second direction D2. The first air gaps AG1 may be inserted between the bit line BL and the semiconductor layer SL. The top surface of the bit line BL may be in contact with air.

[0048] The first air gap AG1 of the first layer L1 may be defined by the bottom surface of the semiconductor layer SL, the top surface of the substrate 100, the sidewalls of the first dielectric layer ILD1, and the sidewalls of the dielectric structure ISS. The first air gap AG1 of each of the second layer L2, the third layer L3, and the fourth layer L4 may be defined by the bottom surface of the semiconductor layer SL, the top surface of the bit line BL, the top surface of the second dielectric layer ILD2, the sidewalls of the first dielectric layer ILD1, and the sidewalls of the dielectric structure ISS.

[0049] The semiconductor layer SL may include a semiconductor material such as silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The first dielectric layer ILD1 and the second dielectric layer ILD2 may include dielectric materials different from each other. The first dielectric layer ILD1 and the second dielectric layer ILD2 may independently include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. For example, the first dielectric layer ILD1 may be a carbon-containing silicon oxide layer (e.g., SiOC), and the second dielectric layer ILD2 may be a silicon nitride layer (e.g., SiN).

[0050] Each of the first stacking structure SS1 and the second stacking structure SS2 can be configured such that one end of each of the second layer L2 and the third layer L3 protrudes more in the first direction D1 than one end of the fourth layer L4. One end of the second layer L2 and one end of the third layer L3 can be vertically aligned with each other. One end of the first layer L1 can protrude more in the first direction D1 than one end of each of the second layer L2 and the third layer L3. The other end of each of the first layer L1 and the second layer L2 can protrude more in the opposite direction to the first direction D1 than the other end of each of the third layer L3 and the fourth layer L4. The other ends of the first layer L1 and the second layer L2 can be vertically aligned with each other. The other ends of the third layer L3 and the fourth layer L4 can be vertically aligned with each other.

[0051] A via HO ​​can be provided to penetrate each of the first stacked structure SS1 and the second stacked structure SS2. Each of the semiconductor layers SL may include a semiconductor pattern SP defined by the via HO. For example, each of the semiconductor layers SL may include an extension EP extending in a first direction D1 and a semiconductor pattern SP extending from the extension EP in a second direction D2 (see [link to documentation]). Figure 3 Holes HO can be located between semiconductor patterns SP.

[0052] Each of the semiconductor pattern SP may include a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH may be inserted between the first impurity region SD1 and the second impurity region SD2. A bit line BL may be disposed on an extension EP of the semiconductor layer SL. The extension EP of each of the semiconductor layers SL may be electrically connected to the bit line BL. For example, the bit line BL may be disposed on and electrically connected to the first impurity region SD1 of the semiconductor pattern SP.

[0053] The gate electrode GE can be configured to extend vertically (e.g., third direction D3) within a via HO, which penetrates one of the corresponding first stacked structures SS1 and second stacked structures SS2. For example, the gate electrode GE can penetrate both the first stacked structures SS1 and the second stacked structures SS2. A pair of gate electrodes GE can be disposed on opposite sides of each of the semiconductor pattern SP. For example, a pair of gate electrodes GE can form a word line WL. As another example, one of the pair of gate electrodes GE can be a word line WL, and the other of the pair of gate electrodes GE can be a back gate.

[0054] Each of the gate electrodes GE may include a barrier pattern BA and a conductor CB. The conductor CB may have a linear or cylindrical shape extending in a third direction D3. The barrier pattern BA may cover one sidewall and the bottom surface of the conductor CB. The conductor CB may include a metal (tungsten, titanium, tantalum, etc.), and the barrier pattern BA may include a conductive metal nitride (titanium nitride, tantalum nitride, etc.). The barrier pattern BA may impede (or alternatively, prevent) the diffusion of metallic material in the conductor CB into the semiconductor pattern SP.

[0055] A gate dielectric layer GI can be disposed on the inner sidewall of a corresponding via HO ​​in each of the first stacked structure SS1 and the second stacked structure SS2. Therefore, the gate dielectric layer GI can be inserted between each of the semiconductor pattern SP and each of the gate electrodes GE. The blocking pattern BA of each of the gate electrodes GE can directly contact the gate dielectric layer GI.

[0056] Each of the vias HO may contain a vertical dielectric pattern VIP covering a gate electrode GE. For example, a pair of adjacent gate electrodes GE in the via HO ​​may include a first gate electrode GE1 and a second gate electrode GE2. The vertical dielectric pattern VIP may be inserted between the first gate electrode GE1 and the second gate electrode GE2. The vertical dielectric pattern VIP may be inserted between a pair of adjacent semiconductor patterns SP. The vertical dielectric pattern VIP may have a cylindrical shape extending in a third direction D3. For example, the vertical dielectric pattern VIP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0057] A second air gap AG2 may be defined in each of the vertical dielectric patterns VIP. The second air gap AG2 may be surrounded by the vertical dielectric patterns VIP. As described above, a pair of adjacent gate electrodes GE in the via HO ​​may include a first gate electrode GE1 and a second gate electrode GE2. The second air gap AG2 may be inserted between the first gate electrode GE1 and the second gate electrode GE2. The second air gap AG2 may be defined in the vertical dielectric pattern VIP between the first gate electrode GE1 and the second gate electrode GE2. The second air gap AG2 may extend in the third direction D3.

[0058] A data storage element DS can be disposed in each of the vias HO. The data storage element DS can be disposed in the remaining portion of the via HO. The remaining portion of the via HO ​​can indicate the space not occupied by the gate dielectric layer GI, the gate electrode GE, and the vertical dielectric pattern VIP.

[0059] Each data storage element DS may include a first electrode EL1, a dielectric layer DL, and a second electrode EL2. Individual data storage elements DS in one of the first stacked structures SS1 and SS2 may share a dielectric layer DL and a second electrode EL2. For example, in one of the first stacked structures SS1 and SS2, multiple first electrodes EL1 may be provided, and a dielectric layer DL may cover the surfaces of multiple first electrodes EL1. A second electrode EL2 may be disposed on a dielectric layer DL.

[0060] The data storage element DS can be connected to a corresponding second impurity region SD2 of the semiconductor pattern SP. For example, the first electrode EL1 can be connected to a corresponding second impurity region SD2 of the semiconductor pattern SP. The second electrode EL2 can have a top surface exposed to the via HO.

[0061] The third dielectric layer IDL3 and the fourth dielectric layer ILD4 can be disposed on each of the first stacked structure SS1 and the second stacked structure SS2. The third dielectric layer ILD3 may include the same dielectric material as the first dielectric layer ILD1, and the fourth dielectric layer ILD4 may include the same dielectric material as the second dielectric layer ILD2.

[0062] A first interlayer dielectric layer 110 and a second interlayer dielectric layer 120 may be provided to cover the first stacked structure SS1 and the second stacked structure SS2. The second interlayer dielectric layer 120 may cover the top surface of the first interlayer dielectric layer 110 and the top surface of the fourth dielectric layer ILD4. For example, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride layers.

[0063] At least one first contact CNT1 can be provided to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and be connected to at least one bit line BL. At least one second contact CNT2 can be provided to penetrate the second interlayer dielectric layer 120 and be connected to at least one gate electrode GE. The first contact CNT1 can be disposed on the bit line BL exposed at the end of one of the first stacked structures SS1 and SS2. The second contact CNT2 can be disposed on the gate electrode GE exposed at the top surface of one of the first stacked structures SS1 and SS2.

[0064] In some example embodiments, a first air gap AG1 may be inserted between vertically stacked bit lines BL. Because the first air gap AG1 has a relatively low dielectric constant, coupling capacitance caused by interference between the bit lines BL can be reduced. When the first air gap AG1 is absent, it may be necessary to increase the thickness of the first dielectric layer ILD1 to reduce the capacitance between the bit lines BL. According to some example embodiments, because a first air gap AG1 with a low dielectric constant is provided between the bit lines BL, the thickness of the first dielectric layer ILD1 can be relatively reduced, and thus the height of each of the first stacked structure SS1 and the second stacked structure SS2 can be relatively reduced.

[0065] In some example embodiments, a second air gap AG2 may be inserted between the first gate electrode GE1 and the second gate electrode GE2. Therefore, the coupling capacitance caused by interference between the first gate electrode GE1 and the second gate electrode GE2 can be reduced. In summary, according to some example embodiments, the electrical characteristics of the semiconductor device can be improved due to the reduced capacitance between adjacent wires.

[0066] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 A plan view illustrating a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention is shown. Figure 7 , Figure 9 , Figure 11A , Figure 13A , Figure 15A , Figure 17A , Figure 19A and Figure 21A Examples are given along the respective Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20A cross-sectional view taken from line A-A'. Figure 11B , Figure 13B , Figure 15B , Figure 17B , Figure 19B and Figure 21B Examples are given along the respective Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 and Figure 20 The cross-sectional view taken by line B-B'. Figure 15C , Figure 17C , Figure 19C and Figure 21C Examples are given along the respective Figure 14 , Figure 16 , Figure 18 and Figure 20 The cross-sectional view taken from line C-C'.

[0067] Reference Figure 6 and Figure 7 A molded structure MS can be formed on the substrate 100. Forming the molded structure MS may include forming a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 stacked in sequence. The molded structure MS may be formed to have a stepped structure at its opposite ends.

[0068] Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a first dielectric layer ILD1, a semiconductor layer SL, and a second dielectric layer ILD2. The first dielectric layer ILD1, the semiconductor layer SL, and the second dielectric layer ILD2 may be formed sequentially. The semiconductor layer SL may include a semiconductor material such as silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The first dielectric layer ILD1 and the second dielectric layer ILD2 may include dielectric materials different from each other. One of the first dielectric layer ILD1 and the second dielectric layer ILD2 may have etch selectivity relative to the other of the first dielectric layer ILD1 and the second dielectric layer ILD2. The first dielectric layer ILD1 and the second dielectric layer ILD2 may independently include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. For example, the first dielectric layer ILD1 may be formed of a carbon-containing silicon oxide layer (e.g., SiOC), and the second dielectric layer ILD2 may be formed of a silicon nitride layer (e.g., SiN).

[0069] A third dielectric layer ILD3 and a fourth dielectric layer ILD4 can be formed on the molded structure MS. One of the third dielectric layer ILD3 and the fourth dielectric layer ILD4 can have etch selectivity relative to the other. The third dielectric layer ILD3 can be formed of a carbon-containing silicon oxide layer (e.g., SiOC), and the fourth dielectric layer ILD4 can be formed of a silicon nitride layer (e.g., SiN). A first interlayer dielectric layer 110 can be formed to cover the molded structure MS. The first interlayer dielectric layer 110 can have a top surface coplanar with the top surface of the fourth dielectric layer ILD4. The first interlayer dielectric layer 110 can be formed using one or more of silicon oxide layers, silicon nitride layers, and silicon oxynitride layers.

[0070] A molded structure MS can be patterned to form a hole HO that penetrates the molded structure MS. The hole HO may not penetrate the first dielectric layer ILD1 at the bottom of the molded structure MS. The first dielectric layer ILD1 at the bottom of the molded structure MS may not allow the hole HO to expose the top surface of the substrate 100.

[0071] Each of the vias HO can have a linear or strip shape extending in the second direction D2. The vias HO can be spaced apart from each other along the first direction D1. Each of the semiconductor layers SL can have a semiconductor pattern SP defined by the vias HO. For example, the semiconductor pattern SP can be defined by a pair of adjacent vias HO.

[0072] Reference Figure 8 and Figure 9 The gate dielectric layer GI can be conformally formed on the inner sidewall of the molded structure MS exposed at the via HO. For example, a high-k dielectric material can be used to conformally form the gate dielectric layer GI.

[0073] A preliminary gate electrode pGE can be formed to partially fill the via HO. The preliminary gate electrode pGE can be formed on the inner sidewall of the molded structure MS exposed in the via HO. Forming the preliminary gate electrode pGE may include conformally forming a barrier layer on the gate dielectric layer GI, conformally forming a conductive layer on the barrier layer, and anisotropically etching the barrier layer and the conductive layer to form a barrier pattern BA and a conductor CB, respectively. The barrier layer can be formed using conductive metal nitrides (titanium nitride, tantalum nitride, etc.), and the conductive layer can be formed using metals (tungsten, titanium, tantalum, etc.).

[0074] After the initial gate electrode pGE is formed, a dielectric material IM can be deposited. The dielectric material IM can be formed to completely fill the via HO. The dielectric material IM can include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Reference Figure 10 , Figure 11A and Figure 11BA planarization process can be performed on the dielectric material IM and the gate dielectric layer GI until the top surface of the first interlayer dielectric layer 110 and the top surface of the fourth dielectric layer ILD4 are exposed.

[0076] A first mask pattern MA1, including a first opening OP1 and a second opening OP2, can be formed on a first interlayer dielectric layer 110 and a fourth dielectric layer ILD4. When viewed in a plan view, the first opening OP1 and the second opening OP2 can overlap with via HO. Each of the first openings OP1 can have a linear or stripe shape extending in a second direction D2. The first openings OP1 can be spaced apart from each other along the first direction D1. The second openings OP2 can be spaced apart from each other along the first direction D1. Each of the second openings OP2 can be spaced apart from its adjacent first opening OP1 in the second direction D2 or in a direction opposite to the second direction D2.

[0077] The first mask pattern MA1 may include closed regions CR. Each of the closed regions CR may be a region between adjacent first openings OP1 and second openings OP2. Each of the closed regions CR may extend in a first direction D1. The closed regions CR may define the location for forming the gate electrode GE as described below.

[0078] A removal process can be performed on the dielectric material IM exposed to the first opening OP1 and the second opening OP2. The dielectric material IM can be removed by an anisotropic etching process. Therefore, the dielectric material IM can be partially removed, and the dielectric material IM below the closed region CR of the first mask pattern MA1 can be retained. During the anisotropic etching process for removing the dielectric material IM, the anisotropic etching process can etch the first dielectric layer ILD1 exposed at the hole HO and disposed at the bottom of the molded structure MS. Therefore, a first groove RS1 can be formed to partially expose the top surface of the substrate 100.

[0079] The initial gate electrode pGE exposed to the first opening OP1 and the second opening OP2 can be removed to form the gate electrode GE. The initial gate electrode pGE can be removed by an anisotropic etching process. Therefore, the initial gate electrode pGE can be partially removed, and the initial gate electrode pGE below the closed region CR of the first mask pattern MA1 can be retained. The remaining initial gate electrode pGE can form the gate electrode GE. The anisotropic etching process can separate one initial gate electrode pGE in a hole HO into four gate electrodes GE spaced apart from each other. The gate electrodes GE can have a linear or strip shape extending in the vertical direction (e.g., the third direction D3). The remaining dielectric material IM can be inserted between a pair of adjacent gate electrodes GE.

[0080] Reference Figure 12 , Figure 13A and Figure 13B The first mask pattern MA1 can be removed. Dielectric material can be additionally deposited in the empty spaces of each of the vias HO, allowing a vertical dielectric pattern VIP to be formed to fill the corresponding via HO. The vertical dielectric pattern VIP can be inserted between a pair of adjacent semiconductor patterns SP. The vertical dielectric pattern VIP can be inserted between a pair of adjacent gate electrodes GE.

[0081] A pair of adjacent gate electrodes GE in the via HO ​​may include a first gate electrode GE1 and a second gate electrode GE2. Forming a vertical dielectric pattern VIP may include removing the dielectric material IM between the first gate electrode GE1 and the second gate electrode GE2, depositing a dielectric layer (e.g., a silicon oxide layer) in the space where the dielectric material IM has been removed, and forming a second air gap AG2 surrounded by the dielectric layer. The dielectric layer can be deposited by a deposition process that can form a dielectric pattern with a high aspect ratio. This deposition process can have a relatively low step coverage.

[0082] Therefore, the second air gap AG2 can be defined within a vertical dielectric pattern VIP inserted between the first gate electrode GE1 and the second gate electrode GE2. The second air gap AG2 can extend in the third direction D3.

[0083] Reference Figure 14 and Figures 15A to 15C A second mask pattern MA2 can be formed on the molded structure MS. The second mask pattern MA2 may include a linear opening extending along the first direction D1.

[0084] A second mask pattern MA2 can be used as an etching mask to pattern a molded structure MS, which can form multiple stacked structures SS1 and SS2. For example, the molded structure MS can be patterned to form a first stacked structure SS1 and a second stacked structure SS2. The patterning process can result in defining trenches TR on opposite sides of each of the first stacked structure SS1 and the second stacked structure SS2. The trenches TR can partially expose the top surface of the substrate 100. When viewed in a plan view, the trenches TR can have a linear shape extending in a first direction D1.

[0085] The trench TR can expose opposing sidewalls of each of the first stacked structure SS1 and the second stacked structure SS2. A second dielectric layer ILD2 exposed in the trench TR can be partially etched, and then a bit line BL can be formed in the etched area of ​​the second dielectric layer ILD2. The bit line BL can have a linear or stripe shape extending in a first direction D1. For example, forming the bit line BL can include forming a conductive layer (e.g., metal) to fill the etched area.

[0086] Before forming the bit line BL, the semiconductor pattern SP exposed through the etched region can be doped with impurities to form a first impurity region SD1. Therefore, the bit line BL can be formed on the top surface of the first impurity region SD1.

[0087] The first dielectric layer ILD1 exposed in the trench TR can be partially etched to form the first air gap AG1. The first dielectric layer ILD1 can be etched using an etchant that selectively etches the first dielectric layer ILD1 via an isotropic etching process. Each of the first air gaps AG1 can be defined by the bottom surface of the first dielectric layer ILD1, the sidewalls of the first dielectric layer ILD1, the top surface of the bit line BL, and the top surface of the second dielectric layer ILD2. The first air gap AG1 can expose the corresponding top surface of the bit line BL.

[0088] Reference Figure 16 and Figures 17A to 17C A dielectric structure ISS can be formed to fill the corresponding trench TR. The dielectric structure ISS can be inserted between the first stack structure SS1 and the second stack structure SS2. The dielectric structure ISS can have a linear shape extending in the first direction D1.

[0089] A dielectric structure ISS can be formed to selectively fill the trench TR but not the first air gap AG1. For example, a deposition process with relatively low step coverage can be used to form the dielectric structure ISS. The dielectric structure ISS may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0090] Reference Figure 18 and Figures 19A to 19C A third mask pattern MA3 with a third opening OP3 can be formed on the first stacked structure SS1 and the second stacked structure SS2. The third opening OP3 can have a linear or strip shape extending in the first direction D1. When viewed in a plan view, the third opening OP3 can pass through the hole HO that penetrates the first stacked structure SS1 and the second stacked structure SS1.

[0091] The third mask pattern MA3 can be used as an etching mask to etch the first stacked structure SS1 and the second stacked structure SS2. This etching process can cause multiple vias HO penetrating one of the first stacked structure SS1 and the second stacked structure SS2 to be merged into a single via HO. The via HO ​​formed by this etching process can expose the sidewalls of the semiconductor pattern SP. The via HO ​​formed by this etching process can expose the sidewalls of the vertical dielectric pattern VIP.

[0092] Return to reference Figure 19CThe semiconductor pattern SP exposed to the hole HO can be selectively etched to form the second groove RS2. The semiconductor pattern SP can be etched using an etchant capable of selectively etching the semiconductor pattern SP via an isotropic etching process. The isotropic etching process can give each of the semiconductor pattern SP a reduced width (or length) in the second direction D2. Each of the second grooves RS2 can be defined by the bottom surface of the second dielectric layer ILD2, the sidewalls of the semiconductor pattern SP, and the top surface of the first dielectric layer ILD1. The second groove RS2 can be inserted between a pair of adjacent vertical dielectric patterns VIP (see...). Figure 19B ).

[0093] The sidewalls of the semiconductor pattern SP exposed at the via HO ​​and the second groove RS2 can be doped with impurities to form a second impurity region SD2. In each of the semiconductor patterns SP, the channel region CH can be defined between the first impurity region SD1 and the second impurity region SD2.

[0094] Reference Figure 20 and Figures 21A to 21C Partial etching can be performed on the vertical dielectric pattern VIP and the gate dielectric layer GI exposed in the via HO ​​and the second groove RS2. The vertical dielectric pattern VIP and the gate dielectric layer GI can be etched using an isotropic etching process with an etchant capable of selectively etching the vertical dielectric pattern VIP and the gate dielectric layer GI. Since the vertical dielectric pattern VIP and the gate dielectric layer GI are partially etched, the second groove RS2 can be extended. For example, the second groove RS2 between a pair of adjacent vertical dielectric patterns VIP can have an increased width in the first direction D1 (see...). Figure 21B ).

[0095] An electrode layer ELL can be conformally formed on the entire surface of substrate 100. The electrode layer ELL can partially fill the second groove RS2. The electrode layer ELL can directly cover the second impurity region SD2.

[0096] Return to reference Figure 3 , Figure 4 and Figures 5A to 5C The third mask pattern MA3 can be removed. The electrode layer ELL can be patterned to form a first electrode EL1 that fills the corresponding second groove RS2. For example, forming the first electrode EL1 may include forming a dielectric pattern to fill the corresponding second groove RS2, and using the dielectric pattern as an etching mask to remove the portion of the electrode layer ELL that is not covered by the dielectric pattern.

[0097] A removal process can be performed to remove the vertical dielectric pattern VIP and the gate dielectric layer GI adjacent to the first electrode EL1. A dielectric layer DL can be conformally formed on the first electrode LEL1. A second electrode EL2 can be formed on the dielectric layer DL, such that the via HO ​​can be completely filled by the second electrode EL2.

[0098] A second interlayer dielectric layer 120 may be formed on the fourth dielectric layer ILD4 and the first interlayer dielectric layer 110. At least one first contact CNT1 may be formed to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and to be connected to at least one bit line BL. At least one second contact CNT2 may be formed to penetrate the second interlayer dielectric layer 120 and to be connected to at least one gate electrode GE.

[0099] Figure 22 Examples of three-dimensional semiconductor memory devices illustrating some exemplary embodiments of the concept according to the present invention are shown. Figure 4 The cross-sectional view taken from line C-C'. Figure 23 Examples of three-dimensional semiconductor memory devices illustrating some exemplary embodiments of the concept according to the present invention are shown. Figure 4 A cross-sectional view taken along line C-C'. In the following embodiments, the reference above will be omitted. Figure 3 , Figure 4 and Figures 5A to 5C The technical features discussed will be described in detail as repeating technical features, and their differences will be discussed in detail.

[0100] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 22 Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a bit line BL located on the sidewall of the semiconductor layer SL. The bit line BL in each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may be located at the same horizontal height as the semiconductor layer SL. The bit line BL may directly contact the first impurity region SD1.

[0101] A first shield line SM1 can be provided in each of the dielectric structures ISS. The first shield line SM1 can extend along the dielectric structure ISS in a first direction D1. The first shield line SM1 can be inserted between the bit line BL of the first stacked structure SS1 and the bit line BL of the second stacked structure SS2. The first shield line SM1 can reduce the coupling capacitance caused by interference between the bit line BL of the first stacked structure SS1 and the bit line BL of the second stacked structure SS2. For example, the first shield line SM1 can be connected to a node where a ground voltage is applied.

[0102] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 23 The bit line BL in each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be located at the same horizontal height as the semiconductor layer SL. A first shield line SM1 can be provided in each of the dielectric structures ISS.

[0103] The first shielding wire SM1 may include a vertically extending vertical extension VP, and also includes a horizontal extension LP extending horizontally from the vertical extension VP in the second direction D2. (Refer to the above...) Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 22 The difference discussed may be that the first air gap AG1 is not set.

[0104] The vertical extension VP can be inserted between the bit line BL of the first stacked structure SS1 and the bit line BL of the second stacked structure SS2. The vertical extension VP can reduce the coupling capacitance caused by interference between the bit line BL of the first stacked structure SS1 and the bit line BL of the second stacked structure SS2.

[0105] Each of the horizontal extensions LP can be inserted between vertically adjacent bit lines BL. The horizontal extensions LP can reduce the coupling capacitance caused by interference between vertically adjacent bit lines BL.

[0106] Figure 24 A plan view illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention is shown. Figure 25 It shows along Figure 24 The cross-sectional view taken by line A-A'. In the following embodiments, the reference above will be omitted. Figure 3 , Figure 4 and Figures 5A to 5C The technical features discussed are repetitive technical features, and their differences will be discussed in detail.

[0107] Reference Figure 24 and Figure 25 , as referenced above Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 23 In the case of the difference discussed, the second air gap AG2 may not be provided. Each of the vertical dielectric patterns VIP may be provided with a second shielding line SM2 instead of the second air gap AG2. The second shielding line SM2 may have a linear or strip shape extending in the vertical direction (e.g., the third direction D3).

[0108] For example, a pair of adjacent gate electrodes GE in the via HO ​​may include a first gate electrode GE1 and a second gate electrode GE2. A second shielding line SM2 may be inserted between the first gate electrode GE1 and the second gate electrode GE2. A vertical dielectric pattern VIP may be inserted between the second shielding line SM2 and the first gate electrode GE1, and between the second shielding line SM2 and the second gate electrode GE2. In this case, the second shielding line SM2 may be spaced apart from the first gate electrode GE1 and the second gate electrode GE2.

[0109] The second shielding line SM2 can reduce the coupling capacitance caused by interference between the first gate electrode GE1 and the second gate electrode GE2.

[0110] For example, the first shield SM1 and the second shield SM2 can be connected to the node where the ground voltage is applied.

[0111] The gate electrode GE and the second shield line SM2 can be connected to different nodes. For example, the gate electrode GE can be connected to the node that applies a signal to the word line, and the second shield line SM2 can be connected to the node that applies a ground voltage.

[0112] The three-dimensional semiconductor memory device according to an exemplary embodiment of the present invention can reduce coupling capacitance caused by interference between bit lines, and also reduce coupling capacitance caused by interference between word lines. Therefore, the three-dimensional semiconductor memory device can improve its electrical characteristics.

[0113] Although some exemplary embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept. Therefore, it will be understood that the above exemplary embodiments are merely illustrative and not intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor memory device, comprising: a plurality of gate electrodes; and a stack structure including a plurality of layers stacked vertically on a substrate, the plurality of gate electrodes extending vertically so that the plurality of gate electrodes penetrate the stack structure, each of the plurality of layers including: a plurality of semiconductor patterns extending in parallel in a first direction, each of the semiconductor patterns including a first impurity region and a channel region, a bit line electrically connected to the first impurity region of the semiconductor pattern and extending in a second direction intersecting the first direction, a first air gap between the channel region and the bit line so that the first air gap is located between a bit line of a first layer of the plurality of layers and a bit line of a second layer of the plurality of layers, and a data storage element electrically connected to a corresponding one of the semiconductor patterns.

2. The semiconductor memory device according to claim 1, wherein, each of the semiconductor patterns further including: a second impurity region electrically connected to the data storage element, the channel region interposed between the first impurity region and the second impurity region.

3. The semiconductor memory device of claim 1, wherein, the data storage element including: a first electrode electrically connected to the corresponding one of the semiconductor patterns; a dielectric layer covering the first electrode; and a second electrode on the dielectric layer.

4. The semiconductor memory device according to claim 1, wherein, the plurality of gate electrodes including a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode each located in a hole penetrating the stack structure, and the semiconductor memory device further including: a second air gap between the first gate electrode and the second gate electrode.

5. The semiconductor memory device of claim 1, wherein, the plurality of gate electrodes including a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode each located in a hole penetrating the stack structure, and the semiconductor memory device further including: a shield line extending vertically between the first gate electrode and the second gate electrode.

6. The semiconductor memory device of claim 1, wherein, the stack structure including a first stack structure and a second stack structure adjacent to each other in the first direction, and the semiconductor memory device further including: a shield line extending in the second direction between a bit line of the first stack structure and a bit line of the second stack structure.

7. The semiconductor memory device of claim 1, wherein, the bit line is located on a top surface of the plurality of semiconductor patterns.

8. The semiconductor memory device of claim 1, wherein, the bit line is at a same horizontal level as the plurality of semiconductor patterns.

9. The semiconductor memory device of claim 1, wherein, each of the plurality of gate electrodes extends vertically adjacent to sidewalls of the semiconductor patterns vertically overlapping each other.

10. A semiconductor memory device, comprising: a stack structure including a plurality of layers stacked vertically on a substrate, each of the plurality of layers including: a plurality of semiconductor patterns extending in parallel in a first direction, each of the semiconductor patterns including a first impurity region and a channel region, a bit line electrically connected to the first impurity region of the semiconductor pattern and extending in a second direction intersecting the first direction, and a data storage element electrically connected to a corresponding one of the semiconductor patterns; a plurality of gate electrodes extending vertically to penetrate the stack structure; and a shield line extending vertically between the first gate electrode and the second gate electrode. a structure between a bit line of a first layer of the plurality of layers and a bit line of a second layer of the plurality of layers adjacent to the first layer, such that the structure reduces a coupling capacitance between adjacent ones of the bit lines, the structure comprising one of a first air gap and a first shield line, the first air gap being between the channel region and the bit line.

11. The semiconductor memory device of claim 10, wherein, each of the plurality of semiconductor patterns further comprises: a second impurity region electrically connected to the data storage element, and wherein the channel region is adjacent to a corresponding one of the plurality of gate electrodes and is interposed between the first impurity region and the second impurity region.

12. The semiconductor memory device of claim 10, wherein, the data storage element comprises: a first electrode electrically connected to the corresponding one of the plurality of semiconductor patterns; a dielectric layer covering the first electrode; and a second electrode on the dielectric layer.

13. The semiconductor memory device of claim 10, wherein the plurality of gate electrodes comprises a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are each in a hole that penetrates the stack structure, and the semiconductor memory device further comprises: a second air gap between the first gate electrode and the second gate electrode.

14. The semiconductor memory device of claim 10, wherein, the plurality of gate electrodes comprises a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are each in a hole that penetrates the stack structure, and the semiconductor memory device further comprises: a shield line extending vertically between the first gate electrode and the second gate electrode.

15. The semiconductor memory device of claim 10, wherein the stack structure comprises a first stack structure and a second stack structure adjacent to each other in the first direction, and the first shield line extends in the second direction between a bit line of the first stack structure and a bit line of the second stack structure.

16. A semiconductor memory device comprising: a stack structure comprising a plurality of layers vertically stacked on a substrate, the plurality of layers comprising: a first semiconductor pattern and a second semiconductor pattern extending in parallel in a first direction, each of the first semiconductor pattern and the second semiconductor pattern comprising a first impurity region and a channel region, a bit line electrically connected to the first impurity region of the first semiconductor pattern and the second semiconductor pattern, the bit line extending in a second direction that intersects the first direction, and a data storage element electrically connected to a corresponding one of the first semiconductor pattern and the second semiconductor pattern; a first gate electrode and a second gate electrode extending vertically in a hole that penetrates the stack structure, the first gate electrode and the second gate electrode being adjacent to the first semiconductor pattern and the second semiconductor pattern, respectively; and a first shield line extending vertically between the first gate electrode and the second gate electrode. a structure between the first gate electrode and the second gate electrode such that the structure reduces a coupling capacitance between the first gate electrode and the second gate electrode, the structure including one of a first air gap and a first shield line, the first air gap being interposed between the channel region of the first semiconductor pattern and the bit line and the channel region of the second semiconductor pattern and the bit line.

17. The semiconductor memory device of claim 16, wherein, Each of the first semiconductor pattern and the second semiconductor pattern further includes: a second impurity region electrically connected to the data storage element, and wherein the channel region is adjacent to a corresponding one of the first gate electrode and the second gate electrode and is located between the first impurity region and the second impurity region.

18. The semiconductor memory device of claim 16, wherein, The data storage element includes: a first electrode electrically connected to a corresponding one of the first semiconductor pattern and the second semiconductor pattern; a dielectric layer covering the first electrode; and a second electrode on the dielectric layer.

19. The semiconductor memory device of claim 16, further comprising: a second air gap between a bit line of a first layer of the plurality of layers and a bit line of a second layer of the plurality of layers.

20. The semiconductor memory device of claim 16, wherein, The stack structure includes a first stack structure and a second stack structure, the first stack structure and the second stack structure being adjacent to each other in the first direction, and the semiconductor memory device further includes: a second shield line extending in the second direction between a bit line of the first stack structure and a bit line of the second stack structure.

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