An I / O ESD circuit

Abstract

The present invention discloses an integrated circuit I / O (input / output) ESD (Electro‑static discharge) protection circuit. It is characterized in that the I / O ESD circuit in the present invention includes a primary protection circuit and a secondary protection circuit. The primary protection circuit provides a bidirectional discharge path from I / O PAD (pressure pad) to VDD (power supply) and from VSS (ground) to I / O PAD, wherein the discharge circuit from VSS to I / O PAD is a low-voltage opening circuit and a static voltage trigger circuit, so it is not only suitable for ordinary I / O PAD ESD protection design, but also suitable for high-speed I / O PAD protection design, and can provide bidirectional ESD protection at the same time. The secondary protection circuit is composed of a current limiting resistor and a clamping circuit for VSS and VDID, which can provide bidirectional clamping protection between I / O PAD and VDD and VSS for the internal devices of I / O PAD. Therefore, the circuit of the present invention is an I / O ESD protection technology with a low trigger voltage and suitable for human body model discharge and charging model discharge of high-speed signal ports.

Description

Technical Field

[0001] The invention relates to an integrated circuit I / O ESD circuit, which is suitable for integrated circuit electrostatic discharge protection design, and is particularly suitable for ESD protection circuit design of human body model discharge and charge model discharge of high frequency signal ports with low turn-on voltage. Background Art

[0002] Integrated circuits will face various unpredictable electrostatic environments throughout their life cycle, from production to packaging, testing, transportation, and application, which can cause electrostatic damage to the integrated circuits. Therefore, integrated circuits must not only be able to meet the functional requirements of the design, but also have a certain level of electrostatic protection capabilities. Usually, static electricity enters the integrated circuit through the I / O pins of the integrated circuit, causing damage to the integrated circuit. Therefore, the electrostatic protection of the integrated circuit is often designed in the I / O unit, where the static electricity is safely discharged, thereby protecting the entire integrated circuit from ESD damage.

[0003] Traditional I / O ESD protection circuits such as Figure 3 As shown, it usually includes two stages of ESD protection. The first is the primary protection, which is formed by P31 and N31, providing the main ESD discharge path from PAD to VDD and PAD to VSS. The secondary protection is formed by D31 and D32, which mainly provides local clamping for the internal circuit, providing discharge clamping under the charging model and discharge clamping under the human body model. At the same time, the primary protection and the secondary protection are isolated by resistor R31, which plays the role of current limiting protection.

[0004] but Figure 3 Circuit technology. Since N31 needs to trigger the parasitic transistor of the substrate through the high voltage of the drain and source to start conduction and discharge, its ESD turn-on voltage is particularly high, and the internal circuit may fail due to ESD, but the ESD circuit has not yet started discharging.

[0005] Therefore, some people proposed Figure 4 The circuit technology, that is, through the coupling effect of RC (resistance and capacitance), reduces the ESD turn-on voltage of N42, which can achieve the effect of lower ESD turn-on voltage discharge. However, since this technology is an RC frequency effect trigger circuit, it is only suitable for ESD protection of low-frequency signal ports, but not for ESD protection of high-speed signal ports. Because in the high-speed port, the RC circuit will trigger N42 to turn on and generate large leakage, affecting the normal operation of the circuit.

[0006] Therefore, in order to solve the above problems, the technical method of the present invention realizes an I / O ESD protection technology with low trigger voltage and suitable for human body model discharge and charge model discharge of high-speed signal ports. Summary of the invention

[0007] The I / O ESD circuit proposed by the present invention comprises a primary protection circuit and a secondary protection circuit. The primary protection circuit comprises a PMOS 103 between I / O PAD1 and VDD. Usually, the gate of PMOS 103 is connected to the power supply VDD 101 through a resistor to protect the gate. PMOS 103 can provide bidirectional discharge protection of I / O PAD1 to VDD101, which can realize the discharge protection of I / O PAD1 to VDD101 and the discharge protection of VDD101 to I / O PAD1. A low voltage opening unit circuit is provided between I / OPAD1 and VSS102, which provides bidirectional discharge protection of I / O PAD1 to VSS, which can realize the discharge protection of I / O PAD1 to VSS102 and the discharge protection of VSS102 to I / O PAD1. The secondary protection circuit includes a clamping circuit 1 between I / O PAD1 and VDD, which can provide bidirectional clamping protection for VDD inside I / O PAD1, and a clamping circuit 2 between I / OPAD1 and VSS, which provides bidirectional clamping protection for VSS inside I / O PAD1. Since the primary protection circuits for VDD and VSS are both bidirectional discharge structures, discharge protection for the human body model can be achieved. Since the secondary protection circuits for VDD and VSS are both bidirectional clamping structures, discharge protection for the charging model can be achieved. Therefore, the present invention can protect the internal circuit from being broken down and failing during the discharge of the human body model and the discharge of the charging model.

[0008] In the first-level protection circuit, the protection structure of I / O PAD1 to VSS is a low-voltage opening unit structure, which consists of three parts: a voltage divider circuit, a signal latch circuit, and an ESD device. The voltage divider circuit is composed of a resistor and a multi-stage series NMOS tube. The signal latch circuit is composed of two inverters that are interconnected at the input and output ends. The ESD device is an NMOS device, which provides discharge protection for I / OPAD1 to VSS. Since the low-voltage opening unit structure has no RC effect, it is suitable for the ESD protection design of high-speed signal ports. Due to the use of low-voltage trigger technology, a lower ESD opening voltage is achieved.

[0009] In the secondary protection circuit, it includes two parts, namely, clamp circuit 1 and clamp circuit 2. Clamp circuit 1 includes a series of diode strings D2, D3, and D4. At the same time, the three diodes are connected in parallel with diode D1 and then connected in series with current limiting protection resistor R2 to form a secondary protection circuit between I / O PAD1 and VDD. When ESD discharge occurs, bidirectional clamp protection between I / O PAD1 and VDD is provided to the internal circuit. Clamp circuit 2 includes a series of diode strings D6, D7, and D8. At the same time, the three diodes are connected in parallel with diode D5 and then connected in series with resistor R1 to form a secondary protection circuit between I / O PAD1 and VSS. When ESD discharge occurs, bidirectional clamp protection between I / O PAD1 and VSS is provided to the internal circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0011] Figure 1 The I / O ESD circuit structure of the present invention;

[0012] Figure 2 The low voltage clamping circuit of the present invention;

[0013] Figure 3 Traditional technology circuit design 1;

[0014] Figure 4 Conventional Technology Circuit Technology2. DETAILED DESCRIPTION

[0015] The present invention discloses an integrated circuit I / O ESD protection circuit, which realizes an I / O ESD protection technology with a low trigger voltage and suitable for human body model discharge and charge model discharge of high-speed signal ports. The implementation scheme is as follows:

[0016] The I / O ESD protection circuit disclosed in the present invention is as follows: Figure 1As shown, it includes a primary protection circuit and a secondary protection circuit. The primary protection circuit includes a PMOS103 between I / O PAD1 and VDD101. Usually, the gate of PMOS103 is connected to the power supply VDD101 through a resistor to protect the gate. The source and substrate of PMOS are connected to the power supply VDD, and the drain is connected to PAD1. PMOS103 can provide bidirectional discharge protection from I / O PAD1 to VDD101, which can realize the discharge protection from I / O PAD1 to VDD101, and the discharge protection from VDD101 to I / O PAD1. In addition, the PMOS can also be replaced by a diode, the anode of the diode is connected to PAD1, and the cathode is connected to the power supply VDD. However, if a diode is used, only ESD protection from PAD1 to the power supply VDD can be provided. Between PAD1 and VSS102 is a low-voltage opening unit, which provides bidirectional discharge protection from PAD1 to the ground VSS. The low-voltage opening unit is a two-terminal circuit structure, one end is connected to PAD1, and the other end is connected to the ground VSS. Through the low voltage start-up unit, the discharge protection of PAD1 to VSS102 can be realized, and the discharge protection of VSS102 to PAD1 can also be realized.

[0017] The secondary protection circuit includes a clamp circuit 1 between PAD1 and the power supply VDD, which can provide bidirectional clamp protection for VDD inside PAD1, and a clamp circuit 2 between PAD1 and VSS, which provides bidirectional clamp protection for VSS inside PAD1. The secondary clamp 1 circuit includes three terminals, one of which is connected to the power supply VDD, the second terminal is connected to PADR1 of the secondary clamp 2 circuit, and the third terminal is connected to PADR2 and the internal circuit. The secondary clamp 2 circuit includes three terminals, one of which is connected to PAD1, the second terminal is connected to PADR1 and the secondary clamp 1 circuit, and the third terminal is connected to the ground VSS.

[0018] In the primary protection circuit, the protection structure of PAD1 to VSS is a low voltage opening unit structure. Figure 2 As shown, PAD2 and Figure 1The PAD1 in the figure is the same node. The low voltage start-up unit structure is composed of three parts: a voltage divider circuit, a signal latch circuit, and an ESD device. The voltage divider circuit is composed of a resistor 203 and a multi-stage series-connected NMOS tube 210. One end of the resistor 203 is connected to PAD2, and the other end is connected to the multi-stage series-connected NMOS tube 210, that is, a common node 204. The multi-stage series-connected NMOS tube 210 can be composed of 2 to 10 stages of NMOS connected in series. The substrates of these NMOS are all grounded to VSS, and the gates are all connected to the common node 204 of the resistor 203. The source and drain of these NMOS are connected in series, the source of the bottom NMOS is grounded, and the drain of the top NMOS is connected to 204. The signal latch circuit is composed of two inverters with input and output terminals connected to each other, that is, PMOS205 and NMOS206 constitute a first-stage inverter, the source and substrate of PMOS205 are connected to the power supply VDD, the source and substrate of NMOS206 are connected to the ground VSS, their gates are connected together to form the input of the first-stage inverter, and their drains are connected together to form the output of the first-stage inverter. PMOS207 and NMOS208 constitute a second-stage inverter, the source and substrate of PMOS207 are connected to the power supply VDD, the source and substrate of NMOS208 are connected to the ground VSS, their gates are connected together to form the input of the second-stage inverter, and their drains are connected together to form the output of the second-stage inverter. The input terminal of the first-stage inverter is connected to 204, the output terminal is connected to the input terminal of the second-stage inverter, and the output terminal of the second-stage inverter is connected to the input terminal of the first-stage inverter, thus forming a signal latch circuit, and the output terminal of the second-stage inverter is connected to the gate of the ESD device. The ESD device 209 is an NMOS device, whose drain is connected to PAD2, and the substrate and source are grounded to VSS. The ESD device 209 provides discharge protection for PAD2 to VSS. Figure 4 The RC effect of the circuit technology shown in the figure is suitable for the ESD protection design of high-speed signal ports. Due to the use of low-voltage trigger technology, a lower ESD turn-on voltage is achieved.

[0019] The secondary protection circuit includes two parts: a clamping circuit 1 and a clamping circuit 2.

[0020] The clamp circuit 1 includes a series of diode strings D2, D3, and D4, wherein the anode of D2 is connected to the power supply VDD, the cathode of D2 is connected to the anode of D3, the cathode of D3 is connected to the anode of D4, and the cathode of D4 is connected to PADR2. The series path of D2, D3, and D4 provides clamp protection from the power supply VDD to PADR2. The number of diodes in the path can be increased or decreased according to the specific power supply VDD voltage level. The anode of diode D1 is connected to PADR2, and the cathode is connected to the power supply VDD, providing clamp protection from PADR2 to the power supply VDD. R2 is an input current limiting protection resistor, one end of which is connected to PADR2, and is also connected to the anode of D1 and the cathode of D4. The other end of R2 is connected to the PADR1 node and is also connected to the secondary clamp 2 circuit. Combined with the current limiting protection resistor R1, a secondary clamp 1 protection circuit between PAD1 and VDD is formed. When ESD discharge occurs, bidirectional clamp protection between PAD1 and VDD is provided to the internal circuit.

[0021] The clamp circuit 2 includes a series of diode strings D6, D7, and D8, wherein the anode of D6 is connected to PADR1, the cathode is connected to the anode of diode D7, the cathode of D7 is connected to the anode of D8, and the cathode of D8 is connected to the ground VSS. The number of diodes in this path can be increased or decreased according to the specific voltage levels of PAD1 and PADR1. At the same time, the three diodes are connected in parallel with the diode D5, the anode of D5 is connected to the ground VSS, and the cathode of D5 is connected to PADR1, and then connected in series with the resistor R1, that is, one end of R1 is connected to PADR1, and the other end is connected to PAD1, forming a secondary clamp 2 protection circuit between PAD1 and VSS. When ESD discharge occurs, bidirectional clamp protection between PAD1 and VSS is provided to the internal circuit.

[0022] The technical method proposed in the present invention uses a voltage triggering method to trigger the ESD device to start discharging, so it is suitable for ESD protection of high-speed signal ports, and adopts low-voltage start-up technology to reduce the ESD start-up voltage. The first-level protection circuit for VDD and VSS is a bidirectional discharge structure, and the second-level protection circuit for VDD and VSS is a bidirectional clamping structure, that is, it can protect the human body model discharge and the charging model discharge. Therefore, the present invention realizes an I / O ESD protection technology with a low trigger voltage and suitable for human body model discharge and charging model discharge of high-speed signal ports.

Claims

1. An I / O ESD circuit, Features It includes a primary protection circuit and a secondary protection circuit. The primary protection circuit includes a PMOS between I / O PAD1 and VDD, which provides bidirectional discharge protection of I / O PAD1 to VDD, a low voltage turn-on unit circuit between I / O PAD1 and VSS, which provides bidirectional discharge protection of I / O PAD1 to VSS, and a secondary protection circuit includes a first clamping circuit between I / OPAD1 and VDD, which provides bidirectional clamping protection of I / O PAD1 to VDD, and a second clamping circuit between I / OPAD1 and VSS, which provides bidirectional clamping protection of I / O PAD1 to VSS. The low-voltage start-up unit circuit consists of three parts: a voltage divider circuit, a signal latch circuit, and an ESD device. The voltage divider circuit consists of a resistor and multiple stages of NMOS tubes connected in series. The signal latch circuit consists of two interactively connected inverters. The ESD device is an NMOS device, which provides discharge protection for I / O PAD1 to VSS.

2. The circuit as claimed in claim 1, Features The first clamping circuit includes a diode string D2, D3, and D4 connected in series. At the same time, the three diodes are connected in parallel with the diode D1 and finally connected in series with the resistor R2 to form a first clamping circuit secondary protection circuit between I / O PAD1 and VDD. The second clamping circuit includes a diode string D6, D7, and D8 connected in series. At the same time, the three diodes are connected in parallel with the diode D5 and finally connected in series with the resistor R1 to form a second clamping circuit secondary protection circuit between I / O PAD1 and VSS.

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