Memory Controller

Abstract

The present disclosure relates to a memory controller. A device includes a first buffer and a second buffer that can be filled with contents of a memory location. A selection circuit is configured to select a fill mode between filling the buffers simultaneously and filling the buffers sequentially. In some examples, the device can be a system on a chip including a non-volatile memory and a processor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 1857517 filed on August 17, 2018, which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic circuits and, more particularly, to devices, such as memory controllers, that receive contents of memory locations. Background Art

[0004] Memory controllers are typically used between memory and circuits that can access the memory, for example, in electronic integrated circuit chips. Summary of the invention

[0005] Embodiments may overcome all or part of the disadvantages of known devices that receive contents of a memory location, such as a memory controller.

[0006] Thus, one embodiment provides a device comprising two buffers that can be filled with contents of memory locations, and a selector for a filling mode between simultaneous filling of the buffers and sequential filling of the buffers.

[0007] According to one embodiment, the content of each location comprises a plurality of data segments, preferably 2 data segments. Each of the buffers is configured to be filled with a plurality of data segments simultaneously.

[0008] According to one embodiment, the apparatus includes circuitry for sending one of the data segments over a bus of the same size as the data.

[0009] According to one embodiment, the two buffers may be filled with respective contents of the first and second locations having alternating addresses (preferably logical).

[0010] According to one embodiment, the device further comprises two additional buffers sequentially fillable with addresses of respective contents of the first memory location and the second memory location.

[0011] According to one embodiment, the device is configured such that a sequential filling of the buffer is a filling with the contents of consecutive memory locations.

[0012] Another embodiment provides an electronic chip comprising the device as described above.

[0013] Another embodiment provides a method that includes a first operation and a second operation of filling two buffers using memory location contents. The buffers are filled simultaneously under the first filling and are filled sequentially under the second filling.

[0014] According to one embodiment, the content of each location comprises a plurality of data segments, preferably 2 data segments. Each of the buffers is filled with the plurality of data segments simultaneously during the first filling operation and the second filling operation.

[0015] According to one embodiment, the method comprises the step of sending one of the data segments over a bus of the same size as the data.

[0016] According to one embodiment, the two buffers are filled with first and second locations, respectively, having alternating addresses (preferably logical).

[0017] According to one embodiment, the method comprises the step of storing one of the addresses of the first location and the second location in an additional buffer.

[0018] According to one embodiment, the method comprises a step of verifying equality between the request address and the address stored in the storing step.

[0019] According to one embodiment, the presence of the step of reading the content of one of the locations is a function of the result of the equality verification step.

[0020] According to one embodiment, at a first filling, the buffer is filled with the corresponding contents of consecutive memory locations.

[0021] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A chip is partially and schematically shown including one embodiment of a device for receiving contents of a memory location;

[0023] Figure 2 Schematically shows the Figure 1 The steps of an embodiment of a method implemented by a device;

[0024] Figure 3 Schematically shows the Figure 1 The type of chip to achieve Figure 2 An example of the method;

[0025] Figure 4 Schematically shows Figure 3 In the example Figure 2 the steps of the method;

[0026] Figure 5 A chip is partially and schematically shown including one embodiment of a device for receiving contents of a memory location;

[0027] Figure 6Schematically shows Figure 5 part of a device; and

[0028] Figure 7 Schematically shows Figure 5 another part of the device. DETAILED DESCRIPTION

[0029] In different drawings, the same elements are denoted by the same reference numerals. In particular, common structural and / or functional elements in different embodiments may be denoted by the same reference numerals and may have the same structure, size and material properties.

[0030] For clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail.

[0031] Throughout this disclosure, the term "connected" is used to indicate a direct electrical connection between circuit elements without intervening elements other than conductors, while the term "coupled" is used to indicate an electrical connection between circuit elements, which may be direct or may be via one or more intervening elements.

[0032] In the following description, unless otherwise stated, when referring to terms defining absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or terms defining relative positions (such as terms "above", "below", "upper", "lower", etc.), or terms defining directions (such as terms "horizontal", "vertical", etc.), reference is made to the orientation of the accompanying drawings.

[0033] The terms "about," "substantially," and "approximately" are used herein to indicate a tolerance of plus or 10%, preferably plus or minus 5%, of the value in question.

[0034] Figure 1 There is schematically shown a device, such as an integrated circuit chip, comprising an embodiment of a device 100 for receiving the contents of a memory 110, preferably a rewritable non-volatile memory of the so-called "Flash" type.

[0035] The chip is preferably of the so-called SOC (“System on a Chip”) type. SOC-type chips are used in particular for onboard or mobile applications, such as mobile phones, connected objects, household appliances or transport.

[0036] The device 100 is coupled (e.g., connected) to a data bus 120. Preferably, a data processing unit such as a microprocessor 130 (CPU) is coupled to the bus 120. The bus 120 enables, in particular, the transfer of data from a memory to a processing unit. Various peripheral devices (not shown, such as sensors, or circuits that communicate with elements external to the chip) may be coupled or connected to the bus 120. Preferably, the coupling between the device 100 and the bus 120 transfers all bits (e.g., 32 bits) of a data segment in parallel. Preferably, the size of the data bus 120 (i.e., the number of bits in parallel) is equal to the number of bits of each data segment.

[0037] Preferably, the microprocessor 130 includes or is coupled to a cache memory 132 (CACHE). For example, the cache memory is a memory having a shorter access time than the memory 110, and the memory is used as a buffer between the bus 120 and the microprocessor 130.

[0038] The memory 110 comprises a series of locations 112 and 114. Preferably, the memory locations 112 and 114 follow each other in an alternating manner in the order of their addresses, preferably their logical addresses. As an example, the locations 112 and 114 have the same number of bits, preferably 64 bits. Then for example, the address has the form 0x...8 for the location 112 and the form 0x...0 for the location 114, where "0x" means a hexadecimal symbol and "..." represents the hexadecimal digits of the address under consideration. The content of each of the locations 112 and 114 corresponds to one or more data segments. Preferably, each of the locations 112 and 114 contains 2 data segments. Preferably, each data segment corresponds to the 32 least or most significant bits of the memory location under consideration.

[0039] The device 100 includes a buffer 102 (BUFA) and a buffer 104 (BUFB). The term "buffer" is used to denote a buffer circuit, such as a buffer memory, for example a component of a flip-flop. Preferably, each buffer 102, 104 contains the same number of bits as one of the memory locations 112, 114.

[0040] Buffers 102 and 104 may be filled with respective contents of memory locations 112 and 114. Preferably, buffer 102 is configured or arranged to be filled with contents of a location selectable from location 112. Preferably, buffer 104 is configured or arranged to be filled with contents of a location selectable from location 114.

[0041] Preferably, when filling each buffer 102 and 104, the filling is performed simultaneously by all bits of the content of the memory location. Specifically, in the case where each location includes multiple data segments, then the filling is performed simultaneously by all data of the content of the memory location.

[0042] The device 100 further comprises a selector 140 for a filling mode of the buffers 102 and 104. In a first filling mode, the buffers 102 and 104 are filled simultaneously, i.e., each buffer 102, 104 is loaded with the corresponding content of one of the memory locations 112, 114 at the same time as the other. In a second filling mode, the buffers 102 and 104 are filled sequentially, i.e., during the filling of one of the buffers, the content of the other buffer remains unchanged.

[0043] Preferably, the selector 140 includes two multiplexers 152 and 154 that control the filling of the corresponding buffers 102 and 104. As an example, the filling of the buffers 102 and 104 is controlled by the corresponding signals 162 and 164. The multiplexers 152 and 154 are controlled by the filling mode selection signal SEL. The multiplexer here has inputs I0 and I1 that can be selected according to the high or low state of the multiplexer control signal. The inputs I0 and I1, as well as the low and high levels of the control signal can be exchanged. The inputs I1 of the multiplexers 152 and 154 are coupled to the application node of the same signal READ_END. For example, the inputs I0 of the multiplexers 152 and 154 are coupled to the application nodes of different corresponding signals READ_ENDA and READ_ENDB. Preferably, as described below, the device is configured to transmit the signals READ_ENDA and READ_ENDB at different times.

[0044] Figure 2 Schematically shows the Figure 1 The receiving device 100 implements the steps of an embodiment of the method.

[0045] Preferably, in step 200, the device 100 receives a request address ADDR, preferably a logical address. For example, when the microprocessor 130 and / or the cache memory 132 need a data segment located at the request address in the memory 110, the address is transmitted by the microprocessor 130 and / or the cache memory 132. The request address ADDR can also be transmitted by any device coupled to the bus 120, such as a device that directly accesses a DMA type ("direct memory access") memory. In order to receive the request address, the device 100 is preferably coupled (e.g., connected) to an address bus not shown. Then, the microprocessor 130 is coupled to the address bus.

[0046] Preferably, at step 210 (HIT?), the device 100 determines whether one of the buffers 102 and 104 already contains data for the corresponding address in memory. If this is not the case (output N of block 210), the method proceeds to step 220.

[0047] At step 220, a filling mode is selected between a simultaneous filling mode (e.g., when the signal SEL is at a high level "1") and a sequential filling mode (e.g., when the signal SEL is at a low level "0"). If the simultaneous filling mode is selected, the method proceeds to step 230. If the sequential filling mode is selected, the method proceeds to step 240. The order of steps 210 and 220 may be swapped.

[0048] In step 230 (READ_A&B), the contents of locations 112 and 114 are preferably read simultaneously from memory 110. Preferably, these locations are consecutive and contain data at the requested address. Preferably, when the reading is finished, a read end signal is transmitted. Preferably, the read end signal is the signal READ_END that controls the simultaneous filling of the buffers. The method then proceeds to step 250 (FILL_BUFA&B) for simultaneously filling buffers 102 and 104.

[0049] Preferably, at step 240 (ADDR(3)), the device 100 selects between the set of locations 112 and the set of locations 114 that contains the data located at the request address. In the example of memory locations 112 and 114 each containing 64 bits, for example, the device determines the 4th bit starting from the least significant bit (bit ADDR(3), which are generally numbered from 0). If bit ADDR(3) is equal to 0, the data contained at the request address is located in one of the locations 112. If bit ADDR(3) is equal to 1, the data contained at the request address is located in one of the locations 114. This example can be applied to any number of bits per location 112, 114, such as 32 or 128 bits.

[0050] If the data contained at the request address is located in one of the locations 112, the content of this location 112 is preferably read out in a step 262 (READ_A). Preferably, when the reading is finished, a read end signal is transmitted. This signal is preferably the signal READ_ENDA that controls the filling of only the buffer 102. The method proceeds to a step 272 (FILL_BUFA) of filling the buffer 102 with the content of the location 112 considered. The content of the buffer 104 remains unchanged at this stage.

[0051] If the data contained at the request address is located in one of the locations 114, the content of this location 114 is preferably read out in a step 264 (READ_B). Preferably, when the reading is finished, a read end signal is transmitted. This signal is preferably the signal READ_ENDB that controls the filling of only the buffer 104. The method proceeds to a step 274 (FILL_BUFA) of filling the buffer 104 with the content of the location 114 considered. At the same time, the content of the buffer 102 is not modified.

[0052] Preferably, after steps 250, 272, and 274, the method proceeds to step 280 (SELECT_DATA). In this step, device 100 determines the location of the data corresponding to the request address in buffers 102 and 104. Preferably, four locations are possible: the least significant bit of buffer 102; the most significant bit of buffer 102; the least significant bit of buffer 104; and the most significant bit of buffer 104.

[0053] Preferably, in a following step 290 (SEND_DATA), the data contained in buffers 102 and 104 at the locations determined in step 280 are sent via data bus 120. The sent data may then be used by microprocessor 130 and / or cache memory 132. After step 290, preferably the method restarts at step 200 to receive a new request address.

[0054] If, at step 210 , the data at the new requested address is already in one of buffers 102 and 104 (output Y of block 210 ), the method proceeds directly to step 280 .

[0055] Preferably, at a step not shown in the method, the signal SEL is modified. The loop method thus implemented includes filling the buffers simultaneously, as well as filling only one of the two buffers and then filling only the other of the two buffers. The method enables the data located at the various request addresses received in step 200 to be sent sequentially via the bus 120.

[0056] In a preferred embodiment, location 112 is located in a first memory group and location 114 is located in a second memory group. When the selected fill mode is sequential fill, for each request address, at most one content is read out from a single group of the two groups. This enables reduced power consumption compared to reading the contents of both groups for each request address. When the selected fill mode is simultaneous fill, the two filled buffers enable time to be saved compared to sequential fill, for example, when the processing unit 130 and / or the cache memory 132 require data located at consecutive addresses. The trade-off between execution speed and power consumption can thus be optimized.

[0057] Figure 3 Schematically shows that when the buffer is filled sequentially, Figure 1 Chip implementation of the type Figure 2 An example of a method.

[0058] In this example, the data is a 32-bit word, the data bus 120 is a 32-bit bus, the locations 112 and 114 of the memory 110 each contain 64 bits, and the cache memory 132 contains locations 302, each of which contains 128 bits. Therefore, each location 302 of the cache memory can contain 4 data segments. For example, each location is intended to receive data at the corresponding logical addresses 0x...0, 0x...4, 0x...8, and 0x...C in the memory 110.

[0059] Assume that the microprocessor needs data at logical address 0x...4, which is not present in cache memory 132. Then one of the locations 302 of the cache memory is completely filled. For this purpose, successive requests are sent to device 100 so that device 100 sends 4 corresponding data segments in sequence via bus 120. The first request relates to address 0x...4. This makes the corresponding data D1 available to the microprocessor as quickly as possible. The subsequent requests have addresses 0x...8, 0x...C and 0x...0 in sequence.

[0060] Figure 4 Schematically shows Figure 3 In the example Figure 2 Steps of the method.

[0061] The request address 0x...4 is received at step 200 (ADDR=0x...4). The data D1 at the request address 0x...4 is contained in one of the locations 112. This location 112 also contains the data D4 at the address 0x...0. The method passes through step 262 (READ_A) of reading the content of the location 112 and then through step 272 of filling the buffer 102 with this content. As a result, the buffer 102 then contains the two data segments D1 and D4. The data D1 is sent in the next step 290 (SEND_D1).

[0062] Then, in step 200 (ADDR=0x...8), the request address 0x...8 is received. The data D2 at the request address 0x...8 is contained in one of the locations 114. This location 114 also contains the data D3 at the address 0x...C. The method passes through a step 264 (READ_B) of reading the content of this location 114, and then a step 274 of filling the buffer 104 with this content. As a result, the buffer 104 then contains the two data segments D2 and D3. The data D2 is sent in the next step 290 (SEND_D2).

[0063] Then, the request address 0x...C is received in step 200 (ADDR=0x...C). After step 210 (HIT), due to the fact that the corresponding data D3 is contained in the buffer 104, the method proceeds directly to step 290 (SEND_D3) of sending the data D3.

[0064] Finally, the request address 0x...0 is received at step 200 (ADDR=0x...0). After step 210 (HIT), due to the fact that the corresponding data D4 is contained in the buffer 102, the method proceeds directly to step 290 (SEND_D4) of sending the data D4.

[0065] Thus, by executing only a step of reading the contents of position 112 and a step of reading the contents of position 114, the four data segments D1, D2, D3 and D4 are sent in that order. If only one buffer can be filled with the contents of positions 112 and 114, three reading steps are required. Thus, the method enables the memory contents to be sent faster than using a single buffer. Furthermore, the trade-off between execution speed and power consumption can be improved compared to a device having an operating mode of filling two buffers simultaneously and an operating mode of filling only one of the two buffers.

[0066] For except Figure 3 and Figure 4 This method is particularly fast for a series of request addresses other than the request addresses disclosed in the example of . This advantage exists in particular in the case where the cache memory 132 is omitted and the microprocessor 130 alternately requires the data contained in the same location 112 and the same location 114. In this case, as soon as the buffers 102 and 104 are filled, the data are sent via the bus 120 without a memory content readout step.

[0067] Figure 5 A chip is shown partially and schematically, the chip comprising one embodiment of a device for receiving contents of a memory location.

[0068] Memory 110 preferably includes a memory bank 110A (BANKA) having a location 112 located therein and a memory bank 110B (BANKB) having a location 114 located therein.

[0069] Preferably, memory group 110A provides the contents of a memory location to input I0 of multiplexer 502. The contents are provided after selection by its address and reading out from the memory. As an example, group 110B similarly provides the contents of a memory location to input I1 of multiplexer 502. For example, multiplexer 502 is controlled by signal ADDR(3) / 0. For example, when simultaneous fill mode is selected, signal ADDR(3) / 0 has a low level. Preferably, when sequential fill mode is selected, the level of signal ADDR(3) / 0 enables selection of the group containing the data at the request address ADDR. Then, signal ADDR(3) / 0 preferably corresponds to bit ADDR(3). The output of multiplexer 502 is coupled to input I1 of multiplexers 512, 522 and 524. As an example, error correction circuit 532 (ECC) is located between the output of multiplexer 502 and the inputs of multiplexers 512, 522 and 524. Multiplexers 512 and 522 each receive the contents of buffer 102 on input I0. Multiplexer 512 is controlled by signal READ_END. Multiplexer 522 is controlled by signal READ_ENDA. Multiplexer 152 ( Figure 1 ) receives the outputs of multiplexers 512 and 522.

[0070] Preferably, the content provided by group 110B is received by input I1 of multiplexer 514. As an example, error correction circuit 534 (ECC) is located between the output of group 110B and input I1 of multiplexer 514. Multiplexers 514 and 524 each receive the content of buffer 104 on input I0. Multiplexer 514 is controlled by signal READ_END. Multiplexer 524 is controlled by signal READ_ENDB. Multiplexer 154 ( Figure 1 ) receives the outputs of multiplexers 514 and 524.

[0071] As an example, the least significant bit of buffer 102 is coupled to input I00 of multiplexer 550; the most significant bit of buffer 102 is coupled to input I01 of multiplexer 550; the least significant bit of buffer 104 is coupled to input I10 of multiplexer 550; and the most significant bit of buffer 104 is coupled to input I11 of multiplexer 550. For example, multiplexer 550 is controlled by a set of the third and fourth bits of the request address starting from the least significant bit ADDR (3:2). Preferably, inputs I00, I01, I10, and I11 are selected according to the respective states '00', '01', '10', and '11' of bits ADDR (3:2). The output of multiplexer 550 is coupled to bus 120.

[0072] Preferably, the links between groups 110A and 110B, multiplexers 152, 154, 502, 512, 514, 522, and 524, and buffers 102 and 104 can transfer all bits of the contents of the memory locations in parallel.

[0073] Preferably, the link between buffers 102 and 104, multiplexer 550, and bus 120 can transfer all bits of a data segment in parallel, preferably 32 bits.

[0074] Figure 6 and Figure 7 Schematically shows Figure 5 The portion of the receiving device which enables Figure 2 Step 210 (HIT?) of the method.

[0075] The device includes two buffers 602 (ADDRBUFA) and 604 (ADDRBUFB) for storing request addresses. The request address is received by input I1 of multiplexers 612, 614, 622 and 624. Multiplexers 612 and 614 receive the contents of buffer 602 on input I0. The outputs of multiplexers 612 and 614 are coupled to the input of multiplexer 632, which is controlled by signal SEL. Multiplexers 622 and 624 receive the contents of buffer 604 on input I0. The outputs of multiplexers 622 and 624 are coupled to the input of multiplexer 634, which is controlled by signal SEL. Multiplexers 612 and 622 are controlled by READ_ENDA and READ_ENDB, respectively. Multiplexers 614 and 624 are controlled together by signal READ_END.

[0076] In operation, when the simultaneous buffer fill mode is selected, the two buffers 602 and 604 are filled with the request addresses associated with the filling of the buffers 102 and 104 ( Figure 2When the sequential filling mode is selected, the buffer 602 or 604 is filled with the request address associated with the filling of the corresponding buffer 102 or 104 (step 262 or 264). When one of the two buffers 602 and 604 is filled, the content of the other buffer of the two buffers 602 and 604 remains unchanged.

[0077] Thus, the contents of buffers 602 and 604 correspond to the request addresses associated with the filling of buffers 602 and 604 .

[0078] exist Figure 7 , buffer 602 is coupled to an input of circuit 702 (EQ), which receives a request address on another input. Circuit 702 is a circuit for verifying equality between values ​​received on its two inputs. Preferably, circuit 702 provides a high level when the received values ​​are equal, and provides a low level when the received values ​​are different. The output of circuit 702 is coupled to the input of AND gate 710. AND gate 710 receives signals OKA&B at another input. The output of circuit 702 is also coupled to AND gate 712. AND gate 712 receives signal OKA at another input.

[0079] Buffer 604 is coupled to an input of circuit 704 (EQ), which is used to verify equality between two inputs. Circuit 704 receives a request address at the other of its two inputs. The output of circuit 704 is coupled to an input of AND gate 714. AND gate 714 receives signal OKB at the other input.

[0080] The outputs of AND gates 712 and 714 are coupled to the input of an OR gate 720. The outputs of OR gate 720 and AND gate 710 are coupled to a multiplexer 730. Multiplexer 730 is controlled by a signal SEL. Multiplexer 730 provides a signal HIT.

[0081] Each of the signals OKA, OKB, and OKA&B is activated (e.g., set high) when valid conditions are met involving: buffers 102 and 602 for signal OKA; buffers 104 and 604 for signal OKB; and the four buffers for signals OKA&B. For example, such conditions are the absence of: continued filling of the associated buffer, continued reading from memory, the presence of valid data in the buffer, etc.

[0082] In operation, when the data in memory at the requested address is already present in the contents of buffers 102 and 104, signal HIT is activated. Figure 2 The signal HIT is used at step 210 (HIT?) of the method.

[0083] You can use it to enable execution Figure 2 Any circuit of the method step 210, instead of Figure 6 and Figure 7 Preferably, the circuit is configured to store the address of the content of the filled buffer into the buffer. The circuit then determines whether the stored address corresponds to the address of the new request. As a variant, step 210 can be omitted.

[0084] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of the various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0085] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0086] These changes, modifications and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the present invention. Therefore, the foregoing description is by way of example only and is not intended to be restrictive. The present invention is limited only as defined in the appended claims and their equivalents.

Claims

1. An electronic device, comprising: a first content buffer capable of being filled with the contents of a first memory location; a second content buffer capable of being filled with the contents of a second memory location, wherein the first memory location and the second memory location have alternating addresses; a first address buffer and a second address buffer, the first address buffer and the second address buffer being capable of being sequentially filled with respective content addresses of the first memory location and the second memory location; as well as a selection circuit configured to select a fill mode between simultaneous fill and sequential fill; wherein during the simultaneous filling, the first address buffer and the second address buffer are filled with request addresses associated with filling of the first content buffer and the second content buffer, such that the first content buffer and the second content buffer are filled simultaneously; Wherein, during sequential filling, one of the first address buffer and the second address buffer is filled with a request address associated with filling of a corresponding content buffer of the first content buffer and the second content buffer, and during filling of the corresponding content buffer, the content of the other content buffer remains unchanged. 2 . The electronic device of claim 1 , wherein the contents of each memory location comprises a plurality of data bits, each of the buffers being configured to be filled with the plurality of data bits simultaneously. 3 . The electronic device of claim 2 , comprising a driver configured to send N data bits via a bus having N parallel lines, N being a real number greater than 1. 4 . The electronic device of claim 3 , wherein the driver comprises a multiplexer. 5 . The electronic device of claim 1 , wherein the electronic device is configured such that the sequential filling of the first content buffer and the second content buffer comprises filling with contents of consecutive memory locations.

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