Floating boost precharge scheme for sense amplifier

Abstract

Embodiments of the present disclosure relate to a floating boost precharge scheme for a sense amplifier. A sensing structure includes: a sense amplifier core configured to compare a measured current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limiting or reducing the voltage overshoot by adjusting a voltage at the control terminal of the first transistor.

Description

Technical Field

[0001] The present invention generally relates to electronic systems and methods and, in a particular embodiment, to a floating boost pre-charge scheme for a sense amplifier. Background Art

[0002] In memory devices such as non-volatile memory (NVM) devices, sense amplifiers are typically used to determine (read) the state of a cell (e.g., 0 or 1) by measuring the current associated with the memory cell. Typically, the sense amplifier compares the current associated with the memory cell to a reference current. The magnitude of this current can be several pA. Typically, a memory device simultaneously reads (in parallel) a word formed by logic values ​​stored in a selected page of memory cells (e.g., containing 64 to 256 memory cells) by using multiple sense amplifiers. Typically, a memory device includes a sense amplifier for each memory cell (e.g., word or page) to be read simultaneously.

[0003] During a read operation, the sense amplifier typically holds its terminals at a predetermined read voltage to receive a measurement current and a reference current. For example, in a nonvolatile memory device including memory cells implemented with floating-gate metal oxide semiconductor (MOS) transistors thereof, the read voltage is used to bias the selected memory cells for reading so that their MOS transistors are conductive or non-conductive depending on the stored logic value.

[0004] Precise control of the sense voltage is required in many applications of sense amplifiers. For example, in non-volatile memory devices, the sense voltage should be maintained at a certain value so that the logic value stored in the selected memory cell can be correctly distinguished without changing the state of the memory cell (i.e., without overwriting the memory cell). This may be particularly important when the value of the sense voltage is relatively low (e.g., <1-2V).

[0005] For this purpose, the sense amplifier is usually equipped with a voltage regulator for regulating the sensing voltage to limit possible variations relative to its desired value. A typical implementation of such a voltage regulator is to have transistors (e.g., MOS type transistors) in a cascode configuration. Since the cascode driver is a low impedance driver, this structure allows the terminals of the sense amplifier to be preloaded to the sensing voltage in a relatively fast manner during the precharge phase. The cascode structure also allows effective separation of the bit line from the core of the sense amplifier, which allows correct operation even when the sense amplifier is coupled to a load with high capacitance (such as a column of memory cells in a non-volatile memory device). Specifically, in a cascode configuration with fixed control (e.g., a gate-type cascode configuration), the sensing voltage is regulated by controlling the transistors of the voltage regulator with a bias voltage of a constant value (provided by a bias stage shared with all sense amplifiers). Summary of the invention

[0006] According to an embodiment, a sensing structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal;

[0007] and a control circuit coupled to the control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal.

[0008] According to one embodiment, a nonvolatile memory includes a plurality of memory cells arranged in rows and columns; a row decoder coupled to the plurality of memory cells via a plurality of word lines; a column decoder coupled to the plurality of memory cells via a plurality of bit lines; a bias stage configured to generate a bias voltage; and a plurality of sense amplifiers, wherein each sense amplifier includes a sense amplifier core configured to compare a measured current with a reference current; a cascode transistor coupled between the sense amplifier core and one of the plurality of bit lines; a switch coupled between an output of the bias stage and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor; and, after disconnecting the local capacitor from the reference terminal, to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.

[0009] According to one embodiment, a reading method of a nonvolatile memory includes: generating a bias voltage at a bias terminal; disconnecting a control terminal of a cascode transistor from the bias terminal during a precharge phase, the cascode transistor being coupled between a sense amplifier core and a bit line of the nonvolatile memory; disconnecting a local capacitor coupled to the control terminal of the cascode transistor from a reference terminal; and after disconnecting the local capacitor from the reference terminal, limiting or reducing a voltage overshoot at the control terminal of the cascode transistor by adjusting a voltage of a control terminal of a first transistor coupled between the local capacitor and the reference terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 An NVM according to an embodiment of the present invention is shown;

[0012] Figure 2 The embodiment of the present invention is shown Figure 1 The sensing structure of NVM;

[0013] Figure 3 The embodiment of the present invention is shown Figure 2 Details of the sensing structure;

[0014] Figure 4 FIG. 1 shows a diagram illustrating a method for performing a read operation according to an embodiment of the present invention. Figure 2 and Figure 3 A timing diagram of signals associated with a sensing structure;

[0015] Figure 5 The embodiment of the present invention is shown Figure 3 Details of the sensing control circuit;

[0016] Figure 6 FIG. 1 shows a diagram illustrating a method for performing a read operation according to an embodiment of the present invention. Figure 5 A timing diagram of signals associated with a sensing control circuit;

[0017] Figure 7 The embodiment of the present invention is shown Figure 1 The waveform of the NVM; and

[0018] Figure 8 An exemplary method of reading a memory cell according to an exemplary embodiment of the present invention is shown.

[0019] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, letters indicating variations of the same structure, material, or process step may follow the figure numerals. DETAILED DESCRIPTION

[0020] The manufacture and use of the present preferred embodiment are discussed in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific environments. The specific embodiments discussed only illustrate the specific ways to manufacture and use the present invention and do not limit the scope of the present invention.

[0021] The following description describes various specific details to provide a deep understanding of several example embodiments according to this specification. Embodiments can be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid blurring the different aspects of the embodiments. References to "embodiments" in this specification indicate that a specific configuration, structure, or feature described in the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific formations, structures, or features may be combined in any appropriate manner.

[0022] The present invention is described in conjunction with embodiments in a specific context, where a NVM device has one or more sense amplifiers. Embodiments of the present invention may be used in other types of memory. Some embodiments may be used in devices other than memory devices that benefit from the use of sense amplifiers.

[0023] Embedded non-volatile memory (eNVM) technology is shrinking. Reduced cell size is often associated with a reduction in the reference current used to sense the state (e.g., 0 or 1) of the NVM cell. Reduced cell size is also associated with low gain. Low measurement current and low cell gain make it difficult to distinguish the state (e.g., 0 or 1) of the NVM cell. Increasing the accuracy of the reference current helps the sense amplifier determine the state (e.g., 0 or 1) of the NVM cell.

[0024] For example, reduced cell size is also associated with increased cell degradation due to cell cycling (ie, programming and erasing of cells).For example, the voltage at the control terminal of a memory device transistor should be limited to a predetermined level to avoid transistor damage or degradation.

[0025] At the same time, the demand for low read current consumption and high read speed (low access time) continues to increase.

[0026] The read speed can be increased by controlling the cascode transistors using a closed loop scheme, where the feedback loop includes an inverter operating in the linear region. Operating the inverter in the linear region causes the inverter to dissipate current (e.g., from Vdd, through the high-side transistor, through the low-side transistor, to ground) that is not used to precharge the bit line.

[0027] Current consumption can be reduced by operating the cascode transistors in an open loop, such as described in U.S. Pat. No. 9,679,618, the entire contents of which are incorporated herein by reference. However, because the closed-loop system is able to cause a controlled overshoot at the gate of the cascode transistor coupled to the bit line to be precharged, the known closed-loop system tends to be faster than the known open-loop system.

[0028] In an embodiment of the present invention, the NVM increases the read speed by reducing the precharge phase time while maintaining low power consumption. The precharge phase time is reduced by causing an overshoot in the gate of the cascode transistor, which increases the charging speed of the bit line to be precharged. In some embodiments, the overshoot is controlled in a closed loop without using an inverter operating in the linear region.

[0029] Figure 1 An NVM 100 according to an embodiment of the present invention is shown. NVM 100 may be embedded in, for example, a microcontroller or processor, a security device or other security element, an application specific integrated circuit (ASIC), a radio frequency identification (RFID) circuit, a memory device, or any other device or apparatus with integrated memory.

[0030] NVM 100 includes a memory plane 102, a column decoder 104, a row decoder 106, a read / write (R / W) unit 108, an input / output (I / O) buffer 110, and a controller 112. Memory plane 102 includes a plurality of memory cells 114 arranged in rows and columns. The memory cells 114 of each row are coupled to the same word line (not shown). The memory cells 114 of each column are coupled to the same bit line (not shown). Each memory cell 114 can have a different state, such as a state represented by a logic value (i.e., 0 or 1).

[0031] During normal operation, the controller 112 sends addresses and instructions (eg, read or write) to the row decoder 106 and column decoder 104. The row decoder 106 and column decoder 104 bias the word lines and bit lines to select the memory cell 114 associated with the address.

[0032] For a write operation, the data to be written is received by the I / O buffer and transferred to the R / W unit 108. The column decoder 104 configures the memory plane 102 to program the selected memory cells 114 by changing the values ​​of the unselected memory cells 114 to reflect the logic values ​​of the data receivers from the I / O buffer 110.

[0033] For a read operation, column decoder 104 configures the memory plane using sense amplifiers (not shown) in R / W unit 108 to read the logic value of the selected memory cell 114. The read data is then transferred to I / O buffer 110.

[0034] The memory cell 114 may be, for example, a floating gate MOS transistor. Other memory cell types may be used. For example, the memory cell 114 may be a phase change memory (PCM) type, a resistance random access memory (RRAM) type, or a magnetoresistive random access memory (MRAM) type. A one-time programmable (OTP) cell may also be used.

[0035] R / W unit 108 includes circuitry for reading and writing memory cell 114. For example, R / W unit 108 includes a sensing structure (not shown) that includes one or more sense amplifiers configured to determine the contents of memory cell 114. The sensing structure is configured to read one or more bits (e.g., words, such as 8-bit, 16-bit, or 32-bit words) at a time.

[0036] Row decoder 106, column decoder 104, and I / O buffer 110 may be implemented in any manner known in the art. For example, in some embodiments, row decoder 106, column decoder 104, and I / O buffer 110 may be implemented using digital techniques in a known manner.

[0037] The controller 112 is configured to control the NVM 100 using a plurality of control signals 116 to perform, for example, a read operation or a write operation. The controller 112 may be implemented in any manner known in the art. For example, the controller 112 may be implemented using a state machine or other digital circuits.

[0038] A read operation typically involves a precharge phase and a read (sensing) phase. Figures 2 to 7 , details of the structure and methods associated with performing a read operation on NVM 100 are described.

[0039] Figure 2 A sensing structure 200 according to an embodiment of the present invention is shown. The sensing structure 200 is internal to the R / W cell 108 and includes n sense amplifiers 202, a bias stage 204, and an adjustment capacitor 206. In some embodiments, the sensing structure 200 includes 8 (i.e., n=8) sense amplifiers 202. A different number (such as 16, 32, 38, 64, etc.) of sense amplifiers may be used.

[0040] During a read operation, the word line WL is used i A group of memory cells 114 are selected to be read. During the precharge phase, the bit lines BL associated with the selected memory cells 114 are biased to a read voltage. In some embodiments, the read voltage is between 1 V and 2 V. Other read voltages may be used.

[0041] After the precharge phase, and after the voltage of the bit line BL associated with the selected memory cell 114 has stabilized to the read voltage, the sense amplifier 202 compares the corresponding current Im with the corresponding reference current Iref to determine the state of the selected memory cell 114. The corresponding sense amplifier 202 generates a corresponding output Vout based on the state of the selected corresponding memory cell 114. For example, in some embodiments, the memory cell 114 exhibits little or no measured current Im (Im) when biased with the read voltage and storing a first logic value (e.g., 0 or 1). low ), and exhibits a higher measured current Im (Im) when biased with a read voltage and storing a second logic value (e.g., 1 or 0) high ). By comparing the measured current Im with the reference current Iref, the sense amplifier 202 determines the logic value stored in the selected memory cell 114. In some embodiments, the reference current Iref is typically about

[0042] The bias stage 204 is configured to generate a voltage V bias And the voltage V biasis provided to all sense amplifiers 202. In some embodiments, bias stage 204 generates voltage V bias , which is greater than the power supply voltage Vdd. The bias stage 204 may generate a boost voltage by using, for example, a charge pump (not shown). Other embodiments may generate a voltage V bias , whose voltage is equal to or less than the power supply voltage Vdd.

[0043] like Figure 2 As shown, the adjustment capacitor 206 is common to all sense amplifiers 202. The capacitor 206 is configured to adjust the voltage V bias and filter noise. Affects voltage V bias The noise of may be caused, for example, by one or more of the measurement currents Im.

[0044] The precharge phase typically takes up a significant portion of the total access time. Therefore, reducing the time to precharge the bit line BL associated with a selected memory cell 114 advantageously increases the speed at which the memory cell 114 can be read.

[0045] In an embodiment, the precharge time is reduced by causing a controlled overshoot in the gate of the cascode transistor. The overshoot is controlled by using a sense control circuit that adjusts a voltage of a gate of a first transistor coupled between a local capacitor and ground, wherein the local capacitor is connected to the gate of the cascode transistor. In some embodiments, the sense control circuit controls the voltage of the first transistor based on a difference between a voltage at the gate of the cascode transistor and a bias voltage.

[0046] Figure 3 Detail of the sensing structure 200 according to an embodiment of the present invention is shown. For clarity, Figure 3 A single sense amplifier 202 is shown. Figure 4 2 is a timing diagram illustrating signals associated with the sensing structure 200 during a read operation according to an embodiment of the present invention. Figure 4 Understandable Figure 3 .

[0047] like Figure 3 As shown, bias stage 204 includes amplifier 308, transistor 310, and current source 312. Sense amplifier 202 includes sense amplifier core 328, detection control circuit 314, transistors 322 and 324, local capacitor 326, and switches 318 and 320.

[0048] When NVM 100 is not performing a read or write operation, switch 316 is closed (ie, conducting), switches 318, 320, and 330 are open (ie, non-conducting), and transistor 324 is turned on (ie, conducting), as shown in FIG. Figure 4In this state, the voltage V bias is applied to the gate terminal of transistor 322, and the voltage across the terminals of capacitor 326 is equal to the voltage V bias .

[0049] At the beginning of the pre-charge phase, switch 316 is opened, switches 318 and 330 are closed, and transistor 324 is turned off. Figure 4 At this time, it is charged to a voltage V bias As a result, current flows through switch 318 and transistor 322, and voltage V cascode The gate-source capacitance of transistor 322 (not shown) begins to overshoot and exceeds the voltage V bias Voltage V cascode The overshoot of φ causes transistor 322 to turn on faster than it would without the overshoot.

[0050] If no overshoot limiting mechanism is used, the voltage V cascode The overshoot can reach Vdd = V bias During the precharge phase, the sensing control circuit 314 monitors the voltage across the switch 316 and controls the gate of the transistor 324 to limit the voltage V cascode For example, in some embodiments, the voltage V324 increases with V cascode and V bias As a result, capacitor 326 is transformed from being connected to ground to being resistively connected to ground, such as Figure 4 At the end of the precharge phase, transistor 324 is fully turned on, capacitor 326 is connected between the gate of transistor 322 and ground, and switch 316 is closed, as shown in FIG. Figure 4 In some embodiments, instead of or in addition to fully turning on transistor 324, capacitor 324 may be connected to ground using a different transistor (not shown).

[0051] At the beginning of the read phase, and on the bit line BL j After reaching the read voltage VBL, the switch 318 is opened and the switch 320 is closed. Figure 4 At this point, the sense amplifier core 328 is connected to the memory cell 114. During the read phase, the sense amplifier core 328 measures the measurement current Im (flowing through the switch 320, the transistor 322 and the switch 330) and compares it with the reference current Iref ( Figure 3 The sense amplifier 328 generates an output Vout based on comparing the measurement current Im with the reference current Iref.

[0052] like Figure 3As shown in FIG. 1 , the signal S controlling switches 316 , 318 and 320 316 , S 318 and S 320 The signal S that controls the switch 330 is generated by the controller 112. 330 Generated by column decoder 104. Switches 316, 318, 320, and 330 may be implemented in any manner known in the art. For example, switches 316, 318, 320, and 330 may be implemented with MOS transistors such as NMOS and / or PMOS transistors.

[0053] Bias stage 204 generates voltage V by using amplifier 308 and transistor 310 bias As shown, the voltage V bias is applied to the gate of transistor 310, so that the voltage V bias1 = VBL. Transistor 310 has similar characteristics to transistor 322, so that when V bias When applied to transistor 322 , the voltage at the source of transistor 322 is equal to voltage VBL.

[0054] like Figure 3 As shown in FIG. 1 , the bias stage 204 receives a power supply voltage Vdd. In some embodiments, the bias stage 204 receives a boost voltage V higher than the power supply voltage Vdd. boost For example, the boost voltage Vdd may be generated by a charge pump. In some embodiments, the bias stage 204 may receive a supply voltage lower than Vdd.

[0055] Transistors 310, 322 and 324 are implemented as NMOS transistors. Those skilled in the art will appreciate that other types of transistors, such as PMOS transistors, may also be used with appropriate modifications to the circuit.

[0056] The sense amplifier core 328 may be implemented in any manner known in the art. For example, some embodiments may use a differential amplifier to compare the measurement current Im with the reference current Iref and generate an output Vout. In some embodiments, the sense amplifier core 328 includes one or more latches. Other implementations are also possible.

[0057] The sensing control circuit 314 is configured to use the voltage V 324 to control transistor 324 to allow voltage V cascode Overshoot and overshoot voltage are limited to reduce precharge time. In some embodiments, such as Figure 3 As shown in FIG. 1 , the sensing control circuit 314 controls the transistor 324 in a closed-loop manner by monitoring the voltage across the switch 316. In other embodiments, the sensing control circuit 314 generates the voltage V in an open-loop manner. 324, without monitoring the voltage across switch 316. In an open-loop embodiment, the voltage V may be determined, for example, during a characterization phase (eg, during manufacturing or testing of a memory device). 324 waveform.

[0058] It should be understood that Figure 4 The voltage V 324 The waveforms of are non-limiting examples of possible waveforms. The voltage V 324 Different waveform shapes may be present, such as, for example, a linear ramp.

[0059] Figure 5 Details of the sense control circuit 314 are shown according to an embodiment of the present invention. Figure 6 2 is a timing diagram illustrating signals associated with the sense control circuit 314 during a read operation according to an embodiment of the present invention. Figure 6 Understandable Figure 5 .

[0060] like Figure 5 As shown in FIG. 1 , the sensing control circuit 314 includes transistors 502, 504, 506, 508, 510, 512, 514, and 516 and terminals. The drain of transistor 508 is coupled to capacitor 326. The gates of transistors 510 and 512 are coupled to both ends of switch 316, respectively. The drain of transistor 514 is coupled to the gate of transistor 324. Terminal NEQ is coupled to the gates of transistors 504, 506, 508, and 514. Terminal BIASP is coupled to the gate of transistor 502.

[0061] During normal operation, the voltage V BIASP is maintained at a bias voltage. In some embodiments, the voltage V BIASP It is also used to bias one or more transistors inside the sense amplifier core 328.

[0062] Before the precharge phase begins, the voltage V NEQ For high, such as Figure 6 As shown in the figure. When the voltage V NEQ When high, transistor 508 is turned on, thereby connecting capacitor 326 to ground. NEQ When it is high, transistor 514 is also turned on, thereby maintaining the voltage V 324 is low, which keeps transistor 324 off. Therefore, capacitor 326 is charged to a voltage V cascode .

[0063] At the beginning of the pre-charge phase, switch 316 is turned on and the voltage V NEQ From high to low, such as Figure 6As a result, transistor 508 stops pulling capacitor 326 to ground, and transistor 514 stops pulling the gate of transistor 324 to ground. Therefore, node N 326 As a result, the voltage V cascode Start overshooting, such as Figure 6 as shown in .

[0064] Low voltage V NEQ This will also turn on transistors 504 and 506. cascode Increases above the voltage V bias , transistor 512 becomes more conductive, while transistor 510 becomes less conductive. Therefore, the current flowing through transistor 516 flows primarily through transistors 506 and 512. As a result, the voltage V applied to the gates of transistors 324 and 516 is 324 Increase.

[0065] With the voltage V 324 increases, transistor 324 becomes more conductive and pulls to ground node N 326 , thereby reducing the voltage V cascode Overshoot, such as Figure 6 At the end of the precharge phase, the voltage V NEQ Transitions from low to high, thereby connecting to grounded capacitor 326 via transistor 508 , and turning off transistors 504 , 506 , and 516 , thereby preventing current from flowing through transistors 502 , 504 , 510 , 512 , and 516 .

[0066] like Figure 6 As shown in FIG. , in some embodiments, V cascode During the read phase, the bias During the read phase, V cascode Keep above V bias .

[0067] Advantages of some embodiments include increasing read speed while maintaining low power consumption. Additional advantages include not propagating noise associated with precharging the bit line to voltage V by disconnecting the gate of the cascode transistor from the bias stage during the precharge phase. bias .

[0068] Figure 7 Waveforms of NVM 100 according to an embodiment of the present invention are shown. Figure 7 Also shown is the waveform of an open loop implementation described in U.S. Patent No. 9,679,618, which does not include transistor 324 and control circuit 314 for comparison purposes. Curves 702 and 752 show the voltage V in NVM 100 and the open loop implementation, respectively.cascode Curves 704 and 754 show the voltage on the bit line BL of the NVM 100 and the open loop implementation, respectively. j Curve 706 shows the voltage V of NVM 100. NEQ Curve 708 shows the voltage V of NVM 100. 324 .

[0069] As shown in curves 702 and 752, the voltage V of the NVM 100 cascode The overshoot is greater than the voltage V of the open loop implementation disclosed in U.S. Patent No. 9,679,618. cascode The overshoot is about 270 mV higher (about 20% higher). Increasing the overshoot results in reducing the precharge time to 1.5 ns in this example, which is about 2 ns faster than the 3.5 ns precharge time of the open loop implementation disclosed in US Pat. No. 9,679,618.

[0070] Figure 8 An embodiment method 800 of reading a memory cell according to an embodiment of the present invention is shown. The method 800 may be implemented, for example, by the NVM 100. The method 800 may also be implemented by other memory devices. The following description assumes that the NVM (such as the NVM 100) implements the method 800 of reading a memory cell.

[0071] During step 802, a NVM such as NVM 100 generates a bias voltage. The bias voltage may be generated by a bias stage such as bias stage 204. Other bias stage implementations may be used.

[0072] During step 804, the NVM receives an instruction to read one or more memory cells. For example, the instruction may be received by the controller 112.

[0073] During step 806, one or more memory cells are read. Step 806 includes step 808 for precharging one or more selected bit lines associated with the one or more memory cells to be read. Step 806 also includes step 810 for reading the one or more memory cells. Although step 806 may be performed with respect to a single memory cell, it should be understood that multiple memory cells may be read simultaneously as described in steps 808 and 810.

[0074] Step 808 includes steps 812, 814, 816, and 818. During step 812, the control terminal of the cascode transistor, such as cascode transistor 322, is disconnected from the output of the bias stage. During step 814, a local capacitor, such as local capacitor 326, is disconnected from a reference terminal, such as a ground terminal. As a result, the control terminal of the cascode transistor is floating.

[0075] During step 816, a control circuit such as control circuit 314 limits a voltage overshoot in a control terminal of the cascode transistor. The voltage overshoot may be limited by adjusting a control terminal of a first transistor coupled between a local capacitor and a reference terminal. In some embodiments, the control circuit adjusts the control terminal of the first transistor based on an output of the bias stage and a voltage at the control terminal of the cascode transistor.

[0076] During step 818, the bit line associated with the memory cell to be read is charged to the read voltage. In some embodiments, the wait time is fixed. In other embodiments, the voltage of the bit line is monitored (measured) and the wait time is based on the measured voltage of the bit line, such as when dummy sensing is used to close the read window. After charging the bit line, the memory cell is read during step 810.

[0077] During step 820, the bit line, already at the read voltage, is connected to a corresponding sense amplifier core, such as sense amplifier core 328. The sense amplifier core compares a measurement current, such as measurement current Im flowing through the corresponding bit line, with a reference current, such as reference current Iref, and determines the value stored in the corresponding memory cell based on the comparison during step 822.

[0078] Example embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0079] Example 1. A sensing structure includes a sense amplifier core configured to compare a measured current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, to limit or reduce the voltage overshoot by adjusting the voltage of the control terminal of the first transistor.

[0080] Example 2. The sensing structure of Example 1, wherein the control circuit is configured to adjust a voltage at a control terminal of the first transistor based on a voltage across the switch.

[0081] Example 3. A sensing structure of one of Examples 1 or 2, wherein the control circuit includes a second transistor coupled between a second terminal of the local capacitor and a reference terminal; a third transistor coupled between a control terminal of the first transistor and a reference terminal; and a first terminal configured to receive a first voltage, wherein the first terminal is coupled to a control terminal of the second transistor and to a control terminal of the third transistor.

[0082] Example 4. A sensing structure of one of Examples 1 to 3, wherein the control circuit further includes a fourth transistor having a control terminal coupled to the control terminal of the first transistor; a fifth transistor coupled between a power terminal of the control circuit and the fourth transistor, the fifth transistor having a control terminal coupled to a bias voltage node; and a sixth transistor coupled between a power terminal of the control circuit and the fourth transistor, the sixth transistor having a control terminal coupled to the control terminal of the common-source common-gate transistor.

[0083] Example 5. A sensing structure of one of Examples 1 to 4, wherein the control circuit further includes a seventh transistor coupled between a power terminal of the control circuit and the fifth transistor, the seventh transistor having a control terminal coupled to the first terminal; and an eighth transistor coupled between a power terminal of the control circuit and the sixth transistor, the eighth transistor having a control terminal coupled to the first terminal.

[0084] Example 6. The sensing structure of one of Examples 1 to 5, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors, and wherein the seventh transistor and the eighth transistor are PMOS transistors.

[0085] Example 7. A sensing structure of one of Examples 1 to 6, wherein the control circuit further includes a ninth transistor coupled between a power supply terminal of the control circuit and the fifth transistor, the ninth transistor having a control terminal configured to receive a second bias voltage and wherein the read amplifier core is configured to receive the second bias voltage.

[0086] Example 8. The sensing structure of one of Examples 1 to 7, wherein the control terminal of the fourth transistor is coupled to the drain terminal of the fifth transistor.

[0087] Example 9. The sensing structure of one of Examples 1 to 8, further comprising a second switch coupled between a power supply terminal of the sensing structure and the cascode transistor; and a third switch coupled between the second switch and the sense amplifier core.

[0088] Example 10. The sensing structure of one of Examples 1 to 9, further comprising a bias stage configured to generate a bias voltage at a bias voltage node, wherein the bias stage comprises an amplifier having an output coupled to the output of the bias stage; a common capacitor coupled to the output of the bias stage; and a tenth transistor having a control terminal coupled to the output of the bias stage.

[0089] Example 11. The sensing structure of one of Examples 1 to 10, wherein the cascode transistor is configured to be coupled to the memory cell as a load.

[0090] Embodiment 12. A nonvolatile memory comprises a plurality of memory cells arranged in rows and columns; a row decoder coupled to the plurality of memory cells via a plurality of word lines; a column decoder coupled to the plurality of memory cells via a plurality of bit lines; a bias stage configured to generate a bias voltage; and a plurality of sense amplifiers, wherein each sense amplifier comprises a sense amplifier core configured to compare a measured current with a reference current; a cascode transistor coupled between the sense amplifier core and one of a plurality of bit lines; a switch coupled between an output of the bias stage and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to a control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to the control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor; and, after disconnecting the local capacitor from the reference terminal, limiting or reducing the voltage overshoot by adjusting a voltage at the control terminal of the first transistor.

[0091] Example 13. The nonvolatile memory of Example 12 further includes a controller configured to: receive a read request; open the switch in response to the read request; and cause the control circuit to disconnect the local capacitor from the reference terminal in response to the read request.

[0092] Example 14. The nonvolatile memory of one of Examples 12 or 13, wherein the controller causes the control circuit to disconnect the local capacitor from the reference terminal simultaneously with opening the switch.

[0093] Example 15. A nonvolatile memory of one of Examples 12 to 14, wherein each sense amplifier further comprises a second switch coupled between a power supply terminal of the sense amplifier and the common-source common-gate transistor; and a third switch coupled between the second switch and the sense amplifier core, and wherein the controller is further configured to close the second switch when the switch is open.

[0094] Example 16. The nonvolatile memory of one of Examples 12 to 15, wherein the bias stage includes an amplifier having an output coupled to the output of the bias stage; a common capacitor coupled to the output of the bias stage; and a tenth transistor having a control terminal coupled to the output of the bias stage.

[0095] Example 17. The nonvolatile memory of one of Examples 12 to 16, wherein each memory cell of the plurality of memory cells comprises a floating gate transistor.

[0096] Example 18. A method for reading a nonvolatile memory, the method comprising: generating a bias voltage at a bias terminal; during a precharge phase, disconnecting a control terminal of a cascode transistor from the bias terminal, the cascode transistor being coupled between a sense amplifier core and a bit line of the nonvolatile memory; disconnecting a local capacitor coupled to the control terminal of the cascode transistor from a reference terminal; and after disconnecting the local capacitor from the reference terminal, limiting or reducing a voltage overshoot at the control terminal of the cascode transistor by adjusting a voltage of a control terminal of a first transistor coupled between the local capacitor and the reference terminal.

[0097] Example 19. The method of Example 18, wherein disconnecting the control terminal of the cascode transistor from the bias terminal includes: opening a first switch coupled between the bias terminal and the control terminal of the cascode transistor, the method further comprising: receiving a read request; and in response to the read request, opening the first switch; closing a second switch coupled between the power terminal and the cascode transistor; and closing a third switch coupled between the cascode transistor and the bit line.

[0098] Example 20. The method of one of Examples 18 or 19, wherein adjusting the voltage of the control terminal of the first transistor comprises: adjusting the voltage of the control terminal of the first transistor based on a voltage across the first switch.

[0099] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A sensing structure, include: a sense amplifier core configured to compare the measured current to a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal; as well as a control circuit coupled to a control terminal of the first transistor, the control circuit being configured to disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor, and to limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor after disconnecting the local capacitor from the reference terminal. 2 . The sensing structure of claim 1 , wherein the control circuit is configured to adjust the voltage at the control terminal of the first transistor based on a voltage across the switch.

3. The sensing structure according to claim 1, wherein the control circuit include: a second transistor coupled between the second terminal of the local capacitor and the reference terminal; a third transistor coupled between the control terminal and the reference terminal of the first transistor; as well as A first terminal is configured to receive a first voltage, wherein the first terminal of the control circuit is coupled to the control terminal of the second transistor and to the control terminal of the third transistor.

4. The sensing structure according to claim 3, wherein the control circuit further include: a fourth transistor having a control terminal coupled to the control terminal of the first transistor; a fifth transistor coupled between a power supply terminal of the control circuit and the fourth transistor, the fifth transistor having a control terminal coupled to the bias voltage node; as well as A sixth transistor is coupled between the power supply terminal of the control circuit and the fourth transistor, the sixth transistor having a control terminal coupled to the control terminal of the cascode transistor.

5. The sensing structure according to claim 4, wherein the control circuit further include: a seventh transistor coupled between the power terminal of the control circuit and the fifth transistor, the seventh transistor having a control terminal coupled to the first terminal of the control circuit; as well as An eighth transistor is coupled between the power supply terminal of the control circuit and the sixth transistor, the eighth transistor having a control terminal coupled to the first terminal of the control circuit. 6 . The sensing structure of claim 5 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors, and wherein the seventh transistor and the eighth transistor are PMOS transistors.

7. A sensing structure according to claim 5, wherein the control circuit further includes a ninth transistor, the ninth transistor being coupled between the power supply terminal of the control circuit and the fifth transistor, the ninth transistor having a control terminal configured to receive a second bias voltage, and wherein the readout amplifier core is configured to receive the second bias voltage.

8. The sensing structure of claim 5, wherein the control terminal of the fourth transistor is coupled to a drain terminal of the fifth transistor.

9. The sensing structure according to claim 1, further comprising: include: a second switch coupled between a power terminal of the sensing structure and the cascode transistor; as well as A third switch is coupled between the second switch and the sense amplifier core.

10. The sensing structure of claim 1, further comprising a bias stage configured to generate a bias voltage at the bias voltage node, wherein the bias stage include: an amplifier having an output coupled to an output of the bias stage; a common capacitor coupled to an output of the bias stage; as well as A tenth transistor has a control terminal coupled to the output of the bias stage. 11 . The sensing structure of claim 1 , wherein the cascode transistor is configured to be coupled to a memory cell as the load.

12. A non-volatile memory, include: a plurality of memory cells arranged in rows and columns; a row decoder coupled to the plurality of memory cells via a plurality of word lines; a column decoder coupled to the plurality of memory cells via a plurality of bit lines; a bias stage configured to generate a bias voltage; as well as A plurality of sense amplifiers, wherein each sense amplifier comprises: a sense amplifier core configured to compare the measured current to a reference current; a cascode transistor coupled between the sense amplifier core and one of the plurality of bit lines; a switch coupled between an output of the bias stage and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between the second terminal of the local capacitor and a reference terminal; and A control circuit is coupled to the control terminal of the first transistor, the control circuit being configured to: disconnect the local capacitor from the reference terminal to generate a voltage overshoot in the control terminal of the cascode transistor; and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting the voltage of the control terminal of the first transistor.

13. The non-volatile memory according to claim 12, further comprising a controller, wherein the controller is configured to: Receive a read request; In response to the read request, opening the switch; and The control circuit is caused to disconnect the local capacitor from the reference terminal in response to the read request. 14 . The nonvolatile memory according to claim 13 , wherein the controller causes the control circuit to disconnect the local capacitor from the reference terminal simultaneously with opening the switch.

15. The nonvolatile memory according to claim 13, wherein each sense amplifier further comprises: include: a second switch coupled between a power supply terminal of the sense amplifier and the cascode transistor; as well as A third switch is coupled between the second switch and the sense amplifier core, and wherein the controller is further configured to close the second switch when the switch is opened.

16. The nonvolatile memory of claim 12, wherein the bias stage include: an amplifier having an output coupled to the output of the bias stage; a common capacitor coupled to the output of the bias stage; as well as A tenth transistor has a control terminal coupled to the output of the bias stage.

17. The non-volatile memory of claim 12, wherein each memory cell of the plurality of memory cells comprises a floating gate transistor.

18. A method for reading a non-volatile memory, the method include: generating a bias voltage at a bias terminal; During the pre-charge phase, disconnecting a control terminal of a cascode transistor from the bias terminal, the cascode transistor being coupled between a sense amplifier core and a bit line of the nonvolatile memory; disconnecting a local capacitor coupled to the control terminal of the cascode transistor from a reference terminal; as well as After disconnecting the local capacitor from the reference terminal, a voltage overshoot at the control terminal of the cascode transistor is limited or reduced by adjusting a voltage of a control terminal of a first transistor coupled between the local capacitor and the reference terminal.

19. The method of claim 18, wherein the control terminal of the cascode transistor is disconnected from the bias terminal include: opening a first switch coupled between the bias terminal and the control terminal of the cascode transistor, the method further comprising: receiving a read request; and In response to the read request, Turning on the first switch; closing a second switch coupled between a power supply terminal and the cascode transistor; and A bit line switch coupled between the cascode transistor and the bit line is closed.

20. The method of claim 19, wherein adjusting the voltage of the control terminal of the first transistor include: The voltage at the control terminal of the first transistor is adjusted based on a voltage across the first switch.

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