Optically isolated latching solid state relay with low on-resistance and linear operation

Abstract

The latching relay includes a power supply terminal, a load terminal, a first coupling circuit and a second coupling circuit, a latching circuit, a first transistor and a second transistor, and a local power supply node coupled to a capacitor. In one example, the power supply terminal is coupled to the power supply node, and the load terminal is coupled to the load. The first transistor and the second transistor control the conductivity of the drive transistor coupled to the load. The microcontroller controls the latching relay to turn the load on and off. To enable the load, the microcontroller sinks the current from the power supply terminal and sinks it through the first coupling circuit. When the load is enabled, the capacitor is discharged. The latching relay can operate in a refresh mode, in which the current pulses through the first coupling circuit to recharge the capacitor from the power supply terminal. To disable the load, the microcontroller sinks the current through the second coupling circuit.

Description

Technical Field

[0001] The present invention relates generally to packaged electronic devices and, more particularly, to switching relays. Background Art

[0002] Latching relays are commonly used in switching applications to turn a load on and off. Once turned on, a latching relay remains latched in the on state and keeps the load on until the latching relay is turned off. One common type of latching relay uses an electromagnet to mechanically operate the switch. These mechanical types of relays tend to be susceptible to damage. For example, a shock caused by a drop can damage the internal mechanical components of the relay, rendering the relay inoperable. Another common type of switching relay is the solid-state relay. Conventional solid-state relays use silicon-controlled rectifiers (SCRs) to turn the load on and keep it on. These conventional solid-state relays typically require a separate power supply to keep the latch in the on state. Additionally, conventional solid-state relays tend to have undesirable operating characteristics. A solution that overcomes these challenges is needed. Summary of the invention

[0003] The latching relay includes a power supply terminal, a load terminal, a first coupling circuit and a second coupling circuit, a latching circuit, a first transistor and a second transistor, and a local power supply node coupled to a capacitor. The latching relay is a discretely packaged power semiconductor device having a package terminal. The power supply terminal and the load terminal are package terminals of the latching relay. The latching relay is controlled by an external signaling mechanism such as a microcontroller to turn on the load, keep the load in a conducting state, and then disconnect the load. The power supply terminal is coupled to the power supply node, and the load terminal is coupled to the load. The first transistor and the second transistor control the conductivity of the driving transistor coupled to the load. In one embodiment, the driving transistor is within the package of the latching relay, and in another embodiment, the driving transistor is outside the package of the latching relay.

[0004] The first coupling circuit and the second coupling circuit relate to any electromagnetic energy coupling method, including optical, inductive or capacitive methods. In one example, the first coupling circuit and the second coupling circuit are optocoupler circuits using optical coupling technology. The first optocoupler includes a light emitting diode (LED) and a photovoltaic stack and photodiode (PVSPD) circuit. The PVSPD circuit includes a photovoltaic stack and a photodiode. The photovoltaic stack of the PVSPD circuit is used to enable a refresh mode of a latching relay. The photodiode of the PVSPD circuit is used to turn on the latching relay. The second optocoupler circuit includes an LED and a photodiode circuit. The photodiode circuit of the second optocoupler is used to disable the latching relay and disconnect the load. The first optocoupler circuit and the second optocoupler circuit ensure that the ground on the control side is isolated from the ground on the load side.

[0005] To enable the load, the microcontroller sinks the current from the power supply terminal and sinks it through the first optocoupler circuit. Sinking the current through the first optocoupler circuit causes the LED of the first optocoupler circuit to radiate energy detected by the photodiode. Enabling the photodiode causes the latch circuit to switch the digital logic level output by the latch circuit. The output of the latch circuit in turn causes the transistor to turn on, thereby controlling the drive transistor to turn on. Once the drive transistor is turned on, current flows from the positive terminal of the load power supply through the load and through the drive transistor to the negative terminal of the load. Unlike traditional latching relays implemented using SCRs, the latching relay exhibits linear operating characteristics. In one example, the latching relay includes: a MOSFET transistor, which exhibits more desirable linear operating characteristics compared to the SCR.

[0006] According to a novel aspect, a local power supply node supplies power to a circuit system in a latching relay. The circuit system includes a first optocoupler circuit and a second optocoupler circuit, a latching circuit and a transistor. The local power supply node is powered by a capacitor. When the latching relay is latched in the on state, the local power supply node supplies power to the latching relay circuit system to maintain the on state without consuming energy from the load side, because there is no available voltage when the drive transistor is in the on state. When the load is enabled, the energy stored in the capacitor is consumed by the latching relay circuit system, which includes the gate of the drive transistor that keeps the load turned on. As the energy stored in the capacitor decreases, the voltage on the local power supply node begins to decrease. If the voltage on the local power supply node decreases below the minimum operating voltage, the gate of the drive transistor will no longer be maintained, thereby disconnecting the drive transistor. In order to avoid the voltage on the local power supply node from being unexpectedly reduced to below the minimum operating voltage level, the latching relay operates in a refresh mode to refresh the capacitor and keep the voltage on the local power supply node above the minimum operating voltage level.

[0007] In refresh mode, current pulses through the LED of the first optocoupler circuit. This causes a voltage to be generated across the photovoltaic stack of the PVSPD circuit in the first optocoupler circuit. The voltage is used to charge the capacitor. In one embodiment, the capacitor is outside the package of the latching relay, and the latching relay has a storage terminal coupled to the lead of the capacitor. In another embodiment, the capacitor is located inside the package of the latching relay and does not include a storage terminal. In yet another embodiment, an additional load power supply terminal is included in the encapsulated latching relay. If the load power supply is accessible through the load power supply terminal, then no capacitor or refresh mode is required because the load power supply is used to keep the local power supply node above the minimum operating voltage level.

[0008] To disable the load, the microcontroller causes current to flow through the second optocoupler circuit. Sinking current through the second optocoupler circuit causes the LED of the second optocoupler circuit to radiate energy detected by the photodiode circuit. Enabling the photodiode circuit resets the latch circuit and causes the output of the latch circuit to switch digital logic states. This in turn causes the conductivity of the transistor to change, thereby pulling the gate of the drive transistor to ground and disconnecting the drive transistor. Once the drive transistor is disconnected, current stops flowing through the load, and the load is disconnected.

[0009] Further details and examples are described in the detailed description below. This summary is not intended to limit the invention. The invention is defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings illustrate embodiments of the present invention, wherein like numerals denote like components.

[0011] Figure 1 is a diagram of a system 10 that includes a novel optically isolated latching solid state switching relay 11.

[0012] Figure 2 is a detailed circuit diagram of the optically isolated latching solid-state switch relay 11.

[0013] Figure 3 is a circuit diagram showing the initial connection of an optically isolated latching solid-state switching relay 11 with a load 13 and a microcontroller 12 .

[0014] Figure 4 is a circuit diagram showing how capacitor 21 is used to power local supply node 63 .

[0015] Figure 5 is a circuit diagram showing how a latching relay is used to enable load 13.

[0016] Figure 6 is a circuit diagram showing how to recharge the capacitor 21 by controlling the optically isolated latching solid-state switch relay 11 in the refresh mode.

[0017] Figure 7 is a circuit diagram showing how a latching relay switches a load 13 from an enabled state to a disabled state.

[0018] Figure 8 is a waveform diagram of voltage and current along various nodes of the system 10 during operation of the optically isolated latching solid-state switching relay 11 .

[0019] Fig. 9 is a flow chart of a method 100 according to one novel aspect.

[0020] Fig.10is a circuit diagram of another configuration of the optically isolated latching solid-state switching relay 11, wherein the load power supply 15 is directly coupled to the load supply terminal 36, thereby avoiding the need for the capacitor 21 or for refresh mode operation.

[0021] Fig.11 is a circuit diagram of another embodiment of a packaged latching relay 200 , in which a drive transistor 201 is located outside the latching relay. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to some embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0023] Figure 1 1 is a diagram of a system 10 that includes a novel optically isolated latching solid-state switch relay 11. The optically isolated latching solid-state switch relay 11 is also referred to herein as a "latch relay 11". The system 10 includes the latch relay 11, a microcontroller 12, a load 13, a voltage supply 14, a load supply 15, a microcontroller supply 16, resistors 17 and 18, a first ground 19, a second ground 20, and a capacitor 21. The latch relay 11 includes a first coupling circuit 22, a second coupling circuit 23, Latch 24 ("latch circuit"), voltage regulator 25, diodes 26-28, inverter 29, enhancement mode n-channel metal oxide semiconductor field effect transistors (MOSFETs) 30 and 31 (also referred to as "NMOS transistors 30 and 31"), enhancement mode p-channel MOSFET 32 (also referred to as "PMOS transistor 32"), power supply terminal 33, set / refresh control terminal 34, reset control terminal 35, load power supply terminal 36, load terminal 37, ground (or return) terminal 38, and storage terminal 39. NMOS transistor 30 is also referred to as a "drive transistor". In this example, the capacitor is external to latch relay 11, first coupling circuit 22 is a voltage regulator, load 13 is a fire alarm, voltage supply 14 is a 3.3-5.0V battery, and load supply 15 is a 24V battery.

[0024] The first coupling circuit 22 and the second coupling circuit 23 are implemented using any coupling method including optical coupling, inductive coupling, or capacitive coupling. Figure 1 In the example of FIG. 1 , the first coupling circuit 22 and the second coupling circuit 23 are optical couplers. The first coupling circuit 22 includes a light emitting diode (LED) 40 and a photovoltaic stack and photodiode (PVSPD) circuit 41. The second coupling circuit 23 includes an LED 42 and a photodiode circuit 43. Reference numeral 44 denotes an optical isolation barrier formed by the first coupling circuit 22 and the second coupling circuit 23.

[0025] The microcontroller 12 includes a power supply terminal 45, control terminals 46 and 47, and a ground terminal 48. Details of the internal circuit system of the microcontroller are not shown and are omitted for simplicity of description. The power supply terminal 45 receives an input supply voltage for powering the microcontroller 12. The microcontroller 12 generates a set / refresh control signal 49 and outputs the set / refresh control signal 49 to the control terminal 46. The microcontroller 12 generates a reset control signal 50 and outputs the reset control signal 50 to the control terminal 47. In one example, the microcontroller 12 is a Z32F128 ARM Cortex M3 commercial microcontroller available from Zilog, Inc, with an address of 1590 Buckeye Dr, Milpitas, CA 95035. In operation, the latching relay 11 is operable to switch current flowing through the load 13 so that the microcontroller 12 selectively controls the load to be turned on and off. Reference is made below to Figures 3 to 7 Explain the operation of latching relay.

[0026] Capacitor 21 powers the circuitry of the latching relay via a local supply node 63 coupled to a storage terminal 39. Local supply node 63 is coupled to voltage regulator 25, the cathode terminal of diode 26, first coupling circuit 22, a terminal of PMOS transistor 32, and latch circuit 24. When the load is enabled, capacitor 21 begins to deplete and the voltage level on local supply node 63 begins to decrease. In order to replenish capacitor 21 and ensure that the voltage on local supply node 63 is sufficient to power the circuitry of the latching relay, microcontroller 12 controls latching relay 11 to be in refresh mode, thereby pulsing current through supply terminal 33 and through first coupling circuit 22. This current pulsation through first coupling circuit 22 recharges capacitor 21. Although capacitor 21 is shown as being external relative to latching relay 11, in other embodiments, capacitor 21 is internal to latching relay 11 and no storage terminal such as terminal 39 is provided.

[0027] Figure 2 Detailed circuit diagram of the optically isolated latching solid-state switch relay 11. The first coupling circuit 22 includes: an LED 40, which controls a PVSPD circuit 41 by radiating energy. The PVSPD circuit 41 includes a photovoltaic stack 51, a photodiode 52, and a resistor 53. The second coupling circuit 23 includes: an LED 42, which controls a photodiode circuit 43 by radiating energy. The photodiode circuit 43 includes a photodiode 54 and a resistor 55. The voltage regulator 25 includes a Zener diode 56, resistors 57 and 58, an NPN bipolar junction transistor 59, and a depletion mode n-channel MOSFET 60.

[0028] Figure 36 is a circuit diagram showing the initial connection of latching relay 11 to load 13 and microcontroller 12. Load 13 is initially disconnected. No significant current flows through the load. After the initial connection, capacitor 21 begins to charge according to current 62. Current 62 is a minimum current level and does not have a sufficient current level to enable load 13. Current 62 is also called "trickle current" or "leakage current". Figure 3 In the example of , the trickle current 62 is less than 100 uA. The trickle current 62 flows through the load 13, through the load terminal 37, through the diode 28, through the voltage regulator 25, through the storage terminal 39, and to the lead of the capacitor 21. The trickle current 62 charges the capacitor 21.

[0029] Figure 4 is a circuit diagram showing how capacitor 21 is used to power local power supply node 63. Capacitor 21 is coupled to local power supply node 63 via storage terminal 39 and powers local power supply node 63. Local power supply node 63 in turn powers the circuit system of latching relay 11. Local power supply node 63 is coupled to first coupling circuit 22, cathode of diode 26, voltage regulator 25, source terminal of PMOS transistor 32, and latching circuit 24. In this example, capacitor 21 is external to latching relay 11. Capacitor 21 has one terminal coupled to storage terminal 39 and another terminal coupled to ground 20. In another example, capacitor 21 is internal and within latching relay 11, and no storage terminal is provided to latching relay 11.

[0030] Figure 5 is a circuit diagram showing how a latching relay is used to enable a load 13. The microcontroller 12 controls the set / refresh control signal 49 to switch from a digital logic high level to a digital logic low level. When the set / refresh control signal 49 is at a digital logic low level, the first coupling circuit 22 sinks current from the voltage supply 14. Current flows from the voltage supply 14 through the LED 40 via the power supply terminal 33, through the resistor 17 via the control terminal 34, and to the terminal 46 of the microcontroller 12. Reference numeral 64 represents this current flow. The flow of current through the LED 40 causes the photodiode 52 to be activated and pulls the node 72 low. This in turn pulls the latch circuit 24 Input set. In response, latch circuit 24 outputs a digital logic high signal 66 at the Q output terminal of latch circuit 24. Inverter 29 receives and inverts digital logic high signal 66 and provides a digital logic low signal 67 to the gate of PMOS transistor 32, thereby enabling PMOS transistor 32. Once PMOS transistor 32 is enabled, local power supply node 63 biases the gate of NMOS transistor 30, thereby enabling NMOS transistor 30. After NMOS transistor 30 is enabled, load 13 is turned on and drives current 65 from load power supply 15, through load 13, through load terminal 37, through NMOS transistor 30 and to the negative terminal of load power supply 15 via terminal 38. Set / refresh control signal 49 switches to a digital logic high level, and current stops flowing through LED 40 of first coupling circuit 22.

[0031] When load 13 is enabled, capacitor 21 begins to discharge. As capacitor 21 discharges, the voltage of local supply node 63 decreases. Discharging of capacitor 21 is undesirable because NMOS transistor 30 is held in a conductive state by powering its gate from local supply node 63. If capacitor 21 discharges such that NMOS transistor 30 were to turn off and no longer conduct, load current 65 would stop flowing and load 13 would be disconnected. As described below with reference to Figure 6 As described above, the latching relay 11 is controlled to be in the refresh mode so that the capacitor 21 is recharged from the power supply terminal 33 instead of from the load terminal 37 .

[0032] Figure 6 1 is a circuit diagram showing how to recharge the capacitor 21 by controlling the latching relay 11 in the refresh mode. In order to keep the local power supply node 63 above the minimum voltage to keep the NMOS transistor 30 in a conductive state and power the other circuit systems of the latching relay 11, the microcontroller 12 controls the latching relay 11 to operate in the refresh mode. In the refresh mode, the set / refresh control signal 49 is pulsed with a predetermined fractional duty cycle. In this example, the duty cycle of the set / refresh control signal 49 in the refresh mode is predetermined based on design factors including integrated circuit leakage, external MOSFET leakage, and board leakage.

[0033] During the refresh mode, the capacitor 21 is charged from the voltage supply 14 via the supply terminal 33. In the refresh mode, the capacitor 21 is not charged from the load supply 15 or from the load terminal 37. When the set / refresh control signal 49 is controlled to a digital logic high level in the refresh mode, no current flows through the LED 40 of the first coupling circuit 22. Neither the LED 40 nor the photovoltaic stack 51 is enabled. Therefore, when the set / refresh control signal 49 is controlled to a digital logic high level, the capacitor is not charged.

[0034] When the set / refresh control signal 49 is controlled to a digital logic low level, the LED 40 causes current to flow from the voltage source 14 via the supply terminal 33 to the control terminal 34. This causes the LED 40 to be enabled and radiate energy absorbed by the photovoltaic stack 51, thereby enabling the photovoltaic stack 51. When the photovoltaic stack 51 is enabled, a voltage +V is generated across the photovoltaic stack 51. The voltage +V across the photovoltaic stack 51 charges the capacitor 21 via the diode 26 and the storage terminal 39. Reference numeral 68 represents the current path from the PVSPD circuit 41, which charges the capacitor 21. Therefore, the capacitor 21 is charged during the low period of the set / refresh control signal 49. By operating the refresh mode so that the capacitor is kept above the minimum operating voltage level of the circuit system within the latching relay 11, the NMOS transistor 30 remains on and the load 13 remains enabled.

[0035] Figure 7 is a circuit diagram showing how the latching relay switches the load 13 from an enabled state to a disabled state. The microcontroller 12 controls the reset control signal 50 to switch from a digital logic high level to a digital logic low level. When the reset control signal 50 is at a digital logic low level, the second coupling circuit 23 sinks the current from the voltage supply 14. The current flows from the voltage supply 14 via the power supply terminal 33 through the LED 42, via the control terminal 35 through the resistor 18, and to the terminal 47 of the microcontroller 12. Reference numeral 69 represents this current flow. The current flow through the LED 42 causes the photodiode 54 to be activated and pulls the node 70 low. This in turn pulls the latch circuit 24 In response, latch circuit 24 outputs a digital logic low signal 66 at the Q output terminal and The digital logic high signal 71 is outputted at the output terminal. The inverter 29 receives the digital logic low signal 66 and inverts it, and provides the digital logic high signal 67 to the gate of the PMOS transistor 32, thereby disabling the PMOS transistor 32. The digital logic high signal 71 is provided to the gate of the NMOS transistor 31, thereby enabling the NMOS transistor 31. Once the NMOS transistor 31 is enabled, the gate of the NMOS transistor 30 is pulled low via the NMOS transistor 31, thereby disabling the NMOS transistor 30. After the NMOS transistor 30 is disabled, the load 13 is disconnected. The reset control signal 50 switches to a digital logic high level, and the current stops flowing through the LED 42 of the second coupling circuit 23.

[0036] Figure 8 1 is a waveform diagram of the voltage and current along various nodes of the system 10 during the operation of the latching relay 11. At time T0, the latching relay is connected to the load 13, such as Figure 3As shown. From time T0 to time T1, capacitor 21 begins to charge from trickle current 62. As capacitor 21 charges, the voltage on local power supply node 63 begins to increase. At time T1, capacitor 21 is fully charged, as shown. Figure 4 In this example, when the capacitor 21 is fully charged, the local power supply node 63 is at 12.0 V. A person skilled in the art will appreciate that the voltage of the local power supply node 63 may be configured to other voltages according to the operating characteristics of the selected capacitor 21 and the load requirements of the load 13.

[0037] At time T2, the microcontroller 12 controls the latching relay 11 to enable the load 13, such as Figure 5 As shown. The set / refresh control signal 49 switches from a digital logic high level to a digital logic low level, which starts the connection to the load 13. From time T1 to time T4, the load current 65 increases. In this example, the load current 65 reaches 5mA, but it should be understood that the load current will reach different current levels depending on the load. Between time T2 and T3, the local power supply node 63 decreases due to the discharge of the capacitor 21. Between time T3 and T4, the local power supply node 63 increases due to the LED 40 being enabled, which causes the local power supply node 63 to be charged.

[0038] At time T5, the microcontroller 12 controls the latching relay 11 to operate in the refresh mode. The refresh mode extends from time T5 to time T11. Between time T5 and time T6, the set / refresh control signal 49 switches from a digital logic high level to a digital logic low level, and the capacitor 21 is charged, thereby increasing the voltage on the local power supply node 63. Between time T6 and time T7, the set / refresh control signal 49 switches from a digital logic low level to a digital logic high level, and the capacitor 21 is discharged, thereby reducing the voltage on the local power supply node 63. As shown in the figure, the pulsation sequence is repeated between times T8, T9 and T10.

[0039] In one embodiment, reference numeral 73 indicates the time (T P ) and the time when the set / refresh control signal 49 is high (T REF ) The relationship between the current I SC represents the current available to charge the capacitor from the photovoltaic stack 51 when the set / refresh control signal 49 is low. DIS represents the current consumed when the set / refresh control signal 49 is high and the capacitor 21 is discharged. The relationship 73 is required to prevent the voltage on the local supply node 63 from dropping below the minimum operating voltage of the latching relay 11.

[0040] At time T11, microcontroller 12 controls latching relay 11 to disable load 13. Reset control signal 50 switches from a digital logic high level to a digital logic low level, which starts disconnection of load 13. From time T11 to time T12, load current 65 decreases until it reaches zero. After time T11, load 13 is disabled and disconnected.

[0041] Fig. 9 is a flow chart of a method 100 according to one novel aspect.

[0042] In the first step (step 101), the load terminals of the latching relay are coupled to the load. When the load remains in the disabled state, the load charges the capacitor via the load terminals. Figure 3 In the example, the latching relay 11 is connected to the load 13 via the load terminal 37. The load 13 is disconnected and the alarm does not sound. The load 13 is powered by the load power supply 15. The latching relay 11 is coupled to the voltage supply 14 via the power supply terminal 33. The latching relay 11 is controlled by the microcontroller 12 via the control terminals 34 and 35. The capacitor 21 supplies power to the local power supply node 63 via the storage terminal 39. Figure 4 As shown, when the local power supply node 63 supplies power to the circuitry of the latching relay, the capacitor 21 begins to discharge.

[0043] In the second step (step 102), the load is switched from the disabled state to the enabled state, causing current to flow from the load power supply, through the load, through the latching relay, and to the other terminal of the latching relay. When the load is in the enabled state, the capacitor powers the latching relay. Figure 5 In the example of FIG. 1 , the microcontroller 12 controls the latching relay 11 to enable the load 13 by driving the set / refresh control signal 49 to a digital logic low level. The NMOS transistor 30 is enabled and turns on the load 13 to sound the alarm. Current flows from the load power supply 15, through the load 13, through the load terminal 37, through the source of the NMOS transistor 30, and to the negative terminal of the load power supply 15 via the return terminal 38.

[0044] In the third step (step 103), the capacitor is charged by pulsing current through the supply terminals of the latching relay. When the load is in the enabled state, the capacitor is charged. Figure 6 In the example of , the microcontroller 12 controls the latching relay 11 to operate in the refresh mode by pulsing the set / refresh control signal 49. The set / refresh control signal 49 is pulsed according to a predetermined duty cycle. The pulsed set / refresh control signal 49 causes current to flow through the LED 40 and causes the LED 40 to radiate energy to the photovoltaic stack 51. A voltage +V is generated across the photovoltaic stack 51, which charges the capacitor 21 via the diode 26 and the storage terminal 39.

[0045] In the fourth step (step 104), the load is switched from the enabled state to the disabled state. For example, the microcontroller 12 controls the latching relay 11 to disable the load 13 by driving the reset signal 50 to a digital logic low level. The NMOS transistor 30 is disabled and the load 13 is disconnected, causing the alarm to stop ringing.

[0046] Fig.10 is a circuit diagram of another configuration of the latching relay 11, in which the load power supply 15 is directly coupled to the load supply terminal 36, thereby avoiding the need for capacitor 21 or for refresh mode operation. When the load power supply is accessible, such as in Fig.10 In the example of FIG. 1 , the load power supply 15 is directly connected to the latching relay 11 and no capacitor is required, e.g. Figure 1 The capacitor 21. Fig.10 In the configuration of FIG. 1 , when the latching relay 11 is latched on, the latching relay 11 does not need to operate in the refresh mode because the local power supply node 63 is powered from the load power supply 15. When the latching relay 11 is latched on, current flows from the load power supply 15 through the load power supply terminal 36 and to the voltage regulator 25 via the diode 27. The voltage regulator 25 in turn supplies power to the local power supply node 63. As long as there is enough energy stored in the load power supply 15 to keep the local power supply node 63 above the minimum operating voltage level, the latching relay 11 will remain enabled and the load 13 will remain on.

[0047] Fig.11 is a circuit diagram of another embodiment of a packaged latching relay 200 , in which a drive transistor 201 is located outside the latching relay. Fig.11 The packaged latching relay 200 has a Figure 1 The latching relay 11 of FIG. 1 is substantially the same structure, except that the drive transistor 201 is located outside the packaged latching relay 200 . In this example, the packaged latching relay 200 includes a drive terminal 202 that drives the gate of the transistor 201 . Fig.11 The packaged latching relay 200 is with Figure 1 The latching relay 11 of the present invention operates in a substantially similar manner, but the packaged latching relay 200 is made smaller and cheaper due to one less transistor disposed within the package. In addition, the packaged latching relay 200 provides flexibility because the packaged latching relay 200 can be configured to drive a variety of drive transistors.

[0048] Although certain specific embodiments are described above for guidance purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. Therefore, various modifications, variations and combinations of the various features of the described embodiments may be practiced without departing from the scope of the invention as set forth in the claims.

Claims

1. A packaged electronic device, comprising: Power supply terminal; Load terminals; A first coupling circuit coupled to the power supply terminal; a second coupling circuit; a first transistor having a first terminal, a second terminal and a third terminal; a second transistor having a first terminal, a second terminal and a third terminal, wherein the third terminal of the first transistor is coupled to the second terminal of the second transistor, and wherein the third terminal of the second transistor is coupled to the second coupling circuit; a third transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the third transistor is coupled to the third terminal of the first transistor, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor, wherein the second terminal of the third transistor is coupled to the load terminal, and wherein the third terminal of the third transistor is coupled to the second coupling circuit; and a latch circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the latch circuit is coupled to the first coupling circuit, wherein the second terminal of the latch circuit is coupled to the second coupling circuit, wherein the third terminal of the latch circuit is coupled to the first terminal of the first transistor via an inverter, wherein the fourth terminal of the latch circuit is coupled to the first terminal of the second transistor, wherein the first coupling circuit is operable to configure the latch circuit such that the conductivity of the first transistor and the second transistor is switched so that current flows through a load coupled to the load terminal, and wherein the second coupling circuit is operable to configure the latch circuit such that the conductivity of the first transistor and the second transistor is switched so that current stops flowing through the load; and a local power supply node that powers the latch circuit, the first coupling circuit, and the second coupling circuit, wherein the second terminal of the first transistor is coupled to the local power supply node, wherein the local power supply node is powered by a capacitor, wherein the packaged electronic device is operable in a refresh mode such that the capacitor is charged when the load is enabled by pulsing current through the first coupling circuit, wherein the packaged electronic device does not include any silicon controlled rectifier (SCR) devices or any mechanical relays.

2. The packaged electronic device according to claim 1, wherein: The latch circuit is coupled to the first coupling circuit via optical coupling, inductive coupling, or capacitive coupling.

3. The packaged electronic device of claim 1 , further comprising: a storage terminal, wherein the packaged electronic device is configurable such that a capacitor is coupled to the storage terminal; a first diode having a first terminal and a second terminal, wherein the first terminal of the first diode is coupled to the first coupling circuit, and wherein the second terminal of the first diode is coupled to the reservoir terminal; a second diode having a first terminal and a second terminal, wherein the first terminal of the second diode is coupled to the load terminal; and A regulator circuit having a first terminal, a second terminal and a third terminal, wherein the first terminal of the regulator circuit is coupled to the storage terminal, wherein the first terminal of the regulator circuit is coupled to the second terminal of the first diode, wherein the second terminal of the regulator circuit is coupled to the second terminal of the second diode, and wherein the third terminal of the regulator circuit is coupled to a ground terminal of the packaged electronic device.

4. The packaged electronic device according to claim 1, wherein: The packaged electronic device is a packaged optically isolated latching relay, and wherein the power supply terminal and the load terminal are packaged terminals of the packaged optically isolated latching relay.

5. The packaged electronic device according to claim 1, wherein: The first coupling circuit comprises: a light emitting diode having a first terminal and a second terminal, wherein the first terminal of the light emitting diode is coupled to the power supply terminal, and wherein the second terminal of the light emitting diode is coupled to a control terminal of the packaged electronic device; and Photovoltaic stack and photodiode circuits.

6. The packaged electronic device according to claim 1, wherein: The second coupling circuit comprises: a light emitting diode having a first terminal and a second terminal, wherein the first terminal of the light emitting diode is coupled to the power supply terminal, and wherein the second terminal of the light emitting diode is coupled to a control terminal of the packaged electronic device; and Photodiode circuit.

7. A method for operating a latching relay, the latching relay not including any silicon controlled rectifier (SCR) device or any mechanical relay, the method comprising: (a) coupling a load terminal of the latching relay to a load, wherein the load is powered by a load power supply, wherein the load power supply charges a capacitor through the load via the load terminal, and wherein the capacitor is charged via the load terminal when the load is maintained in a disabled state; (b) switching the load from the disabled state to an enabled state so that current flows from the load power supply, through the load, through the latching relay, and to another terminal of the latching relay, wherein the capacitor powers the latching relay when the load is in the enabled state; (c) charging the capacitor by pulsing current through power supply terminals of the latching relay, wherein the capacitor is charged when the load is in the enabled state; and (d) switching the load from the enabled state to the disabled state.

8. The method according to claim 7, wherein: The switching of the load in (b) occurs in response to a first signal switching from a first digital logic level to a second digital logic level, wherein the first signal is present at a first terminal of the latching relay, and the switching of the load in (d) occurs in response to a second signal switching from a first digital logic level to a second digital logic level, and wherein the second signal is present at a second terminal of the latching relay.

9. The method according to claim 7, wherein: The switching of (b) involves switching the first transistor from the first conductive state to the second conductive state and switching the second transistor from the second conductive state to the first conductive state, and wherein the switching of (d) involves switching the first transistor from the second conductive state to the first conductive state and switching the second transistor from the first conductive state to the second conductive state.

10. The method according to claim 7, wherein: Charging the capacitor in (c) involves pulsing current through a coupling circuit of the latching relay so that current flows from a power supply terminal of the latching relay through a light emitting diode of the coupling circuit and to a control terminal of the latching relay.

11. The method according to claim 7, wherein: The charging of the capacitor in (c) is a refresh mode of the latching relay, and wherein the switching of (b), the charging of (c), and the switching of (d) are controlled by external signaling generated outside the latching relay.

12. The method according to claim 7, wherein: The latching relay is an optically isolated latching solid-state relay.

13. The method according to claim 7, wherein: The switching of (b), the charging of (c) and the switching of (d) do not involve any mechanical relays.

14. The method according to claim 7, wherein: The capacitor is external to the latching relay.

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