Voltage clamping circuit, device and system for testing dynamic resistance of wide bandgap semiconductor switching devices

Abstract

The present invention discloses a voltage clamping circuit for testing the dynamic resistance of a wide bandgap semiconductor switching device, including: a high-voltage blocking subcircuit, a voltage stabilizing subcircuit, an anti-oscillation subcircuit, a filtering subcircuit and an FPGA main control circuit, which has the characteristics of low measurement delay. The present invention also discloses a controllable test condition device for testing the dynamic resistance of a gallium nitride HEMT, including a voltage clamping circuit, a voltage stress control circuit, a current control circuit, a switch mode control circuit, and a package temperature control circuit for testing the dynamic resistance of a gallium nitride HEMT. Under the premise of greatly reducing the detection delay, various factors in the detection process can also be controlled to provide a guarantee for the accuracy of detecting the dynamic resistance. The present invention also discloses a test system for testing the dynamic resistance of a gallium nitride HEMT, which can restore the real application environment for detecting the dynamic resistance, thereby completing the accurate observation of the dynamic resistance.

Description

Technical Field

[0001] The present invention belongs to the technical field of dynamic resistance detection of wide bandgap semiconductors, and in particular relates to a voltage clamping circuit, a device and a system for testing the dynamic resistance of a wide bandgap semiconductor switch device. Background Art

[0002] Wide bandgap semiconductor gallium nitride HEMT, known as the third-generation semiconductor material, such as gallium nitride HEMT (gallium nitride high electron mobility switch), is a new type of semiconductor gallium nitride HEMT. Since it performs better than traditional silicon gallium nitride HEMT in designing high-efficiency power switching converters, it has broad application prospects in the field of power electronics.

[0003] However, during the use of GaN HEMT, there are factors that cause its performance degradation, specifically, the change in the dynamic resistance of GaN HEMT is one of the reasons for its performance degradation. Since GaN HEMT needs to withstand high voltage stress in the off state, the electrons of GaN HEMT are trapped in the interface, dielectric layer and buffer layer. Therefore, during the period of time when GaN HEMT starts to turn on, its on-resistance is observed to be significantly higher than the on-resistance in the stable state. As the high voltage stress of GaN HEMT in the on state is released, the trapped electrons in GaN HEMT are released, and the on-resistance gradually decreases until it no longer changes. In the above process, the change in dynamic resistance of GaN HEMT will cause an increase in its switching loss in practical applications, and even damage the GaN HEMT. Therefore, the detection of dynamic resistance is crucial for the design and application of GaN HEMT.

[0004] In the current related technology, the commonly used dynamic resistance test method is: use an oscilloscope to obtain the drain-source voltage and drain-source current of the GaN HEMT, and then use Ohm's law to calculate the on-resistance of the GaN HEMT. However, when the GaN HEMT is in the off state, the drain-source voltage is usually as high as hundreds of volts, while when it is in the on state, the drain-source voltage of the GaN HEMT is usually as low as less than 1V. However, the quantization accuracy of a digital oscilloscope is generally only 8 bits. If the maximum voltage range is divided into 2 8=256 parts, assuming that the voltage in the off state is 400V, the measurement accuracy is 400 / 256=1.56V. Then, if the voltage test range requirements in the off state are met, the accuracy requirements of the voltage test in the on state cannot be met. Therefore, it is necessary to clamp the high voltage in the off state near the drain-source voltage drop in the on state to ensure the voltage measurement accuracy requirements in the on state. In this way, it is necessary to introduce a voltage clamping circuit, but when the voltage clamping circuit is introduced, the measurement delay caused by the characteristics of the gallium nitride HEMT will also be introduced. Therefore, it is difficult to detect the dynamic resistance change of the gallium nitride HEMT to be tested during the instant of turning on, and the detection delay is long, which is not conducive to observing the dynamic resistance phenomenon.

[0005] In addition, existing test methods or equipment lack control devices that can quantitatively control test conditions such as voltage stress, voltage stress time, package temperature, stress current, switching mode, etc. that may cause dynamic resistance changes.

[0006] Furthermore, existing testing methods or equipment mostly use the traditional double-pulse detection method, which cannot fully and truly restore the actual application conditions of GaN HEMT in the circuit.

[0007] Therefore, shortening the detection delay, quantitatively controlling the test conditions that affect the dynamic resistance, and the actual application conditions of the real reduced GaN HEMT are technical challenges that need to be overcome in the dynamic resistance detection of GaN HEMT. Summary of the invention

[0008] In order to solve the above-mentioned problem of long detection delay, a first object of the present invention is to provide a voltage clamping circuit for testing the dynamic resistance of a wide bandgap semiconductor switching device, which has the characteristic of low measurement delay.

[0009] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0010] The voltage clamping circuit for testing a wide bandgap semiconductor according to the present invention comprises:

[0011] A high-voltage blocking subcircuit, connected in series with the GaN HEMT to be tested, for blocking the drain-source voltage of the GaN HEMT to be tested in an off state;

[0012] A voltage stabilizing subcircuit, connected in series with the high-voltage blocking subcircuit, for eliminating spikes in the clamping voltage during switching transients;

[0013] an anti-oscillation subcircuit, connected in parallel with the voltage stabilization subcircuit, for limiting the clamping voltage oscillation caused by switching noise;

[0014] A filtering subcircuit, connected in parallel with the voltage stabilizing subcircuit, for filtering out high-frequency noise generated by the entire circuit during the switching process;

[0015] The FPGA main control circuit is connected to the high-voltage blocking subcircuit, and outputs a driving signal with a preset accuracy to increase the switching time of the high-voltage blocking subcircuit, thereby reducing the delay in the measurement process. At the same time, the passband cutoff frequency is set near the rising edge frequency through the filtering subcircuit to suppress harmonics in the switching transient process, and the anti-oscillation subcircuit suppresses the occurrence of clamping voltage spikes, so as to achieve the drain-source voltage clamping of the dynamic resistance of the gallium nitride HEMT within a predetermined range in a short time. .

[0016] Furthermore, the high-voltage blocking sub-circuit is specifically a gallium nitride high-speed switch tube, and its gate is driven by a switch tube driving chip and a gate driving resistor.

[0017] Furthermore, the anti-oscillation sub-circuit specifically includes a first Schottky diode, a second Schottky diode, a third Schottky diode and a fourth Schottky diode; the first Schottky diode and the second Schottky diode are connected in series in the same direction to form a first branch; the third Schottky diode and the fourth Schottky diode are connected in series in the same direction to form a second branch; the first sub-path is connected in reverse parallel with the second branch.

[0018] Furthermore, the voltage stabilizing subcircuit includes a voltage stabilizing tube and a resistor connected in series.

[0019] In order to solve the above-mentioned problem of lack of controllable various influencing factors occurring during the detection process, the second object of the present invention is to provide a controllable test condition device for testing the dynamic resistance of a wide bandgap semiconductor switching device. On the premise of greatly reducing the detection delay, the voltage stress magnitude and time, package temperature, stress current and switching mode in the process of detecting gallium nitride HEMT can be controlled, thereby providing a guarantee for the accuracy of detecting the dynamic resistance.

[0020] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0021] The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to the present invention comprises:

[0022] A voltage clamping circuit for testing the dynamic resistance of a GaN HEMT, connected in parallel between the source and drain of the GaN HEMT to be tested, and used to clamp the drain-source voltage of the GaN HEMT to be tested in a turned-off state within a predetermined range in a short time;

[0023] The voltage stress control circuit is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used to control the magnitude and application time of the voltage stress;

[0024] The current control circuit is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used to control the magnitude of the current stress;

[0025] The switch mode control circuit is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used to switch between the soft and hard switch modes;

[0026] The package temperature control circuit is connected to the gate of the GaN HEMT to be tested, and is used to detect and control the package surface temperature of the GaN HEMT to be tested;

[0027] Under the action of the FPGA main control circuit, the voltage stress control resistor controls the voltage through a programmable high-voltage DC source, and controls the stress time through its internal half-bridge subcircuit, so as to provide the desired voltage stress condition for the GaN HEMT to be tested; the current control circuit adjusts the current stress through the switch tube, and after the current stress reaches the expected value, the current stress is connected by opening the control switch tube; the switch mode control circuit controls the on and off of two electronic switches to select whether to connect the resonant inductor, so as to realize the ZVS zero voltage soft-opening mode for the GaN HEMT to be tested; the package temperature control circuit detects the surface temperature of the GaN HEMT to be tested through a thermocouple, and feeds back to the heater, so as to realize the control of the test package temperature.

[0028] Furthermore, the voltage stress control circuit includes a high-voltage DC source, an electrolytic capacitor C1C2, a first switch tube and a second switch tube; the electrolytic capacitor is connected in parallel with the high-voltage DC source; the first switch tube and the second switch tube are connected in series to form a half-bridge structure, and are connected in parallel with the high-voltage DC source.

[0029] Furthermore, the current control circuit includes a power inductor, a discharge diode, a discharge resistor, a discharge capacitor, an adjustment tube, a third switch tube, a fourth switch tube and an anti-backflow diode; the power inductor is connected to the drain of the switch tube in the voltage stress control circuit through a diode; the discharge resistor is connected in parallel with the discharge capacitor and then in series with the discharge diode, and is connected in parallel with the power inductor, and then in series with the adjustment tube to ground; the switch tube is connected in parallel with the power inductor; the anti-backflow diode is connected in series with the switch tube and then in parallel with the adjustment tube.

[0030] Furthermore, the switch mode control circuit includes a first electronic switch, a second electronic switch, an inductor, a diode and a fifth switch tube; the second electronic switch is connected in series with the diode and the fifth switch tube; the diode is connected in parallel with the fifth switch tube; the diode is connected in series with the first electronic switch and the inductor, and then connected in reverse to the diode.

[0031] Furthermore, the package temperature detection circuit includes a thermocouple and a heating device connected in series; and the current detection circuit is a current shunt.

[0032] In order to solve the above-mentioned problem that the actual application conditions of GaN HEMT cannot be truly restored, the third purpose of the present invention is to provide a test system for testing the dynamic resistance of wide bandgap semiconductor switching devices, which can restore the real application environment for detecting dynamic resistance, thereby completing the accurate observation of dynamic resistance.

[0033] To achieve the above object, the present invention is implemented according to the following technical solutions:

[0034] The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to the present invention comprises:

[0035] A test condition controllable device for testing the dynamic resistance of gallium nitride HEMT, which is used to effectively control the test conditions of the dynamic resistance of gallium nitride HEMT;

[0036] A DC power supply, which provides a DC source for testing the test condition controllable device;

[0037] Oscilloscope, collects drain-source voltage and drain-source current, and transmits voltage and current data;

[0038] The host computer programs the FPGA main control circuit, the DC power supply circuit, and the oscilloscope to determine their respective working states, receive data, complete data processing, and obtain the test results of the dynamic resistance of the GaN HEMT to be tested.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The voltage clamping circuit for testing the dynamic resistance of a wide bandgap semiconductor switch device of the present invention outputs a high-precision driving signal through the FPGA main control circuit, so that the high-voltage blocking subcircuit completes the switching with low measurement delay, thereby blocking the drain-source voltage of the GaN HEMT to be tested in the off state, and limiting various noises in the switching process through the filtering subcircuit and the anti-oscillation subcircuit, thereby achieving the goal of clamping the drain-source voltage of the dynamic resistance of the GaN HEMT within a predetermined range in a short time, so as to facilitate the subsequent observation of the dynamic resistance.

[0041] The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switching device described in the present invention is based on the above-mentioned voltage clamping circuit for testing the dynamic resistance of gallium nitride, and integrates other circuits, namely, the voltage stress control circuit controls the magnitude and application time of voltage stress, the current control circuit controls the magnitude of current stress, the switch mode control circuit is used to switch between soft and hard switch modes, and the package temperature control circuit detects and controls the package surface temperature of the gallium nitride HEMT to be tested, thereby solving the influence of voltage stress magnitude, time, package temperature, stress current, and switch mode on the dynamic resistance change during the observation process, and further realizing the subsequent accurate observation of the dynamic resistance.

[0042] The test system for testing the dynamic resistance of a wide bandgap semiconductor switch device of the present invention is based on the above-mentioned controllable test condition device for testing the dynamic resistance of a gallium nitride HEMT, and integrates a DC power supply, an oscilloscope and a host computer. In the actual process, the test personnel program the FPGA main control circuit, the DC power supply and the oscilloscope through the host computer to determine their respective working states, receive data, complete data processing, and accurately obtain the test result of the dynamic resistance of the gallium nitride HEMT to be tested, so as to better and widely apply the gallium nitride HEMT in the field of power electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The specific embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings, wherein:

[0044] Figure 1 It is a circuit principle diagram of a voltage clamping circuit for testing the dynamic resistance of a wide bandgap semiconductor switching device according to the present invention;

[0045] Figure 2 It is a circuit schematic diagram of a test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to the present invention;

[0046] Figure 3 The invention is a circuit principle block diagram of a test system for testing the dynamic resistance of a wide bandgap semiconductor switch device.

[0047] In the figure:

[0048] 1: Voltage clamp circuit

[0049] 11: High voltage blocking subcircuit 12: Voltage stabilization subcircuit 13: Anti-oscillation subcircuit

[0050] 14: Filter subcircuit 15: FPGA main control circuit

[0051] 2: Test condition controllable device

[0052] 21: Voltage stress control circuit 22: Current control circuit 23: Switch mode control circuit

[0053] 24: Package temperature control circuit

[0054] 3: DC power supply 4: Host computer 5: Oscilloscope DETAILED DESCRIPTION

[0055] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0056] In the prior art, a voltage clamp circuit is introduced to ensure the voltage measurement accuracy in the on state. However, after adding the voltage clamp circuit, the parasitic capacitance of the voltage clamp circuit will form an RC delay problem with the resistor, so the voltage signal at both ends of the drain and source of the device under test cannot be detected at the clamp point at the moment when the device under test is turned on, resulting in a detection delay of about 200us; and due to the limitation of the response speed of passive devices (such as the reverse recovery time of the clamp diode), the measurement delay problem will also occur; the purpose of the present invention is to reduce the measurement delay problem caused by the above reasons. The method adopted is an active switch clamp method.

[0057] The so-called active means that the clamp circuit no longer uses uncontrollable devices, but uses fully controllable GaN HEMT devices, and its on-off is no longer controlled by the change of drain-source voltage, but by the driving chip controlled by FPGA. The advantage of this is that the actively controlled GaN HEMT has an extremely fast switching speed (the switching action can be completed within 10ns), so the delay problem of drain-source voltage measurement mentioned above will be improved and optimized. The on-off characteristics of the high-voltage blocking sub-circuit are fast switching speed, and its timing is precisely controlled by the FPGA chip.

[0058] like Figure 1 As shown, the voltage clamping circuit 1 for testing the dynamic resistance of a wide bandgap semiconductor switch device according to the present invention comprises a high voltage blocking subcircuit 11, a voltage stabilizing subcircuit 12, an anti-oscillation subcircuit 13, a filtering subcircuit 14 and an FPGA main control circuit 15. The gate of the high voltage blocking subcircuit 11 is connected to the FPGA main control circuit 15, the drain is connected in series with the GaN HEMT to be tested, the source is connected in series with the voltage stabilizing subcircuit 12, and the anti-oscillation subcircuit 13 and the filtering subcircuit 14 are connected in parallel with the voltage stabilizing subcircuit 12 respectively.

[0059] Specifically, the FPGA main control circuit 15 controls the high-voltage blocking subcircuit 11 to complete the low-measurement delay on and off by outputting a preset high-precision drive signal. The FPGA main control circuit 15 uses a Xilinx ZYNQ-7000 series FPGA chip, which can be programmed to output a high-precision drive signal, and the internal hardware delay accuracy can reach the picosecond level. Compared with the passive control method of switching the switch tube on and off, the strict and precise timing control method has the advantage of low measurement delay.

[0060] The high-voltage blocking subcircuit 11 is used to block the drain-source voltage of the GaN HEMT to be tested in the off state; specifically, it is the GaN HEMT switch tube Q2. It should be noted that the switch tube driver chip and gate driver resistor connected between the gate of the voltage blocking subcircuit 11 and the FPGA main control circuit 15 are used to improve the driving capability and adjust the rising and falling edge time of the switch tube. The driver chip of the high-voltage blocking subcircuit 11 is powered by an independent DC source, and its reference potential is not ground, but the clamping voltage value. When the GaN HEMT to be tested switches between the off state and the on state, the slew rate will reach 100V / ns or even higher. Due to the parasitic capacitance of the high-voltage blocking subcircuit 11, the voltage of the clamping circuit will have severe voltage spikes and oscillations. To address this problem, the switch tube selected for the voltage blocking subcircuit 11 here should meet two requirements. First, its breakdown voltage value should be higher than the breakdown voltage of the GaN HEMT to be tested to prevent the GaN HEMT from being broken down and damaging the clamping circuit. Second, its parasitic capacitance should be as low as possible to avoid excessive clamping voltage spikes and oscillations during the switching transient process. Comprehensive considerations should be made to select GaN HEMT, whose parasitic capacitance is much smaller than that of the same silicon GaN HEMT. Test points 8 and 11 are the collection points of the clamping voltage. Therefore, the dynamic resistance calculated from the clamping voltage includes the influence of the resistance caused by the leakage current of the high-voltage blocking switch tube. The advantage of selecting GaN HEMT is that its on-resistance is smaller than that of the silicon GaN HEMT of the same magnitude, resulting in a small dynamic resistance measurement offset.

[0061] The voltage stabilizing subcircuit 12 is used to eliminate the peak of the clamping voltage during the switching transient process, and specifically includes a voltage stabilizing tube ZD1 and a resistor R3, which are connected in series and connected between the high-voltage blocking subcircuit 11 and the reference ground. It specifically adopts the series connection of the voltage stabilizing tube ZD1 and the low-resistance resistor R3 to achieve the purpose of voltage stabilization. The breakdown voltage of the voltage stabilizing tube ZD1 is a preset clamping voltage value, and the magnitude of the clamping voltage is related to the measurement accuracy of the on-drain-source voltage of the gallium nitride HEMT to be measured. Therefore, the value of the clamping voltage should not be too large to avoid a reduction in measurement accuracy. However, the value of the clamping voltage should not be lower than the on-drain-source voltage of the gallium nitride HEMT to be measured. If the value of the clamping voltage is lower than the on-drain-source voltage of the gallium nitride HEMT to be measured, it is judged that over-clamping occurs. At this time, the detection voltage is always clamped at the preset clamping voltage value, and the on-drain-source voltage of the gallium nitride HEMT to be measured cannot be observed.

[0062] The anti-oscillation sub-circuit 13 is connected in parallel with the voltage stabilization sub-circuit 12, and is used to limit the clamping voltage oscillation caused by switching noise. It is specifically an anti-parallel Schottky diode circuit, including a first Schottky diode D1, a second Schottky diode D2, a third Schottky diode D3 and a fourth Schottky diode D4; the first Schottky diode D1 and the second Schottky diode D2 are connected in series in the same direction to form a first branch; the third Schottky diode D3 and the fourth Schottky diode D4 are connected in series in the same direction to form a second branch; the first sub-path is connected in anti-parallel with the second branch.

[0063] The above parallel structure is connected between nodes 11 and 12; since the parasitic capacitance of the voltage regulator ZD1 is large and there is a certain reverse recovery time. For this reason, the above zero reverse recovery SiC Schottky diode series-first-parallel structure is introduced to reduce the parasitic capacitance and the influence of the reverse recovery time on the detection delay, thereby suppressing the occurrence of the clamping voltage spike. The sum of the Schottky diode voltage drops of the anti-oscillation subcircuit 13 is consistent with the voltage drop of the voltage regulator subcircuit 12. If oscillation occurs at the detection point of the clamping voltage, one of the reverse parallel diode groups will always be in the on state, which can limit the range of the oscillating voltage to the vicinity of the forward voltage drop of the diode, thereby suppressing the oscillation of the clamping voltage and ensuring that the measurement accuracy will not be affected by over-range when observed by an oscilloscope later. The conduction voltage drop of the Schottky diode of the anti-oscillation subcircuit 12 should be basically consistent with the stable voltage of the voltage regulator ZD1, so it is not limited to the two shown in the figure; as shown in the figure, the anti-oscillation subcircuit 13 can also suppress the occurrence of the clamping voltage spike.

[0064] The filtering subcircuit 14 is specifically an RC low-pass filtering structure, that is, it is composed of a resistor R2 and a capacitor C1 connected in series. By selecting the parameter values ​​of the resistor and the capacitor, the passband cutoff frequency is set to be slightly higher than the switching rising edge frequency to limit the impact of high-frequency noise on the measurement, thereby filtering out the high-frequency noise generated by the entire circuit during the switching process, because the harmonics generated during the switching transient process will cause the clamping voltage to oscillate, thereby introducing measurement noise and increasing the measurement delay.

[0065] The above is a specific structural description of the voltage clamping circuit for testing the dynamic resistance of GaN HEMT according to the present invention. The working principle thereof is as follows:

[0066] When the GaN HEMT to be tested is in the off state, the high-voltage blocking sub-circuit 11 is also in the off state, and its driving signal and the driving signal of the GaN HEMT to be tested are both time-controlled by the FPGA main control circuit 15. In order to prevent the clamping circuit from being damaged by the high voltage, the high-voltage blocking sub-circuit 11 should be turned on after the GaN HEMT to be tested is fully turned on, and the GaN HEMT to be tested should be turned on after the high-voltage blocking sub-circuit 11 is turned off.

[0067] The drive signal is generated by Xilinx ZYNQ-7000 series FPGA chip, which can be programmed to output high-precision drive signals, and can reach picosecond level through internal physical delay. Compared with the passive control method of switching tube on and off, the strict and accurate timing control method has the advantage of low measurement delay.

[0068] At the same time, since the turn-on rising edge time of the GaN HEMT to be tested does not exceed 20ns, after the GaN HEMT to be tested is fully turned on, the voltage blocking sub-circuit 11 will be turned on immediately, and the turn-on rising edge time of the high-voltage blocking sub-circuit 11 does not exceed 20ns. In addition, the oscillation time introduced by the switching waveform is 10ns, so the overall test delay is about 50ns.

[0069] Therefore, it can be seen very intuitively that the voltage clamping circuit for testing the dynamic resistance of the gallium nitride HEMT described in the present invention can greatly reduce the delay problem caused by introducing the voltage clamping circuit in the detection process.

[0070] like Figure 2As shown, the test condition quantitative controllable device 2 includes a voltage clamping circuit 1, a voltage stress control circuit 21, a current control circuit 22, a switch mode control circuit 23 and a package temperature control circuit 24. Under the action of the FPGA main control circuit 15 in the voltage clamping circuit 1, the voltage stress control circuit 21 controls the voltage through a programmable high-voltage DC source, and controls the stress time through its internal half-bridge sub-circuit, so as to provide the desired voltage stress condition for the GaN HEMT to be tested; the current control circuit adjusts the current stress through the switch tube, and after the current stress reaches the expected value, the current stress is connected by opening the control switch tube; the switch mode control circuit selects whether to connect the resonant inductor by controlling the on and off of two electronic switches, so as to realize the ZVS zero voltage soft-opening mode for the GaN HEMT to be tested; the package temperature control circuit detects the surface temperature of the GaN HEMT to be tested through a thermocouple, and feeds back to the heater to realize the control of the test package temperature.

[0071] The voltage clamping circuit 1 is connected in parallel between the source and drain of the GaN HEMT to be tested, and is used to clamp the drain-source voltage of the GaN HEMT to be tested in the off state within a predetermined range in a short time, that is, to clamp the high voltage in the off state to the vicinity of the drain-source voltage drop in the on state, so as to ensure the voltage measurement accuracy requirement in the on state;

[0072] The voltage stress control circuit includes a high-voltage direct current source DC, a first electrolytic capacitor C2, a second electrolytic capacitor C3, a first switch tube Q3 and a second switch tube Q4; the first electrolytic capacitor C2 and the second electrolytic capacitor C3 are respectively connected in parallel with the high-voltage direct current source DC; the first switch tube Q3 and the second switch tube Q4 are connected in series to form a half-bridge structure, and are connected in parallel with the high-voltage direct current source DC.

[0073] When the first switch tube Q3 is in the on state and the second switch tube Q4 is in the off state, the gallium nitride HEMT to be tested is subjected to high voltage stress, and when the first switch tube Q3 is in the off state and the second switch tube Q4 is in the on state, the gallium nitride HEMT to be tested is short-circuited to the ground. The voltage stress control circuit 21 controls the voltage stress time by controlling the first switch tube Q3 and the second switch tube Q4, and controls the voltage stress magnitude by controlling the output voltage of the high voltage DC source 32.

[0074] The current control circuit includes a power inductor L1, a discharge diode D6, a discharge resistor R4, a discharge capacitor C4, an adjustment tube Q7, a third switch tube Q5, a fourth switch tube Q6 and an anti-backflow diode D7; the power inductor L1 is connected to the drain of the first switch tube Q3 in the voltage stress control circuit through the diode D5; the discharge resistor R4 is connected in parallel with the discharge capacitor C4 and then connected in series with the discharge diode D6, and connected in parallel with the power inductor L1, and then connected in series with the adjustment tube Q7 to ground; the third switch tube Q5 is connected in parallel with the power inductor L1; the anti-backflow diode D7 is connected in series with the fourth switch tube Q6 and then connected in parallel with the adjustment tube Q7.

[0075] The third switch tube Q5 is first in a closed state, and at the same time, the reverse current of the voltage stress circuit 21 is isolated by the anti-backflow diode D7. The current of the power inductor L1 is controlled by controlling the on-off of the adjustment tube Q7. The adjustment tube Q7 is turned on, the power inductor L1 is charged, and the current increases. The adjustment tube Q7 is turned off, and the inductor current is reduced through the discharge circuit. In this way, the inductor current can be controlled to be in an approximately constant current mode. The magnitude of the current ripple is controlled by the parameters of the discharge circuit and the switching frequency of the adjustment tube Q7. When the inductor current reaches a preset value, the third switch tube Q5 is turned on, and the current stress is applied to the gallium nitride HEMT0 to be tested. At this time, the first switch tube Q3 and the second switch tube Q4 in the voltage stress control circuit 21 are both in the off state.

[0076] The switch mode control circuit 23 includes a first electronic switch S1, a second electronic switch S2, a resonant inductor L2, a first diode D8, a second diode D9, a third diode D10 and a fifth switch tube Q8; the second electronic switch S2 is connected in series with the first diode D8 and the fifth switch tube Q8; the third diode D10 is connected in parallel with the fifth switch tube Q8; the second diode D9 is connected in series with the first electronic switch S1 and the resonant inductor L2, and is reversely connected to the third diode D10.

[0077] When the electron tubes S1 and S2 are disconnected, the switch mode control circuit 23 is not connected to the current control circuit 22. At this time, the test circuit operates in a hard switch state where the voltage and current overlap. When the electronic switches S1 and S2 are closed, the resonant inductor L2 can be charged by controlling the on and off of the fifth switch tube Q8. The resonant inductor L2 here is much smaller than the power inductor L1, and the inductor current will reach the same current size as the power inductor L1 in a very short time. At this time, turn off the fifth switch tube Q8, and the resonant inductor L2 will pump the drain voltage of the gallium nitride HEMT to be tested to zero potential, realizing the ZVS (Zero Voltage Switching) soft-open mode.

[0078] The package temperature detection circuit 24 is a thermocouple 33, which detects the surface temperature of the GaN HEMT to be tested through the thermocouple 33 and feeds back to the heating device (hot air gun) to achieve the control of the test package temperature. Specifically, it is used to evaluate the influence of the surface temperature change of the GaN HEMT to be tested on the dynamic resistance of the GaN HEMT. The GaN HEMT to be tested is heated by a hot air gun until the temperature is stable before testing. The thermocouple 33 detects the package surface temperature of the GaN HEMT0 to be tested, and the temperature data is fed back to the FPGA main control circuit 15 for processing.

[0079] In order to enable the test device to repeat the pulse test, the test condition controllable device for testing the dynamic resistance of the gallium nitride HEMT further includes a current detection circuit 25, specifically a current shunt.

[0080] Because in most cases, the bandwidth of the sense resistor or shunt is limited by the corner frequency between the resistor and the parasitic series inductance. For a given series inductance, the bandwidth can be improved by increasing the value of the sense resistor, but this is at the expense of increased voltage drop and power consumption. Compared with the sense resistor, the main advantage of the coaxial shunt is that it reduces the parasitic inductance between the measurement nodes and increases the measurement bandwidth. The current shunt increases the accuracy of current sampling, and the smaller parasitic inductance reduces the voltage oscillation between the measurement nodes. The design of the inductor current discharge circuit and the test device can work in repetitive pulse tests to restore the real application environment.

[0081] Furthermore, if Figure 3 As shown, the present invention also proposes a GaN HEMT dynamic resistance test system solution, including a test condition controllable device 2 for testing the GaN HEMT dynamic resistance, a DC power supply 3, a host computer 4 and an oscilloscope 5.

[0082] The FPGA main control circuit 15 in the controllable test condition device 2 for testing the dynamic resistance of gallium nitride HEMT generates a control pulse control to enhance the driving capability, adjust the driving speed, and match the driving voltage, and adjusts the voltage stress magnitude and voltage stress time through the voltage stress control circuit 21, the current magnitude of the current control circuit 22, the switching mode of the switch mode control circuit 23, and the packaging temperature of the package temperature control circuit 24; the voltage clamping circuit 1 for testing the dynamic resistance of gallium nitride HEMT clamps the off-state drain-source voltage of the gallium nitride HEMT to be tested within a predetermined range; the DC power supply 3 provides the DC source required for the test; the oscilloscope 5 collects the drain-source voltage and the drain-source current, and transmits the voltage and current data to the host computer 4; the host computer 4 program-controls the FPGA main control circuit 15, the DC power supply 3, and the oscilloscope 5, determines their respective working states, receives data, completes data processing, and obtains the dynamic resistance test result.

[0083] The other structures of the voltage clamping circuit, the test condition controllable device and the test system for testing the dynamic resistance of the gallium nitride HEMT described in the present invention refer to the prior art and are not described in detail here.

[0084] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Therefore, any modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switching device, characterized in that: include: A voltage clamping circuit for testing the dynamic resistance of a GaN HEMT, wherein the voltage clamping circuit is connected in parallel between the source and drain of the GaN HEMT to be tested, and is used to clamp the drain-source voltage of the GaN HEMT to be tested in an off state within a predetermined range in a short time; The voltage clamping circuit includes: a high-voltage blocking subcircuit connected in series with the GaN HEMT to be tested, used to block the drain-source voltage of the GaN HEMT to be tested in the off state; a voltage stabilizing subcircuit connected in series with the high-voltage blocking subcircuit, used to eliminate the spike of the clamping voltage during the switching transient process; an anti-oscillation subcircuit connected in parallel with the voltage stabilizing subcircuit, used to limit the clamping voltage oscillation caused by the switching noise; a filtering subcircuit connected in parallel with the voltage stabilizing subcircuit, used to filter out the high-frequency noise generated by the entire circuit during the switching process; an FPGA main control circuit connected to the high-voltage blocking subcircuit, outputting a driving signal with a preset accuracy to increase the switching time of the high-voltage blocking subcircuit, thereby reducing the delay in the measurement process, and at the same time setting the passband cutoff frequency near the rising edge frequency through the filtering subcircuit to suppress the harmonics in the switching transient process, and the anti-oscillation subcircuit suppresses the occurrence of the clamping voltage spike, so as to achieve the drain-source voltage clamping of the dynamic resistance of the GaN HEMT within a predetermined range in a short time; It also includes a voltage stress control circuit, which is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used to control the magnitude and application time of the voltage stress; A current control circuit is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used to control the magnitude of the current stress; A switch mode control circuit is connected in parallel between the drain of the GaN HEMT to be tested and the reference ground, and is used for switching between soft and hard switch modes; A package temperature control circuit is connected to the gate of the GaN HEMT to be tested and is used to detect and control the package surface temperature of the GaN HEMT to be tested; Under the action of the FPGA main control circuit, the voltage stress control circuit controls the voltage through a programmable high-voltage DC source, and controls the stress time through its internal half-bridge subcircuit, so as to provide the desired voltage stress condition for the GaN HEMT to be tested; the current control circuit adjusts the current stress through the switch tube, and after the current stress reaches the expected value, the current stress is connected by opening the control switch tube; the switch mode control circuit controls the on and off of two electronic switches to select whether to connect the resonant inductor, so as to realize the ZVS zero voltage soft-opening mode for the GaN HEMT to be tested; the package temperature control circuit detects the surface temperature of the GaN HEMT to be tested through a thermocouple, and feeds back to the heater to realize the control of the test package temperature; The voltage stress control circuit includes a high voltage direct current source DC, a first electrolytic capacitor C2, a second electrolytic capacitor C3, a first switch tube Q3 and a second switch tube Q4; The first electrolytic capacitor C2 and the second electrolytic capacitor C3 are respectively connected in parallel with the high voltage direct current source DC; The first switch tube Q3 and the second switch tube Q4 are connected in series to form a half-bridge structure, and are connected in parallel with the high-voltage DC source DC; the node between the first switch tube Q3 and the second switch tube Q4 is connected to the drain of the GaN HEMT to be tested; The current control circuit includes a power inductor L1, a discharge diode D6, a discharge resistor R4, a discharge capacitor C4, an adjustment tube Q7, a third switch tube Q5, a fourth switch tube Q6 and an anti-backflow diode D7; one end of the power inductor L1 is connected to the cathode of the diode D5, and the anode of the diode D5 is connected to the drain of the first switch tube Q3 in the voltage stress control circuit, thereby realizing the connection between the voltage stress control circuit and the current control circuit; the cathode of the discharge diode D6 is connected to one end of the power inductor L1 and the cathode of the diode D5 and the drain of the third switch tube Q5, and the discharge diode D6 The anode is connected to one end of the capacitor C4 and the resistor R4, the other ends of the capacitor C4 and the resistor R4 are connected to the other end of the power inductor L1, and the source of the third switch tube Q5 is connected to the other end of the power inductor L1; the drain of the adjustment tube Q7 is connected to the source of the third switch tube Q5, and the source of the adjustment tube Q7 is grounded; the source of the fourth switch tube Q6 is connected to the drain of the adjustment tube Q7, and the drain of the fourth switch tube Q6 is connected to the anode of the anti-backflow diode D7; the cathode of the anti-backflow diode D7 is connected to the drain of the second switch tube Q4 in the voltage stress control circuit, so as to realize the connection between the voltage stress control circuit and the current control circuit; The switch mode control circuit includes a first electronic switch S1, a second electronic switch S2, an inductor L2, a first diode D8, a second diode D9, a third diode D10 and a fifth switch tube Q8; one end of the second electronic switch S2 is connected to the cathode of the discharge diode D6 in the current control circuit, so as to realize the connection between the switch mode control circuit and the current control circuit; the other end of the second electronic switch S2 is connected to the cathode of the first diode D8; the anode of the first diode D8 is connected to the drain of the fifth switch tube Q8; the drain of the fifth switch tube Q8 is connected to the cathode of the third diode D10 and the cathode of the second diode D9, and the source of the fifth switch tube Q8 is connected to the anode of the third diode D10 and then grounded; the anode of the second diode D9 is connected to one end of the inductor L2; the other end of the inductor L2 is connected to one end of the first electronic switch S1, and the other end of the first electronic switch S1 is connected to the drain of the gallium nitride HEMT to be tested.

2. The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to claim 1, characterized in that: The high-voltage blocking sub-circuit is specifically a gallium nitride high-speed switch tube Q2, and its gate is driven by a switch tube driving chip and a gate driving resistor.

3. The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to claim 1, characterized in that: The anti-oscillation subcircuit specifically includes a first Schottky diode D1, a second Schottky diode D2, a third Schottky diode D3 and a fourth Schottky diode D4; The first Schottky diode D1 and the second Schottky diode D2 are connected in series in the same direction to form a first branch; The third Schottky diode D3 and the fourth Schottky diode D4 are connected in series in the same direction to form a second branch; The first branch is connected in anti-parallel with the second branch.

4. The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to claim 1, characterized in that: The voltage stabilizing subcircuit includes a voltage stabilizing tube ZD1 and a resistor R3 connected in series.

5. The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switch device according to claim 1, characterized in that: The package temperature control circuit includes a thermocouple and a heating device connected in series; It also includes a current detection circuit, which is a current shunt; the current shunt is connected in series between the source of the gallium nitride HEMT to be tested and the reference ground.

6. A test system for testing the dynamic resistance of a gallium nitride HEMT, characterized in that: include: The test condition controllable device for testing the dynamic resistance of a wide bandgap semiconductor switching device according to any one of claims 1 to 5 is used to effectively control the test conditions of the dynamic resistance of a gallium nitride HEMT; A DC power supply, which provides a DC source for testing the test condition controllable device; Oscilloscope, collects the drain-source voltage and drain-source current of the GaN HEMT to be tested, and transmits the voltage and current data to the host computer; The host computer, FPGA main control circuit, DC power supply, and oscilloscope determine their respective working states, receive data, complete data processing, and obtain the test results of the dynamic resistance of the GaN HEMT to be tested.

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