Semiconductor devices and manufacturing methods thereof

Abstract

A semiconductor device includes: a substrate including a pixel region and an input / output region; a pixel isolation pattern extending through the substrate in the pixel region; a first via disposed on the inner wall of an opening extending through the substrate in the input / output region, wherein the first via includes a first conductive material; an anti-interference pattern disposed on the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material; and a first insulating interlayer disposed on the substrate. The first insulating interlayer covers the first via and the anti-interference pattern, and includes a first portion disposed in the opening and a second portion disposed outside the opening. The first portion includes a recessed upper surface, and the second portion includes a substantially flat upper surface. The device also includes a polishing stop pattern disposed on the first portion of the first insulating interlayer and an insulating pattern disposed on the polishing stop pattern, wherein the insulating pattern fills the remaining portion of the opening, and the insulating pattern includes an upper surface substantially coplanar with the upper surface of the second portion of the first insulating interlayer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0096790, filed on August 20, 2018 with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same, and more specifically, to an image sensor and a method of manufacturing the same. Background Technology

[0004] When forming a CMOS image sensor (CIS), trenches are formed to create via contacts. A metal layer is deposited on the inner walls of the trenches, and an insulating layer is formed to fill the remaining portion of the trenches. Pads are also formed during the via contact formation. As a result, the upper surface of the insulating layer may be uneven due to the pads, potentially requiring a planarization process. Because the trenches are wide and deep, a thick insulating layer may be needed to fill them. Consequently, the planarization process may result in an insulating layer height distribution that depends on the wafer location (e.g., the upper surface of the insulating layer may be uneven). Summary of the Invention

[0005] Exemplary embodiments of the present invention may provide a method for manufacturing a semiconductor device with improved characteristics, and a semiconductor device with improved characteristics.

[0006] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a via comprising a first conductive material on the inner wall of a trench located on a substrate. The method further includes: forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-planar upper surface. The method further includes: forming a polishing stop layer on the first insulating interlayer; forming a second insulating interlayer on the polishing stop layer, wherein the second insulating interlayer fills the remaining portion of the trench; planarizing the second insulating interlayer until the polishing stop layer is exposed; and etching the polishing stop layer, the first insulating interlayer, and the second insulating interlayer using a dry etching process until the remaining portion of the polishing stop layer, except for the portion of the polishing stop layer located within the trench, is removed.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an opening through a substrate in an input / output region, wherein the substrate includes a pixel region and the input / output region; forming a via on an inner wall of the opening; forming an anti-interference pattern on an upper surface of the substrate in the pixel region; and forming a first insulating interlayer on the substrate, wherein the first insulating interlayer covers the via and the anti-interference pattern. The method further includes: forming a polishing stop layer on the first insulating interlayer; forming a second insulating interlayer on the polishing stop layer, wherein the second insulating interlayer fills the remainder of the opening; planarizing the second insulating interlayer until the polishing stop layer is exposed; and etching the polishing stop layer, the first insulating interlayer, and the second insulating interlayer using a dry etching process.

[0008] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a pixel isolation pattern through a substrate in a pixel region, wherein the substrate includes the pixel region, an input / output region, a first surface, and a second surface disposed opposite to the first surface. The method further includes: forming a first insulating interlayer on the first surface of the substrate, wherein the first insulating interlayer includes a plurality of wiring structures; forming an opening through the substrate in the input / output region, wherein the opening exposes at least one wiring structure; forming a via on the sidewall of the exposed at least one wiring structure and the opening; forming an anti-interference pattern on an upper surface of the second surface of the substrate adjacent to the pixel isolation pattern; and forming a second insulating interlayer on the second surface of the substrate, wherein the second insulating interlayer covers the via and the anti-interference pattern. The method further includes: forming a polishing stop layer on the second insulating interlayer; forming a third insulating interlayer on the polishing stop layer, wherein the third insulating interlayer fills the remainder of the opening; planarizing the third insulating interlayer until the polishing stop layer is exposed; and etching the polishing stop layer, the second insulating interlayer, and the third insulating interlayer using a dry etching process.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a pixel region and an input / output region; a pixel isolation pattern extending through the substrate in the pixel region; a first via disposed on the inner wall of an opening extending through the substrate in the input / output region, wherein the first via includes a first conductive material; and an anti-interference pattern disposed on the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material. The device further includes a first insulating interlayer disposed on the substrate, wherein the first insulating interlayer covers the first via and the anti-interference pattern, and wherein the first insulating interlayer includes a first portion disposed in the opening and a second portion disposed outside the opening. The first portion includes a recessed upper surface, and the second portion includes a substantially flat upper surface. The device further includes: a polishing stop pattern disposed on the first portion of the first insulating interlayer; and an insulating pattern disposed on the polishing stop pattern. The insulating pattern fills the remaining portion of the opening, and the insulating pattern includes an upper surface substantially coplanar with the upper surface of the second portion of the first insulating interlayer.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a pixel region, an input / output region, a first surface, and a second surface disposed opposite to the first surface. The device further includes: a pixel isolation pattern extending through the substrate in the pixel region; and a first insulating interlayer disposed on the first surface of the substrate, wherein the first insulating interlayer includes a plurality of wiring structures. The device further includes: a via disposed on the inner wall of an opening extending through the substrate in the input / output region and exposing at least one wiring structure, wherein the via includes a first conductive material. The device further includes: an anti-interference pattern disposed on an upper surface of the second surface of the substrate adjacent to the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material. The device further includes a second insulating interlayer disposed on the second surface of the substrate, wherein the second insulating interlayer covers the via and the anti-interference pattern. The device further includes: a polishing stop pattern disposed on a portion of the opening in the second insulating interlayer; and an insulating pattern disposed on the polishing stop pattern and filling the remaining portion of the opening.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a pixel region and an input / output region; a pixel isolation pattern extending through the substrate in the pixel region; a first insulating interlayer disposed on a first surface of the substrate and including a plurality of wiring structures; and a first via disposed on the inner wall of an opening extending through the substrate in the input / output region and exposing at least one wiring structure, wherein the first via includes a first conductive material. The device further includes: an anti-interference pattern disposed on an upper surface of the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material; a pad filling a trench in the substrate and including a third conductive material; and a second insulating interlayer disposed on the substrate, wherein the second insulating interlayer covers the first via, the pad, and the anti-interference pattern. The device further includes: a polishing stop pattern disposed on a portion of the opening in the second insulating interlayer; and an insulating pattern disposed on the polishing stop pattern and filling the remaining portion of the opening.

[0012] In a semiconductor device according to an exemplary embodiment of the present invention, the color filter, organic photodiode, and microlens disposed in the pixel region can be formed with a uniform height, rather than having a height distribution dependent on their position. As a result, the semiconductor device including the color filter, organic photodiode, and microlens can have improved performance. Attached Figure Description

[0013] The above and other features of the present invention will become clearer from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0014] Figures 1 to 20 These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device (more specifically, an image sensor) according to an exemplary embodiment of the present invention.

[0015] Figure 21 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device (more specifically, an image sensor) according to a concept of the present invention. Detailed Implementation

[0016] In the following description, exemplary embodiments of the inventive concept will be fully described with reference to the accompanying drawings. The same reference numerals throughout the drawings refer to the same elements.

[0017] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in one exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0018] In this document, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” are used to describe the relationship between one element or feature shown in the figure and another (or more) elements or features. It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would therefore be adjusted to “above” other elements or features. Thus, the exemplary terms “below” and “below” can cover both the orientations of “above” and “below.”

[0019] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "located" on, "connected to," "coupled to," or "adjacent to" another component, the component may be directly located on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediate components. It will also be understood that when a component is referred to as being "located" "between" two components, the component may be the only component between the two components, or there may be one or more intermediate components. It will also be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediate components may also cover the component.

[0020] As used herein, the term "approximately" includes the stated value and means within an acceptable range of deviation for a particular value, determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, as understood by one of ordinary skill in the art. Furthermore, it should be understood that while a parameter in this document may be described as having an "approximately" specific value, according to exemplary embodiments, the parameter may be exactly that specific value, or an approximate specific value within the measurement error, as understood by one of ordinary skill in the art.

[0021] In this document, when a surface is described as “substantially” flat, it should be understood that the surface is precisely flat, or nearly / approximately flat, taking into account errors associated with measurements of the surface (i.e., limitations of the measurement system), as understood by those skilled in the art. Similarly, when two or more surfaces are described as “substantially” coplanar, it should be understood that the two or more surfaces are precisely coplanar, or nearly / approximately coplanar, taking into account errors associated with measurements of the surface (i.e., limitations of the measurement system), as understood by those skilled in the art.

[0022] Figures 1 to 20 These are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device (more specifically, an image sensor) according to an exemplary embodiment of the present invention. More specifically, Figure 1 and Figure 14 It's a floor plan. Figures 2 to 13 and Figures 15 to 20 It is a sectional view.

[0023] Figure 2 , Figure 4 , Figure 7 , Figures 9 to 13 , Figure 15 and Figure 19 It is a sectional view taken along line A-A' of the corresponding plan view. Figure 3 , Figure 5 , Figure 8 , Figures 16 to 18 and Figure 20 It is a sectional view taken along line B-B' of the corresponding plan view.

[0024] In the following text, two directions that are substantially parallel to and intersect each other with the upper surface of the substrate are defined as the first direction and the second direction, respectively, and a direction that is substantially perpendicular to the upper surface of the substrate is defined as the third direction. In an exemplary embodiment, the first direction and the second direction may be orthogonal to each other.

[0025] Reference Figures 1 to 3 Pixel isolation pattern 110, via 140, and photodiode 150 can be formed in the first substrate 100. The first substrate 100 includes first regions to third regions I, II, and III.

[0026] The first substrate 100 may include semiconductor materials such as, for example, silicon, germanium, silicon-germanium, or III-V compounds such as, for example, GaP, GaAs, GaSb, etc. In an exemplary embodiment, the first substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In an exemplary embodiment, the first substrate 100 may be doped with p-type impurities.

[0027] like Figure 1 As shown, the first region I of the first substrate 100 may be square or rectangular in plan view, the second region II may surround the first region I, and the third region III may surround the second region II. However, the inventive concept is not limited thereto. In the following, the first to third regions I, II and III may refer not only to the interior of the first substrate 100, but also to the upper and lower spaces of the first substrate 100.

[0028] In an exemplary embodiment, the first region I may be a region in which pixels are formed, the second region may be a region in which pads for checking the electrical characteristics of pixels are formed, and the third region III may be an input / output (I / O) region in which conductive structures for inputting electrical signals to / outputting electrical signals from pixels are formed. Figure 2 and Figure 3 As shown, the first substrate 100 may include a first surface 102 and a second surface 104 opposite thereto.

[0029] In this article, Zone I can also refer to the pixel area, Zone II can also refer to the pad area, and Zone III can also refer to the input / output area.

[0030] Pixel isolation pattern 110 and via 140 can be formed by forming a plurality of trenches extending downward from first surface 102 in a third direction within a first region I of first substrate 100, and filling the trenches respectively. In an exemplary embodiment, in a plan view, pixel isolation pattern 110 may have a grid shape with some portions cut off, and the area cut off from pixel isolation pattern 110 having a grid shape may be referred to as a cut-off portion. Via 140 may be formed at each of the cut-off portions of pixel isolation pattern 110 having a grid shape to be spaced apart from pixel isolation pattern 110. Pixel isolation pattern 110 and via 140 together may define an area in which unit pixels can be formed, and a plurality of unit pixel areas may be arranged within first region I along each of a first direction and a second direction.

[0031] In an exemplary embodiment, the pixel isolation pattern 110 may include an insulating material such as, for example, oxides or nitrides, or a semiconductor material such as, for example, polysilicon. Alternatively, the pixel isolation pattern 110 may include, for example, doped polysilicon, or a conductive material such as, for example, metals, metal nitrides, etc.

[0032] The through-hole 140 may include a first insulating layer 120 disposed on the inner wall of the corresponding trench and a first conductive pattern 130 formed on the first insulating layer 120 to fill the remaining portion of the corresponding trench.

[0033] In an exemplary embodiment, the first insulating layer 120 may include oxides such as silicon oxide, metal oxides, or nitrides such as silicon nitride, and the first conductive pattern 130 may include, for example, doped polysilicon, metal, metal nitride, etc.

[0034] In an exemplary embodiment, the photodiode 150 may have a structure in which a first impurity region doped with n-type impurities and a second impurity region doped with p-type impurities are stacked in sequence. Figure 2 and Figure 3 The diagram shows a photodiode 150 formed at a central portion between a first surface 102 and a second surface 104 of a first substrate 100, but the inventive concept is not limited thereto. For example, the photodiode 150 may extend in a third-order upward direction from the first surface 102 of the first substrate 100 toward the second surface 104 of the first substrate 100, and may be spaced apart from each of the first surface 102 and the second surface 104.

[0035] Isolation patterns, transistors, and floating diffusion (FD) regions may also be formed on the upper portion of the first substrate 100 adjacent to the first surface 102. The transistors may include, for example, transfer transistors, source follower transistors, reset transistors, and select transistors. The FD region may be doped with impurities of a different conductivity type than that of the first substrate 100. For example, in an exemplary embodiment, the first substrate 100 may be doped with p-type impurities, and the FD region may be doped with n-type impurities.

[0036] Reference Figure 4 and Figure 5 A first insulating interlayer 200 containing a first wiring structure to a third wiring structure 160, 170 and 180 disposed therein can be formed on the first surface 102 of the first substrate 100.

[0037] The first to third wiring structures 160, 170, and 180 can be formed in the first to third regions I, II, and III, respectively. In an exemplary embodiment, the first wiring structure 160 can be formed to overlap with the via 140 and / or the pixel isolation pattern 110 in the third direction. However, the inventive concept is not limited thereto. For example, in an exemplary embodiment, the first wiring structure 160 can be formed according to different layouts.

[0038] Figure 4 and Figure 5 It is shown that each of the first wiring structure 160 and the second wiring structure 170 is formed at four horizontal heights in a third-direction orientation, and the third wiring structure 180 is formed at two horizontal heights in a third-direction orientation. For example, in Figure 4 and Figure 5In the exemplary embodiment shown, each of the first wiring structure 160 and the second wiring structure 170 includes four portions adjacent to each other in a third-order upward direction, and the third wiring structure 180 includes two portions adjacent to each other in a third-order upward direction. However, the inventive concept is not limited thereto. For example, in the exemplary embodiment, each of the first to third wiring structures 160, 170 and 180 may be formed at other numbers of horizontal heights.

[0039] A first wiring structure 160, a second wiring structure 170, and a third wiring structure 180, each formed at a plurality of horizontal heights, can be formed in a first insulating interlayer 200 such that they are electrically connected to each other through a first via disposed therebetween. In an exemplary embodiment, the first to third wiring structures 160, 170, and 180 and the first via can be formed using a double damascene process or a single damascene process.

[0040] In an exemplary embodiment, the through-hole 140 can be electrically connected to the first wiring structure 160 via a first contact plug 190 disposed in the first insulating interlayer 200. The FD area can also be electrically connected to the first wiring structure 160 via a second contact plug disposed in the first insulating interlayer 200.

[0041] Reference Figure 6 A second insulating interlayer 330, which includes a fourth wiring structure 310 and a fifth wiring structure 320, can be formed on the first surface 302 of the second substrate 300. The second substrate 300 includes a first surface 302 and a second surface 304 disposed opposite to the first surface 302.

[0042] The fourth wiring structure 310 and the fifth wiring structure 320 can be formed in the second zone II and the third zone III, respectively. Figure 6 The fourth wiring structure 310 and the fifth wiring structure 320 are shown to be formed at three horizontal heights in a third-direction orientation. For example, in Figure 6 In the exemplary embodiment shown, each of the fourth wiring structure 310 and the fifth wiring structure 320 includes three portions arranged adjacent to each other in a third-order upward direction. However, the inventive concept is not limited thereto. For example, in the exemplary embodiment, each of the fourth wiring structure 310 and the fifth wiring structure 320 may be formed at other numbers of horizontal heights.

[0043] A fourth wiring structure 310 and a fifth wiring structure 320, each formed at a plurality of horizontal heights, can be formed in a second insulating interlayer 330 such that they are electrically connected to each other through a second via disposed therebetween. In an exemplary embodiment, the fourth wiring structure 310, the fifth wiring structure 320, and the second via can be formed using a double damascene process or a single damascene process.

[0044] Reference Figure 7 and Figure 8 After the first insulating interlayer 200 placed on the first substrate 100 and the second insulating interlayer 330 placed on the second substrate 300 are bonded to each other, a portion of the second surface 104 of the first substrate 100 adjacent to the first substrate 100 can be removed.

[0045] In an exemplary embodiment, the first insulating interlayer 200 and the second insulating interlayer 330 may be bonded to each other via a bonding layer. Alternatively, the first insulating interlayer 200 and the second insulating interlayer 330 may be bonded to each other without a bonding layer. After the first insulating interlayer 200 and the second insulating interlayer 330 are bonded to each other, the orientation of the bonded structure may be flipped so that the second surface 104 of the first substrate 100 faces upward. Hereinafter, the second surface 104 of the first substrate 100 may be considered to be facing upward.

[0046] In an exemplary embodiment, this portion of the first substrate 100 adjacent to the second surface 104 can be removed by a polishing process, such as a grinding process. Therefore, the pixel isolation pattern 110 and via 140 extending through the first substrate 100 can be exposed.

[0047] For example, a portion of the upper surface of the first insulating layer 120 covering the first conductive pattern 130 in the through-hole 140 can be removed by a polishing process (see...). Figure 3 ), to form the first insulating pattern 125 (see Figure 8 Therefore, the through hole 140 may include a first conductive pattern 130 and a first insulating pattern 125 covering the sidewalls of the first conductive pattern 130.

[0048] Reference Figure 9 It can form a trench 332 extending through the upper part of the second surface 104 adjacent to the first substrate 100, a first opening 334 adjacent to the trench 332 and extending through the first substrate 100, and a second opening 336 extending through the first substrate 100 and the first insulating interlayer 200. The first opening 334 exposes the second wiring structure 170, and the second opening 336 exposes both the third insulating structure 180 and the fifth insulating structure 320.

[0049] Trench 332, first opening 334, and second opening 336 can be formed on the second surface 104 of the first substrate 100 by forming an etching mask such as, for example, a photoresist pattern, and performing a dry etching process using the etching mask. Trench 332 and first opening 334 can be formed in a second region II, and second opening 336 can be formed in a third region III.

[0050] In an exemplary embodiment, the second opening 336 may have a wider width than the first opening 334.

[0051] Reference Figure 10 A second conductive pattern 342 can be formed on the second surface 104 of the first substrate 100 to fill the trench 332. A third via 344 can be formed to fill the first opening 334 and contact the lower surface of the second conductive pattern 342. A fourth via 346 can be formed on the inner wall of the second opening 336 and the second surface 104 of the first substrate 100. An anti-interference pattern 348 can be formed on the pixel isolation pattern 110. The fourth via 346 and the anti-interference pattern 348 can each include a conductive material. In an exemplary embodiment, the fourth via 346 and the anti-interference pattern 348 can include the same conductive material.

[0052] For example, a second conductive layer can be formed on the second surface 104 of the first substrate 100 at the location where the trench 332, the first opening 334, and the second opening 336 are formed, and the second conductive layer can be patterned to form an anti-interference pattern 348, a second conductive pattern 342, a third via 344, and a fourth via 346 in the first to third regions I, II, and III, respectively.

[0053] In an exemplary embodiment, the anti-interference pattern 348 may be formed to overlap the pixel isolation pattern 110 in a third-order upward direction on the upper surface of the pixel isolation pattern 110. Therefore, the anti-interference pattern 348 may also have a grid shape with some portions cut off. The anti-interference pattern 348 can serve as a barrier to prevent light incident on one pixel from entering adjacent pixels, thereby preventing or reducing interference between adjacent pixels.

[0054] The second conductive pattern 342 can fill the trench 332 and can be formed on a portion of the second surface 104 of the first substrate 100 adjacent to the trench 332. The third via 344 can fill the first opening 334 and can contact the lower second wiring structure 170 and the upper second conductive pattern 342.

[0055] The second opening 336 may have a wider width than the first opening 334 and a deeper depth than the trench 332. Therefore, in an exemplary embodiment, the second conductive layer may completely fill the trench 332 and the first opening 334, but not the second opening 336. Consequently, the fourth via 346 disposed in the second opening 336 may be conformally formed on the sidewall of the second opening 336 and on the upper surfaces of the third wiring structure 180 and the fifth wiring structure 320 exposed by the second opening 336.

[0056] In an exemplary embodiment, the second conductive layer may include a metal such as tungsten, titanium, tantalum, etc.

[0057] The portion of the second conductive pattern 342 that overlaps with the trench 332 in a third-direction orientation may have a recessed upper surface that depends on the depth of the trench 332, and a third conductive pattern 350 may also be formed on the recessed upper surface of the second conductive pattern 342. Therefore, the sequentially stacked second conductive pattern 342 and third conductive pattern 350 can form a pad 355.

[0058] The first region I can correspond to the pixel region, the second region II can correspond to the pad region, and the third region III can correspond to the input / output region. Therefore, as... Figure 10 As shown, in an exemplary embodiment, the anti-interference pattern 348 may be formed in the pixel area (first area I), the pad 355 may be formed in the pad area (second area II), and the fourth via 346 may be formed in the input / output area (third area III).

[0059] In an exemplary embodiment, the pads 355 and the anti-interference pattern 348 may be formed of substantially the same conductive material.

[0060] In an exemplary embodiment, the third conductive pattern 350 can be formed by forming a third conductive layer on the second conductive pattern 342 and etching the third conductive layer. The third conductive pattern 350 may include a metal such as aluminum.

[0061] Reference Figure 11 After forming a third insulating interlayer 360 on the anti-interference pattern 348, pad 355, fourth via 346, and the second surface 104 of the first substrate 100, a polishing stop layer 370 and a fourth insulating interlayer 380 can be sequentially formed on the third insulating interlayer 360. The third insulating interlayer 360 can cover the fourth via 346 and partially fill the trench where the fourth via 346 is provided. Furthermore, the third insulating interlayer 360 can have a non-flat upper surface. Additionally, the third insulating interlayer 360 can include a first portion disposed within the trench where the fourth via 346 is provided and a second portion disposed outside the trench. Figure 11and Figure 12 As shown, the first portion of the third insulating interlayer 360 disposed in the trench having the fourth through hole 346 may include a recessed upper surface, and the second portion of the third insulating interlayer 360 disposed outside the trench may include a substantially flat upper surface.

[0062] In an exemplary embodiment, the third insulating interlayer 360 does not completely fill the second opening 336, thus allowing it to have a recessed upper surface within the second opening 336. Alternatively, the third insulating interlayer 360 may have a protruding upper surface on the anti-interference pattern 348 and the pad 355 located on the second surface 104 of the first substrate 100. Therefore, the third insulating interlayer 360 may have a curved upper surface rather than a flat upper surface.

[0063] Therefore, the polishing stop layer 360 and the fourth insulating interlayer 380 stacked on the third insulating interlayer 360 can also have curved upper surfaces instead of flat upper surfaces. The polishing stop layer 370 can be formed to have a thinner thickness than the third insulating interlayer 360 and the fourth insulating interlayer 380, and thus can be conformally formed on the third insulating interlayer 360 such that the polishing stop layer 370 does not completely fill the second opening 336. However, the fourth insulating interlayer 380 can be formed to have sufficient thickness to completely fill the remaining portion of the second opening 336. Figure 11 As shown, the fourth insulating interlayer 380 can fill the remaining portion of the trench where the fourth via 346 is provided. For example, as described above, the third insulating interlayer 360 can only partially fill the trench. The fourth insulating interlayer 380 can fill the remaining portion of the trench that is not filled by the third insulating interlayer 360.

[0064] The third insulating interlayer 360 and the fourth insulating interlayer 380 may comprise oxides such as, for example, silicon oxide. In an exemplary embodiment, the third insulating interlayer 360 and the fourth insulating interlayer 380 may comprise the same material. Alternatively, the third insulating interlayer 360 and the fourth insulating interlayer 380 may comprise materials different from each other. In this case, these materials may have low etch selectivity relative to each other.

[0065] In an exemplary embodiment, the polishing stop layer 370 may have a material with a high polishing selectivity (e.g., about equal to or less than about 1:10) relative to the fourth insulating interlayer 380. That is, the polishing selectivity between the fourth insulating interlayer 380 and the polishing stop layer 370 may be about equal to or greater than about 10:1. For example, the polishing stop layer 370 may include nitrides such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), or carbides such as silicon carbide (SiC), silicon oxynitride (SiOC), etc.

[0066] Reference Figure 12 A polishing process can be performed on the fourth insulating interlayer 380 until the polishing stop layer 370 is exposed. For example, the fourth insulating interlayer 380 can be planarized until the polishing stop layer 370 is exposed.

[0067] In an exemplary embodiment, the polishing process may include a chemical mechanical polishing (CMP) process. Cerium oxide (CeO) may be used, for example. x ), silicon dioxide (SiO) x ), aluminum oxide (Al) x O y Zirconium oxide (ZrO) x The CMP process is performed on the slurry, etc. In the CMP process, the fourth insulating interlayer 380 and the polishing stop layer 370 can have high polishing selectivity relative to each other, so the CMP process can be effectively performed until the polishing stop layer 370 is exposed.

[0068] The polishing stop layer 370 may have a curved upper surface instead of a flat upper surface. As a result, after the polishing process is performed, the fourth insulating interlayer 380 may not be completely removed, and a portion of the fourth insulating interlayer 380 may remain on the polishing stop layer 370.

[0069] Reference Figure 13 The remaining portions of the polishing stop layer 370, the fourth insulating interlayer 380, and the third insulating interlayer 360 can be removed until all remaining portions of the polishing stop layer 370 except for the portion located in the second opening 336 are completely removed.

[0070] In an exemplary embodiment, the polishing stop layer 370, the third insulating interlayer 360, and the fourth insulating interlayer 380 can be removed by a dry etching process. The dry etching process can be performed using an etching gas with low etching selectivity (e.g., an etching selectivity of about 0.5:1.5 to about 1.5:0.5 between the polishing stop layer 370 and the third and fourth insulating interlayers 360). Therefore, the polishing stop layer 370, the third insulating interlayer 360, and the fourth insulating interlayer 380 can be etched at similar rates during the etching process, such that the remaining upper surface of the third insulating interlayer 360 after the etching process is flat. For example, by utilizing a dry etching process instead of a planarization process such as CMP, the third insulating interlayer 360 can have a flat upper surface. The etching gas can include, for example, fluorocarbons (CH4), fluoroform (CHF3), oxygen (O2), etc.

[0071] After the etching process, except for the fourth via 346 and the third insulating interlayer 360, the polishing stop layer 370 and the fourth insulating interlayer 380 can be retained to form the polishing stop pattern 375 and the second insulating pattern 385 in the second opening 336, respectively.

[0072] For example, such as Figure 12 and Figure 13 As shown, a dry etching process can be used to etch the polishing stop layer 370, the third insulating interlayer 360, and the fourth insulating interlayer 380 until the remaining portion of the polishing stop layer 370, except for a portion located in the trench where the fourth via 346 is provided (e.g., polishing stop pattern 375), is removed. Furthermore, as... Figure 13 As shown, the third insulating interlayer 360 covering the fourth via 346 and the anti-interference pattern 348 has a non-flat upper surface before the dry etching process is performed, and the third insulating interlayer 360 covering the fourth via 346 and the anti-interference pattern 348 has a substantially flat upper surface after the dry etching process has been performed.

[0073] As described above, the third insulating interlayer 360 may include a first portion disposed within a trench having a fourth through-hole 346 and a second portion disposed outside the trench. A portion of the second insulating pattern 385 may fill the remaining portion of the trench and may include an upper surface substantially coplanar with the upper surface of the second portion of the third insulating interlayer 360 disposed outside the trench, such as... Figure 13 As shown. For example, the upper surface of the second insulating pattern 385 that fills the remaining portion of the trench can be substantially aligned with the upper surface of the second portion of the third insulating interlayer 360 disposed outside the trench.

[0074] like Figure 13 As shown, in an exemplary embodiment, the upper surface of the second insulating pattern 385, the uppermost surface of the polishing stop pattern 375, and the upper surface of the third insulating interlayer 360 may be substantially coplanar with each other.

[0075] Reference Figures 14 to 16 After the fifth insulating layer 400 is formed on the third insulating layer 360, the polishing stop pattern 375 and the second insulating pattern 385, a third contact plug 410 can be formed through the third insulating layer 360 and the fifth insulating layer 400 to contact the through hole 140.

[0076] The through-hole 140 can be formed at the cut-off portion of the pixel isolation pattern 110, which has a grid shape in which some parts are cut off. Therefore, the third contact plug 410 can also overlap with the cut-off portion of the pixel isolation pattern 110 in the third direction, so that the third contact plug 410 does not overlap with the pixel isolation pattern 110 in the third direction.

[0077] The fifth insulating interlayer 400 may include an oxide such as, for example, silicon oxide. The third contact plug 410 may include, for example, a metal, a metal nitride, doped polysilicon, etc.

[0078] Reference Figure 17 After removing the fifth insulating interlayer 400 to expose the upper surface of the third insulating interlayer 360, the upper surface of the polishing stop pattern 375, the upper surface of the second insulating pattern 385, and the upper part of the third contact plug 410, a third insulating layer 420 can be formed on the upper surface of the third insulating interlayer 360, the upper surface of the polishing stop pattern 375, the upper surface of the second insulating pattern 385, and the upper part of the third contact plug 410.

[0079] The third insulating layer 420 may include an oxide such as silicon oxide or a nitride such as silicon nitride.

[0080] A color filter 430 can be formed that penetrates the third insulating layer 420 and the third insulating interlayer 360. In an exemplary embodiment, the color filter 430 can be formed within a unit pixel region defined by the pixel isolation pattern 110 and the via 140, and does not overlap with the pixel isolation pattern 110 and the via 140 in the third direction.

[0081] In an exemplary embodiment, the color filter 430 may be a red filter or a blue filter.

[0082] Reference Figure 18 After the fourth insulating layer 450 is formed on the third insulating layer 420 and the color filter 430, the fourth insulating layer 450 can be planarized until the upper surface of the third contact plug 410 is exposed.

[0083] In an exemplary embodiment, the planarization process may include a CMP process, and in the CMP process, a portion of the third insulating layer 420 located on the upper surface of the third contact plug 410 may be removed, thereby retaining the third insulating pattern 425. Therefore, the third insulating pattern 425 may cover the upper sidewall of the third contact plug 410.

[0084] The fourth insulating layer 450 may include oxides such as silicon oxide.

[0085] Reference Figure 19 and Figure 20 The first transparent electrode 460, the organic layer 470, the second transparent electrode 480, the protective layer 490 and the microlens 500 can be sequentially stacked on the fourth insulating layer 450, the third insulating pattern 425 and the third contact plug 410 in the first region I.

[0086] In an exemplary embodiment, the first transparent electrode 460 may be correspondingly formed in each of the respective unit pixel areas and may contact the upper surface of the third contact plug 410. The sidewalls of the first transparent electrode 460 may be covered by a fifth insulating layer 465.

[0087] In an exemplary embodiment, the organic layer 470, the second transparent electrode 480, and the protective layer 490 may be formed over the entire first region I, and the microlens 500 may be correspondingly formed in each of the respective unit pixel regions. The first transparent electrode 460, the organic layer 470, and the second transparent electrode 480, stacked sequentially in a third-upward direction, may form an organic photodiode.

[0088] The first transparent electrode 460 and the second transparent electrode 480 may include, for example, ITO, IZO, ZnO, SnO2, antimony-doped tin oxide (ATO), antimony-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), TiO2, fluorine-doped tin oxide (FTO), etc. The organic layer 470 may include an organic material in which electron donors and electron acceptors are mixed. For example, the organic layer 470 may include multiple layers in which p-type semiconductor materials and n-type semiconductor materials can form a pn junction or a bulk heterojunction. The protective layer 490 may include an oxide such as, for example, silicon oxide.

[0089] An upper wiring structure can be formed to electrically connect it to pad 355 and fourth via 346 in Zone II and Zone III.

[0090] As described above, when the third insulating interlayer 360 is initially configured to cover the anti-interference pattern 348, pad 355, and fourth via 346, the third insulating interlayer 360 may not have a flat upper surface, but rather a curved upper surface due to the anti-interference pattern 348, pad 355, and fourth via 346. However, in the exemplary embodiment, after the polishing stop layer 370 and the fourth insulating interlayer 380 are sequentially formed on the third insulating interlayer 360, the fourth insulating interlayer 380 can be planarized by a CMP process until the polishing stop layer 370 is exposed, and a dry etching process can be performed using an etching gas with low etch selectivity between the polishing stop layer 370 and the third and fourth insulating interlayers 360 to remove the third and fourth insulating interlayers 380 until the polishing stop layer 370 is removed. Therefore, the remaining third insulating interlayer 360 can have a flat upper surface.

[0091] If the third insulating interlayer 360 is formed with a sufficiently large thickness on the anti-interference pattern 348, pad 355, and fourth via 346 to completely fill the remaining portion of the relatively wide second opening 336, and the upper surface of the third insulating interlayer 360 is planarized by a CMP process, then due to the removal of a large amount of the third insulating interlayer 360 by the CMP process, the final remaining third insulating interlayer 360 may have an overall uneven upper surface. For example, the upper surface of the third insulating interlayer 360 may have a height distribution depending on its location.

[0092] If CMP and subsequent processes are performed after the formation of the third insulating interlayer 360 to partially fill the second opening 336, which has a relatively large width, without filling the remaining portion of the second opening 336, a void may form in the second opening 336. As a result, residue will remain in the void, which can lead to defects during the CMP and subsequent processes.

[0093] However, as described above, in the exemplary embodiment, after initially forming the third insulating interlayer 360 to cover the anti-interference pattern 348, the pad 355, and the fourth via 346 and partially filling the second opening 336 (rather than completely filling the second opening 336), a polishing stop layer 370 can be formed on the third insulating interlayer 360, and a fourth insulating interlayer 380 can be formed to fill the remaining portion of the second opening 336. Therefore, a CMP process can be performed only on the fourth insulating interlayer 380 until the polishing stop layer 370, which has high polishing selectivity, is exposed, thus allowing the CMP process to be performed efficiently at a high rate. Additionally, a dry etching process with low etch selectivity between the polishing stop layer 370 and the third and fourth insulating interlayers 360 can be performed on the polishing stop layer 370 and the third and fourth insulating interlayers 380, such that the final remaining upper surface of the third insulating interlayer 360 can have a uniform height, rather than a height distribution dependent on its position. In other words, the third insulating interlayer 360 can have a flat upper surface rather than an uneven upper surface.

[0094] Therefore, a color filter 430 and an organic photodiode or microlens 500 can be formed at a uniform height in a third insulating interlayer 360 in a first region I where pixels can be formed, and an image sensor including a color filter 430, an organic photodiode and / or microlens 500 can have improved characteristics.

[0095] Up to this point, the fourth via 346 is formed on the inner wall of the second opening 336, which extends through the first substrate 100 to expose the third wiring structure 180 and the fifth wiring structure 320, and the third insulating interlayer 360 covering the fourth via 346 and partially filling the second opening 336 has a curved upper surface rather than a flat upper surface. However, the inventive concept is not limited thereto. For example, according to an exemplary embodiment of the inventive concept, a conductive structure can be formed on the inner wall of a trench that does not completely penetrate the first substrate 100 but extends partially through the first substrate 100 and has a large width, and the insulating interlayer covering the conductive structure and partially filling the trench can have a curved upper surface rather than a flat upper surface.

[0096] The image sensor manufactured by the above process may include: a pixel isolation pattern 110 extending through the first region I of a first substrate 100 including a first region I to a third region III; a first insulating interlayer 200 and a second insulating interlayer 330 below the first substrate 100, the first insulating interlayer 200 and the second insulating interlayer 330 including a first wiring structure to a fifth wiring structure 160, 170, 180, 310 and 320; and a fourth via 346 including conductive material on the inner wall of a second opening 336, the second opening 336 extending through the third region III of the first substrate 100 to expose the third wiring structure. Line structure 180 and fifth wiring structure 320; anti-interference pattern 348, which includes conductive material on the upper surface of pixel isolation pattern 110; pad 355, which fills trench 332 located on first substrate 100 and includes conductive material; third insulating interlayer 360, which is on first substrate 100 and covers fourth via 346, pad 355 and anti-interference pattern 348; polishing stop pattern 375, which is on the portion of third insulating interlayer 360 located in second opening 336; and second insulating pattern 385, which is on polishing stop pattern 375 and fills the remaining portion of second opening 336.

[0097] In an exemplary embodiment, the third insulating interlayer 360 may have a recessed upper surface in the second opening 336. In an exemplary embodiment, a polishing stop pattern 375 may be formed on a first portion of the third insulating interlayer 360 located in the second opening 336, and a second insulating pattern 385 may be formed on the polishing stop pattern 375 to fill the remaining portion of the second opening 336.

[0098] In an exemplary embodiment, the upper surface of the second insulating pattern 385 and the uppermost surface of the polishing stop pattern 375 may be formed at substantially the same height as the upper surface of the second portion of the third insulating interlayer 360 located outside the second opening 336, and the upper surface of the second portion of the third insulating interlayer 360 may be substantially flat.

[0099] Figure 21 This is a cross-sectional view showing a semiconductor device (more specifically, an image sensor) according to an exemplary embodiment.

[0100] Besides the shape of the solder pads Figure 21 The image sensor shown can be compared with the reference. Figures 1 to 20 The image sensors described are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and detailed descriptions of previously described elements and technical features are omitted here.

[0101] Reference Figure 21 ,and Figure 19 The difference between pad 355 shown is that... Figure 21 The pads 355 included in the image sensor can be fully embedded in the first substrate 100.

[0102] For example, the sequentially stacked second conductive pattern 342 and third conductive pattern 350 can be completely embedded in the upper portion of the first substrate 100 adjacent to the second surface 104, and the lower surface and sidewalls of the third conductive pattern 350 can be covered by the second conductive pattern 342. Furthermore, the upper surfaces of the second conductive pattern 342 and third conductive pattern 350 can be substantially aligned with the second surface 104 of the first substrate 100, such that the upper surfaces of the second conductive pattern 342 and third conductive pattern 350 do not extend above the second surface 104.

[0103] The third via 344 can be formed below the trench 332 in which the second conductive pattern 342 and the third conductive pattern 350 are formed, so as to contact the lower surface of the second conductive pattern 342.

[0104] The third insulating interlayer 360 included in the image sensor may have the same characteristics as the reference layer. Figure 19 and Figure 20 The third insulating interlayer 360 is described as having a flat upper surface similar to a flat upper surface.

[0105] The aforementioned semiconductor devices can be applied to contact image sensors (CIS), as well as various other types of semiconductor devices and systems including insulating interlayers that can cover conductive structures, such as volatile memory devices such as DRAM devices, non-volatile memory devices such as flash memory devices, and logic devices.

[0106] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various modifications in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes pixel areas and input / output areas; A pixel isolation pattern that extends through the substrate in the pixel region; A first via is disposed on the inner wall of an opening that extends through the substrate in the input / output region, wherein the first via comprises a first conductive material; An anti-interference pattern is disposed on the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material; A first insulating interlayer is disposed on the substrate. The first insulating interlayer covers the first via and the anti-interference pattern, and includes a first portion disposed in the opening and a second portion disposed outside the opening. The first portion includes a recessed upper surface, and the second portion includes a substantially flat upper surface. A polishing stop pattern is disposed on the first portion of the first insulating interlayer, and the polishing stop pattern is confined within a groove defined by the recessed upper surface of the first portion of the first insulating interlayer; and An insulating pattern is disposed on the polishing stop pattern, wherein the insulating pattern fills the remaining portion of the opening, and the insulating pattern includes an upper surface that is substantially coplanar with the upper surface of the second portion of the first insulating interlayer.

2. The semiconductor device according to claim 1, wherein, The polishing stop pattern includes at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon carbide (SiC), and silicon carbon oxynitride (SiOC).

3. The semiconductor device according to claim 1, wherein, The first insulating interlayer and the insulating pattern comprise silicon oxide.

4. The semiconductor device according to claim 1, wherein, The first conductive material and the second conductive material are the same material.

5. The semiconductor device according to claim 1, wherein, The first via is formed on the upper surface of the substrate in the input / output area adjacent to the opening.

6. The semiconductor device according to claim 1, wherein, The pixel isolation pattern has a grid shape in the planar view, in which some parts are cut off.

7. The semiconductor device according to claim 6, further comprising: Through-holes extend through the substrate in the pixel region and are spaced apart from the pixel isolation pattern.

8. The semiconductor device according to claim 7, wherein, The via is formed at a cut-off portion of the pixel isolation pattern having the grid shape, the cut-off portion being a region cut out from the pixel isolation pattern having the grid shape, and the pixel isolation pattern and the via define a unit pixel area.

9. The semiconductor device according to claim 7, further comprising: A second insulating interlayer is disposed beneath the substrate and includes multiple wiring structures. The through-hole is electrically connected to at least one of the plurality of wiring structures.

10. The semiconductor device of claim 9, further comprising: The first contact plug is disposed within the second insulating interlayer. The through hole is connected to the at least one wiring structure via the first contact plug.

11. The semiconductor device according to claim 7, further comprising: A second contact plug is disposed on the upper surface of the through hole; as well as An organic photodiode is disposed on and in contact with the second contact plug.

12. The semiconductor device according to claim 1, further comprising: A second insulating interlayer is disposed beneath the substrate and includes multiple wiring structures. The opening exposes at least one of the plurality of wiring structures, and the first via contacts the exposed at least one wiring structure.

13. The semiconductor device according to claim 1, wherein, The substrate further includes: a pad area disposed between the pixel area and the input / output area, and The semiconductor device further includes: A pad is disposed on a substrate in the pad area, wherein the first insulating interlayer covers the pad.

14. The semiconductor device according to claim 13, wherein, The pads fill trenches in the substrate disposed in the pad area, and have portions formed in the pad area adjacent to the trenches.

15. The semiconductor device of claim 14, further comprising: A second insulating interlayer is disposed beneath the substrate and includes multiple wiring structures, and The second via extends through the substrate in the pad area and contacts at least one of the plurality of wiring structures.

16. The semiconductor device according to claim 13, wherein, The pads are filled in trenches on the substrate disposed in the pad area.

17. A semiconductor device, comprising: The substrate includes a pixel region, an input / output region, a first surface, and a second surface disposed opposite to the first surface; A pixel isolation pattern that extends through the substrate in the pixel region; A first insulating interlayer is disposed on a first surface of the substrate, wherein the first insulating interlayer includes a plurality of wiring structures; A via is disposed on the inner wall of an opening that extends through the substrate in the input / output area and exposes at least one of the plurality of wiring structures, wherein the via comprises a first conductive material; An anti-interference pattern is disposed on the upper surface of the second surface of the pixel isolation pattern adjacent to the substrate, wherein the anti-interference pattern includes a second conductive material; A second insulating interlayer is disposed on a second surface of the substrate, wherein the second insulating interlayer covers the via and the anti-interference pattern; A polishing stop pattern is disposed on a portion of the opening in the second insulating interlayer, and the polishing stop pattern is confined within a groove defined by the recessed upper surface of the portion of the second insulating interlayer in the opening; and An insulating pattern is disposed on the polishing stop pattern and fills the remainder of the opening.

18. The semiconductor device of claim 17, wherein the upper surface of the insulating pattern, the uppermost surface of the polishing stop pattern, and the upper surface of the second insulating interlayer are substantially coplanar with each other.

19. The semiconductor device according to claim 17, wherein, The second insulating interlayer has a substantially flat upper surface.

20. A semiconductor device, comprising: The substrate includes pixel areas and input / output areas; A pixel isolation pattern that extends through the substrate in the pixel region; A first insulating interlayer is disposed on the surface of the substrate and includes a plurality of wiring structures; A first via is disposed on the inner wall of an opening that extends through the substrate in the input / output area and exposes at least one of the plurality of wiring structures, wherein the first via comprises a first conductive material; An anti-interference pattern is disposed on the upper surface of the pixel isolation pattern, wherein the anti-interference pattern includes a second conductive material; The pads fill trenches on the substrate and include a third conductive material; A second insulating interlayer is disposed on the substrate, wherein the second insulating interlayer covers the first via, the pad, and the anti-interference pattern; A polishing stop pattern is disposed on a portion of the opening in the second insulating interlayer, and the polishing stop pattern is confined within a groove defined by the recessed upper surface of the portion of the second insulating interlayer in the opening; and An insulating pattern is disposed on the polishing stop pattern and fills the remainder of the opening.

Images