System and method for synchronizing integrated circuit chips

Abstract

An input device has a display device integrated with a capacitive sensing device. A first of the IC chips is a master IC chip, and a second of the IC chips is a slave IC chip. The master IC chip is configured to transmit synchronization signals to and from the slave IC chips so that a capacitive frame is acquired by each of the IC chips at substantially the same time, a synchronization sensing signal is initiated for each of the IC chips, and a clock signal of the slave IC chip is synchronized with a clock signal of the master IC chip.

Description

Technical Field

[0001] Embodiments disclosed herein relate generally to electronic devices and, more particularly, to synchronous integrated circuit chips. Background Art

[0002] Input devices including proximity sensor devices can be used in a variety of electronic systems. Proximity sensor devices can include a sensing area distinguished by a surface, wherein the proximity sensor device determines the presence, position, force and / or motion of one or more input objects. Proximity sensor devices can be used to provide an interface for an electronic system. For example, proximity sensor devices can be used as input devices for larger computing systems, such as touch pads integrated in or on the periphery of a notebook or desktop computer. Proximity sensor devices can also be frequently used in smaller computing systems, such as touch screens integrated in cellular phones or vehicles (e.g., cars). Summary of the invention

[0003] In one embodiment, an input device includes a plurality of sensor electrodes, a master integrated circuit (IC) chip, and a first slave IC chip. The master integrated circuit (IC) chip is communicatively coupled to the plurality of sensor electrodes and is configured to generate a vertical timing signal and a horizontal timing signal, and to initiate acquisition of a first capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with a first sensing signal including one or more sensing bursts. The first slave IC chip is communicatively coupled to the master IC chip and is communicatively coupled to the plurality of sensor electrodes, and is configured to receive the vertical timing signal and the horizontal timing signal from the master IC chip, and to initiate acquisition of a second capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with a second sensing signal including one or more sensing bursts.

[0004] In one embodiment, a method for synchronizing IC chips includes: generating a vertical timing signal and a horizontal timing signal using a master IC chip, transmitting the vertical timing signal and the horizontal timing signal from the master IC chip to a slave IC chip, initiating acquisition of a first sensing measurement by the master IC chip based on at least one of the vertical timing signal and the horizontal timing signal, and initiating acquisition of a second sensing measurement by the slave IC chip based on at least one of the vertical timing signal and the horizontal timing signal.

[0005] In one embodiment, a processing system for a display device with an integrated capacitive sensing device includes a master IC chip and a slave IC chip that are communicatively coupled to a plurality of sensor electrodes. The master IC chip is configured to generate a vertical timing signal and a horizontal timing signal, and to drive the plurality of sensor electrodes with a first sensing signal corresponding to one or more sensing bursts to initiate acquisition of a first capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal. The slave IC chip is communicatively coupled to the master IC chip and to the plurality of sensor electrodes, and is configured to receive the vertical timing signal and the horizontal timing signal from the master IC chip, and to drive the plurality of sensor electrodes with a second sensing signal corresponding to the one or more sensing bursts to initiate acquisition of a second capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order that the manner in which the above-recorded features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the accompanying drawings illustrate only exemplary embodiments and are therefore not to be considered as limiting the scope of the invention, as the present disclosure may admit to other equally effective embodiments.

[0007] Figure 1 is a schematic block diagram of an input device according to one or more embodiments.

[0008] Figure 2 Example display devices and sensor devices are illustrated in accordance with one or more embodiments.

[0009] Figure 3 A multi-chip configuration for driving a display panel according to one or more embodiments is illustrated.

[0010] Figure 4 is a block diagram of a synchronization device according to one or more embodiments.

[0011] Figure 5A Various signal connections are illustrated in accordance with one or more embodiments.

[0012] Figure 5B A system for generating a synchronization signal according to one or more embodiments.

[0013] Fig. 6A , 6A continued , 6B, 6B-6C illustrate block diagrams for synchronizing chips according to one or more embodiments.

[0014] Figure 7A-1 , 7A-2, 7A-3, 7A-4, 7B-1, 7B-2, 7B-3, and 7B-4 illustrate block diagrams for synchronizing chips according to one or more embodiments.

[0015] Fig. 8A and 8B A block diagram of signal paths is illustrated in accordance with one or more embodiments.

[0016] Fig. 9 Synchronization signals according to one or more embodiments are illustrated.

[0017] Fig.10 , 11 , 12 and 13 illustrate various methods for synchronizing integrated circuit chips according to one or more embodiments.

[0018] For ease of understanding, the same reference numerals have been used, where possible, to designate the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific recitation. Unless otherwise specified, the drawings referred to herein should not be understood as being drawn to scale. Moreover, for clarity of presentation and explanation, the drawings are often simplified and details or components are omitted. The drawings and discussion are used to explain the principles discussed below, where similar names represent similar elements. DETAILED DESCRIPTION

[0019] The following detailed description is merely exemplary in nature and is not intended to limit the present disclosure or the application and use of the present disclosure. In addition, there is no intention to be bound by any express or implied theory presented in the foregoing background technology, the invention summary or the following detailed description.

[0020] In one or more embodiments, the input device includes a plurality of display driver integrated circuit chips configured for display updating and performing capacitive sensing. Each of the display driver integrated circuit chips is configured to drive sensor electrodes and update display electrodes of a common display panel, and if the display driver integrated circuit chips are not synchronized with each other, artifacts and / or errors in the sensed data may occur. In the following description, various systems and methods for synchronizing the display driver integrated circuit chips are described.

[0021] Turning now to the accompanying drawings, Figure 11 is a block diagram of an exemplary input device 100 according to an embodiment of the present disclosure. The input device 100 can be configured to provide input to an electronic system (not shown). As used in this document, the term "electronic system" refers broadly to any system capable of electronically processing information. Some non-limiting examples of electronic systems include personal computers of all sizes and shapes, such as desktop computers, laptop computers, netbook computers, tablet computers, web browsers, e-book readers, and personal digital assistants (PDAs). Additional example electronic systems include composite input devices, such as physical keyboards including input device 100 and separated joysticks or key switches. Other example electronic systems include peripheral devices, such as data input devices (e.g., remote controls and mice) and data output devices (e.g., display screens and printers). Other examples include remote terminals, kiosks, and video game consoles, such as video game consoles, portable game devices, etc. Other examples include communication devices, such as cellular phones such as smart phones, and media devices, such as recorders, editors, and players, such as televisions, set-top boxes, music players, digital photo frames, and digital cameras. In addition, the electronic system can be a host or slave of an input device. Electronic systems can also be called electronic devices.

[0022] The input device 100 may be implemented as a physical part of the electronic system, or may be physically separate from the electronic system. As appropriate, the input device 100 may communicate with portions of the electronic system using any one or more of the following: a bus, a network, and other wired or wireless interconnects. Examples include I 2 C, SPI, PS / 2, Universal Serial Bus (USB), Bluetooth, RF, and IRDA.

[0023] exist Figure 1 , the input device 100 is shown as a proximity sensor device that is configured to sense input provided by one or more input objects 140 in the sensing region 120. Example input objects 140 include fingers and styluses, such as Figure 1 An exemplary proximity sensor device may be a touch pad, a touch screen, a touch sensor device, etc.

[0024] The sensing region 120 encompasses any space above, around, in, and / or near the input device 100 where the input device 100 is capable of detecting user input, such as user input provided by one or more input objects 140. The size, shape, and location of a particular sensing region may vary widely from embodiment to embodiment. In some embodiments, the sensing region 120 extends from the surface of the input device 100 in one or more directions into space until the signal-to-noise ratio prevents sufficiently accurate object detection. In various embodiments, the distance to which the sensing region 120 extends in a particular direction may be approximately less than one millimeter, several millimeters, several centimeters, or more, and may vary significantly depending on the type of sensing technology used and the desired accuracy. Therefore, the sensing input of some embodiments includes: no contact with any surface of the input device 100; contact with an input surface (e.g., a touch surface) of the input device 100: contact with an input surface of the input device 100 coupled with a certain amount of applied force or pressure; and / or a combination thereof. In various embodiments, the input surface may be provided by a surface of a housing in which a sensor electrode (also referred to herein as a sensing electrode) is located, by a panel applied to the sensor electrode or any housing, and the like. In some embodiments, the sensing region 120 has a rectangular shape when projected onto the input surface of the input device 100 .

[0025] The input device 100 can utilize any combination of sensor components and sensing technologies to detect user input in the sensing region 120. The input device 100 includes one or more sensing elements for detecting user input. As several non-limiting examples, the input device 100 can use capacitive, elastic, resistive, inductive, magnetic, acoustic, ultrasonic and / or optical technologies.

[0026] Some embodiments are configured to provide images spanning one, two, three or higher dimensional spaces. Some embodiments are configured to provide projections of inputs along specific axes or planes.

[0027] In some resistive embodiments of the input device 100, a flexible and conductive first layer is separated from a conductive second layer by one or more spacer elements. During operation, one or more voltage gradients are created across the layers. Pressing the flexible first layer may deflect it sufficiently to create electrical contact between the layers, thereby generating a voltage output reflecting the contact point(s) between the layers. These voltage outputs may be used to determine position information.

[0028] In some inductive implementations of the input device 100, one or more sensing elements pick up a loop current induced by a resonant coil or coil pair. Some combination of the amplitude, phase, and frequency of the current can then be used to determine position information.

[0029] In some capacitive implementations of input device 100, a voltage or current is applied to create an electric field. Nearby input objects cause changes in the electric field and produce detectable changes in capacitive coupling, which can be detected as changes in voltage, current, etc.

[0030] Some capacitive embodiments utilize arrays or other regular or irregular patterns of capacitive sensing elements to create an electric field. In some capacitive embodiments, separate sensing elements can be ohmically shorted together to form a larger sensor electrode. Some capacitive embodiments utilize a resistive sheet, which can be uniformly resistive.

[0031] Some capacitive implementations utilize a "self-capacitance" (also often referred to as "absolute capacitance") sensing method based on changes in the capacitive coupling between a sensor electrode and an input object. In various embodiments, an input object near a sensor electrode changes the electric field near the sensor electrode, thereby changing the measured capacitive coupling. In one implementation, the absolute capacitance sensing method operates by modulating the sensor electrode relative to a reference voltage (e.g., system ground), and by detecting the capacitive coupling between the sensor electrode and the input object.

[0032] Some capacitive embodiments utilize a "mutual capacitance" (also often referred to as "transcapacitance") sensing method based on changes in capacitive coupling between sensor electrodes. In various embodiments, an input object near the sensor electrodes changes the electric field between the sensor electrodes, thereby changing the measured capacitive coupling. In one embodiment, the transcapacitive sensing method operates by the following steps: detecting capacitive coupling between one or more transmitter sensor electrodes (also referred to herein as "transmitter electrodes" or "transmitters") and one or more receiver sensor electrodes (also referred to herein as "receiver electrodes" or "receivers"). The transmitter sensor electrodes can be modulated relative to a reference voltage (e.g., system ground) to transmit transmitter signals. The receiver sensor electrodes can be kept substantially constant relative to the reference voltage to facilitate reception of the generated signal. The generated signal can include (one or more) effects corresponding to one or more transmitter signals and / or one or more environmental interference sources (e.g., other electromagnetic signals). The sensor electrodes can be dedicated transmitters or receivers, or can be configured to both transmit and receive.

[0033] exist Figure 1, the processing system 110 is shown as part of the input device 100. The processing system 110 is configured to operate the hardware of the input device 100 to detect input in the sensing area 120. The processing system 110 includes part or all of one or more integrated circuits (ICs) and / or other circuit components. For example, a processing system for a mutual capacitance sensor device may include a transmitter circuit configured to transmit a signal using a transmitter sensor electrode and / or a receiver circuit configured to receive a signal using a receiver sensor electrode. In some embodiments, the processing system 110 also includes electronically readable instructions, such as firmware code, software code, and / or the like. In some embodiments, the components that make up the processing system 110 are positioned together, such as near (one or more) sensing elements of the input device 100. In other embodiments, the components of the processing system 110 are physically separated, with one or more components being close to (one or more) sensing elements of the input device 100, and one or more components being elsewhere. For example, the input device 100 may be a peripheral device coupled to a desktop computer, and the processing system 110 may include software configured to run on a central processing unit of the desktop computer and one or more ICs separate from the central processing unit (with associated firmware in another embodiment). As another example, the input device 100 may be physically integrated into a phone, and the processing system 110 may include circuits and firmware that are part of the phone's main processor. In some embodiments, the processing system 110 is dedicated to implementing the input device 100. In other embodiments, the processing system 110 also performs other functions, such as operating a display screen, driving a tactile actuator, etc.

[0034] The processing system 110 may be implemented as a collection of modules that handle different functions of the processing system 110. Each module may include circuitry, firmware, software, or a combination thereof that is part of the processing system 110. In various embodiments, different combinations of modules may be used. Example modules include: hardware operation modules for operating hardware such as sensor electrodes and display screens; data processing modules for processing data such as sensor signals and position information; and reporting modules for reporting information. Additional example modules include: a sensor operation module configured to operate (one or more) sensing elements to detect inputs; a recognition module configured to recognize gestures such as mode change gestures; and a mode change module for changing operating modes.

[0035] In some embodiments, the processing system 110 directly responds to user input (or lack of user input) in the sensing region 120 by causing one or more actions. Example actions include changing operating modes and GUI actions such as cursor movement, selection, menu navigation, and other functions. In some embodiments, the processing system 110 provides information about the input (or lack of input) to some portion of the electronic system (e.g., to a central processing system of the electronic system that is separate from the processing system 110, if such a separate central processing system exists). In some embodiments, some portion of the electronic system processes the information received from the processing system 110 to act on the user input, such as to facilitate a full range of actions, including mode change actions and GUI actions.

[0036] For example, in some embodiments, the processing system 110 operates the (one or more) sensing elements of the input device 100 to generate an electrical signal indicating an input (or lack of input) in the sensing area 120. The processing system 110 can perform any appropriate amount of processing on the electrical signal in generating information provided to the electronic system. For example, the processing system 110 can digitize an analog electrical signal obtained from a sensor electrode. As another example, the processing system 110 can perform filtering or other signal conditioning. As yet another example, the processing system 110 can subtract or otherwise account for a baseline so that the information reflects the difference between the electrical signal and the baseline. As yet other examples, the processing system 110 can determine position information, identify input as a command, recognize handwriting, etc.

[0037] As used herein, "position information" broadly encompasses absolute position, relative position, velocity, acceleration, and other types of spatial information. Exemplary "zero-dimensional" position information includes near / far or contact / no-contact information. Exemplary "one-dimensional" position information includes position along an axis. Exemplary "two-dimensional" position information includes motion in a plane. Exemplary "three-dimensional" position information includes instantaneous or average velocity in space. Additional examples include other representations of spatial information. Historical data about one or more types of position information may also be determined and / or stored, including, for example, historical data tracking position, motion, or instantaneous velocity over time.

[0038] In some embodiments, input device 100 is implemented with additional input components operated by processing system 110 or by some other processing system. These additional input components may provide redundant functionality for input in sensing region 120 or some other functionality. Figure 1 A button 130 is shown proximate the sensing region 120, which can be used to facilitate selection of items using the input device 100. Other types of additional input components include sliders, balls, wheels, switches, etc. Conversely, in some embodiments, the input device 100 may be implemented without additional input components.

[0039] In some embodiments, the input device 100 includes a touch screen interface, and the sensing area 120 overlaps at least part of the display screen. For example, the sensing area 120 may overlap at least a portion of the active area of ​​the display screen. The active area of ​​the display screen may correspond to a portion of the updated image of the display screen. In one or more embodiments, the input device 100 may include a substantially transparent sensor electrode covering the display screen and provide a touch screen interface for an associated electronic system. The display screen may be any type of dynamic display capable of displaying a visual interface to a user, and may include any type of light emitting diode (LED), organic LED (OLED), cathode ray tube (CRT), liquid crystal display (LCD), plasma, electroluminescence (EL) or other display technology. The input device 100 and the display screen may share physical elements. For example, some embodiments may utilize some of the same electronic components for display and sensing. As another example, the display screen may be partially or fully operated by the processing system 110. The display screen may also be referred to as a display panel.

[0040] It should be understood that although many embodiments of the present disclosure are described in the context of a fully functional device, the mechanisms of the present disclosure can be distributed as program products (e.g., software) in a variety of forms. For example, the mechanisms of the present disclosure can be implemented and distributed as a software program on an information bearing medium readable by an electronic processor, for example, a non-transitory computer-readable and / or recordable / writable information bearing medium readable by the processing system 110. In addition, regardless of the specific media type used to perform the distribution, the embodiments of the present disclosure are equally applicable. Examples of non-transitory electronically readable media include various disks, memory sticks, memory cards, storage modules, etc. Electronically readable media can be based on flash, optical, magnetic, holographic, or any other storage technology.

[0041] Figure 2 1 shows a portion of an exemplary pattern of sensor electrodes 205 configured to sense in a sensing region 120 associated with the pattern, according to some embodiments. For clarity of illustration and description, Figure 2 The area of ​​capacitive sensor electrodes 205 is presented in a simple rectangular pattern; however, in other embodiments, the sensor electrodes 205 may be arranged in other patterns and may have other shapes. For example, one or more of the sensor electrodes 205 may span the entirety of the sensing region 120 in a first direction (e.g., along the X-axis), and another one or more of the sensor electrodes may span the entirety of the sensing region in a second direction (along the Y-axis) that is different from the first direction. Furthermore, in various embodiments, the sensor electrodes 205 may be arranged in overlapping or non-overlapping rows and columns of sensor electrodes.

[0042] In one embodiment, the sensor electrodes 205 are areas of local capacitance. Areas of local capacitance may be formed between individual sensor electrodes and ground in a first mode of operation, and between groups of sensor electrodes used as transmitter and receiver electrodes in a second mode of operation. Capacitive coupling changes with the proximity and movement of an input object in the sensing region 120, and thus may be used as an indicator of the presence of an input object in the sensing region 120 of an input device.

[0043] An exemplary pattern includes sensor electrodes 205 arranged in X columns and Y rows in a common plane. X，Y , where X and Y are positive integers, although one of X and Y may be zero. It is contemplated that the pattern of sensor electrodes 205 may include a plurality of sensing pixels 205 having other configurations, such as an annular array, a repeating pattern, a non-repeating pattern, a non-uniform array, a single row or column, or other suitable arrangements. In addition, as will be discussed in more detail below, the sensor electrodes 205 may be any shape, such as a circle, a rectangle, a diamond, a star, a square, a non-convex shape, a convex shape, a non-concave shape, a concave shape, etc. As shown here, the sensor electrodes 205 are coupled to the processing system 110 and used to determine the presence (or absence) of an input object in the sensing region 120.

[0044] In a first operating mode, at least one sensor electrode may be used to detect the presence of an input object via an absolute sensing technique. The sensor module 204 in the processing system 110 is configured to drive the sensor electrode using the trace 240 in each sensor electrode 205 using an absolute capacitive sensing signal, and to measure the capacitance between the sensor electrode and the input object based on the absolute capacitive sensing signal, which is used by the processing system 110 or other processor to determine the position of the input object. The absolute capacitive sensing signal may be a modulated signal including a varying voltage. In one embodiment, the absolute capacitive sensing signal includes a plurality of pulses (e.g., a plurality of positive and negative voltage transitions). In addition, the positive and negative voltage transitions may be referred to as bursts, and the absolute capacitive sensing signal includes one or more bursts.

[0045] One or more of the sensor electrodes 205 may be ohmically isolated from one or more other of the sensor electrodes 205. Additionally, one or more insulators separate the sensor electrodes and prevent them from electrically shorting to each other.

[0046] In the second operating mode, the sensor electrodes 205 are used to detect the presence of an input object via transcapacitive sensing technology. That is, the processing system 110 can drive at least one sensor electrode 205 with a transmitter signal and use one or more of the other sensor electrodes 205 to receive the generated signal, wherein the generated signal includes an effect corresponding to the transmitter signal. The generated signal is used by the processing system 110 or other processor to determine the position of the input object. The sensor electrode driven by the transmitter signal is modulated by the transmitter signal relative to the sensor electrode receiving the generated signal. In one embodiment, the sensor electrode driven by the transmitter signal and the sensor electrode receiving the generated signal are both modulated. In one embodiment, the transmitter signal includes multiple pulses (e.g., multiple positive and negative voltage transitions). In addition, the positive and negative voltage transitions can be referred to as bursts, and the transmitter signal includes one or more bursts.

[0047] The term "sensing signal" may refer to an absolute capacitive sensing signal or a transmitter signal.

[0048] The input device 100 can be configured to operate in any of the above modes. The input device 100 can also be configured to switch between the above two modes.

[0049] In some embodiments, the sensor electrodes 205 are "scanned" to determine these capacitive couplings. That is, in one embodiment, one or more sensor electrodes are driven to transmit a transmitter signal. The transmitter can be operated so that one transmitter electrode transmits at a time, or multiple transmitter electrodes transmit at the same time. In the case where multiple transmitter electrodes transmit simultaneously, the multiple transmitter electrodes can transmit the same transmitter signal and effectively produce a substantially larger transmitter electrode. Alternatively, the multiple transmitter electrodes can transmit different transmitter signals. For example, the multiple transmitter electrodes can transmit different transmitter signals according to one or more encoding schemes that enable their combined impact on the resulting signal of the receiver electrode to be independently determined.

[0050] The sensor electrodes configured as receiver sensor electrodes may be operated individually or in plurality to acquire the generated signal. The generated signal may be used to determine a measure of the capacitive coupling at the capacitive pixel 205.

[0051] In other embodiments, "scanning" the sensor electrodes 205 to determine these capacitive couplings includes driving with an absolute capacitive sensing signal and measuring the absolute capacitance of one or more sensor electrodes. In another embodiment, the sensor electrodes can be operated so that the absolute capacitive sensing signal is driven on the sensor electrodes 205 at the same time. In such an embodiment, an absolute capacitive measurement can be obtained from each of the one or more sensor electrodes 205 at the same time. In one embodiment, the input device 100 drives the sensor electrodes in multiple sensor electrodes 205 at the same time and measures the absolute capacitive measurement of each sensor electrode 205 in the same sensing cycle. In various embodiments, the processing system 110 can be configured to selectively drive and receive with a portion of the sensor electrodes. For example, the sensor electrodes can be selected based on, but not limited to, the application running on the main processor, the state of the input device, the operating mode of the sensing device, and the determined position of the input device. The main processor can be a central processing unit or any other processor of an electronic device.

[0052] As discussed above, the collection of measurements from the sensor electrodes 205 forms a capacitive image or capacitive frame representing the capacitive coupling at the sensor electrodes 205. Multiple capacitive images may be acquired over multiple time periods, and the differences between them used to derive information about the input in the sensing region. For example, consecutive capacitive images acquired over consecutive time periods may be used to track the motion (s) of one or more input objects entering, leaving, and within the sensing region.

[0053] In some embodiments, one or more of the sensor electrodes 205 include one or more display electrodes for updating the display of the display screen. In one or more embodiments, the display electrode includes one or more segments of a common voltage electrode (also referred to as a Vcom electrode), a source drive line (or source electrode), a gate line (or gate electrode), an anode electrode or a cathode electrode, or any other display element. These display electrodes can be disposed on an appropriate display screen substrate. For example, in display screens such as in-plane switching (IPS) and plane-to-line switching (PLS) organic light emitting diodes (OLEDs), the display electrodes can be disposed on a transparent substrate, such as a glass substrate, TFT glass, or any other transparent material. In other embodiments, in display screens such as patterned vertical alignment (PVA) and multi-domain vertical alignment (MVA), the display electrodes can be disposed on the bottom of the color filter glass. In one or more embodiments, the display electrode can be disposed on the light emitting layer of the OLED display. In such embodiments, an electrode used as both a sensor electrode and a display electrode can also be referred to as a combined electrode because it performs multiple functions. In one embodiment, the display electrodes may be gate electrodes used to select sub-pixels of a display line for updating, source electrodes configured to drive data signals onto the sub-pixels for updating, and / or one or more Vcom electrodes. The source electrodes may be coupled to columns of sub-pixels, and the gate electrodes may be coupled to rows of sub-pixels.

[0054] Continue to refer Figure 2 In various embodiments, the processing system 110 coupled to the sensing electrodes may include one or more integrated circuit (IC) chips, wherein each IC chip includes a sensor module 204 and a display driver module 208. In one embodiment, the sensor module 204 includes circuitry configured to drive a transmitter signal or an absolute capacitive sensing signal onto the sensing electrodes and receive the resulting signal using the sensing electrodes during a period in which input sensing is desired. In addition, the processing system may include multiple IC chips, wherein each IC chip may include a sensor module 204 and a display driver module 208.

[0055] In one or more embodiments, the sensor module 204 includes a transmitter module, which includes a circuit configured to drive a transmitter signal to a sensing electrode during a period in which input sensing is desired. In one or more embodiments, the transmitter signal is modulated and contains one or more bursts in a period of time allocated for input sensing. The transmitter signal can have an amplitude, a frequency, and a voltage, which can be changed to obtain more robust position information of an input object in the sensing area 120. The absolute capacitive sensing signal can be the same or different from the transmitter signal used in transcapacitive sensing. The sensor module 204 can be selectively coupled to one or more of the sensor electrodes 205. For example, the sensor module 204 can be coupled to a selection of sensor electrodes and operate in an absolute or transcapacitive sensing mode. In another example, when operating in an absolute sensing mode rather than in a transcapacitive sensing mode, the sensor module 204 can be coupled to different sensor electrodes.

[0056] In various embodiments, the sensor module 204 includes a sensor circuit (e.g., Figure 3 In one or more embodiments, the sensor module 204 is configured to receive the generated signal from the sensor electrode, which is driven with an absolute capacitive sensing signal to determine the change in absolute capacitance between the sensor electrode and the input object. In one or more embodiments, the sensor module 204 determines the position of the input object in the sensing area 120. In one or more embodiments, the sensor module 204 provides a signal including information indicating the generated signal to another module or processor, such as a determination module of the processing system 110 or a processor (e.g., a main processor) of the electronic device, for determining the position of the input object in the sensing area 120. In one or more embodiments, the sensor circuit of the sensor module includes a receiver circuit, wherein the receiver circuit may include multiple analog front ends (AFEs).

[0057] In one or more embodiments, capacitive sensing or input sensing and display updating may occur during at least partially overlapping periods. Display updating may include updating the voltage on each of the display electrodes during a display frame. During each display frame, each of the display lines of the display device may be updated. In one embodiment, the display frame may be updated every 16 milliseconds, or at a display frame rate of 60 Hz. In other embodiments, other display frame rates may be utilized. For example, display frame rates of 48 Hz, 120 Hz, and / or 240 Hz may be utilized. For example, when driving a combined electrode for display updating, the combined electrode may also be driven for capacitive sensing. Overlapping capacitive sensing and display updating may include modulating the reference voltage (one or more) of the display device and / or modulating at least one display electrode of the display within a time period that at least partially overlaps the time that the sensor electrode is configured for capacitive sensing. In another embodiment, capacitive sensing and display updating may occur during non-overlapping periods (also referred to as non-display update periods). In various embodiments, a non-display update period may occur between display line update periods of two display lines of a display frame, and may be at least as long in time as a display update period. In such embodiments, the non-display update period may be referred to as a long horizontal blanking period, a long h-blanking period, or a distributed blanking period. In other embodiments, the non-display update period may include a horizontal blanking period and a vertical blanking period. The processing system 110 may be configured to drive the sensor electrodes for capacitive sensing during any one or more or any combination of the different non-display update times.

[0058] Figure 3 Multiple IC chip solutions for driving a display panel are illustrated. In one or more embodiments, the display device 300 may be part of an input device (e.g., input device 100) for a vehicle (e.g., a car). As illustrated, Figure 3 A display device 300 is included having a display panel having a substrate 320 and display electrodes 330. In the illustrated embodiment, three IC chips (e.g., a master IC chip 340, a right slave IC chip 350, and a left slave IC chip 360) are used to drive the display panel and perform capacitive sensing. In one embodiment, one or more of the IC chips may be disposed on a first substrate, and another one or more of the IC chips may be disposed on a second substrate.

[0059] Each of the IC chips may include an instance of the sensor module 204 and the display driver module 208. In addition, each of the IC chips may include a timing controller (Tcon) 209 configured to generate timing signals for display updating and capacitive sensing, and a sensing circuit 206 configured to perform capacitive sensing using the sensor electrodes 205. In one embodiment, the Tcon 209 is configured to communicate with a capacitive sensing circuit configured to synchronize display updating and capacitive sensing.

[0060] In various embodiments, each of IC chips 340, 350, and 360 includes a plurality of input / output pins. Figure 3 As shown in FIG. 3 , IC chips 340, 350, and 360 include input / output pins such as sense_sync_i / o_1, sense_sync_i / o_r, tsvd_i / o_1, tsvd_i / o_r, tshd_i / o_1, tshd_i / o_r, Hcal_pulse_i / o_1, Hcal_pulse_i / o_r, and general purpose input / output (GPIO) pins. The input / output pins of the IC chips can be communicatively coupled to associated input / output pins of another IC chip via one or more routing lines disposed on substrate 320, or in one or more embodiments, coupled between IC chips via routing lines disposed on different substrates. For example, the sense_sync_i / o_l of the master IC chip 340 may be coupled to the sense_sync_i / o_r of the left slave IC chip 360, and the sense_sync_i / o_r of the master IC chip 340 may be coupled to the sense_sync_i / o_l of the right slave IC chip 350. Similarly, for example, the tsvd_i / o_l of the master IC chip 340 may be coupled to the tsvd_i / o_r of the left slave IC chip 360, and the tsvd_i / o_r of the master IC chip 340 may be coupled to the tsvd_i / o_l of the right slave IC chip 350. In addition, the tshd_i / o_l of the master IC chip 340 can be coupled to the tshd_i / o_r of the left slave IC chip 360, and the tshd_i / o_r of the master IC chip 340 can be coupled to the tshd_i / o_l of the right slave IC chip 350. The Hcal_pulse_i / o_l of the master IC chip 340 can be coupled to the Hcal_pulse_i / o_r of the left slave IC chip 360, and the Hcal_pulse_i / o_r of the master IC chip 340 can be coupled to the Hcal_pulse_i / o_l of the right slave IC chip 350.

[0061] In other embodiments, each of the IC chips may include other input / output pins. For example, each of the IC chips may include input / output pins used to drive sensor electrodes 205 for capacitive sensing and to drive display electrodes for display updating.

[0062] In one or more embodiments, the IC chips configured for both capacitive sensing and display updating (e.g., master IC chip 340, right slave IC chip 350, and left slave IC chip 360) may be referred to as touch and display driver integration (TDDI) chips. For example, the IC chip may be configured to drive one or more sensor electrodes 205 for at least one of transcapacitive sensing and absolute capacitive sensing.

[0063] Although Figure 3 The embodiment of the embodiment illustrates three IC chips, but in other embodiments, other numbers of IC chips can be implemented in the input device 100. For example, in one embodiment, at least two IC chips can be used to drive the display panel and perform touch sensing. Each IC chip may include an IC that is different and separate from the other IC chips. In addition, each of the IC chips can be configured to update different parts of the display panel and operate different parts of the sensor electrodes 205 (e.g., sensor electrodes 205a, 205b, and 205c) for capacitive sensing. In one or more embodiments, two or more IC chips can drive at least one common sensor electrode 205 for capacitive sensing. In one embodiment, each IC chip is coupled to and configured to update different parts of the line or source electrode of the display panel. In addition, the IC chip can be configured to drive different parts of the Vcom electrode for display update. In an embodiment where the Vcom electrode is used for capacitive sensing and display update, each IC chip is configured to operate different parts of the Vcom electrode for capacitive sensing and display update.

[0064] In one embodiment, each of the master IC chip 340, the right slave IC chip 350, and the left slave IC chip 360 is independently coupled to the substrate 320 of the display panel. In addition, the master IC chip is coupled to each slave IC chip through one or more traces disposed on the substrate 320. In one embodiment, the substrate 320 is a glass substrate, and the IC chips are communicatively coupled via one or more traces disposed on the glass substrate.

[0065] In an embodiment using two or more IC chips, one IC chip can be configured as a "master" (e.g., master IC chip 340), while other IC chips (e.g., slave IC chips 350 and / or 360) can be configured as "slaves". The IC chip configured as a "master" can be configured to provide one or more synchronization signals to the IC chip configured as a "slave" to synchronize at least one of the display updates and capacitive sensing functions between the IC chips. In an embodiment using three IC chips, the master IC chip can be disposed between two slave IC chips. In other embodiments, the master IC chip can be positioned so that each of the slave IC chips is located on the same side of the master IC chip.

[0066] The main IC chip 340 can be configured to receive display data from a host processor for updating a display panel. For example, the main IC chip 340 can process display data and communicate the processed display data to slave IC chips 350 and 360. In addition, the main IC chip 340 can be configured to communicate sensor data to the host processor. For example, the main IC chip 340 can be configured to receive sensor data from each of the slave IC chips 350 and 360, combine the sensor data from the slave IC chip with the sensor data from the main IC chip, and communicate the combined sensor data to the host processor. In one embodiment, each of the IC chips can be configured to process the sensor data received at each corresponding IC chip before the sensor data is sent to the host processor. In other embodiments, raw sensor data (e.g., substantially unprocessed sensor data) is communicated to the host processor. In other embodiments, the main IC chip 340 is configured to receive raw sensor data from each of the slave IC chips 350 and 360, process the sensor data, and then communicate the processed sensor data to the host processor. Processing the sensor data may include at least one of baselining the sensor data, filtering the sensor data, and determining position information of one or more input objects.

[0067] In one or more embodiments, the master IC chip 340 and the slave IC chips 350, 360 can be synchronized so that the digital circuits of each IC chip operate within at least about 50ns of each other IC chip. In other embodiments, the IC chips can be synchronized with each other so that the timing of the digital circuits of each IC chip differs by more than 50ns, but does not introduce errors in the sensor data or display updates. In one embodiment, the IC chips can be synchronized with each other so that the timing of the digital circuits of each IC chip does not introduce display artifacts and / or introduce errors in the sensor data collected from the sensor electrodes when the display panel is updated. In addition, the synchronization IC chip synchronizes the timing of the sensing signals driven by each of the IC chips to the corresponding sensor electrodes 205.

[0068] In one embodiment, any timing mismatch between the sensing signals (e.g., sensing signals 342, 352, and 362) across the master IC chip 340 and the slave IC chips 350 and 360 may result in a display panel capacitance that is not well protected, which causes a large amount of charge to flow into the AFE of the receiver circuit of each IC chip. In such an embodiment, the sensor electrode or one or more display electrodes of the display panel are at a different voltage than the sensor electrodes operated for capacitive sensing. Capacitive coupling is formed between the electrodes with voltage mismatch, which can be referred to as background capacitance.

[0069] Because background capacitance is present in the sensor data collected from the sensor electrodes, the dynamic range of the receiver circuit that can be used to handle potential interference and changes in the capacitance of the sensor electrodes is reduced. In one embodiment, the value of the background capacitance can be greater than the value of the capacitive coupling between the sensor electrodes 205 and / or between the sensor electrodes 205 and the input object. Therefore, it is difficult to detect and / or measure the capacitive coupling between the sensor electrodes and / or between the sensor electrodes and the input object. In addition, the background capacitance may cause the AFE of the receiver circuit to saturate or clip, making it impossible to detect and / or measure the capacitive coupling between the sensor electrodes and / or between the sensor electrodes and the input object.

[0070] In one or more embodiments, the master IC chip 340 is configured to perform one or more of the following with each of the slave IC chips 350 , 360 : frame synchronization, sense burst synchronization, sense cycle synchronization, and high-speed oscillator clock synchronization.

[0071] Each IC chip 340, 350, 360 can be configured to operate a different portion of the sensor electrode 205 for capacitive sensing at a capacitive frame rate of one of 60 Hz or 120 Hz. In other embodiments, other capacitive frame rates can be utilized. In one embodiment, each IC chip 340, 350, 360 is coupled to each non-overlapping portion of the sensor electrode 205 so that the sensor electrode is only coupled to one of the IC chips 340, 350 and 360. For example, the slave IC chip 360 is communicatively coupled to the sensor electrode 205a, the master slave IC chip 340 is communicatively coupled to the sensor electrode 205b, and the slave IC chip 350 is communicatively coupled to the sensor electrode 205c. The IC chips can be coupled to the same number of sensor electrodes, or, in one or more embodiments, at least the IC chip is coupled to a different number (e.g., more or less) of sensor electrodes than another IC chip. The IC chips can be coupled to the corresponding sensor electrodes via one or more routes disposed on the substrate 320. In other embodiments, there may be some overlapping portions of sensor electrodes 205 coupled to one or more of IC chips 340 , 350 , 360 .

[0072] Each IC chip can be configured to operate each corresponding sensor electrode once (or twice) per capacitive frame. In one embodiment, operating the sensor electrode for capacitive sensing includes driving the corresponding sensor electrode using a corresponding one of the sensing signals 342, 352, and 362. The capacitive frame rate corresponds to a time period during which sensor data is received from the sensor electrode coupled to each corresponding IC chip. In one embodiment, the rate at which a capacitive image is collected is a capacitive frame rate (or sensing rate). For example, a capacitive image can be collected once every 16ms, generating a capacitive frame rate of 60Hz. In other embodiments, the capacitive frame rate can be about 120Hz, 240Hz, or greater. In addition, in one or more embodiments, the capacitive frame rate can be less than 60Hz.

[0073] The master IC chip 340 can be configured to perform frame synchronization with each of the slave IC chips 350, 360 so that each IC chip starts a new capacitive frame at substantially the same time. In one embodiment, frame synchronization can occur at startup of the IC chip, after a reset of one or more IC chips, and / or after a plurality of capacitive frames have occurred.

[0074] The Tcon 209 of each IC chip 340, 350, 360 can generate a timing control signal, which can be used by the IC chip to perform display updates and capacitive sensing. In one embodiment, the timing signal used to indicate the start of one or more of the capacitive sensing frame and the display frame is a timing signal for the vertical direction (i.e., a vertical timing signal) or a TSVD signal. In addition, the timing signal configured to indicate the start of the display line of the display frame is a timing signal for the horizontal direction (i.e., a horizontal timing signal) or a TSHD signal. Both the TSVD and TSHD signals can be generated by the Tcon 209 of the master IC chip 340 and communicated to each of the slave IC chips 350, 360.

[0075] Figure 4 An example embodiment of a trigger lookup table (LUT) logic 410 is illustrated. In one embodiment, each of the IC chips 340, 350, 360 includes the trigger LUT logic 410. The TSVD signal generated by the Tcon 209 of the master IC chip 340 can be routed to the trigger LUT logic of each of the master IC chip 340 and the slave IC chips 350, 360. In one embodiment, the TSVD signal can be communicated from the TSVD_I / O_L and TSVD_I / O_R of the master IC chip 340 to the TSVD_I / O_R of the left slave IC chip 360 and the TSVD_I / O_L of the right slave IC chip 350. In addition, the Tcon 209 of the master IC chip 340 can be configured to communicate the TSHD signal to each of the slave IC chips 350, 360. For example, the tshd signal may be communicated from tshd_i / o_l and tshd_i / o_r of the master IC chip 340 to pins tshd_i / o_r of the right slave IC chip 360 and tshd_i / o_l of the left slave IC chip 350 .

[0076] The Tcon 209 of the master IC chip 340 communicates both the tsvd and tshd signals to the trigger LUT logic 410 of the master IC chip 340, and to the trigger LUT logic 410 of each of the slave IC chips 350, 360. The trigger LUT logic 410 of each slave IC chip 350, 360 is configured to generate a local sense_trig_event pulse 420 from the tsvd and tshd signals provided by the master IC chip 340. In addition, each IC chip 340, 350, and 360 can initiate a burst sensing state machine that can enable the collection of sensor data in response to the corresponding local sense_trig_event pulse 420. The burst sensing state machine of each IC chip initiates steps for collecting sensor data corresponding to the burst of sense signals.

[0077] INT_TCON_TRIG registers 432, 434 allow the IC chip to generate corresponding tshd and tsvd signals using the TCON of the IC chip. SLAVE_SELECT registers 436, 438 specify whether the chip is in a single IC configuration, configured as a master IC chip, configured as a left slave IC chip, or configured as a right slave IC chip. In addition, sense_trig_event signal 420 can be used by each corresponding IC chip to start a sense burst. Each sense burst corresponds to at least one positive and negative voltage transition. Each sense signal includes multiple bursts. In one embodiment, SLAVE_SELECT registers 436, 438 and INT_TCON_TRIG registers 432, 434 are communicatively coupled to multiplexers 462 and 464, and can control the signals coupled to trigger LUT 410 through multiplexers 462 and 464. For example, the SLAVE_SELECT register 436 and the INT_TCON_TRIG register 432 are used to select one of the tshd_in_l_dest, tshd_in_r_dest, and Tshd_Tcon signals coupled to the trigger LUT 410 via the multiplexer 462. In addition, the SLAVE_SELECT register 438 and the INT_TCON_TRIG register 434 are used to select one of the tsvd_in_l_dest, tsvd_in_r_dest, and Tsvd_Tcon signals coupled to the trigger LUT 410 via the multiplexer 464.

[0078] At the start of a new capacitive frame, the FW_SENSE_TRIG register 450 is programmed to generate the sense_trig_event signal 420 when the tsvd signal is received. Furthermore, since the tsvd signal is generated at substantially the same time for all IC chips, the start of a new capacitive frame will start at the same time for all IC chips.

[0079] Figure 5AThe schematic diagram of the origin of the signal used in the above figure is illustrated. Component 510 identifies the input / output pins tsvd_in_1 and tshd_in_1 on the left side of slave IC chip 360. These pins can receive tsvd and tshd signals from master IC chip 340. The tsvd_in_1 pin and tshd_in_1 pin can be communicatively coupled to tsvd_in_1_dest and tshd_in_1_dest inputs of the multiplexer of slave IC chip 360. Similarly, component 520 identifies the input / output pins tsvd_in_r and tshd_in_r on the right side of slave IC chip 350. These can receive tsvd and tshd signals from master IC chip 340. The tsvd_in_l and tshd_in_l may be communicatively coupled to tsvd_in_r_dest and tshd_in_r_dest of the multiplexer of the slave IC chip 360. In addition, the Tcon 209 of the master IC chip 340 is configured to output signals tshd and tsvd to pins tshd_Tcon and tsvd_Tcon of the multiplexer, which are coupled to the trigger LUT 410 of the master IC chip 340.

[0080] In one or more embodiments, the master IC chip 340 can be configured to perform burst synchronization with the slave IC chips 350 and 360. Burst synchronization can occur whenever a burst occurs, after multiple bursts, and / or whenever one or more capacitive frames occur. Each capacitive frame can include multiple bursts. In one embodiment, the Tcon (e.g., Tcon209) of the master IC chip 340 sends the tshd signal of the master IC chip to the trigger LUT logic (e.g., trigger LUT logic 410) of the master IC chip 340. In addition, after the first sensing burst of the capacitive frame, each IC chip adopts the FW_SENSE_TRIG signal, which is programmed to generate the sense_trig_event signal based on the corresponding tshd signal. Since the tshd signal arrives at substantially the same time for all three IC chips, each IC chip generates the sense_trig_event signal at substantially the same time, which maintains burst synchronization.

[0081] Figure 5B is a block diagram of a system 500 configured to generate a sense_trig_event signal 420 according to one or more embodiments. Figure 4 As stated, Figure 5BIn an embodiment, the sense_trig_event signal 420 may be initiated by the fw_sense_trig signal 566. In an embodiment, synchronizers 550 and 552 may be used to synchronize the tshd and tsvd signals with corresponding signals of the master IC chip 340. Figure 5B , the tshd signal is input to the delay unit 540, and the tsvd signal is input to the delay unit 542. In one or more embodiments, both the tshd signal and the delayed tshd signal, and both the tsvd and the delayed tsvd signal are provided to the LUT 544. The register sense_trig_LUT 548 can be used to control the generation of the sense_trig signal 546 by the LUT 544. The sense_trig signal 546 is used by the pulse generator 560 to generate an output pulse 562. The pulse generator 560 outputs a pulse 562 for each detected rising edge of the sense_trig 546 signal. The output 562 of the pulse generator 560 can be combined with the delayed fw_sense_trig_dlyd signal 564 to generate the sense_trig_event pulse 420. The fw_sense_trig signal 566 is delayed by a delay unit 568 to generate a fw_sense_trig_dlyd signal 564. In one embodiment, delay units 540, 542, and 568 are programmable delays that ensure that each IC chip 340, 350, 360 generates a sense_trig_event pulse 420 at substantially the same time. The programmable delay may be different for each of the IC chips. In addition, in one or more embodiments, the programmable delay may be determined as described below.

[0082] The sensing signal (e.g., Vguard signal) of the IC chip (e.g., the master IC chip 340, the slave IC chips 350, 360) can be generated using a waveform generator (e.g., a direct digital synthesis (DDS) device or a similar device). The sensing signal waveform can be a periodic voltage waveform generated by the waveform generator. In one embodiment, the waveform generator generates a sensing signal of half a cycle each time. In one embodiment, the waveform generator is reset at the beginning of each sensing burst. In addition, in one or more embodiments, the burst sensing state machine for each IC chip is also reset and started at the beginning of each sensing burst. In one embodiment, the sensing signal can be driven onto one or more sensor electrodes to perform capacitive sensing, and driven onto one or more display electrodes (e.g., gate electrodes, source electrodes, etc.) to protect the display electrodes as a protection signal.

[0083] The master IC chip 340 can be configured to perform sensing cycle synchronization with the slave IC chips 350, 360. In one embodiment, synchronizing the sensing cycles ensures that the waveform generator of each IC chip is started once every half cycle at substantially the same time. In one embodiment, the delay between the start of each half cycle is no greater than about 50ns between the three chips. In other embodiments, the delay between the start of each half cycle is less than a time period that may cause display artifacts and errors in the sensor data.

[0084] Fig. 6A , 6A continued 6B, 6B-S each illustrate an example sensing synchronization signal loopback path of a master IC chip according to one or more embodiments. Each loopback path corresponds to a communication coupling between a slave IC chip and a master IC chip. Fig. 6A and 6A continued An example path 610 for a master IC chip for a left slave IC chip is shown, while Figure 6B and 6B continued An example path 620 for a master IC chip for a right slave IC chip is shown. Fig. 6A , 6A continued In the embodiment shown in FIGS. 6B, 6B-cont., the master IC chip sends a sense_sync_out signal from the master IC chip's waveform generator 612. The label start indicates where the path begins with the sense_sync_out signal 668 provided by the waveform generator 612. The sense_sync_out signal 668 then flows along the indicated path 610 where it is routed out of the master IC chip.

[0085] exist Fig. 6A and 6A continuedIn the embodiment of the present invention, the sense_sync_out signal 668 flows through the pulse_extension block 669, through the delay block (or sense_sync_out_1_DLY block) 617, and flows out through the sense_sync_out_1 pin 619 of the main IC chip 340, and then returns to the main IC chip 340 via the sense_sync_in_1 pin 621. The sense_sync_out_1_DLY block 617 can be a programmable delay. In addition, the signal through the sense_sync_in_1 pin 621, that is, the sense_sync_in_1_dest signal 622, flows through the multiplexer 613, and then enters the waveform generator 612 at the tag end via the circuit 614. The circuit 614 generates the sense_sync_in signal 665 from the sense_sync_in_1_dest signal 622. Circuit 614 may include a delay block (or SENSE_SYNC_IN_LP_DLY block) 670 and a multiplexer 664 .

[0086] exist Figure 6B and 6B continued In the embodiment of the present invention, the sense_sync_out signal 668 flows along the path 620 through the pulse_extension block 669, through the delay block (or sense_sync_out_r_DLY block) 671, and flows out through the sense_sync_out_r pin 623 of the main IC chip, and then returns to the main IC chip through the sense_sync_in_r pin 624. The sense_sync_out_r_DLY block 671 can be a programmable delay. In addition, the signal through the sense_sync_in_r pin 624, that is, the sense_sync_in_r_dest signal 625, flows through the multiplexer 613, and then enters the waveform generator 612 at the tag end through the circuit 614.

[0087] In one or more embodiments, the master IC chip is configured to simultaneously transmit a sense_sync_out signal for slave IC chips (eg, right and left slave IC chips) coupled to the master IC chip, and a loopback path may exist for each of the slave IC chips.

[0088] Figure 6C An example loopback path circuit 660 for a master IC chip is shown in accordance with one or more embodiments. Fig. 6A , 6A continued, 6B, 6B to be used in the embodiments of the continuation of FIG. As shown, a sense_sync_short_lb signal 667 can be generated from a sense_sync_out signal 668. The sense_sync_short_lb signal 667 can be used by the master IC chip 340 as a trigger to generate a sense_sync_out signal 668, and the master IC chip 340 is synchronized with the slave IC chips 350 and 360. For example, in one embodiment, when the sense_sync_short_lb signal 667 flows into the multiplexer 666 without being transmitted through the input / output pins 619, 621, 623 and 624, the sense_sync_short_lb signal 667 can alleviate or avoid timing jitter, because the timing generated by the sense_sync_short_lb signal is not affected by external interference. This improves the synchronization between the master IC chip 340 and the slave IC chips 350 and 360.

[0089] Reference again Fig. 6A , 6A continued , 6B, 6B cont., and 6C, in one or more embodiments, the master IC chip is configured to control which side (e.g., left or right) the signal is routed back to the master IC chip 340 via a selector, such as a multiplexer 613 ( Fig. 6A , 6A continued 、6B、6BContinued)、666( Figure 6C ) of the SENSE_SYNC_IN_LR_SEL register 615 ( Fig. 6A , 6A continued , 6B, 6B continued) and SENSE_SYNC_IN_SEL register 616 ( Figure 6C ). In addition, the signal can be delayed by SENSE_SYNC_IN_LP_DLY block 670. SENSE_SYNC_IN_LP_DLY block 670 can be a programmable delay. The signal then travels through multiplexer 664 and is received by the sense_sync_in input port of the master IC chip. Multiplexer 664 can be controlled via SLAVE_SELECT register 618. In one embodiment, when the master IC chip 340 receives the sense_sync_out signal, a new half cycle of the sense signal (e.g., sense signal 342) is started.

[0090] Figure 7A-1 , 7A-2 , 7A-3, 7A-4, 7B-1, 7B-2, 7B-3, and 7B-4 illustrate embodiments in which the master IC chip communicates the sense_sync_out signal 668 to the slave IC chip for sense cycle synchronization. Figure 7A-1 , 7A-2 In the embodiments of 7A-3 and 7A-4, the master IC chip 340 is communicatively coupled to the slave IC chip 350 located to the right of the master IC chip 340. Figure 7B-1 , 7B-2 , 7B-3, and 7B-4, the master IC chip 340 is communicatively coupled to the slave IC chip 360 located to the left of the master IC chip 340. In one embodiment, the master IC chip 340 communicates the sense_sync_out signal 668 from the master IC chip 340 along the same side of the master IC chip 340 where the slave IC chip is located. For example, the slave IC chip 350 is located along the right side of the master IC chip 340, then the sense_sync_out signal 668 is output from the pin along the right side of the master IC chip 340. In other embodiments, the sense_sync_out signal 668 can be output from the pin on a side of the master IC chip 340 that is different from the side of the master IC chip 340 where the slave IC chip is located.

[0091] In one embodiment, the sense_sync_out signal 668 is delayed by a programmable delay before it is transmitted from the master IC chip 340 to the slave IC chips 350, 360. Then, the sense_sync_out signal 668 can be transmitted from the pins of the master IC chip 340 to the sense_sync_i / o pins of the slave IC chips 350, 360. In one embodiment, the trace along which the sense_sync_out signal 668 travels is disposed on a glass substrate of a display panel. The display panel can be part of an input device (e.g., input device 100). In one embodiment, after the sense_sync_out signal 668 is received via the sense_sync_i / o pins of the slave IC chips, the sense_sync_out signal 668 is routed to the waveform generator of the corresponding slave IC chip via a multiplexer.

[0092] In one or more embodiments, when performing synchronization with the sensing cycle of the slave IC chips 350 and 360, the master IC chip 340 is configured to utilize programmable delays, such as sense_sync_out_r_dly 712 and sense_sync_out_l_dly722, to synchronize the sensing cycle of the master IC chip 340 with the sensing cycle of the slave IC chips 350 and 360. By adjusting each of the programmable delays within the master IC chip 340, the sensing cycle synchronization between the master IC chip 340 and each slave IC chip 350 and 360 may occur. In one embodiment, the amount of the programmable delay can be determined by performing one or more delay calibration techniques in the delay calibration techniques described herein. For example, the programmable delay can be calibrated so that the sense_sync_out signal 668 generated by the master IC chip 340 arrives at the waveform generators 612, 612a, 612b of the IC chips 340, 350, 360 within about 50ns of each other. In other embodiments, the programmable delays may be calibrated so that the sense_sync_out signal 668 is received by the waveform generators 612, 612a, 612b of the IC chips 340, 350, 360 within time periods relative to each other that at least minimizes errors and / or differences in sensor data collected by each of the IC chips.

[0093] In other embodiments, to perform delay calibration, the master IC chip transmits timing pulses along a loopback path within the master IC chip and along a round-trip path to and from the slave IC chip. The master IC chip can time the signal propagation of the timing pulses along these paths. For example, the master IC chip times the signal propagation of the timing pulses transmitted via the loopback path of the master IC chip and the signal propagation of the timing pulses transmitted via a path from the master IC chip to the slave IC chip and then back to the master IC chip. The timing pulse can be the sense_sync_out signal 668.

[0094] Fig. 8A 3 is a schematic diagram of signal paths for performing delay calibration in an embodiment with two slave IC chips 350, 360 and one master IC chip 340 according to one or more embodiments. In an embodiment with a single slave IC chip and a master IC chip, one or more of the signal paths may be omitted. For example, in an embodiment where the right slave IC chip is omitted, the corresponding signal path is also omitted. In addition, in an embodiment where the left slave IC chip is omitted, the corresponding signal path is also omitted.

[0095] In one embodiment, the master IC chip 340 starts the delay calibration clock and sends the sense_sync_out signal to the slave IC chips 350, 360 via signal paths 812 and 813, and is also transmitted locally to both sides of the master IC chip 340, which is coupled to the slave IC chips 350, 360 via signal paths 810 and 811. The sense_sync_out signal is transmitted along Fig. 8A For example, the sense_sync_out signal may be communicated from the master IC chip 340 to each of the slave IC chips 350, 360 and then returned to the master IC chip 340. In addition, the sense_sync_out signal may be transmitted locally on the master IC chip 340 via a loopback path.

[0096] With reference to the loopback paths 810 and 811 of the main IC chip 340, the sense_sync_out signal may be sent out of at least one of the right (SSO_R) pad and the left (SSO_L) pad. The sense_sync_out signal may be sent back to the waveform generator of the main IC chip 340 via signal paths 810 and 811 on the pad. In one embodiment, the main IC chip 340 may measure only one of the loopback paths at a time and determine along which path (left path or right path) to measure the delay. In this embodiment, for example, the value of the SENSE_SYNC_IN_LR_SEL register 615 of the main IC chip 340 may be used to make a determination. In other embodiments, each of the paths may be measured simultaneously.

[0097] In one embodiment, the sense_sync_out signal is communicated to the right slave IC chip 350 via the SSO_R pad of the master IC chip. The sense_sync_out signal travels from the master IC chip 340 to the SSI_L pad of the right slave IC chip 350 across the substrate (e.g., substrate 320) to which each of the IC chips is mounted. The right slave IC chip 350 receives the sense_sync_out signal and routes the sense_sync_out signal back over the substrate through the TSHDO_L pad to the TSHDI_R pad of the master IC chip 340. The master IC chip 340 receives this sense_sync_out signal, stops the timer, and records the corresponding round trip propagation time.

[0098] In one embodiment, reference Figure 7A-1 , 7A-2, 7A-3 and 7A-4, a timing signal (e.g., sense_sync_out signal 668) is transmitted from the waveform generator 612 of the master IC chip 340, from the sense_sync_out_r pin 716 of the master IC chip 340 to the sense_sync_in_l pin 720 of the slave IC chip 350 and then to the waveform generator 612a of the slave IC chip 350. When the timing signal is transmitted by the waveform generator 612, a counter is started. Then, the timing signal is transmitted from the waveform generator 612a, through the sense_sync_out_l pin 740 of the slave IC chip 350 to the sense_sync_in_r pin 742 of the master IC chip 340 and then into the waveform generator 612. When the signal timing signal is received, the waveform generator 612 stops the counter. The value of the counter corresponds to the amount of delay between the master IC chip 340 and the slave IC chip 350.

[0099] In another embodiment, the sense_sync_out signal is communicated to the left slave IC chip 360 via the SSO_L pad of the master IC chip 340. The sense_sync_out signal travels from the master IC chip 340 to the SSI_L pad of the left slave IC chip 360 across the substrate (e.g., substrate 320) on which each of the IC chips is mounted. The left slave IC chip 360 receives the sense_sync_out signal and routes the sense_sync_out signal back over the substrate via the TSHDO_R pad to the TSHDI_L pad of the master IC chip 340. The master IC chip 340 receives this sense_sync_out, stops the timer, and records the corresponding round trip propagation time.

[0100] In one embodiment, reference Figure 7B-1 , 7B-2, 7B-3 and 7B-4, a timing signal (e.g., sense_sync_out signal 668) is transmitted from the waveform generator 612 of the master IC chip 340, from the sense_sync_out_l pin 718 of the master IC chip 340 to the sense_sync_in_l pin 756 of the slave IC chip 360 and then to the waveform generator 612b of the slave IC chip 360. When the timing signal is transmitted by the waveform generator 612, a counter is started. Then, the timing signal is transmitted from the waveform generator 612b, through the sense_sync_out_r pin 752 of the slave IC chip 360 to the sense_sync_in_l pin 754 of the master IC chip 340 and then into the waveform generator 612. When the signal timing signal is received, the waveform generator 612 stops the counter. The value of the counter corresponds to the amount of delay between the master IC chip 340 and the slave IC chip 360.

[0101] In one embodiment, the signal propagation measurement on the main IC chip loopback path on the right side (e.g., path 811) can be referred to as M2M_R, and the measurement on the path on the left side (e.g., path 810) can be referred to as M2M_L. In addition, the round-trip signal propagation measurement from the main IC chip 340 to the slave IC chip 350 (e.g., path 812) can be referred to as M_RS_M. The round-trip signal propagation measurement from the main IC chip 340 to the slave IC chip 360 (e.g., path 813) can be referred to as M_LS_M. In addition, in one or more embodiments, paths 812 and 813 can be substantially symmetrical to each other.

[0102] In one embodiment, the signal propagation measurement M2M_R and / or the left side M2M_L is smaller than the signal propagation measurements M_RS_M and M_LS_M. For example, the signal propagation measurement M2M_R and / or the left side M2M_L may be about 10ns to about 30ns, and the signal propagation measurements M_RS_M and M_LS_M may be about 80ns to 100ns.

[0103] In one embodiment, the programmable delay from the master IC chip 340 to the right slave IC chip 350 may be determined by the following equation:

[0104] R DLY = 0. Equation 1

[0105] In one embodiment, the programmable delay from the master IC chip 340 to the left slave IC chip 360 may be determined by the following equation:

[0106] L DLY =.5*(M_RS_M-M_LS_M). Equation 2

[0107] In one embodiment, the programmable delay on the loopback path of the master IC chip 350 can be determined by the following equation:

[0108] LP DLY =.5*(M_RS_M+T sync )-M2M_R. Equation 3

[0109] Left delay (L DLY ) may correspond to a difference in propagation time for the routing of the right slave IC chip 350 and the left slave IC chip 360. Thus, the master IC chip 340 may be configured to generate a delay corresponding to a delay in the routing between the master IC chip 340 and the slave IC chips 350, 360. In one or more embodiments, the propagation times of different sides of the master IC chip 340 may be used to further generate a programmable delay.

[0110] In one or more embodiments, the master-to-master loopback path (M2M_T) delay is approximately 2 delayed touch analog control (TAC) clocks. The TAC clock can be used by the sensor module 204 and the sensor circuit 206 to control the collection of sensor data from the sensor electrode 205. In addition, in various embodiments, M2M_T+LP DLY Equal to M2LS+L DLY In addition, M2M_T can be a fixed delay of about 2, and L DLY It can be about 0.5*MLSM=M2LS or TchipL+TglassL+TchipR+Tsync+2. Therefore, L DLY It can be equal to TchipL+TglassL+TchipR+Tsync. TglassL and TglassR correspond to the routing delay between IC chips.

[0111] Figure 8B Various signal paths between the master IC chip 340 and each slave IC chip (e.g., the left slave IC chip 360 and the right slave IC chip 350) according to one or more embodiments are illustrated. For example, the master IC chip 340 transmits tshd, tsvd, sense_sync_out, and HSO calibration pulse output (hpo) signals to the slave IC chips 350, 360 via corresponding input / output pins on the slave IC chips 350, 360 and the master IC chip 340. In one embodiment, the sense_sync_out signal is provided via signal paths 824, 826, 836, and 838. The Tshd signal can be provided via signal paths 820, 822. The Tsvd signal can be provided via signal paths 828, 830. The hpo signal can be provided via signal paths 832 and 834.

[0112] Although four sets of input / output pins are used on either side of the master IC chip 340 to communicate with each of the slave IC chips 350, 360, in other embodiments, all of the input / output pins may be disposed along a common side of the master IC chip 340. In addition, instead of disposing one grouping of input / output pins along one side of the master IC chip 340, one or more sides of the master IC chip 340 may include multiple groups of input / output pins. In such an embodiment, each grouping of pins corresponds to a different slave IC chip that may be coupled to the master IC chip 340.

[0113] In one or more embodiments, the master IC chip 340 can be configured to synchronize the high speed oscillator (HSO) circuits of the slave IC chips 350 and 360. The HSO circuit can generate an HSO clock signal used by the digital circuits of the corresponding IC chip. In one embodiment, the TAC clock signal can be generated based on the HSO clock. Synchronizing the HSO clocks of the IC chips synchronizes the capacitive sensing across all IC chips (e.g., 340, 350, and 360). In one embodiment, the HSO clocks can be calibrated to substantially the same frequency. Each HSO clock can be calibrated to a frequency within a tolerance of about 0.2% relative to another. In other embodiments, each HSO clock is calibrated to a frequency within a tolerance of 0.2% different from each other, so that no error is introduced in the sensing data collected from the sensor electrode 205.

[0114] In one embodiment, in order to synchronize the HSO clock, the master IC chip 340 can, for example, transmit the Hcal_pulse_i / o pin ( Figure 3 ) transmits a periodic square wave signal 910 of programmable frequency to each of the slave IC chips 350 and 360. The slave IC chips 350 and 360 can use the square wave signal 910 as an accurate time base for the clock of the master IC chip 340. In one embodiment, when each of the slave IC chips 350 and 360 receives the first rising edge of the periodic square wave 910, the measurement cycle begins. The measurement cycle can correspond to the number of clock pulses of the clock of each of the n slave IC chips 350 and 360 that occurs after the first rising edge and before the falling edge is detected. In one embodiment, each of the slave IC chips 350 and 360 includes a register for counting the number of clock pulses. In one embodiment, the number of clock pulses is about 8. In other embodiments, other numbers of clock pulses can be used.

[0115] Fig. 9An example periodic square wave 910 is illustrated. Half a period of the square wave reference may be controlled by the HCAL_PULSE_DUR register of the main IC chip 340. In one embodiment, the HCAL_PULSE_DUR register is a 10-bit register. In other embodiments, registers of other sizes may be used. Equation 4 may be used to determine the frequency of the square wave pulse.

[0116] In one embodiment, on the rising edge of the square wave, each slave IC chip 350, 360 starts counting the number of rising edges of the HSO clock of each corresponding slave IC chip. If the slave IC chip HSO clock is fully aligned with the clock of the master IC chip, the slave IC chip will measure the 2*HALF_PULSE_DUR rising edges of its own HSO during one cycle of the square wave reference. The slave IC chip can be configured to count the number of its HSO rising edges over multiple cycles of the square wave. The number of cycles used to perform this measurement is controlled by HSO_CALIB_TIME. The total number of rising edges of the HSO clocks of the slave IC chips 350, 360 that occur during the measurement window is stored in a register called HSO_CALIB_CNT of the corresponding slave IC chip. The value of HSO_CALIB_CNT is governed by Equation 5:

[0117]

[0118] Each slave IC chip 350, 360 can measure HSO_CALIB_CNT during HSO calibration, and after dividing by the known term, the slave IC chip is left with . Therefore, each of the slave IC chips determines the relative error (fractional error) between the HSO clock and the HSO of each corresponding slave IC chip and the master IC chip. In this way, each of the slave IC chips can make corrections for the HSO error by adjusting the register that controls the HSO clock of the slave IC chip. For example, each slave IC chip can adjust the frequency modulation (FMOD) register to adjust the HSO clock. In one embodiment, the FMOD register is configured to shift the frequency of the HSO clock. In one or more embodiments, the FMOD register is configured to apply a shift of one or more Hz and / or KHz to the frequency of the HSO clock.

[0119] In one embodiment, when HSO_CALIB_CNT is 0, an indication may be generated that the slave IC chip has not received enough pulses from the master IC chip 340 to accurately perform HSO calibration. In one embodiment, HSO calibration is performed during power-up of the IC chip, after a reset of the IC chip, after power-down of the IC chip, and / or after multiple sensing bursts have been completed. In addition, HSO calibration may occur after a period of time to account for drift in the HSO clock of the master IC chip or the slave IC chip. In addition, tracking may be used to detect if the slave clock or the master clock has drifted and initiate HSO calibration.

[0120] Fig.10 A method 1000 for synchronizing a master IC chip (e.g., master IC chip 340) with a slave IC chip (e.g., slave IC chips 350, 360) is illustrated. At step 1010, a vertical timing signal (or TSVD) and a horizontal timing signal (or TSHD) are generated. In one embodiment, the master IC chip 340 receives display data from a master processor, processes the display data, and generates a vertical timing signal and a horizontal timing signal. The vertical timing signal may correspond to the start of a display frame, and the horizontal timing signal may correspond to the start of a display line. In addition, the vertical timing signal and the horizontal timing signal may include one or more pulses. In one or more embodiments, the capacitive frame may be initiated by the master IC chip and the slave IC chip using the vertical timing signal. At step 1020, the vertical timing signal and the horizontal timing signal are transmitted from the master IC chip to the slave IC chip. For example, the horizontal timing signal and the vertical timing signal may be transmitted from an input / output pin on the master IC chip 340 to a corresponding pin on the slave IC chip 350 and / or 360.

[0121] In step 1030, the master IC chip starts the acquisition of the first capacitive frame. In one embodiment, the master IC chip 340 starts the acquisition of the first capacitive frame based on at least one vertical timing signal and a horizontal timing signal. For example, the master IC chip 340 can start the acquisition of the first capacitive frame by detecting the rising edge of the vertical timing signal. The master IC chip can be configured to operate the sensor electrodes 205b for absolute capacitive sensing and / or transcapacitive sensing. For example, when the rising edge of the vertical timing signal is detected, the master IC chip 340 drives each of the sensor electrodes 205b with an absolute capacitive sensing signal.

[0122] At step 1040, the slave IC chip initiates the acquisition of the second capacitive frame. In one embodiment, the slave IC chips 350, 360 initiate the acquisition of the second capacitive frame based on at least one vertical timing signal and a horizontal timing signal provided by the master IC chip 340. For example, the master IC chip 340 may communicate the vertical and horizontal timing signals to the slave IC chip 350. The slave IC chip receives the vertical and horizontal timing signals and initiates the acquisition of the second capacitive frame by detecting the rising edge of the vertical timing signal and driving the first one or more of the sensor electrodes 205a with the sensing signal 352 to operate the sensor electrodes 205a for transcapacitive sensing and / or absolute capacitive sensing. For example, upon detecting the rising edge of the vertical timing signal, the slave IC chip 350 drives each of the sensor electrodes 205a with the absolute capacitive sensing signal.

[0123] Fig.11 The method 1100 illustrates the steps for synchronizing the sensing signals of two or more IC chips. In step 1110, the master IC chip generates a first delay and a second delay. The first delay corresponds to a signal propagation measurement within the master IC chip, and the second delay corresponds to a signal propagation measurement between the master IC chip and the slave IC chip. In one embodiment, the master IC chip transmits a first timing signal, which is fed back to the master IC350 chip via a loopback path and received by the waveform generator of the master IC chip. The timing difference between when the timing signal is transmitted and then received by the master IC chip 340 is used to determine the first delay. In one embodiment, the master IC chip 340 can be configured to start a counter when the timing signal is transmitted and stop the counter when the timing signal is received. The value of the counter can correspond to the first delay.

[0124] The second delay can be measured by transmitting a timing signal from the master IC chip 340 to the slave IC chip 350 and then back to the master IC chip 340. The difference in time from when the timing signal is transmitted from the master IC chip 340 and when the timing signal is received by the master IC chip can be used to determine the second delay. In one embodiment, the master IC chip 340 can be configured to start a counter when the timing signal is transmitted to the slave IC chip and stop the counter when the timing signal is received.

[0125] At step 1120 , the second delay is output from the master IC chip to the slave IC chip. For example, the second delay is output from the master IC chip 340 to the slave IC chip 350 .

[0126] At step 1130, a first sensing signal is generated by the master IC chip based at least in part on the first delay. The first delay can be used to delay when the first sensing signal 342 is output by the master IC chip 340 to the sensor electrode 205b. In one embodiment, the first pulse of the first sensing signal 342 is delayed by the first delay.

[0127] At step 1140, a second sensing signal is generated by the slave IC chip based at least in part on the second delay. The second delay can be used to delay when the second sensing signal 352 is output by the slave IC chip 350. In one embodiment, the first pulse of the second sensing signal 352 is delayed by the second delay so that the sensor electrodes 205a and 205b are driven at substantially the same time. For example, the difference in time between driving the sensor electrodes 205a and 205b is less than about 50ns.

[0128] Fig.12 A method 1200 for synchronizing sense bursts between two or more IC chips is illustrated. At step 1210, the master IC chip initiates a sense burst of a first sense signal based on a horizontal timing signal. For example, the master IC chip 340 is configured to detect a rising edge of the horizontal timing signal and generate a first burst of sense signals 342. The master IC chip 340 outputs the first sense signal to one or more sensor electrodes 205b.

[0129] At step 1220, the slave IC chip initiates a sensing burst of the second sensing burst. For example, the slave IC chip 350 is configured to detect the rising edge of the horizontal timing signal and generate a first burst of sensing signals 352 and output the first sensing signals to one or more sensor electrodes 205a. Since both the bursts of the first and second sensing signals are initiated based on the horizontal timing signal of the master IC chip 340, the initiation of the first and second sensing signals is synchronized.

[0130] Fig.13 The method 1300 of the embodiment of the present invention illustrates a method for synchronizing the clock signal of a master IC chip with the clock signal of a slave IC chip. At step 1310, a clock timing signal is output from the master IC chip to the slave IC chip. For example, the master IC chip 340 can output the clock signal of the master IC chip to the slave IC chip 350. At step 1320, the clock signal of the slave IC chip is compared with the clock timing signal. For example, the slave IC chip 350 can be configured to detect the first rising edge of the clock timing signal and determine how many rising edges of the clock signal of the slave IC chip occur before the falling edge of the clock timing signal is detected.

[0131] At step 1330, based on the comparison between the clock signal of the slave IC chip and the clock timing signal, the clock signal of the slave IC chip is changed. For example, if it is determined that the number of rising edges of the clock of the slave IC chip occurring between the rising edge and the falling edge of the clock timing signal has changed, the clock signal of the slave IC chip can be increased or decreased in frequency, respectively. For example, when the number of rising edges of the clock signal of the slave IC chips 350, 360 has been determined to have decreased, the frequency of the clock signal of the slave IC chips 350, 360 can be increased. Alternatively, when the number of rising edges of the clock signal of the slave IC chips 350, 360 has been determined to have increased, the frequency of the clock signal of the slave ICs 350, 360 can be reduced.

[0132] Therefore, the embodiments and examples set forth herein are presented in order to best explain embodiments according to the present technology and its specific applications, and thereby enable those skilled in the art to make and use the present disclosure. However, it will be appreciated by those skilled in the art that the foregoing description and examples are presented for illustration and example purposes only. The set forth description is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed.

[0133] In view of the foregoing, the scope of the present disclosure is determined by the following claims.

Claims

1. An input device, comprising: multiple sensor electrodes; a main integrated circuit chip, the main integrated circuit chip being communicatively coupled to the plurality of sensor electrodes, the main integrated circuit chip being configured to: generating a vertical timing signal and a horizontal timing signal; generating a first sense signal comprising a plurality of first sense bursts by adjusting a timing of a first sense burst of the plurality of first sense bursts based at least in part on a first delay associated with the master integrated circuit chip; as well as initiating acquisition of a first capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with the first sensing signal; as well as A first slave integrated circuit chip, the first slave integrated circuit chip being communicatively coupled to the master integrated circuit chip and to the plurality of sensor electrodes, the first slave integrated circuit chip being configured to: receiving the vertical timing signal and the horizontal timing signal from the master integrated circuit chip; generating a second sense signal comprising a plurality of second sense bursts by adjusting timing of one of the plurality of second sense bursts based at least in part on a second delay associated with a connection between the master integrated circuit chip and the first slave integrated circuit chip; as well as initiating acquisition of a second capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with the second sensing signal, Wherein each sensing burst corresponds to at least one positive and negative voltage transition.

2. The input device according to claim 1, wherein the main integrated circuit chip is further configured to: generating the first delay and the second delay, the first delay corresponding to a signal propagation measurement within the master integrated circuit chip and the second delay corresponding to a signal propagation measurement between the master integrated circuit chip and the first slave integrated circuit chip; and The second delay is output.

3. The input device according to claim 2, wherein the main integrated circuit chip is further configured to: determining the signal propagation measurement within the master integrated circuit chip by measuring a time difference between outputting a first timing pulse and receiving the first timing pulse within the master integrated circuit chip; and The signal propagation measurement between the master integrated circuit chip and the first slave integrated circuit chip is determined by measuring a time difference between outputting a second timing pulse to the first slave integrated circuit chip and receiving the second timing pulse from the first slave integrated circuit chip.

4. The input device of claim 3, wherein the first delay is a function of the signal propagation measurement within the host integrated circuit chip.

5. The input device according to claim 2, wherein: The first slave integrated circuit chip is further configured as: The second delay is received from the master integrated circuit chip.

6. The input device according to claim 1, wherein: The master integrated circuit chip is further configured to initiate at least one of the plurality of first sensing bursts based on the horizontal timing signal, and The first slave integrated circuit chip is further configured to initiate at least one of the plurality of second sensing bursts based on the horizontal timing signal.

7. The input device according to claim 1, wherein: The master integrated circuit chip is also configured to output a clock timing signal, and The first slave integrated circuit chip is further configured as: receiving the clock timing signal; comparing a clock signal of the first slave integrated circuit chip to the clock timing signal; and The clock signal of the first slave integrated circuit chip is changed based on the comparison.

8. The input device according to claim 1, further comprising: a second slave integrated circuit chip, the second slave integrated circuit chip being communicatively coupled to the master integrated circuit chip and to the plurality of sensor electrodes, the second slave integrated circuit chip being configured to: receiving the vertical timing signal and the horizontal timing signal from the master integrated circuit chip; and Acquisition of a third capacitive frame is initiated based on at least one of the vertical timing signal and the horizontal timing signal, wherein acquiring the third capacitive frame includes driving the plurality of sensor electrodes with a third sensing signal including one or more sensing bursts.

9. The input device of claim 8, wherein the first slave integrated circuit chip and the second slave integrated circuit chip are disposed on different sides of the master integrated circuit chip.

10. The input device of claim 1, wherein each of the plurality of sensor electrodes comprises at least one display electrode of a plurality of display electrodes of a display device, and wherein the master integrated circuit chip and the first slave integrated circuit chip are configured to drive the plurality of display electrodes to update the display device.

11. The input device of claim 1 , wherein driving the plurality of sensor electrodes through the master integrated circuit chip comprises driving a first portion of the plurality of sensor electrodes, and wherein driving the plurality of sensor electrodes through the first slave integrated circuit chip comprises driving a second portion of the plurality of sensor electrodes.

12. A method for synchronizing integrated circuit chips, the method comprising: generating a vertical timing signal and a horizontal timing signal using a main integrated circuit chip; transmitting the vertical timing signal and the horizontal timing signal from the master integrated circuit chip to a slave integrated circuit chip; generating, with the master integrated circuit chip, a first sense signal including a plurality of first sense bursts by adjusting a timing of a first sense burst of the plurality of first sense bursts based at least in part on a first delay associated with the master integrated circuit chip; generating, with the slave integrated circuit chip, a second sense signal comprising a plurality of second sense bursts by adjusting timing of a second sense burst of the plurality of second sense bursts based at least in part on a second delay associated with a connection between the master integrated circuit chip and the slave integrated circuit chip; initiating, by the master integrated circuit chip, acquisition of a first sensing measurement based on at least one of the vertical timing signal and the horizontal timing signal by driving a first sensor electrode with the first sensing signal; as well as initiating, by the slave integrated circuit chip, acquisition of a second sensing measurement based on at least one of the vertical timing signal and the horizontal timing signal by driving the first sensor electrode with the second sensing signal, Wherein each sensing burst corresponds to at least one positive and negative voltage transition.

13. The method of claim 12, wherein the first delay corresponds to a signal propagation measurement within the master integrated circuit chip and the second delay corresponds to a signal propagation measurement between the master integrated circuit chip and the slave integrated circuit chip, and The method further includes outputting the second delay from the master integrated circuit chip to the slave integrated circuit chip.

14. The method according to claim 13, further comprising: determining, by the master integrated circuit chip, the signal propagation measurement within the master integrated circuit chip by measuring a time difference between outputting a first timing pulse within the master integrated circuit chip and receiving the first timing pulse; as well as The signal propagation measurement between the master integrated circuit chip and the slave integrated circuit chip is determined by the master integrated circuit chip by measuring a time difference between outputting a second timing pulse to a first slave integrated circuit chip and receiving the second timing pulse from the first slave integrated circuit chip.

15. The method according to claim 13, further comprising: initiating, by the master integrated circuit chip, at least one sensing burst of the plurality of first sensing bursts based on the horizontal timing signal; as well as At least one sensing burst of the plurality of second sensing bursts is initiated by the slave integrated circuit chip based on the horizontal timing signal.

16. The method according to claim 12, further comprising: outputting a clock timing signal from the master integrated circuit chip to the slave integrated circuit chip; as well as comparing a clock signal of the slave integrated circuit chip with the clock timing signal; as well as The clock signal of the slave integrated circuit chip is changed based at least in part on the comparison.

17. A processing system for a display device having an integrated capacitive sensing device, the processing system comprising: a main integrated circuit chip, the main integrated circuit chip being communicatively coupled to the plurality of sensor electrodes, the main integrated circuit chip being configured to: generating a vertical timing signal and a horizontal timing signal; generating a first sense signal comprising a plurality of first sense bursts by adjusting a timing of a first sense burst of the plurality of first sense bursts based at least in part on a first delay associated with the master integrated circuit chip; initiating acquisition of a first capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with the first sensing signal; as well as A slave integrated circuit chip, the slave integrated circuit chip being communicatively coupled to the master integrated circuit chip and to the plurality of sensor electrodes, the slave integrated circuit chip being configured to: receiving the vertical timing signal and the horizontal timing signal from the master integrated circuit chip; generating a second sense signal comprising a plurality of second sense bursts by adjusting timing of one of the plurality of second sense bursts based at least in part on a second delay associated with a connection between the master integrated circuit chip and the slave integrated circuit chip; as well as initiating acquisition of a second capacitive frame based on at least one of the vertical timing signal and the horizontal timing signal by driving the plurality of sensor electrodes with the second sensing signal, Wherein each sensing burst corresponds to at least one positive and negative voltage transition.

18. The processing system of claim 17, wherein the master integrated circuit chip is further configured to: determining a signal propagation measurement within the master integrated circuit chip by measuring a time difference between outputting a first timing pulse within the master integrated circuit chip and receiving the first timing pulse; determining a signal propagation measurement between the master integrated circuit chip and the slave integrated circuit chip by measuring a time difference between outputting a second timing pulse to a first slave integrated circuit chip and receiving the second timing pulse from the first slave integrated circuit chip; as well as generating the first delay based at least on the signal propagation measurement within the host integrated circuit chip; generating the second delay based at least on the signal propagation measurement between the master integrated circuit chip and the first slave integrated circuit chip; and The second delay is output.

19. The processing system of claim 18, wherein: The slave integrated circuit chip is further configured as: The second delay is received from the master integrated circuit chip.

20. The processing system of claim 17, wherein: The master integrated circuit chip is further configured to: initiate at least one of the plurality of first sensing bursts of the first sensing signal based on the horizontal timing signal, and The slave integrated circuit chip is also configured to initiate at least one of the plurality of second sense bursts of the second sense signal based on the horizontal timing signal.

21. The processing system of claim 17, wherein: The main integrated circuit chip is also configured to: output a clock timing signal, and The slave integrated circuit chip is further configured as: receiving the clock timing signal; comparing a clock signal of the slave integrated circuit chip with the clock timing signal; and The clock signal of the slave integrated circuit chip is changed based on the comparison.

22. The processing system of claim 17, wherein driving the plurality of sensor electrodes through the master integrated circuit chip comprises driving a first portion of the plurality of sensor electrodes, and wherein driving the plurality of sensor electrodes through the slave integrated circuit chip comprises driving a second portion of the plurality of sensor electrodes.

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