Power semiconductor device with self-aligned source region

Abstract

A power semiconductor device has a semiconductor body, which is coupled to a first load terminal and a second load terminal and configured to conduct a load current between the terminals. The power semiconductor device also includes a first trench and a second trench extending into the semiconductor body in a vertical direction, the two trenches including corresponding trench sidewalls, the trench sidewalls facing each other laterally defining a mesa region along a first lateral direction; corresponding trench electrodes; a corresponding trench portion protruding from the surface of the semiconductor body by a protruding distance of at least 50 nm in the vertical direction, the trench electrode extending into the protruding trench portion; a source region of a first conductive type and a body region of a second conductive type, the two regions being arranged in the mesa region adjacent to the trench sidewall of the first trench, the first trench being configured to induce an inversion channel in the body region to control the load current in the mesa region, the source region being arranged adjacent to only one of the two trench sidewalls and spatially displaced from the other of the two trench sidewalls along the first lateral direction.

Description

Technical Field

[0001] The present description relates to embodiments of power semiconductor devices and embodiments of methods of processing power semiconductor devices. In particular, the present description relates to aspects of a novel source region formation process and corresponding devices. Background Art

[0002] Modern devices in automotive, consumer and industrial applications rely on power semiconductor switches for many functions such as converting electrical energy and driving motors or electric machines. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power converters and power supplies.

[0003] A power semiconductor device generally includes a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. In addition, the load current path may be controlled by an insulated electrode sometimes referred to as a gate electrode.

[0004] For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of an on state and an off state. In some cases, the gate electrode can be included in a trench of the power semiconductor switch, where the trench can exhibit, for example, a stripe configuration or a needle configuration.

[0005] It is generally desirable to keep losses such as switching losses (on-state losses during the on-state and off-state losses during the off-state of the power semiconductor device) low.

[0006] Furthermore, power semiconductor devices should generally exhibit high reliability. For this purpose, an accurate formation of the doped semiconductor regions, for example with regard to their position, is desired. Summary of the invention

[0007] According to one embodiment, a method for forming a power semiconductor device includes: providing a semiconductor body having a semiconductor body surface; forming an auxiliary layer above the semiconductor body surface, the auxiliary layer coupled to the semiconductor body and having an auxiliary layer surface; forming a plurality of grooves, the grooves extending from the auxiliary layer surface through the auxiliary layer into the semiconductor body in a vertical direction, wherein two groove sidewalls facing each other of two adjacent grooves in the grooves laterally define a mesa region of the semiconductor body along a first lateral direction, wherein the two adjacent grooves include corresponding groove portions protruding from the semiconductor body surface by a protruding distance of at least 50 nm in the vertical direction; filling the grooves with at least one trench filling material; planarizing the at least one trench filling material to expose the auxiliary layer; at least partially removing the auxiliary layer while maintaining the protruding groove portion including the at least one trench filling material; subjecting the mesa region to an implantation processing step for forming a semiconductor partition in the mesa region, wherein the implantation is inclined at an angle of at least 10° relative to the vertical direction, and wherein the protruding groove portions of the adjacent grooves are at least partially used as a mask during the inclined implantation.

[0008] According to another embodiment, a power semiconductor device includes a semiconductor body, which is coupled to a first load terminal and a second load terminal and is configured to conduct a load current between the terminals, wherein the power semiconductor device also includes: a first trench and a second trench extending into the semiconductor body in a vertical direction, wherein the two trenches include: corresponding trench sidewalls, wherein the trench sidewalls facing each other laterally define a mesa region of the semiconductor body along a first lateral direction; corresponding trench electrodes; corresponding trench portions, which protrude from the surface of the semiconductor body by a protrusion distance of at least 50 nm in the vertical direction, wherein the trench electrodes extend into the protruding trench portions; a source region of a first conductive type and a semiconductor body region of a second conductive type, the two regions being arranged in the mesa region adjacent to the trench sidewalls of the first trench, wherein the first trench is configured to induce an inversion channel in the body region to control the load current in the mesa region, wherein the source region is arranged adjacent to only one of the two trench sidewalls and is spatially displaced from the other of the two trench sidewalls along the first lateral direction.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The parts in the drawings are not necessarily drawn to scale, but the emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding parts. In the drawings:

[0011] Figure 1A -D schematically and exemplarily illustrates a method for processing a power semiconductor device according to one or more embodiments;

[0012] Figure 2A schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments;

[0013] Figure 2B schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; and

[0014] Figure 3 A portion of a vertical cross section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0016] In this regard, directional terms such as "top", "bottom", "below", "front", "rear", "front", "tail", "above", etc. may be used with reference to the orientation of the accompanying drawings. Because portions of the embodiments may be positioned in many different orientations, directional terms are used for illustrative purposes and are not limiting in any way. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be considered to be limiting, and the scope of the present invention is defined by the appended claims.

[0017] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation and is not meant to be a limitation of the invention. For example, a feature illustrated or described as part of one embodiment may also be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps are referred to by the same reference numerals in different drawings unless otherwise specified.

[0018] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. It may be, for example, a surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0019] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. In this document, the extension direction Z is also referred to as the "vertical direction Z".

[0020] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be adopted, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0021] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, partitions, portions or parts of a semiconductor device or different terminals of one or more devices or between a terminal or metallization or electrode and a portion or part of a semiconductor device. In addition, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, the transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0022] In addition, in the context of this specification, if not otherwise specified, the term "electrically insulated" is used in the context of its general effective understanding, and is therefore intended to describe two or more components that are located separately from each other and there is no ohmic connection connecting these components. However, components that are electrically insulated from each other can still be coupled to each other, such as mechanically coupled and / or capacitively coupled and / or inductively coupled. For example, two electrodes of a capacitor can be electrically insulated from each other, such as by insulation such as a dielectric, and at the same time mechanically and capacitively coupled to each other.

[0023] The specific embodiments described in this specification pertain to, but are not limited to, power semiconductor switches exhibiting a strip unit or honeycomb unit configuration, such as power semiconductor devices that can be used within a power converter or power supply. Thus, in one embodiment, such a device can be configured to carry a load current to be fed to a load and / or provided by a power source. For example, a power semiconductor device can include one or more active power semiconductor cells, such as a monolithic integrated diode cell (e.g., a monolithic integrated cell of two anti-series connected diodes), a monolithic integrated transistor cell (e.g., a monolithic integrated IGBT cell), and / or derivatives thereof. Such a diode / transistor cell can be integrated in a power semiconductor module. A plurality of such cells can constitute a cell field arranged together with an active region of a power semiconductor device.

[0024] The term "power semiconductor device" as used in this specification is intended to describe a semiconductor device on a single chip having a high voltage cutoff and / or a high current carrying capability. In other words, such a power semiconductor device is intended for high currents (e.g. up to tens or hundreds of amperes) and / or high voltages (typically above 15V, more typically 100V and above, e.g. up to at least 400V or even higher, e.g. up to at least 3kV, or even up to 10kV or higher), typically in the ampere range.

[0025] For example, the power semiconductor device described below may be a semiconductor device exhibiting a stripe cell configuration or a honeycomb (column / needle) cell configuration, and may be configured to be used as a power component in low, medium, and / or high voltage applications.

[0026] For example, the term "power semiconductor device" as used in this specification is not directed to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0027] Figure 2A and Figure 2B Both schematically and exemplarily illustrate a power semiconductor device 1 according to one or more embodiments. Figure 2A and 2B Both.

[0028] The power semiconductor device 1 has a semiconductor body 10 which is coupled to a first load terminal 11 and a second load terminal 12 and is configured to conduct a load current between said terminals 11 , 12 .

[0029] For example, the power semiconductor device 1 has a MOSFET configuration or an IGBT configuration or an RC-IGBT configuration or a configuration derived from one of these basic power semiconductor device configurations, such as an RC-IGBT with diode control (RCDC) configuration. Therefore, the first load terminal 11 may be a source terminal or an emitter terminal, and the second load terminal 12 may be a drain terminal or a collector terminal.

[0030] The power semiconductor device 1 may have a vertical configuration, according to which the semiconductor body 10 is sandwiched between the first load terminal 11 and the second load terminal 12 , and according to which the load current flows in a direction substantially parallel to the vertical direction Z.

[0031] Depending on the configuration of the power semiconductor device 1 , the semiconductor body 10 is provided with a plurality of doping regions.

[0032] For example, a major portion of the semiconductor body 10 is formed by a drift zone 103 of the first conductivity type, wherein the dopant concentration of the drift zone 103 is relatively low.

[0033] The drift region 103 may be coupled to the second load terminal 12 via a first doped region 108, which may include a first emitter region of a second conductivity type arranged to be in electrical contact with the second load terminal 12, for example in the case of an IGBT configuration. Furthermore, the first doped region 108 may include a second emitter region of the first conductivity type also arranged to be in electrical contact with the second load terminal 12, for example in order to provide an RC-IGBT configuration. In addition to at least one of the first emitter region and the second emitter region, the first contact region 108 may include a field stop region of the first conductivity type, wherein the field stop region may have a dopant of the first conductivity type with a higher dopant concentration than the drift region. In another embodiment, for example in the case of a MOSFET configuration, the first doped region 108 is entirely a region of the first conductivity type. In the context of IGBTs, RC-IGBTs and MOSFETs, the general function and configuration of the first doped region 108 is known to the skilled person, and according to the embodiments described herein, no deviation is made from the general function and configuration of the first doped region 108.

[0034] A plurality of power cells may be formed in the portion of the semiconductor body 10 bordering the first load terminal 11. For example, the power semiconductor device 1 comprises a plurality of equally configured power cells, for example at least 10, 100 or 1000 power cells, or at least 10,000 power cells or even more than 100,000 power cells.

[0035] For example, each power cell comprises a plurality of trenches, for example at least one or more first trenches 14 and at least one or more second trenches 15, each trench extending from the surface 100 of the semiconductor body 10 along a vertical direction Z, wherein the trenches 14 and 15 laterally define a mesa region 105 along a first lateral direction X. Of course, each power cell may comprise more than the two trenches 14 and 15 shown and thus also more than just one mesa region 105.

[0036] The grooves 14 and 15 may exhibit a stripe configuration according to which the lateral extension along the second lateral direction Y is significantly greater than the total extension along the first lateral direction X, i.e. significantly greater than the groove width. In one embodiment, the grooves of the power cells all exhibit the same groove width (in the first lateral direction X), the same groove depth (in the vertical direction Z), and are spatially displaced from each other along the first lateral direction X according to a fixed pattern.

[0037] The trench width may be defined as the distance between two trench sidewalls 144 ( 154 , respectively) of each trench 14 ( 15 , respectively), and the trench depth may be defined as the distance between the semiconductor body surface 100 and the trench bottom 145 ( 155 , respectively).

[0038] Each trench 14 , 15 may include a respective trench electrode 141 , 151 and a respective trench insulator 142 , 152 which insulates the trench electrode 141 , 151 from the semiconductor body 10 .

[0039] The plurality of doped regions of the semiconductor body 10 may include a semiconductor source region 101 of a first conductivity type and a semiconductor body region 102 of a second conductivity type, both regions 101 , 102 being arranged in a mesa region 105 adjacent to a trench sidewall 144 of the first trench 14 and electrically connected to the first load terminal 11 .

[0040] The semiconductor source region 101 typically, but not necessarily, exhibits a significantly higher dopant concentration than the drift region 103. The source region 101 is arranged in electrical contact with the first load terminal 11. For example, the semiconductor source region 101 forms a portion of a surface of a mesa region 105 that borders the first load terminal 11. The first trench 14 may, for example, have the semiconductor source region 101 arranged adjacent to one of its trench sidewalls 144, as shown, which will become more apparent from the subsequent description.

[0041] The semiconductor body region 102 (of the second conductivity type) typically, but not necessarily, exhibits a significantly higher dopant concentration than the drift zone 103, wherein the dopant concentration of the body region 102 may vary. For example, a sub-portion of the body region 102 (also referred to as body contact region) 1021 that borders the first load terminal 11 may be more strongly doped than another sub-portion of the body region 102, as will be explained in more detail below.

[0042] The body region 102 is arranged in electrical contact with the first load terminal 11. For example, the semiconductor body region 102 also forms a portion of a surface of a mesa region 105 bordering the first load terminal 11. For example, a subportion 1021 of the semiconductor body region 102 bordering the first load terminal 11 has a relatively higher dopant concentration than the rest of the semiconductor body region 102.

[0043] As shown, the semiconductor body region 102 may extend over the entire width of the mesa region 105. The semiconductor body region 102 isolates the semiconductor source region 101 from the semiconductor drift region 103. The transition between the semiconductor body region 102 and the drift region 103 forms a pn junction 1025, wherein the pn junction 1025 may be arranged within the mesa region 105.

[0044] The first trench 14 is configured to induce an inversion channel in the body region 102, for example in a sub-portion generally referred to as a channel region, to control a load current in the plane region 105. For example, an inversion channel is formed in the channel region of the body region 102, wherein the channel region may be arranged adjacent to the trench sidewall 144 and may extend below the semiconductor source region 101.

[0045] By controlling the load current in each mesa region 105 having the configuration just described (in particular: both the source region and the body region are electrically connected to the first load terminal 11 ), the load current of the power semiconductor device 1 can be controlled.

[0046] For example, the trench electrode 141 of the first trench 14 is a gate electrode, which receives a gate signal from a driver (not shown), which is formed, for example, by applying a voltage between a gate terminal (not shown) and the first load terminal 11, where the gate terminal can be electrically connected to the trench electrode 141 of the first trench 14.

[0047] In the context of IGBTs, RC-IGBTs and MOSFETs, the configuration of pn isolation within mesa regions laterally defined by trenches as described above is known to the skilled person and according to the embodiments described herein the general function and configuration of such pn isolation is not deviated from.

[0048] Each power cell of the power semiconductor device 1 may include more than just one mesa region 105 (e.g., at least two or three or four mesa regions 105 or even more than four mesa regions 105) and a corresponding number of grooves. However, it should be understood that not every mesa region 105 of a corresponding one of the power cells must be configured for conducting a load current. More specifically, according to some embodiments, one or more mesa regions 105 of a corresponding one of the power cells are not configured for conducting a load current, wherein such a configuration may be implemented in different ways. For example, if not electrically connected to the first load terminal 11, the (not shown) mesa region is not configured for conducting a load current. In addition or alternatively, if a source region is not provided, the mesa region is not configured for load current conduction.

[0049] In addition, regarding the exemplary embodiment of the mesa region 105 disposed between the first trench 14 and the second trench 15, Figure 2A As shown in FIG. 1B , it should be understood that along the second lateral direction Y, the mesa region 105 can change its configuration regarding its ability to conduct load current. For example, this can be achieved by configuring the semiconductor source region 101 along the second lateral direction Y.

[0050] At least one or more of the optional other second trenches 15 of each power cell (eg, second trenches 15 adjacent to the mesa region 105 including the source region 101 ) may be source trenches, whose trench electrodes 151 are electrically connected or at least electrically coupled to the first load terminal 11 .

[0051] One or more of the optional (not shown) other second trenches 15 may, but need not necessarily, be different from both the source trench and the gate trench. For example, additional trench types may be provided for forming power cells, such as trenches with electrically floating electrodes, trenches with gate electrodes that are not arranged adjacent to semiconductor source regions (so-called dummy gate trenches), etc.

[0052] Therefore, in view of the above explanations about different configurations of mesa regions and trenches, the power cell of the semiconductor device 1 can be configured according to various so-called contact schemes, i.e., schemes that define what type of trench is arranged adjacent to what type of mesa region. However, in the context of IGBTs, RC-IGBTs and MOSFETs, a variety of different contact schemes are known to the skilled person, and the embodiments described herein are not limited to a specific contact scheme.

[0053] For example, according to embodiments described herein, the load current conducting mesa region 105 is adjoined by a first trench 14 implemented as a gate trench and a second trench 15 implemented as a source trench. The additional second trench 15 of each power cell, if included, may include one or more of a dummy gate trench, a source trench, and a floating trench.

[0054] The semiconductor body surface 100 may be covered by an insulating structure 17 , 19 having an opening 171 (see Figure 1D ), so as to allow electrical connection between the first load terminal 11 and the mesa region 105.

[0055] The insulating structures 17, 19 may include or consist of various electrically insulating materials. For example, the insulating structures 17, 19 may include or consist of oxides and / or low-k dielectric materials. In addition, the insulating structures 17, 19 may exhibit a thickness of at least 200 nm, or at least 400 nm, or at least 450 nm along the vertical direction Z. The insulating structures 17, 19 may include multiple insulating sublayers, such as TEOS (tetraethyl orthosilicate) or spin-on glass (e.g. BPSG, borophosphosilicate glass) or another silicate glass sublayer or another oxide sublayer. Other aspects of the insulating structures 17, 19 will be explained below.

[0056] The insulation structure 17 , 19 is arranged above the semiconductor body surface 100 and may have a plurality of openings 171 , wherein the first load terminal 11 may extend into the openings 171 to contact both the semiconductor body region 102 and the semiconductor source region 101 of the mesa region 105 of the power supply.

[0057] For example, Figure 2B As shown, the electrical contact between the first load terminal 11 and the mesa region 105 may be realized as a planar contact which may be arranged substantially coplanar with the semiconductor body surface 100 .

[0058] In another embodiment, as in Figure 2A As schematically and exemplarily illustrated in FIG. 1 , electrical contact between the first load terminal 11 and the mesa region 105 may be achieved by employing a contact trench 111 extending from the level of the semiconductor body surface 100 in the vertical direction Z into the mesa region 105. For example, such a contact trench 111 may be etched into the semiconductor body 10 and subsequently filled with an electrically conductive material.

[0059] If implemented, the contact trench 111 may extend further into the semiconductor body 10 than the source region 101 in the vertical direction Z. The contact trench 111 may, for example, be etched by implantation as further described below before or after forming the source region 101 .

[0060] The semiconductor source region 101 may be based on a first implant material or a set of first implant materials. The semiconductor body region 102 may be based on a second implant material or a set of second implant materials. Thus, in order to form the semiconductor source region 101 and the semiconductor body region 102, one or more implantation processing steps may be performed. The implantation processing steps may be combined with one or more thermal diffusion steps (also referred to herein as thermal annealing steps).

[0061] Various aspects described herein relate to forming the mesa region 105 including the semiconductor source region 101 and the semiconductor body region 102 by at least one implantation processing step in a manner that allows for more reliable achievement of proper electrical contact between the first load terminal 11 and the mesa region 105 .

[0062] For example, according to one embodiment, a method for forming a power semiconductor device includes: providing a semiconductor body having a semiconductor body surface; forming an auxiliary layer above the semiconductor body surface, the auxiliary layer coupled to the semiconductor body and having an auxiliary layer surface; forming a plurality of grooves, the grooves extending from the auxiliary layer surface through the auxiliary layer into the semiconductor body in a vertical direction, wherein two groove sidewalls facing each other of two adjacent grooves in the grooves laterally define a mesa region of the semiconductor body along a first lateral direction, wherein the two adjacent grooves include corresponding groove portions protruding from the semiconductor body surface by a protruding distance of at least 50 nm in the vertical direction; filling the grooves with at least one trench filling material; planarizing the at least one trench filling material to expose the auxiliary layer; at least partially removing the auxiliary layer while maintaining the protruding trench portion including the at least one trench filling material; subjecting the mesa region to an implantation processing step for forming a semiconductor partition in the mesa region, wherein the implantation is inclined at an angle of at least 10° relative to the vertical direction, and wherein the protruding trench portions of the adjacent trenches are at least partially used as a mask during the inclined implantation.

[0063] For example, now refer to Figure 1AThe provision (step 20) of a semiconductor body 10 having a surface 100 can be performed in a conventional manner known to the skilled person. The semiconductor body 10 can be provided as part of a semiconductor wafer.

[0064] Still referring to step 20, an auxiliary layer 19 is formed above the semiconductor body surface 100, the auxiliary layer 19 being coupled to the semiconductor body 10 and having an auxiliary layer surface 190. The auxiliary layer 19 may include a first sublayer 191 in contact with the semiconductor body surface 100 and a second sublayer 192 above the first sublayer 191. The first sublayer 191 may be different from the second sublayer 192; for example, the first sublayer 191 and the second sublayer 192 are formed by separate processing steps. The first sublayer 191 may be an oxide layer. The second sublayer 192 may be formed by depositing a second sublayer material. At least one of the first sublayer 191 and the second sublayer 192 may be electrically insulating. For example, both the first sublayer 191 and the second sublayer 192 are electrically insulating. Thus, the auxiliary layer 19 may be an electrically insulating auxiliary layer 19. For example, the first sublayer 191 includes an oxide. The second sublayer 192 may include silicon nitride (SiN). The second sublayer 192 may have a thickness in the vertical direction Z of at least 50 nm, at least 100 nm, or at least 250 nm. For example, the thickness of the second sublayer 192 is greater than the thickness of the first sublayer 191. For example, the first sublayer 191 may be a thin oxide layer having a thickness in the range of a few nm, for example in the range of 5 nm to 15 nm. In another embodiment, the auxiliary layer 19 may include more than two sublayers.

[0065] The formation of a plurality of trenches 14, 15 (see step 21) can be performed in a conventional manner known to the skilled person. The trenches 14, 15 extend from the auxiliary layer surface 190 along the vertical direction Z through the auxiliary layer 19 into the semiconductor body 10, wherein two trench sidewalls 144, 154 of two adjacent trenches 14, 15 of the trenches facing each other laterally delimit the mesa region 105 of the semiconductor body 10 along the first lateral direction X. Two adjacent trenches 14, 15 comprise respective trench portions 149, 159 which protrude from the semiconductor body surface 100 by a protrusion distance A of at least 50 nm for the vertical direction Z.

[0066] Forming the trenches 14, 15 may include performing one or more etching process steps, wherein both the auxiliary layer 19 (including, for example, the first sublayer 191 and the second sublayer 192) and the semiconductor body 10 are exposed to the one or more etching process steps. Thus, the trench sidewalls 144 and 154 extend along the vertical direction Z, but only within the semiconductor body 10, but also within the auxiliary layer 19. Along the vertical direction Z, the trenches 14, 15 may be defined by respective trench bottoms 145 and 155.

[0067] The total vertical extension of the trenches 14 and 15 may be identical to each other and may be in the range of 1 μm to 15 μm, for example about 5 μm. The total vertical extension may be measured as the distance between the auxiliary layer surface 190 and the respective trench bottom 145 / 155 .

[0068] In one embodiment, the width of the trenches 14 and 15 in the auxiliary layer 19 along the first lateral direction X at least substantially corresponds to the width of the trenches 14 and 15 in the semiconductor body 10 along the first lateral direction X.

[0069] For example, the protrusion distance A is at least substantially the same as the thickness of the auxiliary layer 19, i.e., at least substantially the same as the distance between the auxiliary layer surface 190 and the semiconductor body surface 100 along the vertical direction Z. According to the above exemplary thicknesses of the auxiliary layer 19, the protrusion distance A may correspond to at least 50 nm, at least 100 nm, or at least 250 nm.

[0070] Reference now Figure 1B Once the trenches 14, 15 are formed, for example by applying the one or more etching process steps, the trenches 14, 15 may be filled with at least one trench filling material, which is illustrated in steps 22 and 23. Filling (steps 22, 23) the trenches 14, 15 with the at least one trench filling material may include forming trench electrodes 141, 151 in the trenches 14, 15, wherein the trench electrodes 141, 151 form part of the protruding trench portions 149, 159 and protrude from the semiconductor body surface 100 by the protrusion distance A with respect to the vertical direction Z.

[0071] As described above, the protrusion distance A may correspond to at least 50 nm, at least 100 nm or at least 250 nm. For example, the protrusion distance A corresponds to, for example, a region in which the semiconductor source region 101 (see Figure 2A / B) is at least half of the width of the mesa region 105 in the first lateral direction X measured at a vertical level of the first lateral direction X.

[0072] However, before forming the trench electrodes 141 and 151, filling the trenches 14, 15 may include forming respective trench insulators 142 / 152 in the trenches 14 and 15. This may be achieved, for example, by performing at least one of an oxidation process step and a deposition process step. For example, within the scope of this trench filling step, a further sublayer 193 may be formed on top of the auxiliary layer 19, wherein the further sublayer 193 is seamlessly coupled to the trench insulators 142 and 152. That is, the further sublayer 193 and the trench insulators 142, 152 may be formed by the same (one or more) process steps.

[0073] In addition, before or after forming the trench electrodes 141 and 151, the method may include performing at least one planarization step to expose the auxiliary layer 19, i.e., its auxiliary layer surface 190, as shown in step 23. Therefore, it should be understood that filling the trenches 14, 15 may include at least two separate steps, and forming the trench insulators 142, 152 and forming the trench electrodes 141, 151, wherein a planarization step may be performed between or after these two separate steps. For example, the planarization step may include completely or at least partially removing the third sublayer 193.

[0074] For example, during the planarization process, both the first sublayer 191 and the second sublayer 192 are maintained, wherein the thickness of the second sublayer 192 can be slightly reduced due to planarization, for example, by about 5 nm to 20 nm. However, even after planarization, the thickness of the second sublayer 192 can be equivalent to at least 50 nm, equivalent to at least 100 nm, or equivalent to at least 200 nm.

[0075] Furthermore, it should be understood that the concept of "filling the trenches" may mean that the trenches 14, 15 are completely filled, for example by the trench insulators 142, 152 and the trench electrodes 141, 151. In another embodiment, the trenches 14, 15 are not completely filled. For example, within the scope of the present embodiment, one or more void spaces may remain in the trenches 14, 15, for example, a void space in at least one of the trench electrodes 141, 151. However, the concept of "filling the trenches" with respect to all embodiments described herein may mean that both the trench insulators 142, 152 and the trench electrodes 141, 151 extend from the semiconductor body surface 100 with respect to the vertical direction Z so as to at least partially fill the protruding trench portions 149, 159. That is, according to the embodiments described herein, both the trench insulators 142, 152 and the trench electrodes 141, 151 may protrude from the semiconductor body surface 100 with respect to the vertical direction Z by substantially the protrusion distance A of at least 50 nm, at least 100 nm or at least 250 nm. As described above, the distance may be measured as the distance between the auxiliary layer surface 190 (which may be slightly leveled down due to planarization) and the semiconductor body surface 100 .

[0076] Reference now Figure 1C, the method for processing a power semiconductor device may be continued by at least partially removing (see step 24) the auxiliary layer 19 while maintaining the protruding trench portions 149, 159 (e.g. the portions of the trench insulators 142, 152 and the portions of the trench electrodes 141, 151) comprising at least one trench filling material. For example, partially removing the auxiliary layer 19 may comprise removing only the second sublayer 192 while maintaining both the first sublayer 191 and the trench insulators 142, 152 protruding from the semiconductor body 10, as Figure 1C This partial removal of the auxiliary layer 19 may, for example, comprise a selective etching process step, for example an isotropic etching process step.

[0077] The following processing stage (see step 25) is directed to forming one or more semiconductor sub-regions / areas in the mesa region 105. For example, this stage 25 comprises forming in the mesa region 105 a semiconductor source region 101 of a first conductivity type and a semiconductor body region 102 of a second conductivity type.

[0078] As already mentioned above, the semiconductor source region 101 may be based on a first implant material or a group of first implant materials. The semiconductor body region 102 may be based on a second implant material or a group of second implant materials. Therefore, in order to form the semiconductor source region 101 and the semiconductor body region 102, one or more implantation processing steps may be performed. The implantation processing steps may be combined with one or more thermal annealing steps.

[0079] Forming the semiconductor body region 102 of the second conductivity type in the mesa region 105 may involve standard processes known to the skilled person, such as a first blanket (i.e., unmasked with respect to the mesa region) implantation process step, e.g., a non-tilted implantation. During the formation of the body region 102 by implantation, which may be performed, for example, after partial removal of the auxiliary layer 19 and before performing the tilted (source) implantation 251, the first sublayer 191 may remain and serve as a stray oxide, e.g., in order to avoid the effect commonly referred to as channeling.

[0080] Regardless of how the semiconductor body region 102 is formed, according to some or all embodiments described herein, and before performing the next processing steps to follow the body region formation process, it can be ensured that the surface of the semiconductor body region 102 in the mesa region 105 at least partially or completely forms a mesa region surface. Furthermore, it should be noted that further processing steps can be performed at a subsequent stage to further modify the body region 102, for example by performing a masked or unmasked body contact implantation, in order to provide a portion that subsequently interfaces with the first load terminal 11 or with the contact trench 111 (with respect to Figure 2A / 2B mentioned, that is, the body region 102 with high dopant concentration in the body contact region 1021).

[0081] Before or after forming the body region 102 (typically: after forming the body region 102), the mesa region 105 is subjected to an implantation treatment step 25 for forming the semiconductor subregion 101 in the mesa region 105, wherein the implantation 251 is tilted at an angle of at least 10°, at least 20°, at least 35° or at least 45° with respect to the vertical direction Z, wherein the protruding trench portions 149, 159 of the adjacent trenches 14, 15 at least partially serve as a mask during the tilted implantation, as Figure 1C As shown in the figure exemplarily.

[0082] For example, the tilt angle applied during the implantation 251 for forming the semiconductor partitions 101 may be in the range of 10° to 60°, wherein the semiconductor wafer and / or the implantation apparatus may be tilted in order to achieve said tilt angle.

[0083] For example, during the tilted implantation 251, only the first sublayer 191 of the auxiliary layer 19 is present above the mesa region 105. Before or after the tilted implantation, the first sublayer 191 and the protruding groove portions 149 and 159 may be covered by an additional sublayer 194. For example, the additional sublayer 194 is provided before the tilted implantation, wherein the additional sublayer 194 may include an insulating material. For example, the additional sublayer 194 serves as a liner or spacer. It is clear to the skilled person that the sublayer 194 may affect the geometry during the implantation 251 and may therefore define the lateral position and size of the semiconductor partition 101 relative to the grooves 14 and 15.

[0084] For example, during the implantation 251 for forming the semiconductor partition 101, with respect to the first lateral direction X, only the protruding trench portions 149, 159 (and optionally the additional sublayer 194) are used as a mask, but no additional or "lithographic mask". In fact, the protruding trench portions 149, 159 (and optionally the additional sublayer 194) are not masks in the strict sense, but are used as masks in combination with the tilted implantation 251. However, it should be understood that, as further described above, the semiconductor partition 101 can be structured along the second lateral direction Y. Therefore, in order to realize such a structure along the second lateral direction Y, a corresponding mask can be used during the tilted implantation 251.

[0085] In one embodiment, the implantation 251 is performed such that the semiconductor partition 101 is arranged adjacent to only one of the two trench sidewalls, for example adjacent to only the trench sidewall 144 and spatially displaced from the other of the trench sidewalls, for example the trench sidewall 154, along the first lateral direction X, also as Figure 1C This spatial shift is achieved due to at least the protruding trench portions 149, 159 (which can be covered by the additional sublayer 194) used as a mask basis and the tilted implantation 251. Thus, from the other trench sidewall (about Figure 1CThe amount of spatial displacement of the intermediate mesa region 105 (154) in the first lateral direction X can be adjusted by adjusting at least one of the tilt angle applied during the tilt implantation 251 (a larger tilt angle results in a larger spatial displacement along the first lateral direction X) and the protrusion distance A (a larger protrusion distance A results in a larger spatial displacement along the first lateral direction X).

[0086] For example, the protrusion distance A and the tilt angle are set so that the semiconductor partition 101 extends no more than 80%, no more than 70% or no more than 60% of the width of the mesa region 105 along the first lateral direction X. As described above, this can be achieved by performing the implantation 251 such that a sub-portion of the mesa region 105 adjacent to the other of the two trench sidewalls 154 is not subjected to the implantation 251. The sub-portion may include a portion of the mesa region that is “shadowed” by one or more of the protruding trench portions 149, 159.

[0087] For example, the semiconductor subregion 101 is a semiconductor source region of the first conductivity type. Below, therefore, it is referred to as the semiconductor source region 101. As further described above, the semiconductor body region 102 can be formed before the semiconductor source region 101. For example, the semiconductor body region 102 is not constructed with respect to the mesa region 105, and the semiconductor body region 102 can be exposed to the tilted implantation 251. That is, the semiconductor body region 102 can extend along the entire width of the mesa region 105 in the first lateral direction X, and can be arranged to contact both the trench sidewalls 144, 154 that laterally define the mesa region 105.

[0088] Reference now Figure 1D The method may further include, at stage 26, forming a vertical direction Z extending into the mesa region 105 between adjacent trenches 14 and 15 ( Figure 1D , Figure 2A ) or only down to the semiconductor body surface 100 ( Figure 2B , for example terminating at the semiconductor body surface 100 ). For example, the contact trench 111 extends in the vertical direction Z approximately as far as the source region 101 , or further than the source region 101 , for example to border both the source region 101 and the body region 102 .

[0089] Still referring to stage 26, forming the contact groove 111 may include forming a spacer element 18 laterally adjacent to the protruding groove portions 149, 159. If previously formed, the spacer element 18 may be arranged laterally adjacent to the first sublayer 194, as exemplarily illustrated. Forming the spacer element 18 may be performed according to one or more processing steps known to the skilled person, which may include depositing a spacer element material and then performing an anisotropic etching processing step so that only the spacer elements 18 shown remain. For example, forming the spacer element 18 according to a self-aligned process may include a conformal deposition processing step (e.g., over the entire wafer surface) and a subsequent anisotropic (e.g., dry) etching processing step.

[0090] For example, the spacer elements 18 include or are made of silicon nitride SiN, for example in order to facilitate a subsequent selective dry etching.

[0091] Therefore, the spacer elements 18 are self-aligned with respect to the trench locations and also with respect to the mesa regions; i.e., with respect to the active area of ​​the semiconductor device including one or more power cells, no mask needs to be employed to form the spacer elements 18. In short: according to one or more embodiments, the spacer elements 18 can be formed by a self-alignment process with respect to the protruding trench portions 149, 159.

[0092] For example, after forming the spacer elements 18, a contact implant (eg, non-tilted) may be performed to produce the body contact regions 1021 (see Figure 2A ). However, regarding Figure 2B It should be noted that the body contact region 1021 may also be formed by a tilted implant, e.g. a tilted implant tilted with respect to the tilt direction applied during the tilted (source) implant 251. Therein, during the contact implant, the protruding trench portions 149, 159 are also used as a mask together with the optional spacer elements 18.

[0093] Referring to stage 27, forming the contact groove 111 may include forming an intermediate insulating layer 17 over the protruding groove portions 149, 159. The intermediate insulating layer 17 may subsequently serve as isolation (and / or as support for) the conductive material forming the first load terminal 11, as will be explained in further detail below.

[0094] For example, the contact groove 111 is formed ( Figure 2A ) may include multiple etching steps, such as a first etching step that etches down to the spacer elements 18, a second etching step that is selective to these spacer elements 18 (i.e., does not etch them, but only removes the isolation material 17) and etches down to the surface 100 of the mesa region 105, and a third optional etching step that forms a defined contact groove in the mesa region 105.

[0095] like Figure 2A and 2B , the shape and depth of the contact groove 111 may vary. However, according to the embodiments described herein, the processing method results in a contact groove 111 that is self-aligned with the trench sidewalls 144, 145 and has a CD (critical dimension) defined by the spacer elements 18 when in contact with the mesa region 105 and can be placed in the middle / center of the mesa region with respect to the first lateral direction X.

[0096] Thus, forming the contact groove 111 may include at least one etching process step for causing the formation of an opening 171 through the intermediate insulating layer 17. The opening 171 is laterally defined by the spacer elements 18 and extends into the mesa region 105, thereby forming the contact groove 111. At least one etching process step may be or include a selective etching process step in which the spacer elements 18 are not etched away. Thus, with respect to the above explanations about the spacer elements 18, the formation of the contact groove 111 may be performed according to a self-aligned process. At least with respect to the first lateral direction X, the position of the contact groove 111 is defined by the spacer elements 18. That is, the etching process step performed to form the opening 171 does not necessarily have to be constructed with the pitch accuracy necessary for the contact groove 111, but may be constructed with a lower accuracy, thereby ensuring that only the opening defined by two adjacent spacer elements 18 above the mesa region 105 is subjected to etching.

[0097] In one embodiment, the contact trench 111 is self-aligned with the mesa region 105 and the trench sidewalls 144, 154 independent of the overlay error of the photolithography mask process, which may mean that the contact trench 111 is placed in the center with respect to the width of the mesa region 105. The thickness of the spacer element 18 may define the distance and size of the opening 171.

[0098] refer to Figure 2A , which schematically and exemplarily illustrates an intermediate result of the method of processing a semiconductor device described herein and explained above, a subsequent processing step may include forming a first load terminal 11 by depositing a conductive material over an intermediate insulating layer 17. The conductive material extends into a contact 111 to electrically contact the semiconductor source region 101. For example, the conductive material contacts both the semiconductor source region 101 and the semiconductor body region 102 (e.g., with a body contact region 1021). Over the intermediate insulating layer 17, the deposited conductive material may form a conductive layer 112.

[0099] If through Figure 2A As shown in FIG. 1B , the contact groove 111 may be formed as a flat contact (eg, a groove extending from the conductive layer 112 downward along the vertical direction Z to the surface 100 of the semiconductor body) Figure 2B), or formed as a mesa region penetrating contact further extending into the mesa region 105 along the vertical direction Z ( Figure 2A ). However, both variations of the contact groove 111 can be formed according to the self-alignment process.

[0100] about Figure 2B It should be noted again that the body contact region 1021 can also be formed by a tilted contact implant (e.g., a tilted implant that is tilted with respect to the tilt direction applied during the tilted (source) implant), wherein during the tilted contact implant the protruding groove portions 149, 159 can also be used as a mask, as during the tilted source implant 251.

[0101] Presented herein are not only the above-described exemplary embodiments of a method for processing a power semiconductor device, but also embodiments of the power semiconductor device itself.

[0102] Generally, an embodiment of a power semiconductor device is proposed, wherein the power semiconductor device includes a semiconductor body, which is coupled to a first load terminal and a second load terminal and is configured to conduct a load current between the terminals, wherein the power semiconductor device also includes: a first trench and a second trench extending into the semiconductor body in a vertical direction, wherein the two trenches include: corresponding trench sidewalls, wherein the trench sidewalls facing each other laterally define a mesa region of the semiconductor body along a first lateral direction; corresponding trench electrodes; corresponding trench portions, which protrude from the surface of the semiconductor body by a protrusion distance of at least 50 nm in the vertical direction, wherein the trench electrodes extend into the protruding trench portions; a source region of a first conductive type and a semiconductor body region of a second conductive type, the two regions being arranged in the mesa region adjacent to the trench sidewalls of the first trench, wherein the first trench is configured to induce an inversion channel in the body region to control the load current in the mesa region, wherein the source region is arranged adjacent to only one of the two trench sidewalls and is spatially displaced from the other of the two trench sidewalls along the first lateral direction.

[0103] Figure 2A -B schematically and exemplarily illustrates an embodiment of such a power semiconductor device 1, which has generally been explained above. Common features of the two embodiments shown are

[0104] a respective trench portion 149 , 159 which protrudes from the surface 100 of the semiconductor body 10 by a protrusion distance A of at least 50 nm, at least 100 nm or at least 250 nm with respect to the vertical direction Z, wherein the trench electrodes 141 , 151 extend into the protruding trench portion 149 , 159 ; and

[0105] The source region 101 is arranged adjacent to only one 144 of the two trench sidewalls and is spatially displaced along the first lateral direction X from the other 154 of the two trench sidewalls.

[0106] The above description of embodiments of the power semiconductor device processing method has explained how the protruding trench portions 149 , 159 and the “single-sided” semiconductor source region 101 can be formed. Therefore, regarding optional implementations of these aspects of the power semiconductor device 1 , reference is made to the above description.

[0107] For example, according to an embodiment of the power semiconductor device 1 , the intermediate insulating layer 17 may be arranged over the protruding trench portions 149 , 159 and, with respect to the vertical direction Z, between the semiconductor body 10 and the conductive layer 112 of the first load terminal 11 .

[0108] Furthermore, a contact groove 111 may be arranged between the trenches 14, 15 with respect to the first lateral direction X and filled with a conductive material, and extend from the conductive layer 112 through the intermediate insulating layer 19 into the mesa region 105 (see Figure 2A ) or extends along the vertical direction Z to the semiconductor body surface 100 (see Figure 2B ) so as to electrically contact both the semiconductor source region 101 and the semiconductor body region 102.

[0109] For example, the contact groove 111 and the portion of the trench electrodes 141, 151 extending into the protruding trench portions 149, 159 have a common extension of at least 50 nm, at least 100 nm, or at least 250 nm in the vertical direction Z. The common extension may be substantially the same as the above-mentioned protrusion distance A. For example, the common extension may exist (e.g., exclusively) above the semiconductor body surface 100.

[0110] If the contact groove 111 extends into the mesa region 105 (see Figure 2A ), it can divide the mesa region 105 into a first lateral portion 1051 and a second lateral portion 1052, the first lateral portion 1051 being arranged between the first trench 14 and the contact groove 111 with respect to the first lateral direction X, and the second lateral portion 1052 being arranged between the second trench 15 and the contact groove 111 with respect to the first lateral direction X, wherein the source region 101 only extends into the first lateral portion 1051 and not into the second lateral portion 1052. Therefore, according to one embodiment, the source region 101 extends no more than 80%, no more than 70%, or no more than 60% of the width of the mesa region 105, and is only arranged adjacent to the trench sidewall 144 and spatially displaced from the trench sidewall 154.

[0111] Furthermore, according to one embodiment, the contact groove 111 may be arranged to contact the spacer element 18 that is positioned laterally adjacent to the protruding groove portions 149 , 159 , as described above.

[0112] about Figure 3, which schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device 1 according to one or more embodiments, some exemplary dimensions shall be explained:

[0113] In this figure (wherein, for simplicity, the auxiliary layer 17 and the intermediate layer 19 are shown as a common structure),

[0114] -A indicates the protrusion distance, as described above;

[0115] -B represents the width of the trench electrode 141 (also the trench electrode 151);

[0116] - C represents the width of the spacer element 18;

[0117] -D represents the width of the effective substrate contact (i.e., the width of the conductive material filling the contact trench 111 and contacting the mesa region 105);

[0118] -E represents the width of the opening of the mask used to form the opening 171;

[0119] -F denotes the width of a further opening of a mask for forming a further contact hole 172 for contacting a trench electrode 151 of a second trench 15 (eg, a source trench) through a further contact groove 113 which may be filled with a conductive material;

[0120] -G represents the width of the additional contact groove 113 at the interface with the trench electrode 151;

[0121] −H represents the sum of the widths of the mesa region 105 and the trench insulators 152 and 142 .

[0122] For example, embodiments of the power semiconductor device 1 described herein may implement one or more or all of the following expressions:

[0123] (i) E>D

[0124] (ii) F>G

[0125] (iii) D = H-2*C

[0126] (iv) C <= A

[0127] (v) E < H - CD / OVL (overlap) edge.

[0128] It should be understood that the contact grooves 111 and 113 do not necessarily have to be implemented with overlapping ranges in the second lateral direction. More specifically, for example, the trench electrode 151 can be contacted elsewhere. Of course, additional contact grooves (not shown) can also be provided for contacting the trench electrode 141 of the first trench 14.

[0129] In the above, embodiments related to power semiconductor switches and corresponding processing methods are explained. For example, these semiconductor devices are based on silicon (Si). Therefore, a single crystal semiconductor region or layer (e.g., semiconductor body 10 and its regions / regions, such as regions, etc.) can be a single crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can also be used.

[0130] However, it should be understood that the semiconductor body 10 and its regions / divisions can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, basic semiconductor materials such as silicon (Si) or germanium (Ge), Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), just to name a few examples. The above semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0131] For ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," etc. may be used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the respective devices in addition to orientations that are different from those shown in the figures. In addition, terms such as "first," "second," etc. are also used to describe various elements, regions, portions, etc., and are not intended to be limiting. Similar terms refer to the same elements throughout the specification.

[0132] As used herein, "having," "containing," "including," "comprising," "exhibiting," and the like are open-ended terms indicating the presence of stated elements or features, but not excluding additional elements or features.

[0133] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A method (2) for forming a power semiconductor device (1), comprising: - providing a semiconductor body (10) having a semiconductor body surface (100); - forming (20) an auxiliary layer (19) above the semiconductor body surface (100), the auxiliary layer (19) being coupled to the semiconductor body (10) and having an auxiliary layer surface (190); - forming (21) a plurality of trenches (14, 15) extending from the auxiliary layer surface (190) in a vertical direction (Z) through the auxiliary layer (19) into the semiconductor body (10), wherein two trench side walls (144, 154) facing each other of two adjacent trenches (14, 15) of the trenches laterally delimit a mesa region (105) of the semiconductor body (10) in a first lateral direction (X), wherein two adjacent trenches (14, 15) comprise respective trench portions (149, 159) which protrude from the semiconductor body surface (100) by a protrusion distance (A) of at least 50 nm with respect to the vertical direction (Z); - filling (22, 23) the trenches (14, 15) with at least one trench filling material; - planarizing at least one trench filling material to expose the auxiliary layer (19); - at least partially removing (24) the auxiliary layer (19) while maintaining the protruding trench portion (149, 159) comprising at least one trench filling material (142, 152); - subjecting the mesa region (105) to an implantation treatment step (25) for forming a semiconductor partition (101) in the mesa region (105), wherein the implantation (251) is inclined at an angle of at least 10° with respect to the vertical direction (Z), and wherein protruding trench portions (149, 159) of adjacent trenches (14, 15) are at least partially used as a mask during the inclined implantation, wherein the implantation (251) is performed such that the semiconductor partition (101) is arranged adjacent to only one (144) of the two trench sidewalls and is spatially displaced from the other (154) of the two trench sidewalls along the first lateral direction (X).

2. The method (2) according to claim 1, wherein: The semiconductor subregion (101) extends for no more than 80% of the width of the mesa region (105) along the first lateral direction (X).

3. The method (2) according to any one of the preceding claims 1 to 2, wherein: The semiconductor subregion (101) is a source region (101) of a first conductivity type, and the method (2) further comprises: - forming a semiconductor body region (102) of a second conductivity type in the mesa region (105), wherein the semiconductor body region (102) of the second conductivity type is subjected to the implantation (251).

4. The method (2) according to claim 3, wherein: The semiconductor body region (102) extends along the entire width of the mesa region (105) in the first lateral direction (X) and is arranged in contact with both trench sidewalls (144, 154).

5. The method (2) according to any one of the preceding claims 1 to 2, wherein: The implantation (251) is performed so as not to subject a sub-portion of the mesa region (105) adjacent to the other of the two trench sidewalls (154) to the implantation (251).

6. The method (2) according to any one of the preceding claims 1 to 2, wherein: Filling (22, 23) trenches (14, 15) with at least one trench filling material comprises forming trench electrodes (141, 151) in the trenches (14, 15), wherein the trench electrodes (141, 151) form part of a protruding trench portion (149, 159) and protrude at least 50 nm from a semiconductor body surface (100) in a vertical direction.

7. The method (2) according to one of the preceding claims 1 to 2, further comprising, after at least partially removing (24) the auxiliary layer (19) and before performing the implantation (251) for forming the semiconductor partition (101): - Covering the protruding groove parts (149, 159) with insulating material (194).

8. The method according to any one of the preceding claims 1-2, further comprising: - forming a contact groove (111) between adjacent trenches (14, 15) and extending in a vertical direction (Z) into the mesa region (105) or to the surface (100) of the semiconductor body.

9. The method (2) according to claim 8, wherein: Forming the contact groove (111) includes: - forming (26) a spacer element (18) laterally adjacent to the protruding groove portion (149, 159).

10. The method (2) according to claim 9, wherein: The spacer elements (18) are formed (26) by a self-alignment process with respect to the protruding groove portions (149, 159).

11. The method (2) according to claim 9 or 10, further comprising: - forming (27) an intermediate insulating layer (17) above the protruding groove portions (149, 159), wherein forming the contact groove (111) includes at least one etching process step for making an opening (171) through the intermediate insulating layer (17), the opening (171) being laterally defined by the spacer elements (18) and extending into the mesa region (105), thereby forming the contact groove (111).

12. The method (2) according to claim 11, further comprising: - forming a first load terminal (11) of the power semiconductor device (1) by depositing an electrically conductive material over the intermediate insulating layer (17), the electrically conductive material extending into the contact trench (111) so as to make electrical contact with the semiconductor partition (101).

13. The method (2) according to any one of the preceding claims 1 to 2, wherein: Two adjacent trenches (14, 15) are formed as - a control trench (14) having a trench electrode (141) configured to induce an inversion channel in the mesa region (105) to control a load current in the mesa region (105); and A source trench (15) having a trench electrode (151) electrically connected to a potential different from that of the control electrode (141).

14. The method according to any one of the preceding claims 1 to 2, wherein: - the auxiliary layer (19) comprises a first sublayer (191) in contact with the semiconductor body surface (100) and a second sublayer (192) above the first sublayer (191), and optionally, wherein the second sublayer (192) comprises silicon nitride (SiN) and / or wherein the second sublayer (192) has a thickness in the vertical direction (Z) of at least 50 nm; and / or wherein - during said implantation (251) for forming the semiconductor partition (101) only the protruding trench portions (149, 159) are used without an additional mask; and / or wherein - the spacer element (18) comprises silicon nitride (SiN); and / or wherein - forming (26) the spacer elements (18) according to a self-aligned process comprising a conformal deposition process step and a subsequent anisotropic etching process step.

15. A power semiconductor device (1) having a semiconductor body (10), the semiconductor body (10) being coupled to a first load terminal (11) and a second load terminal (12) and being configured to conduct a load current between the first load terminal and the second load terminal (11, 12), wherein the power semiconductor device (1) further comprises: - a first trench (14) and a second trench (15) extending into the semiconductor body (10) in a vertical direction (Z), wherein the two trenches (14, 15) comprise: - respective trench sidewalls (144, 154), wherein two trench sidewalls (144, 154) facing each other laterally delimit a mesa region (105) of the semiconductor body (10) along a first lateral direction (X); - corresponding trench electrodes (141, 151); - a respective trench portion (149, 159) which protrudes from the surface (100) of the semiconductor body (10) by a protrusion distance (A) of at least 50 nm with respect to the vertical direction (Z), wherein the trench electrode (141, 151) extends into the protruding trench portion (149, 159); - a source region (101) of a first conductivity type and a semiconductor body region (102) of a second conductivity type, the two regions (101, 102) being arranged in a mesa region (105) adjacent to a trench sidewall (144) of a first trench (14), wherein the first trench (14) is configured to induce an inversion channel in the body region (102) to control a load current in the mesa region (105), wherein the source region (101) is arranged adjacent to only one (144) of the two trench sidewalls and is spatially displaced from the other (154) of the two trench sidewalls along a first lateral direction (X).

16. The power semiconductor device (1) according to claim 15, further comprising: - an intermediate insulating layer (17) arranged above the protruding groove portion (149, 159) and between the semiconductor body (10) and the conductive layer (112) of the first load terminal (11) with respect to the vertical direction (Z); and - a contact groove (111) between the trenches (14, 15) with respect to a first lateral direction (X), which is filled with a conductive material and extends in a vertical direction (Z) from the conductive layer (112) through the intermediate insulating layer (19) into the mesa region (105) or to the semiconductor body surface (100) so as to be in electrical contact with both the source region (101) and the semiconductor body region (102).

17. The power semiconductor device (1) according to claim 16, wherein: The contact groove (111) and the portion of the trench electrode (141, 151) extending into the protruding trench portion (149, 159) have a common extension of at least 50 nm in the vertical direction (Z).

18. The power semiconductor device (1) according to claim 16 or 17, wherein: The contact groove (111) extends into the mesa region (105), dividing the mesa region (105) into a first lateral portion (1051) and a second lateral portion (1052), wherein the first lateral portion (1051) is arranged between the first trench (14) and the contact groove (111) with respect to a first lateral direction (X), and the second lateral portion (1052) is arranged between the second trench (15) and the contact groove (111) with respect to the first lateral direction (X), wherein the source region (101) only extends into the first lateral portion (1051) but not into the second lateral portion (1052).

19. The power semiconductor device (1) according to claim 16 or 17, wherein: The contact groove (111) is arranged to contact a spacer element (18) which is located laterally adjacent to the protruding groove portion (149, 159).

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