Semiconductor device and method for manufacturing the same

Abstract

A device includes: a lower semiconductor substrate; a lower gate structure on the lower semiconductor substrate, the lower gate structure including a lower gate electrode; a lower interlayer insulating film on the lower semiconductor substrate; an upper semiconductor substrate on the lower interlayer insulating film; an upper gate structure on the upper semiconductor substrate; and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covering the sidewalls of the upper semiconductor substrate. The upper gate structure includes an upper gate electrode extending in a first direction and a gate sidewall extending along the sidewall of the upper gate electrode. The upper gate electrode includes a long sidewall extending in the first direction and a short sidewall extending in the second direction. The gate sidewall is on the long sidewall of the upper gate electrode, but not on the short sidewall of the upper gate electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0099413, filed on August 24, 2018, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments relate to a semiconductor device and / or a method for manufacturing the same, and more particularly, to a three-dimensional stacked semiconductor device and / or a method for manufacturing the same. Background Art

[0004] A multi-gate transistor has been proposed as one of the scaling technologies for increasing the density of semiconductor devices. The multi-gate transistor is obtained by forming a fin-shaped or nanowire-shaped multi-channel active pattern on a substrate (e.g., a silicon body) and forming a gate on the surface of the multi-channel active pattern. However, the technology for increasing the density of semiconductor devices is approaching the scaling limit.

[0005] In order to increase the density of semiconductor devices, a semiconductor device three-dimensionally stacked by wafer bonding is proposed. Such a three-dimensionally stacked semiconductor device not only increases the density of semiconductor devices, but also integrates different types of integrated circuits into one semiconductor chip. Summary of the invention

[0006] Aspects of the exemplary embodiments provide a semiconductor device having improved integration density and performance by improving alignment accuracy between integrated circuits formed on a lower semiconductor substrate and integrated circuits formed on an upper semiconductor substrate.

[0007] Aspects of the exemplary embodiments also provide a method of manufacturing a semiconductor device capable of improving element integration density and performance by improving alignment accuracy between integrated circuits formed on a lower semiconductor substrate and integrated circuits formed on an upper semiconductor substrate.

[0008] According to some exemplary embodiments in the exemplary embodiments, a semiconductor device is provided, comprising: a lower semiconductor substrate; a lower gate structure, on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode; a lower interlayer insulating film, on the lower semiconductor substrate, the lower interlayer insulating film covers the lower gate structure; an upper semiconductor substrate, on the lower interlayer insulating film; an upper gate structure, on the upper semiconductor substrate; and an upper interlayer insulating film, on the lower interlayer insulating film, the upper interlayer insulating film covers the sidewall of the upper semiconductor substrate. The upper gate structure comprises an upper gate electrode extending in a first direction and an upper gate sidewall extending along the sidewall of the upper gate electrode. The upper gate electrode comprises a long sidewall extending in the first direction and a short sidewall extending in a second direction, the second direction being different from the first direction. The upper gate sidewall is on the long sidewall of the upper gate electrode, but not on the short sidewall of the upper gate electrode.

[0009] According to some exemplary embodiments among the exemplary embodiments, a semiconductor device is provided, including: a lower semiconductor substrate including a first region and a second region; a lower gate structure on the lower semiconductor substrate, the lower gate structure including a lower gate electrode; an upper semiconductor substrate on the lower semiconductor substrate in the first region, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; a plurality of upper gate structures on the first surface of the upper semiconductor substrate, each of the plurality of upper gate structures including an upper gate electrode; a plurality of upper source / drain regions on at least one side of each corresponding upper gate structure in the upper gate structures; and an etch stop layer extending along the first surface of the upper semiconductor substrate. The etch stop layer is on the first region of the lower semiconductor substrate.

[0010] According to some exemplary embodiments of the exemplary embodiments, a semiconductor device is provided, comprising: a lower semiconductor substrate, comprising a first region and a second region defined around the first region; a plurality of lower transistors, in the lower semiconductor substrate, the plurality of lower transistors comprising a plurality of lower gate structures and a plurality of lower source / drain regions, the plurality of lower gate structures extending in a first direction, and the plurality of lower source / drain regions being between the plurality of lower gate structures; a lower interlayer insulating film, on the lower semiconductor substrate, the lower interlayer insulating film covering both the plurality of lower gate structures and the plurality of lower source / drain regions; an upper semiconductor substrate, on the lower interlayer insulating film in the first region; the upper interlayer insulating film A film, on the lower interlayer insulating film, the upper interlayer insulating film covers the sidewall of the upper semiconductor substrate; a plurality of upper transistors, in the upper semiconductor substrate, the plurality of upper transistors are at a position overlapping with the first region of the lower semiconductor substrate, the plurality of upper transistors include a plurality of upper gate structures and a plurality of upper source / drain regions, the plurality of upper gate structures extend in a first direction, and the plurality of upper source / drain regions are between the plurality of upper gate structures; a first connection contact, connecting at least one of the plurality of upper gate structures to at least one of the plurality of lower transistors; and a second connection contact, connecting at least one of the plurality of upper source / drain regions to at least one of the plurality of lower transistors. At least one of the first connection contact and the second connection contact penetrates the upper semiconductor substrate.

[0011] According to some exemplary embodiments among the exemplary embodiments, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of lower transistors in a lower semiconductor substrate, the plurality of lower transistors comprising a plurality of lower gate structures and a plurality of lower source / drain regions; forming a lower interlayer insulating film on the lower semiconductor substrate to cover the plurality of lower gate structures and the plurality of lower source / drain regions; forming a plurality of upper transistors in an upper semiconductor substrate, the plurality of upper transistors comprising a plurality of upper gate structures and a plurality of upper source / drain regions; bonding the upper semiconductor substrate to the lower interlayer insulating film; after bonding the upper semiconductor substrate to the lower interlayer insulating film, performing a first etching process to remove some of the plurality of upper gate structures and some of the plurality of upper source / drain regions; after bonding the upper semiconductor substrate to the lower interlayer insulating film, performing a second etching process to partially remove the upper semiconductor substrate; and after the first etching process and the second etching process, forming a connecting contact, the connecting contact connecting at least one of the plurality of lower transistors to at least one of the plurality of upper transistors.

[0012] However, aspects of the exemplary embodiments are not limited to the embodiments set forth herein. The above and other aspects of the exemplary embodiments will become more apparent to those skilled in the art to which the exemplary embodiments pertain by referring to the detailed description of the exemplary embodiments given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] These and / or other aspects will become apparent and more readily understood through the following description of some exemplary embodiments in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a layout diagram showing a semiconductor device according to some exemplary embodiments;

[0015] Figure 2 yes Figure 1 An enlarged view of region P;

[0016] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0017] Figure 4 is along Figure 2 A cross-sectional view taken along line BB';

[0018] Figure 5 is along Figure 2 A cross-sectional view taken along line CC';

[0019] Figure 6 and Figure 7 A semiconductor device according to some exemplary embodiments is shown;

[0020] Figure 8 and Fig. 9 A semiconductor device according to some exemplary embodiments is shown;

[0021] Fig.10 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments;

[0022] Fig.11 is along Fig.10 A cross-sectional view taken along line BB';

[0023] Figure 12 to Figure 14 A semiconductor device according to some exemplary embodiments is shown;

[0024] Fig.15 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments;

[0025] Fig.16 is along Fig.15 A cross-sectional view taken along line AA';

[0026] Fig.17 is along Fig.15 A cross-sectional view taken along line BB';

[0027] Fig.18 is along Fig.15 A cross-sectional view taken along line CC';

[0028] Fig.19 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments;

[0029] Fig. 20 is along Fig.19 A cross-sectional view taken along line D-D';

[0030] Fig.21 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments;

[0031] Fig. 22 is along Fig.21 A cross-sectional view taken along line EE';

[0032] Figures 23 to 30 are views for explaining steps of a method of manufacturing a semiconductor device according to some exemplary embodiments; and

[0033] Fig.31 are views for explaining steps of a method of manufacturing a semiconductor device according to some exemplary embodiments. DETAILED DESCRIPTION

[0034] In the drawings related to semiconductor devices according to some exemplary embodiments, transistors formed on the lower semiconductor substrate and the upper semiconductor substrate are shown as fin field effect transistors (FinFETs), each transistor including a channel region in the shape of a fin pattern. However, exemplary embodiments are not limited thereto. In semiconductor devices according to some exemplary embodiments, each or at least some of the transistors formed on the lower semiconductor substrate and the transistors formed on the upper semiconductor substrate may also include a planar transistor, a buried channel array transistor (BCAT), a recessed channel array transistor (RCAT), a tunneling FET, a transistor including a nanowire, a transistor including a nanosheet, or a vertical transistor.

[0035] In the drawings related to the semiconductor device according to some exemplary embodiments, the transistor formed on the lower semiconductor substrate and the transistor formed on the upper semiconductor substrate are shown as the same type of fin transistors, but the exemplary embodiments are not limited thereto. In the semiconductor device according to some exemplary embodiments, the transistor formed on the lower semiconductor substrate and the transistor formed on the upper semiconductor substrate may also be different types of transistors.

[0036] For example, the semiconductor element formed on the lower semiconductor substrate may be or include a semiconductor element including a memory cell, and the semiconductor element formed on the upper semiconductor substrate may be a logic element. For another example, a logic element may be formed on the lower semiconductor substrate, and a semiconductor element including a memory cell may be formed on the upper semiconductor substrate. The semiconductor element formed on the lower semiconductor substrate and the semiconductor element formed on the upper semiconductor substrate may also be or include a logic element including different transistor types.

[0037] The semiconductor element including the memory cell may be or include a volatile memory element or a non-volatile memory element. The semiconductor element including the memory cell may be but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM) and / or a flash memory.

[0038] Figure 1 is a layout diagram illustrating a semiconductor device according to some exemplary embodiments. Figure 2 yes Figure 1 Magnified view of area P. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 is along Figure 2 For reference, Figure 2 A layout of a fin pattern and a gate electrode structure formed only on an upper semiconductor substrate is shown.

[0039] exist Figure 1 , the lower semiconductor substrate 100 may include first to fourth active regions ACT1 to ACT4. The lower semiconductor substrate 100 may include a field region FA defined around the first to fourth active regions ACT1 to ACT4.

[0040] Gate electrodes, source / drain regions, etc. may be formed on the lower semiconductor substrate 100 of the first to fourth active regions ACT1 to ACT4. The field region FA may be or include a region for electrically isolating the first to fourth active regions ACT1 to ACT4.

[0041] The first to fourth upper semiconductor substrates 200 to 500 may be respectively disposed on the lower semiconductor substrate 100 of the first to fourth active regions ACT1 to ACT4. The first to fourth upper semiconductor substrates 200 to 500 are formed by etching the same base substrate. Therefore, the first to fourth upper semiconductor substrates 200 to 500 may include the same material.

[0042] Since the first to fourth upper semiconductor substrates 200 to 500 are disposed on the lower semiconductor substrate 100, the size of the lower semiconductor substrate 100 may be greater than that of each of the first to fourth upper semiconductor substrates 200 to 500. For example, the width of the lower semiconductor substrate 100 in one direction is greater than the width of each of the first to fourth upper semiconductor substrates 200 to 500 in the same direction.

[0043] The first to fourth upper semiconductor substrates 200 to 500 are shown as being disposed on the first to fourth active regions ACT1 to ACT4, respectively, but not disposed on the field region FA. However, this is merely an example for ease of description, and exemplary embodiments are not limited to this example. For example, a portion of each of the first to fourth upper semiconductor substrates 200 to 500 may also be disposed on the field region FA of the lower semiconductor substrate 100.

[0044] Although the first to fourth upper semiconductor substrates 200 to 500 are illustrated as partially covering the first to fourth active regions ACT1 to ACT4 , respectively, exemplary embodiments are not limited thereto.

[0045] exist Figure 1 , the lower semiconductor substrate 100 is illustrated as including first to fourth active regions ACT1 to ACT4 , but exemplary embodiments are not limited thereto.

[0046] In addition, although the first to fourth upper semiconductor substrates 200 to 500 are shown as being respectively disposed on the first to fourth active regions ACT1 to ACT4 of the lower semiconductor substrate 100, this is merely an example for ease of description, and exemplary embodiments are not limited to this example. For example, one upper semiconductor substrate may also be disposed on a plurality of active regions defined in the lower semiconductor substrate 100.

[0047] Elements (eg, transistors) having the same and / or different structures may be formed in the first to fourth active regions ACT1 to ACT4 .

[0048] Reference Figures 2 to 5 According to some exemplary embodiments, the semiconductor device may include a lower semiconductor substrate 100, a first upper semiconductor substrate 200, a plurality of lower gate structures 120 and 120_1, a plurality of lower source / drain regions 150, a plurality of first upper gate structures 220, a plurality of first upper source / drain regions 250 and 250_1, an upper source / drain connection contact 270, and an upper gate connection contact 275.

[0049] Each of the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 may be or include a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In addition, each of the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 may be or include, without limitation, a silicon substrate, or a substrate made of other materials (e.g., silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide).

[0050] The first upper semiconductor substrate 200 may include a first surface 200a and a second surface 200b opposite to each other. A sidewall 200s of the first upper semiconductor substrate 200 may connect the first surface 200a of the first upper semiconductor substrate 200 to the second surface 200b of the first upper semiconductor substrate 200. The second surface 200b of the first upper semiconductor substrate 200 may face the lower semiconductor substrate 100.

[0051] A plurality of lower transistors may be formed on the lower semiconductor substrate 100. The lower transistors may include a plurality of lower fin patterns 110, lower gate structures 120, and lower source / drain regions 150. The lower transistors may be formed where the lower fin patterns 110 intersect the corresponding lower gate structures 120.

[0052] A plurality of upper transistors may be formed on the first upper semiconductor substrate 200. The upper transistors may include a plurality of first upper fin patterns 210, first upper gate structures 220, and first upper source / drain regions 250. The upper transistors may be formed where the first upper fin patterns 210 intersect the corresponding first upper gate structures 220.

[0053] The lower fin patterns 110 may protrude from the lower semiconductor substrate 100. Each of the lower fin patterns 110 may extend in a first direction (eg, direction X). Each of the lower fin patterns 110 may include a long side extending in the first direction X and a short side extending in a second direction (eg, direction Y).

[0054] A lower field insulating layer 105 may be formed on the lower semiconductor substrate 100 . The lower field insulating layer 105 may partially cover a sidewall of each of the lower fin patterns 110 .

[0055] exist Figure 3 and Figure 4In the embodiment of the present invention, a deep trench and / or a protruding pattern defining the first active area ACT1 is not formed, but the exemplary embodiment is not limited thereto. Here, the deep trench may be or include a trench deeper than the trench defining the lower fin pattern 110. Unlike in the accompanying drawings, for example, a deep trench may be formed near the outermost lower fin pattern 110 to define the first active area ACT1. Alternatively or additionally, a protruding pattern may be formed near the outermost lower fin pattern 110 to define the first active area ACT1. Here, the upper surface of the protruding pattern may be covered by the lower field insulating layer 105.

[0056] The first upper fin patterns 210 may protrude from the first upper semiconductor substrate 200 . For example, each of the first upper fin patterns 210 may protrude from the first surface 200 a of the first upper semiconductor substrate 200 .

[0057] Each of the first upper fin patterns 210 may extend in the first direction X. Each of the first upper fin patterns 210 may include a long side extending in the first direction X and a short side extending in the second direction Y.

[0058] In the description of the semiconductor device according to some exemplary embodiments, the lower fin pattern 110 and the first upper fin pattern 210 are described as extending in the first direction X. However, exemplary embodiments are not limited thereto, and the lower fin pattern 110 and the first upper fin pattern 210 may also extend in different directions. As an example, the lower fin pattern 110 may extend in the first direction X, and the first upper fin pattern may extend in the second direction Y. As an example, the lower fin pattern 110 may extend in the second direction Y, and the first upper fin pattern 210 may extend in the first direction X.

[0059] An upper field insulating layer 205 may be formed on the first surface 200 a of the first upper semiconductor substrate 200 . The upper field insulating layer 205 may partially cover a sidewall of each of the first upper fin patterns 210 .

[0060] Each of the lower fin pattern 110 and the first upper fin pattern 210 may include an elemental semiconductor material such as silicon or germanium. Alternatively or additionally, each of the lower fin pattern 110 and the first upper fin pattern 210 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be or include, for example, a binary or ternary compound including two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping a binary or ternary compound with a group IV element. The group III-V compound semiconductor may be or include, for example, a binary, ternary, or quaternary compound composed of at least one of aluminum (Al), gallium (Ga), and indium (In) (i.e., group III elements) combined with one of phosphorus (P), arsenic (As), and antimony (Sb) (i.e., group V elements).

[0061] Each of the lower field insulating layer 105 and the upper field insulating layer 205 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0062] exist Figure 3 and Figure 4 In the embodiment, four lower fin patterns 110 and three first upper fin patterns 210 are disposed in the first active region ACT1, but the exemplary embodiment is not limited thereto. In addition, the number of lower fin patterns 110 and the number of first upper fin patterns 210 disposed in the first active region ACT1 are different, but the exemplary embodiment is not limited thereto.

[0063] exist Figure 2 , short sides of the first upper fin patterns 210 are aligned on a line along the second direction Y. However, this is merely an example for convenience of description, and example embodiments are not limited to this example.

[0064] If the first upper semiconductor substrate 200 is, for example, an SOI substrate, the first upper semiconductor substrate 200 may have a shape in which a base semiconductor substrate, an insulating layer (e.g., a buried oxide layer) on the base semiconductor substrate, and a first upper fin pattern 210 on the insulating layer are sequentially disposed (e.g., stacked).

[0065] Alternatively, if the first upper fin pattern 210 is formed using an SOI substrate, the first upper semiconductor substrate 200 may be or include an insulating layer instead of a semiconductor layer.

[0066] If portions of the first upper semiconductor substrate 200 disposed under the first upper fin pattern 210 are entirely removed during a manufacturing process of bonding the first upper semiconductor substrate 200 to the lower semiconductor substrate 100 , only the first upper fin pattern 210 may remain on the lower interlayer insulating film 190 .

[0067] The lower gate structures 120 and 120_1 may extend in the second direction Y on the lower field insulating layer 105. The lower gate structures 120 and 120_1 may be disposed on the lower fin pattern 110 to respectively intersect the lower fin pattern 110. The lower gate structures 120 and 120_1 may include a dummy lower gate structure 120_1 intersecting an end of the lower fin pattern 110, and a lower gate structure 120 not intersecting an end of the lower fin pattern 110.

[0068] Each of the lower gate structures 120 and 120_1 may include a lower gate spacer 140, a lower gate insulating layer 135, a lower gate electrode 130, and / or a lower capping pattern 145. The lower gate insulating layer 135 may be formed along the sidewalls of the lower gate spacer 140 and the contour of the lower fin pattern 110. The lower gate electrode 130 may be formed on the lower gate insulating layer 135. The lower capping pattern 145 may be formed on the lower gate electrode 130 and disposed between the lower gate spacers 140.

[0069] The lower gate electrode 130 may include a long sidewall 130a extending in the second direction Y and a short sidewall 130b extending in the first direction X. The lower gate spacer 140 may be disposed on the long sidewall 130a of the lower gate electrode 130 and the short sidewall 130b of the lower gate electrode 130. The lower gate spacer 140 on the long sidewall 130a of the lower gate electrode 130 may include the same material as or a different material from the lower gate spacer 140 on the short sidewall 130b of the lower gate electrode 130.

[0070] The first upper gate structure 220 may extend in the second direction Y on the upper field insulating layer 205. The first upper gate structure 220 may be disposed on the first upper fin pattern 210 to intersect with the first upper fin pattern 210. The first upper gate structure 220 may be disposed at a position overlapping with the first active region ACT1 of the lower semiconductor substrate 100. The first upper gate structure 220 may be disposed on the first surface 200a of the first upper semiconductor substrate 200.

[0071] Each or at least some of the first upper gate structures 220 may include an upper gate spacer 240, an upper gate insulating layer 235, an upper gate electrode 230, and an upper capping pattern 245. The upper gate insulating layer 235 may be formed along the sidewalls of the upper gate spacer 240 and the contour of the first upper fin pattern 210. The upper gate electrode 230 may be formed on the upper gate insulating layer 235. The upper capping pattern 245 may be formed on the upper gate electrode 230 and disposed between the upper gate spacers 240.

[0072] The upper gate electrode 230 may include a long sidewall 230a extending in the second direction Y, and a short sidewall 230b extending in the first direction X. The upper gate spacer 240 may be disposed on the long sidewall 230a of the upper gate electrode 230. The upper gate spacer 240 is not disposed on the short sidewall 230b of the upper gate electrode 230. The short sidewall 230b of the upper gate electrode 230 and the sidewall 200s of the first upper semiconductor substrate 200 may be arranged side by side in the thickness direction of the first upper semiconductor substrate 200. The short sidewall 230b of the upper gate electrode 230, the sidewall of the upper field insulating layer 205, and the sidewall 200s of the first upper semiconductor substrate 200 may have a continuous profile.

[0073] In the semiconductor device according to some example embodiments, the lower gate structures 120 and 120_1 , the first upper semiconductor substrate 200 , and the first upper gate structure 220 may be stacked (eg, sequentially disposed) on the lower semiconductor substrate 100 .

[0074] Each of the lower gate insulating layer 135 and the upper gate insulating layer 235 may include a high dielectric constant insulating layer. The high dielectric constant insulating layer may include a high dielectric material having a higher dielectric constant than the silicon oxide layer. Each of the lower gate insulating layer 135 and the upper gate insulating layer 235 may include one or more of the following: hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium lead tantalum oxide, and lead zinc niobate.

[0075] Each of the lower gate electrode 130 and the upper gate electrode 230 may include, for example, at least one of the following or a combination thereof: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminide (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), Titanium (TiC), Tantalum Carbonitride (TaCN), Tungsten (W), Aluminum (Al), Copper (Cu), Cobalt (Co), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Platinum (Pt), Nickel Platinum (Ni-Pt), Niobium (Nb), Niobium Nitride (NbN), Niobium Carbide (NbC), Molybdenum (Mo), Molybdenum Nitride (MoN), Molybdenum Carbide (MoC), Tungsten Carbide (WC), Rhodium (Rh), Palladium (Pd), Iridium (Ir), Osmium (Os), Silver (Ag), Gold (Au), Zinc (Zn), Vanadium (V).

[0076] The lower gate spacer 140 and the upper gate spacer 240 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), or silicon oxycarbon nitride (SiOCN).

[0077] Each of the lower and upper capping patterns 145 and 245 may include, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SIN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and silicon oxycarbon nitride (SiOCN).

[0078] Unlike the drawings, each of the lower gate structures 120 and 120_1 may not include the lower capping pattern 145. Each of the first upper gate structures 220 may not include the upper capping pattern 245.

[0079] exist Figure 2 , short sides of the first upper gate structure 220 (ie, short sidewalls 230 b of the upper gate electrode 230 ) are illustrated as being aligned on a line along the first direction X. However, this is merely an example for ease of description, and example embodiments are not limited to this example.

[0080] exist Figure 3 , the first upper gate structure 220 is not misaligned with the lower gate structure 120. However, this is merely an example for convenience of description, and example embodiments are not limited to this example.

[0081] The lower source / drain region 150 may be disposed on at least one side of the lower gate structures 120 and 120_1. The lower source / drain region 150 may be disposed between the lower gate structures 120. The lower source / drain region 150 may be formed on the lower fin pattern 110.

[0082] The first upper source / drain regions 250 and 250_1 may be disposed on at least one side of the first upper gate structure 220. The first upper source / drain regions 250 and 250_1 may be formed on the first upper fin pattern 210.

[0083] The first upper source / drain regions 250 and 250_1 may include a first upper source / drain region 250 and a first cut upper source / drain region 250_1. The first upper source / drain region 250 may be disposed between the first upper gate structures 220. The first cut upper source / drain region 250_1 may be formed at an end of the first upper fin pattern 210. Each of the first cut upper source / drain regions 250_1 may include a cut surface 250_1s extending in a thickness direction of the first upper semiconductor substrate 200. The cut surface 250_1s of the first cut upper source / drain region 250_1, the short sidewall of the first upper fin pattern 210, and the sidewall 200s of the first upper semiconductor substrate 200 may have a continuous profile.

[0084] The first upper gate structure 220 and the first upper source / drain regions 250 and 250_1 may not be disposed in the field region FA of the lower semiconductor substrate 100 (see Figure 1 )superior.

[0085] exist Figure 5 , the lower source / drain regions 150 are spaced apart from each other, and the first upper source / drain regions 250 are spaced apart from each other. However, this is merely an example for ease of description, and example embodiments are not limited to this example. Some of the lower source / drain regions 150 may also be connected to each other, and some of the first upper source / drain regions 250 may also be connected to each other.

[0086] exist Figure 3 , the bottom surface of the first upper source / drain region 250 is shown to be higher than the first surface 200a of the first upper semiconductor substrate 200, but exemplary embodiments are not limited thereto. The bottom surface of the first upper source / drain region 250 may also be located on the same horizontal plane as the first surface 200a of the first upper semiconductor substrate 200, or may be located at a lower position than the first surface 200a of the first upper semiconductor substrate 200.

[0087] Lower etch stop layer 155 may be formed along the upper surface of lower semiconductor substrate 100. Lower etch stop layer 155 may be formed along the upper surface of lower field insulating layer 105 and the contour of lower source / drain region 150. Lower etch stop layer 155 may be formed along the sidewalls of lower gate structures 120 and 120_1.

[0088] The upper etch stop layer 255 may extend along the first surface 200a of the first upper semiconductor substrate 200. The upper etch stop layer 255 may be formed along the contours of the upper surface of the upper field insulating layer 205 and the upper surface of the first upper source / drain region 250. The upper etch stop layer 255 may be formed along the sidewall of the first upper gate structure 220.

[0089] The upper etch stop layer 255 is not formed on the cut surface 250_1s of the first cut upper source / drain region 250_1, the short sidewalls of the first upper fin pattern 210, and the sidewalls 200s of the first upper semiconductor substrate 200. The upper etch stop layer 255 may not protrude more than the sidewalls 200s of the first upper semiconductor substrate 200 in the first direction X. The upper etch stop layer 255 does not protrude more than the cut surface 250_1s of the first cut upper source / drain region 250_1 in the first direction X.

[0090] The upper etch stop layer 255 may be disposed on the first active region ACT1 of the lower semiconductor substrate 100. The upper etch stop layer 255 may not be disposed in the field region FA of the lower semiconductor substrate 100 (see Figure 1 )superior.

[0091] The lower etch stop layer 155 and the upper etch stop layer 255 may include, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and / or silicon oxycarbon nitride (SiOCN).

[0092] The lower interlayer insulating film 190 may be formed on the lower semiconductor substrate 100. The lower interlayer insulating film 190 may cover the lower gate structures 120 and 120_1 and the lower source / drain regions 150. The lower interlayer insulating film 190 may be formed on the lower etch stop layer 155. The lower interlayer insulating film 190 may include: a bonding insulating layer 201 (see Fig. 27 ), which is formed to combine the first upper semiconductor substrate 200 with the lower semiconductor substrate 100 during the manufacturing process.

[0093] The first upper semiconductor substrate 200 may be disposed on the lower interlayer insulating film 190. An upper surface of the lower interlayer insulating film 190 may face the second surface 200b of the first upper semiconductor substrate 200.

[0094] An upper interlayer insulating film 290 may be formed on the lower interlayer insulating film 190. The upper interlayer insulating film 290 may cover the sidewalls 200s of the first upper semiconductor substrate 200. The upper interlayer insulating film 290 may cover the first upper gate structure 220 and the first upper source / drain regions 250 and 250_1.

[0095] Each of the lower interlayer insulating film 190 and the upper interlayer insulating film 290 may include, but is not limited to, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), Tossilazane (TOSZ), undoped quartz glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide and / or porous polymer materials.

[0096] At least one of the lower transistors formed on the lower semiconductor substrate 100 may be connected to at least one of the transistors formed on the first upper semiconductor substrate 200. At least one of the first upper gate structures 220 may be connected to at least one of the lower gate structures 120 and 120_1 and / or at least one of the lower source / drain regions 150. At least one of the first upper source / drain regions 250 and 250_1 may be connected to at least one of the lower gate structures 120 and 120_1 or at least one of the lower source / drain regions 150.

[0097] In the following description, a case will be described where the first upper gate structure 220 is connected to the lower gate structure 120 and the first upper source / drain region 250 is connected to the lower source / drain region 150. However, this is merely an example for convenience of description, and example embodiments are not limited to this example.

[0098] The lower source / drain contact 170 may contact the lower source / drain region 150. The lower source / drain contact 170 may be formed on the lower source / drain region 150.

[0099] The first lower landing pad 171 may be formed on the lower source / drain contact 170. The first lower landing pad 171 may contact the lower source / drain contact 170.

[0100] A lower source / drain contact 170 and a first lower landing pad 171 may be formed in the lower interlayer insulating film 190 .

[0101] The lower gate contact 175 may contact the lower gate electrode 130. The lower gate contact 175 may be formed on the second gate electrode 130.

[0102] The second lower landing pad 176 may be formed on the lower gate contact 175. The second lower landing pad 176 may contact the lower gate contact 175.

[0103] A lower gate contact 175 and a second lower landing pad 176 may be formed in the lower interlayer insulating film 190 .

[0104] Each of the upper gate connection contact 275 and the upper source / drain connection contact 270 may penetrate the first upper semiconductor substrate 200. Each of the upper gate connection contact 275 and the upper source / drain connection contact 270 may be formed at a position where the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 overlap each other.

[0105] Each of the upper gate connection contact 275 and the upper source / drain connection contact 270 may be connected to one or more transistors.

[0106] The upper source / drain connection contact 270 may penetrate the first upper semiconductor substrate 200 to be directly connected to the first lower landing pad 171. The upper source / drain connection contact 270 may be electrically connected to the lower source / drain contact 170 through the first lower landing pad 171.

[0107] The upper source / drain connection contact 270 may be connected to at least one of the first upper source / drain regions 250. Since the upper transistor includes the first upper source / drain region 250, the upper source / drain connection contact 270 may electrically connect the upper transistor and the lower transistor. The upper source / drain connection contact 270 may connect at least one of the first upper source / drain regions 250 to the lower transistor.

[0108] The upper source / drain connection contact 270 may be formed in the first connection contact hole 270h. The upper source / drain connection contact 270 may fill the first connection contact hole 270h. For example, the first connection contact hole 270h may be formed in the first upper fin pattern 210, the first upper semiconductor substrate 200, and the lower interlayer insulating film 190.

[0109] When the upper source / drain connection contact 270 is formed to be connected to at least two first upper source / drain regions 250, the upper source / drain connection contact 270 may be formed at a position overlapping with the first upper fin pattern 210, such as Figure 2 Alternatively, with Figure 2 Differently, the upper source / drain connection contact 270 may be formed at a position not overlapping the first upper fin pattern 210 and the first upper gate structure 220 .

[0110] The upper gate connection contact 275 may penetrate the first upper semiconductor substrate 200 to be directly connected to the second lower landing pad 176. The upper gate connection contact 275 may be electrically connected to the lower gate contact 175 through the second lower landing pad 176.

[0111] The upper gate connection contact 275 may be connected to at least one of the upper gate electrodes 230. Since the upper transistor includes the upper gate electrode 230, the upper gate connection contact 275 may electrically connect the upper transistor and the lower transistor. The upper gate connection contact 275 may connect at least one upper gate electrode 230 to the lower transistor.

[0112] The upper gate connection contact 275 may be formed in the second connection contact hole 275h. The upper gate connection contact 275 may fill the second connection contact hole 275h. For example, the second connection contact hole 275h may be formed in the first upper gate structure 220, the first upper semiconductor substrate 200, and the lower interlayer insulating film 190.

[0113] Each or at least one of the lower gate contact 175, the lower source / drain contact 170, the first lower landing pad 171, the second lower landing pad 176, the upper gate connection contact 275, and the upper source / drain connection contact 270 may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), and / or doped polysilicon. Each or at least one of the lower gate contact 175, the lower source / drain contact 170, the first lower landing pad 171, the second lower landing pad 176, the upper gate connection contact 275, and the upper source / drain connection contact 270 may include different materials. Different from the drawings, a silicide layer may also be formed between the lower source / drain contact 170 and the lower source / drain region 150.

[0114] Unlike the drawings, a wiring structure connected to the upper gate connection contact 275 and the upper source / drain connection contact 270 may also be formed on the upper gate connection contact 275 and the upper source / drain connection contact 270 .

[0115] In the drawing, there is shown one upper gate connection contact 275 and one upper source / drain connection contact 270. However, this is merely an example for convenience of description, and example embodiments are not limited to this example.

[0116] Figure 6 and Figure 7 A semiconductor device according to some embodiments is shown. For ease of description, the following will mainly focus on the semiconductor device according to the above reference Figures 3 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0117] Reference Figure 6 and Figure 7 , the semiconductor device according to some exemplary embodiments may further include a first wiring structure 180 and a second wiring structure 185 formed in the lower interlayer insulating film 190 .

[0118] The first and second wiring structures 180 and 185 may be disposed between the lower semiconductor substrate 100 and the first upper semiconductor substrate 200. Each of the first and second wiring structures 180 and 185 may include wirings and / or vias formed at a plurality of metal levels.

[0119] The first wiring structure 180 may be connected to the lower source / drain contact 170. The first wiring structure 180 may be connected to the upper source / drain connection contact 270.

[0120] The first wiring structure 180 may electrically connect the lower source / drain contact 170 and the upper source / drain connection contact 270. The first wiring structure 180 may electrically connect the first upper source / drain region 250 of the upper transistor and the lower source / drain region 150 of the lower transistor.

[0121] The second wiring structure 185 may be connected to the lower gate contact 175. The second wiring structure 185 may be connected to the upper gate connection contact 275.

[0122] The second wiring structure 185 may electrically connect the lower gate contact 175 and the upper gate connection contact 275. The second wiring structure 185 may electrically connect the upper gate electrode 230 of the upper transistor and the lower gate electrode 130 of the lower transistor.

[0123] In the first wiring structure 180 and the second wiring structure 185 , wirings and vias formed at the same metal level may be formed simultaneously (eg, by a dual damascene process).

[0124] Figure 8 and Fig. 9 A semiconductor device according to some exemplary embodiments is shown. For ease of description, the following will mainly focus on the semiconductor device according to the above reference Figures 3 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0125] Reference Figure 8 and Fig. 9 In the semiconductor device according to some exemplary embodiments, the upper etch stop layer 255 may be formed in parallel with the second surface 200 b of the first upper semiconductor substrate 200 .

[0126] The upper etch stop layer 255 may extend along the upper surface of the first upper gate structure 220. A portion of the upper interlayer insulating film 290 may be interposed between the upper etch stop layer 255 and each of the first upper source / drain regions 250 and 250_1.

[0127] Fig.10 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments. Fig.11 is along Fig.10 For ease of description, the focus will be on the cross-sectional view taken along the line BB' of FIG. Figures 2 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0128] For reference, Fig.10 yes Figure 1 Magnified view of area P in FIG.

[0129] Reference Fig.10 and Fig.11 In the semiconductor device according to some exemplary embodiments, the upper gate connection contact 275 may be formed in the upper interlayer insulating film 290 and the lower interlayer insulating film 190. The upper source / drain connection contact 270 may penetrate the first upper semiconductor substrate 200.

[0130] The upper gate connection contact 275 does not penetrate the first upper semiconductor substrate 200. The upper gate connection contact 275 may be disposed on an upper surface of the lower semiconductor substrate 100 that does not overlap with the first upper semiconductor substrate 200. The upper gate connection contact 275 may be formed at a position where the first upper semiconductor substrate 200 and the lower semiconductor substrate 100 do not overlap.

[0131] The upper gate connection pad 275 may be electrically connected to the upper gate electrode 230 through an upper connection line 276 and an upper gate contact 277 .

[0132] Different from the drawings, for example, the upper gate connection contact 275 may penetrate the first upper semiconductor substrate 200 , and the upper source / drain connection contact 270 may not penetrate the first upper semiconductor substrate 200 .

[0133] Alternatively, for example, each of the upper gate connection contact 275 and the upper source / drain connection contact 270 may not penetrate the first upper semiconductor substrate 200. The upper gate connection contact 275 and the upper source / drain connection contact 270 may be formed at positions where the first upper semiconductor substrate 200 and the lower semiconductor substrate 100 do not overlap.

[0134] Figure 12 to Figure 14 A semiconductor device according to some exemplary embodiments is shown. For ease of description, the following will mainly focus on the semiconductor device according to the above reference Figures 3 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0135] Reference Figure 12 to Figure 14 In the semiconductor device according to some example embodiments, the lower gate structures 120 and 120_1 and the first upper gate structure 220 may be disposed between the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 .

[0136] The lower source / drain region 150 and the first upper source / drain regions 250 and 250_1 may also be disposed between the lower semiconductor substrate 100 and the first upper semiconductor substrate 200 .

[0137] For example, the first surface 200 a of the first upper semiconductor substrate 200 may face the lower semiconductor substrate 100 . The first upper fin pattern 210 may protrude from the first upper semiconductor substrate 200 toward the lower semiconductor substrate 100 .

[0138] The upper source / drain connection contact 270 may sequentially penetrate the first upper semiconductor substrate 200 , the first upper fin pattern 210 , and the first upper source / drain region 250 . Thus, the upper source / drain connection contact 270 may be directly connected to the first lower landing pad 171 .

[0139] The upper gate connection contact 275 may sequentially penetrate the first upper semiconductor substrate 200, the upper field insulating layer 205, and the first upper gate structure 220. Therefore, the upper gate connection contact 275 may be directly connected to the second lower landing pad 176.

[0140] exist Fig.12 In the embodiment, an insertion insulating layer and an upper etch stop layer 255 formed during the manufacturing of the first upper gate structures 220 may be disposed on the lower interlayer insulating film 190 between the first upper gate structures 220 .

[0141] Fig.15 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments. Fig.16 is along Fig.15 A cross-sectional view taken along line AA'. Fig.17 is along Fig.15 A cross-sectional view taken along line BB'. Fig.18 is along Fig.15 For ease of description, we will focus on the cross-sectional view taken along the line CC'. Figure 2 and Figure 12 to Figure 14 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0142] For reference, Fig.15 yes Figure 1 Magnified view of area P in FIG.

[0143] Reference Figures 15 to 18 In the semiconductor device according to some exemplary embodiments, at least one of the plurality of first upper fin patterns 210 may protrude further in the first direction X than the sidewall 200 s of the first upper semiconductor substrate 200 .

[0144] At least one of the plurality of first upper gate structures 220 may protrude further in the second direction Y than the sidewall 200 s of the first upper semiconductor substrate 200 .

[0145] A portion of each of the first upper fin patterns 210 may laterally protrude further than the sidewall 200 s of the first upper semiconductor substrate 200 . A portion of each of the first upper gate structures 220 may laterally protrude further than the sidewall 200 s of the first upper semiconductor substrate 200 .

[0146] A portion of each of the first cut upper source / drain regions 250_1 may protrude further than the sidewall 200 s of the first upper semiconductor substrate 200 (similar to the first upper fin pattern 210 in the first direction X). Here, a portion of the upper etch stop layer 255 may protrude further laterally than the sidewall 200 s of the first upper semiconductor substrate 200 .

[0147] Unlike the drawings, the first upper fin pattern 210 may not protrude further than the sidewall 200s of the first upper semiconductor substrate 200 in the first direction X. Alternatively, the first upper gate structure 220 may not protrude further than the sidewall 200s of the first upper semiconductor substrate 200 in the second direction Y.

[0148] Fig.19 is a schematic layout diagram of a semiconductor device according to some exemplary embodiments. Fig. 20 is along Fig.19 For ease of description, we will focus on the cross-sectional view taken along the line D-D' of FIG. Figures 2 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0149] Reference Fig.19 and Fig. 20 In the semiconductor device according to some exemplary embodiments, a first dummy upper spacer 240_1 may be disposed on the first upper semiconductor substrate 200 .

[0150] The first dummy upper spacer 240_1, the short sidewall of each first upper fin pattern 210, and the sidewall 200s (e.g., the sidewall extending in the second direction Y) of the first upper semiconductor substrate 200 may be aligned in the thickness direction of the first upper semiconductor substrate 200. The first cut upper source / drain region 250_1 may not be formed on the side of the first upper semiconductor substrate 200 where the first dummy upper spacer 240_1 is formed. The first dummy upper spacer 240_1 may be a portion of the first upper gate structure 220.

[0151] The second dummy upper spacer 340_1 may be disposed on the second upper semiconductor substrate 300 disposed adjacent to the first side of the first upper semiconductor substrate 200. The second dummy upper spacer 340_1 may be disposed on each of the second upper fin patterns 310 formed on the second upper semiconductor substrate 300.

[0152] The second dummy upper spacer 340_1 may face the first dummy upper spacer 240_1. The upper interlayer insulating film 290 may be disposed between the second dummy upper spacer 340_1 and the first dummy upper spacer 240_1, between the short sidewalls of each first upper fin pattern 210 and each second upper fin pattern 310, and between the first upper semiconductor substrate 200 and the second upper semiconductor substrate 300.

[0153] The second upper source / drain region 350 formed on each second upper fin pattern 310 may be arranged along the first direction X together with the first upper source / drain region 250 .

[0154] exist Fig. 20 In the embodiment, the first cut upper source / drain region 250_1 is not formed on the first side of the first upper semiconductor substrate 200, but is formed on the other side of the first upper semiconductor substrate 200. However, exemplary embodiments are not limited thereto. The first cut upper source / drain region 250_1 may also not be formed on the second side of the first upper semiconductor substrate 200. In an exemplary embodiment, the first dummy upper spacer 240_1 may be disposed near the boundary of the second side of the first upper semiconductor substrate 200.

[0155] During the manufacturing process, at least one pre-upper gate structure 220p (see Fig.25 )'s gate electrode and the upper semiconductor substrate 200p to form the first upper semiconductor substrate 200 and the second upper semiconductor substrate 300.

[0156] Fig.21is a schematic layout diagram of a semiconductor device according to some exemplary embodiments. Fig. 22 is along Fig.21 For ease of description, the focus will be on the cross-sectional view taken along the line E-E'. Figures 2 to 5 The present embodiment is described with reference to the differences of some of the exemplary embodiments described.

[0157] Reference Fig.21 and Fig. 22 In the semiconductor device according to some exemplary embodiments, the sidewalls 200s of the first upper semiconductor substrate 200 (e.g., the sidewalls extending in the second direction Y), the short sidewalls of each first upper fin pattern 210, and the sidewalls of the first upper gate structure 220 may be aligned in the thickness direction of the first upper semiconductor substrate 200.

[0158] The first cut upper source / drain region 250_1 may not be formed on one side of the first upper semiconductor substrate 200 .

[0159] A sidewall of the second upper semiconductor substrate 300 disposed adjacent to one side of the first upper semiconductor substrate 200 may be aligned with a sidewall of each second upper fin pattern 310 and a sidewall of the second upper gate structure 320 in a thickness direction of the second upper semiconductor substrate 300 .

[0160] The second upper gate structure 320 may face the first upper gate structure 220. The upper interlayer insulating film 290 may be disposed between the first and second upper gate structures 220 and 320, between the short sidewalls of each first upper fin pattern 210 and each second upper fin pattern 310, and between the first and second upper semiconductor substrates 200 and 300.

[0161] The second upper source / drain region 350 formed on each second upper fin pattern 310 may be arranged along the first direction X together with the first upper source / drain region 250 .

[0162] During the manufacturing process, the pre-upper gate structure 220p (see Fig.25 ) and the pre-upper fin pattern 210p between the upper semiconductor substrate 200p (see Fig.26 ) to form a first upper semiconductor substrate 200 and a second upper semiconductor substrate 300.

[0163] exist Figures 1 to 22 In the embodiment, a first upper semiconductor substrate 200 is stacked on the lower semiconductor substrate 100. However, exemplary embodiments are not limited thereto. For example, a semiconductor substrate including another gate structure may also be stacked on the first upper semiconductor substrate 200.

[0164] Figures 23 to 30are views for explaining steps of a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0165] For reference, Fig.23 may be a region of the lower semiconductor substrate 100 (more specifically, Figure 1 Layout diagram of the first active area ACT1). Fig.24 is along Fig.23 A cross-sectional view taken along line F-F'. Fig.25 It may be a layout diagram of a region of the upper semiconductor substrate 200 p . Fig.26 is along Fig.25 A cross-sectional view taken along line G-G'. Fig.30 is along Fig.29 A cross-sectional view taken along line H-H'.

[0166] refer to Fig.23 and Fig.24 , a plurality of lower transistors may be formed on the lower semiconductor substrate 100 .

[0167] The lower transistors may include a plurality of lower fin patterns 110, a plurality of lower gate structures 120 and 120_1, and a plurality of lower source / drain regions 150. The lower transistors may be formed at locations where the lower fin patterns 110 and the lower gate structures 120 intersect, respectively.

[0168] The lower fin pattern 110 may extend in the first direction X. The lower gate structures 120 and 120_1 may extend in the second direction Y.

[0169] A lower interlayer insulating film 190 may be formed on the lower semiconductor substrate 100 to cover the lower gate structures 120 and 120_1 and the lower source / drain regions 150 .

[0170] A lower source / drain contact 170 and a first lower landing pad 171 connected to the lower source / drain region 150 may be formed in the lower interlayer insulating film 190 .

[0171] The lower interlayer insulating film 190 may be formed not by one process but by a plurality of processes. For example, after forming a portion of the lower interlayer insulating film 190, the lower source / drain contact 170 and the first lower landing pad 171 may be formed. Then, the remaining portion of the lower interlayer insulating film 190 may be formed.

[0172] A lower transistor, a lower source / drain contact 170 , and a first lower landing pad 171 may be formed in a lower element region 115 on the lower semiconductor substrate 100 .

[0173] refer to Fig.25 and Fig.26 , a plurality of upper transistors may be formed on the upper semiconductor substrate 200p.

[0174] The upper transistors may include a plurality of preliminary upper fin patterns 210p, a plurality of preliminary upper gate structures 220p, and a plurality of first upper source / drain regions 250. The upper transistors may be formed at locations where the preliminary upper fin patterns 210p and the preliminary upper gate structures 220p intersect, respectively.

[0175] On the upper semiconductor substrate 200 p , the preliminary upper fin pattern 210 p may extend in the first direction X. The preliminary upper gate structure 220 p may extend in the second direction Y.

[0176] Either or both of the pre-upper fin pattern 210p and the pre-upper gate structure 220p may be regularly arranged on the upper semiconductor substrate 200p. For example, the pre-upper fin pattern 210p may be arranged at a constant pitch P1 in the Y direction, and / or the pre-upper gate structure 220p may be arranged at a constant pitch P2 in the X direction. The constant pitch P1 in the Y direction may be the same as or different from the constant pitch P2 in the X direction.

[0177] A preliminary upper interlayer insulating film 291 may be formed on the upper semiconductor substrate 200 p .

[0178] The upper transistor may be formed in an upper element region 215 on the upper semiconductor substrate 200 p .

[0179] refer to Fig. 27 , the upper semiconductor substrate 200 p may be bonded to the support substrate 50 .

[0180] The upper element region 215 may be placed between the upper semiconductor substrate 200 p and the support substrate 50 .

[0181] Then, at least a portion of the upper semiconductor substrate 200 p may be removed to reduce the thickness of the upper semiconductor substrate 200 p.

[0182] For example, the upper semiconductor substrate 200p may be partially removed to leave a portion of the upper semiconductor substrate 200p below the upper element region 215. Alternatively, the entire upper semiconductor substrate 200p except for the upper element region 215 may be removed.

[0183] After the thickness of the upper semiconductor substrate 200 p is reduced, a bonding insulating layer 201 may be formed on the surface of the upper semiconductor substrate 200 p .

[0184] If the upper semiconductor substrate 200 p is or includes an SOI substrate, and a buried insulating layer of the SOI substrate is exposed during the partial removal of the upper semiconductor substrate 200 p , the bonding insulating layer 201 may not be formed.

[0185] refer to Fig.28 , the lower semiconductor substrate 100 and the upper semiconductor substrate 200p may be bonded together.

[0186] The upper semiconductor substrate 200p and the lower semiconductor substrate 100 may be bonded using the bonding insulating layer 201 (see Fig. 27 ). The bonding insulating layer 201 becomes a part of the lower interlayer insulating film 190 .

[0187] The bonding of the upper semiconductor substrate 200p and the lower semiconductor substrate 100 may cause misalignment of the preliminary upper gate structure 220p and the lower gate structures 120 and 120_1. However, since the preliminary upper fin pattern 210p and the preliminary upper gate structure 220p are regularly formed (e.g., as an array with a constant pitch) on the upper semiconductor substrate 200p, the size of the misalignment between the preliminary upper gate structure 220p and the lower gate structures 120 and 120_1 may not be large.

[0188] For example, the size of the misalignment may be less than half of the distance between corresponding sidewalls of adjacent lower gate structures 120 and 120_1. Alternatively, the size of the misalignment may be less than half of the distance between corresponding sidewalls of adjacent pre-upper gate structures 220p. For example, if the pre-upper gate structure 220p is formed with a constant pitch, the misalignment between the pre-upper gate structure 220p and the lower gate structures 120, 120_1 may be as small as the contact to polyester (CPP) pitch of the pre-upper gate structure 220p.

[0189] The first gate structure and the second gate structure may be adjacent to each other. Here, the first gate structure may include one sidewall and another sidewall, and the second gate structure may include one sidewall and another sidewall. If a source / drain region is formed between a first sidewall of the first gate structure and a second sidewall of the second gate structure (the first sidewall and the second sidewall face each other), one sidewall of the first gate structure and one sidewall of the second gate structure may be corresponding sidewalls.

[0190] Reference Fig.29 and Fig.30 , a first etching process may be performed to remove some of the preliminary upper gate structure 220p and some of the first upper source / drain region 250. In addition, a second etching process may be performed to partially remove the upper semiconductor substrate 200p.

[0191] After the first etching process and the second etching process, the first active area ACT1 (see Figure 2 ), leaving a first upper semiconductor substrate 200, a plurality of first upper gate structures 220, a plurality of first upper source / drain regions 250 and a plurality of first upper fin patterns 210 at corresponding positions.

[0192] The mask pattern used in the first etching process and the mask pattern used in the second etching process may be the same as or different from each other.

[0193] Through the first etching process, a short sidewall 230 b of the upper gate electrode may be formed, and a cut surface 250_1 s of the first cut upper source / drain region 250_1 may be formed.

[0194] Through the second etching process, a sidewall 200 s of the first upper semiconductor substrate 200 may be formed.

[0195] Next, refer to Fig.30 , an upper interlayer insulating film 290 may be formed on the lower interlayer insulating film 190 to cover the sidewalls 200 s of the first upper semiconductor substrate 200 .

[0196] After forming the upper interlayer insulating film 290 , the upper source / drain connection contacts 270 may be formed.

[0197] Unlike the accompanying drawings, the fin transistor including the first upper fin pattern 210 may not be formed on the upper semiconductor substrate 200p. Alternatively or additionally, a planar transistor may be formed. In this case, the first upper semiconductor substrate 200 may be a semiconductor substrate without an element isolation layer. Here, the first upper source / drain region 250 extending along the second direction Y may be formed between a plurality of first upper gate structures 220 extending along the second direction Y.

[0198] Fig.31 are views for explaining steps of a method of manufacturing a semiconductor device according to some exemplary embodiments. Fig.31 It can be in Figure 23 to Figure 26 The process that is then executed.

[0199] Reference Fig.31 , by placing the upper element region 215 and the lower element region 115 to face each other, the lower semiconductor substrate 100 and the upper semiconductor substrate 200 p may be bonded together.

[0200] The upper semiconductor substrate 200 p may be partially removed to reduce the thickness of the upper semiconductor substrate 200 p.

[0201] Then, a second etching process may be performed to partially remove the upper semiconductor substrate 200 p . In addition, a first etching process may be performed to remove some of the plurality of preliminary upper gate structures 220 p and some of the plurality of first upper source / drain regions 250 .

[0202] The mask pattern used in the second etching process and the mask pattern used in the first etching process may be the same as or different from each other.

[0203] For example, if the mask pattern used in the second etching process is the same as the mask pattern used in the first etching process, it is possible to manufacture a Figure 12 to Figure 14 A semiconductor device such as the semiconductor device shown in .

[0204] For another example, if the mask pattern used in the second etching process and the mask pattern used in the first etching process are different from each other, it is possible to manufacture a Figures 15 to 18 A semiconductor device such as the semiconductor device shown in .

[0205] The foregoing is an illustration of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, it will be readily appreciated by those of ordinary skill in the art that a variety of modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A semiconductor device, comprising: a lower semiconductor substrate; A lower gate structure, on the lower semiconductor substrate, the lower gate structure comprising a lower gate electrode; a lower interlayer insulating film, on the lower semiconductor substrate, the lower interlayer insulating film covering the lower gate structure; an upper semiconductor substrate on the lower interlayer insulating film; an upper gate structure on the lower interlayer insulating film; an upper interlayer insulating film, on the lower interlayer insulating film, the upper interlayer insulating film covering the sidewalls of the upper semiconductor substrate; a lower gate contact, in contact with the lower gate electrode; a landing pad in contact with the lower gate contact; and an upper gate connection contact connected to an upper transistor, the upper transistor including an upper gate electrode, wherein the upper gate connection contact is directly connected to the landing pad, The upper gate structure includes an upper gate electrode extending in a first direction and an upper gate spacer extending along a sidewall of the upper gate electrode. wherein the upper gate electrode comprises a long sidewall extending in the first direction and a short sidewall extending in a second direction, the second direction being different from the first direction, and The upper gate spacer is on the long sidewall of the upper gate electrode, but not on the short sidewall of the upper gate electrode.

2. The semiconductor device according to claim 1, further comprising: An upper source / drain connection contact penetrates the upper semiconductor substrate, wherein the upper source / drain connection contact electrically connects a lower transistor to the upper transistor, the lower transistor including the lower gate electrode.

3. The semiconductor device according to claim 1, wherein The upper gate connection contact is provided in the upper interlayer insulating film and is provided in the lower interlayer insulating film, The upper gate connection contact electrically connects a lower transistor to the upper transistor, the lower transistor including the lower gate electrode, and The upper gate connection contact is on an upper surface of the lower semiconductor substrate that does not overlap with the upper semiconductor substrate.

4. The semiconductor device according to claim 1, wherein: The lower gate structure, the upper semiconductor substrate and the upper gate structure are sequentially stacked on the lower semiconductor substrate.

5. The semiconductor device according to claim 1, wherein The lower gate structure and the upper gate structure are between the lower semiconductor substrate and the upper semiconductor substrate.

6. The semiconductor device according to claim 1, wherein In the first direction, a portion of the upper gate structure protrudes further than a sidewall of the upper semiconductor substrate.

7. The semiconductor device according to claim 1, wherein The lower transistor includes the lower gate electrode, The lower transistor includes a fin field effect transistor FinFET, a vertical field effect transistor VFET, a transistor including a nanowire, a transistor including a nanosheet, or a planar transistor, and The upper transistor includes a fin field effect transistor FinFET, a vertical field effect transistor VFET, a transistor including a nanowire, a transistor including a nanosheet, or a planar transistor.

8. A semiconductor device comprising: A lower semiconductor substrate including a first region and a second region, wherein the second region surrounds the first region; A lower gate structure, on the lower semiconductor substrate, the lower gate structure comprising a lower gate electrode; an upper semiconductor substrate, on the first region of the lower semiconductor substrate, the upper semiconductor substrate comprising a first surface and a second surface opposite to the first surface; A plurality of upper gate structures, each of which comprises an upper gate electrode on the first surface of the upper semiconductor substrate; a plurality of upper source / drain regions on at least one side of each respective one of the upper gate structures; as well as an etch stop layer extending along the first surface of the upper semiconductor substrate, wherein the etching stop layer is on the first region of the lower semiconductor substrate but not on the second region of the lower semiconductor substrate, and The upper semiconductor substrate is on a portion of the lower semiconductor substrate, and the portion is smaller than the entire lower semiconductor substrate.

9. The semiconductor device according to claim 8, wherein: The etching stop layer extends along the upper surface of the source / drain region.

10. The semiconductor device according to claim 8, wherein At least one of the plurality of upper source / drain regions includes a cut surface extending in a thickness direction of the upper semiconductor substrate, and the etch stop layer is not on the cut surface.

11. The semiconductor device according to claim 8, wherein Each of the upper gate structures includes a gate sidewall, the upper gate electrode includes a long sidewall extending in a first direction and a short sidewall extending in a second direction, the second direction is different from the first direction, the gate sidewall is on the long sidewall of the upper gate electrode, and the gate sidewall is not on the short sidewall of the upper gate electrode.

12. A semiconductor device comprising: a lower semiconductor substrate comprising a first region and a second region defined around the first region; a plurality of lower transistors, wherein in the lower semiconductor substrate, the plurality of lower transistors include a plurality of lower gate structures and a plurality of lower source / drain regions, the plurality of lower gate structures extend in a first direction, and the plurality of lower source / drain regions are between the plurality of lower gate structures; a lower interlayer insulating film, on the lower semiconductor substrate, the lower interlayer insulating film covering the plurality of lower gate structures and the plurality of lower source / drain regions; an upper semiconductor substrate on the lower interlayer insulating film in the first region; an upper interlayer insulating film, on the lower interlayer insulating film, the upper interlayer insulating film covering the sidewalls of the upper semiconductor substrate; a plurality of upper transistors, wherein the plurality of upper transistors are located at positions overlapping the first region of the lower semiconductor substrate in the upper semiconductor substrate, the plurality of upper transistors comprising a plurality of upper gate structures and a plurality of upper source / drain regions, the plurality of upper gate structures extending in the first direction, and the plurality of upper source / drain regions being between the plurality of upper gate structures; a first connection contact connecting at least one of the plurality of upper gate structures to at least one of the plurality of lower transistors; as well as a second connection contact connecting at least one of the plurality of upper source / drain regions to at least one of the plurality of lower transistors; Wherein, at least one of the first connection contact and the second connection contact penetrates the upper semiconductor substrate.

13. The semiconductor device according to claim 12, wherein: Each of the plurality of upper gate structures comprises an upper gate electrode and a gate spacer extending along a sidewall of the upper gate electrode, wherein The upper gate electrode includes a long sidewall extending in the first direction and a short sidewall extending in a second direction, the second direction being different from the first direction, and The gate spacer is on the long sidewall of the upper gate electrode but not on the short sidewall of the upper gate electrode.

14. The semiconductor device according to claim 12, wherein: At least one upper source / drain region among the plurality of upper source / drain regions includes a cut surface extending in a thickness direction of the upper semiconductor substrate.

15. The semiconductor device according to claim 12, wherein: The plurality of lower gate structures, the upper semiconductor substrate, and the plurality of upper gate structures are sequentially stacked on the lower semiconductor substrate.

16. The semiconductor device according to claim 12, wherein: The plurality of lower gate structures and the plurality of upper gate structures are between the lower semiconductor substrate and the upper semiconductor substrate.

17. The semiconductor device according to claim 12, wherein: The plurality of upper gate structures include a boundary gate structure at an outermost edge of the upper semiconductor substrate, Wherein, the sidewall of the boundary gate structure extending in the first direction and the sidewall of the upper semiconductor substrate extending in the first direction are aligned in the thickness direction of the upper semiconductor substrate.

18. The semiconductor device according to claim 12, further comprising: a dummy sidewall spacer, on the upper semiconductor substrate, the dummy sidewall spacer is parallel to the upper gate structure, The sidewall of the dummy spacer extending in the first direction and the sidewall of the upper semiconductor substrate extending in the first direction are aligned in the thickness direction of the upper semiconductor substrate.

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