Buck Mode Valley Current Sense Replica Linearization

Abstract

The present application discloses a buck mode valley current sensing replica linearization. A current measurement linearization circuit (105) for a DC / DC boost converter (100) includes a back gate sense transistor (Mbg, sense) and a back gate reset transistor (Mbg, reset). The back gate sense transistor has a first terminal (drain) coupled to a first body contact (BG_MP0) of a high side power transistor (MP0) and a second terminal (source) coupled to a second body contact (BG_MP1) of a first replica transistor (MP1) in a valley current detection circuit 110. The back gate reset transistor has a first terminal (source) coupled to a maximum reference voltage (Vmax) and a second terminal (drain) coupled to a second body contact, the maximum reference voltage being equal to the greater of an input voltage (Vin) and an output voltage (Vout).

Description

[0001] Priority under 35 USC § 119(e) & 37 CFR § 1.78

[0002] This non-provisional application claims priority based on the following prior U.S. provisional patent applications: (i) “Down-Mode Valley-Current-Sense Replica Linearization”, in the name of Stefan Dietrich and Joerg Kirchner, filed on August 23, 2018, Application No.: 62 / 723,803, all of which are incorporated herein by reference. Technical Field

[0003] The disclosed embodiments relate generally to the field of power circuits. More specifically, and without limitation, the present disclosure relates to buck mode valley current sensing replica linearization. Summary of the invention

[0004] The disclosed embodiments provide a current measurement linearization circuit for a valley current controlled boost converter in down-mode operation. During the buck mode, the current measurement linearization circuit isolates the back gate of the replica transistor from the capacitive coupling between the switch node and the sense node and allows the replica voltage to be reset. The current measurement linearization circuit can provide higher current sensing accuracy in the buck mode, which can increase the boost mode to buck mode line conversion performance.

[0005] In one aspect, an embodiment of a current measurement linearization circuit for a DC / DC boost converter is disclosed. The current measurement linearization circuit includes a back-gate sense transistor having a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley current sense circuit; and a back-gate reset transistor having a first terminal coupled to a maximum reference voltage and a second terminal coupled to a second body contact, the maximum reference voltage being equal to the greater of an input voltage and an output voltage.

[0006] In another aspect, one embodiment of a DC / DC boost converter implemented on an integrated circuit (IC) chip is disclosed. The DC / DC boost converter includes: a low-side power transistor coupled in series with a high-side power transistor between a first pin and a second pin, a switch node between the low-side power transistor and the high-side power transistor being coupled to a third pin; a back-gate disconnect transistor coupled between a first body contact and the second pin of the high-side power transistor; a valley current sensing circuit including a first replica transistor and a second replica transistor, the first replica transistor coupled in series with a first current sink between the switch node and a lower rail, a node between the first replica transistor and the first current sink being coupled to provide a replica voltage to an inverting input of a comparator, a second replica transistor coupled in series with a second current sink between a maximum reference voltage and the lower rail, a node between the second replica transistor and the second current sink being coupled to provide a comparison voltage at a non-inverting input of the comparator; and a current measurement linearization circuit including a back-gate sense transistor and a back-gate reset transistor, the back-gate sense transistor being coupled between the first body contact and a second body contact of the first replica transistor, the back-gate reset transistor being coupled between the second body contact and the maximum reference voltage.

[0007] On the other hand, an embodiment of a method of operating a DC / DC boost converter is disclosed. The method includes providing a DC / DC boost converter implemented in an integrated circuit chip, the DC / DC boost converter including a high-side power transistor as a P-type metal oxide silicon (PMOS) transistor, the DC / DC boost converter coupled to provide an output voltage using valley current control; coupling a first pin to a ground plane; coupling a second pin to an output capacitor and a load; and coupling a third pin to an input voltage through an inductor, thereby coupling the inductor to the high-side power transistor and a first replica transistor; wherein the DC / DC boost converter is coupled during a boost mode to connect a first body contact of the high-side power transistor and a second body contact of the first replica transistor together and further coupled during a buck mode to connect the first body contact and the second body contact together when the low-side power transistor is turned off, and during a buck mode to disconnect the first body contact and the second body contact when the low-side power transistor is turned on, and to couple the second body contact to a maximum reference voltage, the maximum reference voltage being equal to the larger of the input voltage and the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, embodiments of the present disclosure are illustrated by way of example and not limitation, in which like reference numerals represent similar elements. It should be noted that different references to "one" or "an" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such reference may represent at least one. In addition, when describing a particular feature, structure or characteristic in conjunction with an embodiment, it is proposed that the knowledge of those skilled in the art is to implement such feature, structure or characteristic in conjunction with other embodiments, whether or not explicitly described. As used herein, the term "coupled" is meant to represent an indirect or direct electrical connection, unless limited to "communicatively coupled", which may include a wireless connection. Therefore, if a first device is coupled to a second device, the connection may be by a direct electrical connection, or by an indirect electrical connection via other devices and connections.

[0009] The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, wherein:

[0010] Figure 1 An example of a DC / DC boost converter according to one embodiment of the present disclosure is depicted;

[0011] Figure 2A Depicted is a diagram of a process during boost mode according to one embodiment of the present disclosure. Figure 1 Various voltage and current values ​​on the DC / DC boost converter;

[0012] Figure 2B Depicted is a diagram of a process during buck mode according to one embodiment of the present disclosure. Figure 1 Various voltage and current values ​​on the DC / DC boost converter;

[0013] Figure 3 A flow chart depicting a method of operating a DC / DC boost converter implemented on an IC chip according to one embodiment of the present disclosure;

[0014] Figure 3A Provided Figure 3 A further elaboration and continuation of a method of operating a DC / DC boost converter implemented on an IC chip;

[0015] FIG4 depicts an example DC / DC boost converter with valley current sensing according to the prior art;

[0016] Figure 5A depicts various voltage and current values ​​across the DC / DC boost converter of FIG. 4 during boost mode; and

[0017] Figure 5BDepicted are various voltage and current values ​​across the DC / DC boost converter of FIG. 4 during buck mode, and potential issues addressed by the present disclosure. DETAILED DESCRIPTION

[0018] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of embodiments of the present invention, many specific details are set forth in order to provide a more thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that the present invention can be practiced without these specific details. In other cases, well-known features are not described in detail to avoid making the description unnecessarily complicated.

[0019] Modern boost converters operating at very large duty cycles can support two modes of operation. Boost-mode operation occurs during steady-state operation when the output voltage Vout is greater than the input voltage Vin. Down-mode operation occurs less frequently but is used during startup or in special steady-state applications where the output voltage Vout is less than the input voltage Vin.

[0020] 4 depicts a DC / DC boost converter 400 having a low-side power transistor MN0 and a high-side power transistor MP0 located between a ground node 402 and an output node 404, wherein the low-side power transistor MN0 is an N-type metal oxide silicon (NMOS) transistor, coupled in series with the high-side power transistor MP0, which is a P-type metal oxide silicon (PMOS) transistor. The ground node 402 is coupled to a lower rail, such as a ground plane, and the output node 404 is coupled to provide an output voltage Vout. The input voltage Vin is coupled to an inductor L, which is also coupled to a switch node SW located between the low-side power transistor MN0 and the high-side power transistor MP0. The capacitor C is typically an external capacitor, and the resistor Rload represents the load on the DC / DC boost converter 400.

[0021] A back gate disconnect transistor Mbg is also shown, which is coupled between the back gate (also called body contact) of the high side power transistor MP0 and the output node 404 providing the output voltage Vout. The body contact of the back gate disconnect transistor Mbg is also coupled to the body contact of the high side power transistor MP0. The circuit 410 is designed to measure the valley current through the high side power transistor MP0, and includes a first replica transistor MP1, a second replica transistor MP2, a comparator 412, a first current sink CS1 that absorbs the error amplifier control current Ictrl, and a second current sink CS2 that absorbs the constant reference current Iccm. The first replica transistor MP1 is coupled in series with the first current sink CS1 between the switch node SW and the lower rail, wherein a replica voltage N1 obtained from a point between the first replica transistor MP1 and the first current sink CS1 is provided to the non-inverting input of the comparator 412. Similarly, the second replica transistor MP2 is coupled in series with the second current sink CS2 between the maximum reference voltage Vmax and the lower rail, and a comparison voltage N2 taken from a point between the second replica transistor MP2 and the second current sink CS2 is provided to the non-inverting input of the comparator 412 .

[0022] The first replica transistor MP1 is a much smaller version of the high-side power transistor MP0. In one embodiment, the high-side power transistor MP0 is a very large switch, and the first replica transistor MP1 is one ten-thousandth smaller, so the resistance across the gate of the first replica transistor MP1 is ten thousand times that of the high-side power transistor MP0. The first current sink CS1 is controlled so that the current I multiplied by the drain / source on-resistance Rds,on of the high-power transistor MP0 is equal to the current multiplied by the drain / source on-resistance of the replica transistor MP1, that is,

[0023] I MP0 ×R ds,on,MP0 = l MP1 ×R ds,on,MP1 Equation 1

[0024] This relationship sets the value of replica voltage N1, which can be used to determine the current through high-side power transistor MP0.

[0025] When the DC / DC boost converter 400 operates in boost mode, the low-side power transistor MN0 and the high-side power transistor MP0 are turned on and off in opposite phases, and their duty cycle is determined based on the input voltage Vin and the output voltage Vout. When valley current control is implemented, the circuit 410 senses the high-side transistor current and compares the high-side transistor current with a reference current. Once the sensed valley current is equal to the reference current, the high-side power transistor MP0 is turned off and the low-side power transistor MN0 is turned on. The low-side power transistor MN0 remains turned on until a clock signal (e.g., in a constant frequency system) or a timer (e.g., in a constant on-time system) provides a trigger to turn off the low side and turn on the high side again.

[0026] During the boost mode, the low-side power transistor MN0 and the high-side power transistor MP0 are driven in a linear mode when turned on to act as switches. However, when the DC / DC boost converter 400 operates in the buck mode, the high-side power transistor MP0 cannot operate in a linear mode when turned on because the output voltage Vout is less than the input voltage Vin. This means that during the discharge phase, i.e., when the high-side power transistor MP0 is turned on, the voltage across the inductor L is still positive and the inductor current increases.

[0027] In order to allow inductor current regulation in buck mode, the high-side power transistor MP0 is placed in a special operating mode in which the gate of the high-side power transistor MP0 is connected to the input voltage Vin and the body contact BG_PMOS is disconnected from the output node 404 and therefore disconnected from the output voltage Vout. It is necessary to disconnect the body contact BG_PMOS from the output node 404 to avoid back-gate current flow. Because the output voltage Vout is not the highest potential present in buck mode, connecting the input voltage Vin at the switch node SW will cause a back-gate current to flow through the high-side power transistor MP0, so that the high-side power transistor MP0 no longer provides isolation. The back-gate disconnect transistor Mbg is turned off to disconnect the body contact BG_PMOS+ of the high-side power transistor MP0 from the output voltage Vout.

[0028] To disconnect the body contact BG_PMOS from the output voltage Vout in buck mode, the gate of the back gate disconnect transistor Mbg is tied to the input voltage Vin. When the body contact BG_PMOS is disconnected from the output node 404 and the gate of the high side power transistor MP0 is connected to the input voltage Vin, the high side power transistor MP0 acts as a passive diode instead of a switch.

[0029] When current flows from the switch node SW to the output node 404, the switch node voltage Vsw will increase to a value VThigh-side above the input voltage Vin, where VThigh-side is the threshold voltage of the high-side power transistor MP0, at which point the high-side power transistor MP0 begins to conduct current. In order to seamlessly transition between the boost mode where the output voltage Vout is greater than the input voltage Vin and the buck mode where the output voltage Vout is less than the input voltage Vin without interference, a current sensing circuit that can handle both modes is required.

[0030] Circuit 410 is a typical replica transistor-based valley current control sensing circuit that operates in boost mode and buck mode. When the current across the high-side power transistor MP0 flows from the switch node SW to the output node 404, the current generates a voltage drop proportional to the respective drain / source on-resistance Rds,on multiplied by the load current. Using the first replica switch MP1 connected to the switch node SW and the error amplifier control current Ictrl, the voltage drop across the first replica transistor MP1 matches the voltage drop across the high-side power transistor MP0 divided by the replica factor and generates a replica voltage N1. Once the value of the replica voltage N1 drops below the comparison voltage N2, the current across the high-side power transistor MP0 drops below the desired valley current, and the comparator 412 provides a high value on the valley current comparison signal VAL_COMP, which turns on the low-side power transistor MN0.

[0031] In order to be able to sense negative valley current, the second replica transistor MP2 is used to generate an offset voltage combined with a constant reference current Iccm. The second replica transistor MP2 is coupled to a maximum reference voltage Vmax, which is the higher voltage of the output voltage Vout and the input voltage Vin. In boost mode, the maximum reference voltage Vmax is equal to the output voltage Vout, and in drop mode, the maximum reference voltage Vmax is equal to the input voltage Vin. The constant reference current Iccm and the drain / source on-resistance Rds,on of the second replica transistor MP2 generate a comparison voltage N2, which is typically set to match the zero load current across the high-side power transistor MP0. If the error amplifier control current Ictrl is greater than the constant reference current Iccm, the DC / DC boost converter 400 adjusts to a positive valley current across the high-side power transistor MP0. For the error amplifier control current Ictrl less than the constant reference current Iccm, the DC / DC boost converter 400 adjusts to a negative valley current, and if the error amplifier control current Ictrl is equal to the constant reference current Iccm, the DC / DC boost converter 400 adjusts to a zero valley current. However, in the boost mode, the comparison voltage N2 is approximately equal to the output voltage Vout, and in the buck mode, the comparison voltage N2 is approximately equal to the input voltage Vin, because the maximum reference voltage Vmax is equal to the input voltage Vin, which is greater than the output voltage Vout in the buck mode.

[0032] The first replica transistor MP1 maintains the same operating mode as the high-side power transistor MP0. Accordingly, when the high-side power transistor MP0 is in the boost mode, the first replica transistor MP1 is also in the boost mode, and when the high-side power transistor MP0 is in the buck mode, the first replica transistor MP1 is in the buck mode. As a result, under the buck mode operation, the body contact of the first replica transistor MP1 also needs to be disconnected from the output voltage Vout. As shown in FIG4, the body contact of the first replica transistor MP1 is coupled to both the drain and the body contact of the high-side power transistor MP0.

[0033] Figure 5A depicts a plurality of graphs showing voltage and current values ​​of the DC / DC boost converter 400 during boost mode, and Figure 5BGraphs with the same voltage and current values ​​during buck mode are depicted, and illustrate the problems associated with disconnected and high impedance body contact BG_PMOS during buck mode operation of prior art solutions. Graph 500A depicts the voltage waveforms on switch node SW, body contact BG_PMOS, replica voltage N1, and comparison voltage N2 during boost mode operation. During the same time period, graph 500B depicts the back gate current IBG_MP1 across the first replica transistor MP1 equal to zero, and graph 500C depicts the time when each of the high-side power transistor MP0 and the low-side power transistor MN0 is turned on, the clock / timer signal 505 that turns on the high-side power transistor MP0, and the valley current comparison signal VAL_COMP 510 that turns on the low-side power transistor MN0.

[0034] When the high-side power transistor MP0 in boost mode is turned on during time period TA, graph 500A illustrates that for a positive load current across the high-side power transistor MP0, the voltage on the switch node SW is greater than the output voltage Vout. The body contact BG_PMOS is connected to the output voltage Vout, which is the highest potential in the circuit and is therefore the same as the maximum reference voltage Vmax. The comparison voltage N2 is constant and less than the output voltage Vout. The replica voltage N1 drops during the current measurement phase in time period TA. Once the replica voltage N1 is equal to the comparison voltage N2, a high value (graph 500C) is provided on the valley current comparison signal VAL_COMP 510, which turns on the low-side power transistor MN0 in time period TB. The replica voltage N1 (graph 500A) is reset to a value of the output voltage Vout during the conduction phase of the low-side power transistor MN0 in time period TB, so that false triggering of the valley current comparison signal VAL_COMP 510 does not occur. After a certain on-time of the low-side power transistor MN0 (for a constant-time on converter) or the converter clock (for a fixed frequency converter), a high value on the clock / timer signal 505 (graph 500C) again causes the low-side power transistor MN0 to be turned off and the high-side power transistor MP0 to be turned on. During the boost mode, the back-gate current IBG_MP1 (graph 500B) on the first replica transistor MP1 remains at zero.

[0035] When the converter is in buck mode, Figure 5BAs shown, the gate of the high-side power transistor MP0 is connected to the input voltage Vin, the body contact BG_PMOS is disconnected from the output voltage Vout and is therefore floating, and the high-side power transistor MP0 behaves as a passive diode. However, sharing the disconnected body contact BG_PMOS with the first replica transistor MP1 may cause several problems with current sensing during buck mode. During the time period TC after the low-side power transistor MN0 is turned off (graph 500F), the voltage on the switch node SW rises to approximately the input voltage Vin and then slowly decreases (graph 500D). The voltage on the body contact BG_PMOS rises to a value equal to the input voltage Vin plus the threshold voltage VTbg, where VTbg is the threshold voltage of the back gate disconnect transistor Mbg of the DC / DC boost converter 400. The comparison voltage N2 has a constant value less than the input voltage Vin and the replica voltage N1 is initially set to a value equal to the voltage on the switch node SW, but decreases faster than the switch node SW until the replica voltage N1 is equal to the comparison voltage N2 and triggers the conduction of the valley current comparison signal VAL_COMP 510.

[0036] When the low-side power transistor MN0 is enabled in time period TD, the switch node SW is pulled to ground, as shown in graph 500D, and the body contact BG_PMOS is pulled to the value of Vout-VTbg. Since both the high-side power transistor MP0 and the first replica transistor MP1 are connected to the switch node SW, the high-impedance body contact BG_PMOS suffers from capacitive coupling introduced by the switch node SW. When the low-side power transistor MN0 is turned on, the replica voltage N1 is usually reset to a potential higher than the comparison voltage N2, as shown in graph 500A for boost mode. This reset is performed by connecting the first replica transistor MP1 to the maximum reference voltage Vmax, which is not specifically shown in FIG. 4, and it is completed to prevent the comparator 412 from triggering an erroneous valley current comparison signal VAL_COMP. However, when the body contact BG_PMOS is equal to (Vout-VTbg), the replica voltage N1 is discharged toward the back gate disconnect transistor Mbg with a non-zero static back gate current IBG_MP1 across the back gate of the first replica transistor MP1 (graph 500E), however, the comparison voltage N2 remains constant near the input voltage Vin, which is the value of the maximum reference voltage Vmax during the buck mode. The parasitic discharge of the replica voltage N1 to a value far below the comparison voltage N2, which is approximately equal to the input voltage Vin in the buck mode, has several disadvantages. Once the low-side power transistor MN0 is disabled, the comparator 412 is used to measure the valley current. Because the replica voltage N1 has been parasitically discharged, the comparator can trigger an erroneous high value on the valley current comparison signal VAL_COMP 510 (graph 500F), and the converter control can generate a glitch, which will turn on the low-side power transistor MN0 again. In the worst case, this may result in higher frequency operation without maintaining stable operation. The second disadvantage is the static back-gate current IBG,MP1 across the first replica transistor MP1.

[0037] Once the low-side power transistor MN0 is disabled at the end of the time period TD, the voltage on the switch node SW floats to the value (Vin+VThigh-side), causing the high-side power transistor MP0 to start conducting as a passive diode. As the switch node SW increases, the voltage on the body contact BG_PMOS also increases to the value (Vin+VTbg) until the back-gate disconnect transistor Mbg is forward biased. The potential on the body contact BG_PMOS is now the highest potential again, causing the back-gate current IBG,MP1 across the first replica transistor MP1 to stop, allowing the replica voltage N1 to rise to a normal value.

[0038] After studying the possible problems in the DC / DC boost converter 400, we now turn to Figure 1 , which provides a solution. Figure 1 An example of a DC / DC boost converter 100 implemented in an integrated circuit chip 101 according to an embodiment of the present invention is depicted. In the DC / DC boost converter 100, a low-side power transistor MN0 is coupled in series with a high-side power transistor MP0 between a first pin P1 and a second pin P2. A switch node SW located between the low-side power transistor MN0 and the high-side power transistor MP0 is coupled to a third pin P3. During operation of the DC / DC boost converter 100, the first pin P1 is coupled to a lower rail, which may be a ground plane; the second pin P2 is coupled to a first node of a capacitor C and a load coupled to a resistor Rload; and the third pin P3 is coupled to an input voltage through an inductor L. Because the connections between the various body contacts are relevant to the present disclosure, the individual body contacts are referenced by their respective transistors as follows: the high-side power transistor MP0 has a first body contact BG_MP0, the first replica transistor MP1 has a second body contact BG_MP1, and the back-gate disconnect transistor Mbg has a third body contact BG_Mbg. The back gate disconnect transistor Mbg is coupled between the first body contact BG_MP0 and the second pin to decouple the first body contact BG_MP0 from the output voltage Vout as required. The third body contact BG_Mbg is coupled to the first body contact BG_MP0.

[0039] The valley current sensing circuit 110 includes a first replica transistor MP1 coupled in series with a first current sink CS1 between a switch node SW and a lower rail. The first current sink CS1 controls the current Ictrl through an error amplifier. A replica voltage N1 captures a point between the first replica transistor MP1 and the first current sink CS1 and is provided to an inverting input of a comparator 112. A second replica transistor MP2 is coupled in series with the second current sink CS2 between a maximum reference voltage Vmax and the lower rail. The maximum reference voltage Vmax is equal to the higher value of the input voltage Vin and the output voltage Vout. A comparison voltage N2 captures a point between the second replica transistor MP2 and the second current sink CS2 and is provided to a non-inverting input of the comparator 112. The comparator 112 provides a valley current comparison signal VAL_COMP, which can be used to initiate the conduction of the low-side power transistor MN0 and can also be used to initiate the cutoff of the high-side power transistor MP0 when the high-side power transistor MP0 is operated as a switch.

[0040] A new current measurement linearization circuit 105 has been added to the DC / DC boost converter 100 and includes two new transistors. The back-gate sense transistor Mbg,sense has a first terminal coupled to the first body contact BG_MP0 and the third body contact BG_Mbg and a second terminal coupled to the second body contact BG_MP1. The back-gate sense transistor Mbg,sense is capable of isolating the second body contact BG_MP1 from the first body contact BG_MP0 and the third body contact BG_Mbg. The back-gate reset transistor Mbg,reset is coupled between the maximum reference voltage Vmax and the second body contact BG_MP1.

[0041] When the low-side power transistor MN0 is activated, the back-gate sense transistor Mbg,sense and the back-gate reset transistor Mbg,reset are controlled to separate the first body contact BG_MP0 and the third body contact BG-Mbg from the second body contact BG_MP1. However, during the buck mode, when the low-side power transistor MN0 is enabled, the first body contact BG_MP0 still floats to (Vout-VTbg) and when the low-side power transistor MN0 is disabled, the first body contact BG_MP0 still floats to (Vin+VTbg), when the low-side power transistor MN0 is not activated, the second body contact BG_MP1 is only connected to the first body contact BG_MP0, and when the low-side power transistor MN0 is activated, the second body contact BG_MP0 is connected to the maximum reference voltage Vmax.

[0042] During the on-phase of the low-side power transistor MN0, when the first body contact BG_MP0 drops to (Vout-VTbg), the back-gate reset transistor Mbg,reset is also turned on to connect the second body contact BG_MP1 to the maximum reference voltage Vmax. During this same period, the back-gate sense transistor Mbg,sense is turned off. Connecting the second body contact BG_MP1 to the maximum reference voltage Vmax avoids any discharge of the replica voltage N1 toward the first body contact BG_MP0, because the maximum reference voltage Vmax is greater than the replica voltage N1 and the body diode of the first replica transistor MP1 is not forward biased. This feature improves Figure 5B In the prior art sampling method shown in , parasitic discharge of the replica voltage N1 may occur.

[0043] When the low-side power transistor MN0 is turned off and the first body contact BG_MP0 floats to (Vin+ VTbg), the back-gate sense transistor Mbg,sense is turned on to connect the second body contact BG_MP1 to the first body contact BG_MP0 so that the high-side power transistor MP0 and the corresponding replica transistor MP1 have the same body potential. This body connection during the current regulation phase enables accurate current regulation and no mismatch between the high-side power transistor MP0 and the replica transistor MP1. During this period, the back-gate reset transistor Mbg,reset is turned off.

[0044] The waveforms associated with the DC / DC boost converter 100 are shown in FIG. Figure 2A and Figure 2B As shown in FIG. 2 , graphs 200A, 200B and 200C depict waveforms during boost mode, and graphs 200D, 200E and 200F depict waveforms during buck mode. During boost mode, the first body contact BG_MP0 is connected to the output voltage Vout and turns on the back gate sense transistor Mbg,sense. This means that, as shown in graph 200A, the voltage on the second body contact BG_MP1 is equal to the voltage on the first body contact BG_MP0, so that the operation is the same as Figure 5A It can be seen that there is no back gate current IBG,MP1 across the first replica transistor MP1, as shown in the graph 200B, and both the clock / timer signal 205 and the valley current comparison signal VAL_COMP210 are the same as Figure 5A The operation proceeds similarly, as shown in graph 200C.

[0045] However, in the buck mode, the back gate sense transistor Mbg,sense is used to couple the second body contact BG-MP1 to the first body contact BG_MP0 only during the first time period T1 when the low side power transistor MN0 is turned off. During the second time period T2 when the low side power transistor MN0 is turned on, the back gate reset transistor Mbg,reset is turned on and couples the second body contact BG-MP1 to the maximum reference voltage Vmax. Therefore, the switching of the back gate sense transistor Mbg,sense and the back gate reset transistor Mbg,reset generates an updated voltage on the second body contact BG_MP1, which is divided into two parts and controlled by the switching cycle of the low side power transistor MN0.

[0046] The connection of the first body contact BG_MP0 to the second body contact BG_MP1 is critical for accurate valley current sensing using the replica voltage N1 and the comparison voltage N2. During the current sensing period in the inductor discharge phase, for example, the first time period T1 and the third time period T3, the first replica transistor MP1 must match the high-side power transistor MP0, as shown in the graph 200D, because any difference in the first body contact BG_MP0 and the second body contact BG_MP1 will produce static errors and degrade performance during the transition between the boost mode and the buck mode.

[0047] When the low-side power transistor MN0 is enabled in the second time period T2, the first body contact BG_MP0 is equal to (Vout-VTbg), and the back-gate reset transistor Mbg,reset is turned on to couple the second body contact BG_MP1 to the maximum reference voltage Vmax. The resulting voltage on the second body contact BG_MP1 prevents parasitic discharges across the first replica transistor MP1 and the back-gate disconnect transistor Mbg, and means that the replica voltage N1 does not drop to a potential below the comparison voltage N2. The reset of the replica voltage N1 defined relative to the comparison voltage N2 avoids false triggering of the valley current comparator, as shown in the curve 200F, and also avoids a static current from the replica voltage N1 flowing through the first replica transistor MP1 and the back-gate sense transistor Mbg,sense toward the back-gate disconnect transistor Mbg, as shown in the curve 200E. Once the low-side power transistor MN0 is turned off, the switch node SW increases and due to capacitive coupling, the voltage at the first body contact BG_MP0 increases to (Vin+VTbg). Because (Vin+VTbg) is process and temperature dependent, the second body contact BG_MP1 needs to follow the first body contact BG_MP0, which is achieved through the back gate sense transistor Mbg,sense coupling.

[0048] Figure 3A flow chart of a method 300 of operating a DC / DC boost converter implemented in an integrated circuit chip is depicted. The method 300 begins by providing 305 a DC / DC boost converter implemented in an integrated circuit chip. The DC / DC boost converter includes a high-side power transistor that is a PMOS transistor and is coupled to provide an output voltage using valley current control. The method continues by coupling 310 a first pin to a ground plane; coupling 315 a second pin to an output capacitor and a load; and coupling 320 a third pin to an input voltage through an inductor, whereby the inductor is coupled to the high-side power transistor and the first replica transistor. During a boost mode, the DC / DC boost converter is coupled to connect together a first body contact of the high-side power transistor and a second body contact of the first replica transistor, and further coupled during a buck mode in which the low-side power transistor is turned off to connect together the first body contact and the second body contact. During a buck mode in which the low-side power transistor is on, the DC / DC boost converter is coupled to decouple the first and second body contacts and couple the second body contact to a maximum reference voltage equal to a maximum of an input voltage and an output voltage of the DC / DC converter.

[0049] Figure 3A Further elaboration and continuation of element 305 is provided, which provides that the DC / DC boost converter also includes providing 325 a back gate disconnect transistor coupled between the high side power transistor and the second pin, a back gate sense transistor coupled between a body contact of the back gate disconnect transistor and a body contact of the first replica transistor, and a back gate reset transistor coupled between a back gate of the first reset transistor and a maximum reference voltage.

[0050] Applicants have disclosed a DC / DC boost converter including a current measurement linearization circuit to isolate a first body contact of a high-side power transistor from a second body contact of a replica transistor during a time period when the boost converter is in buck mode and the low-side transistor is activated. When the second body contact is isolated from the first body contact, the second body contact is coupled to a maximum reference voltage Vmax, which is the greater of an input voltage Vin and an output voltage Vout. The current measurement linearization circuit can prevent back-gate currents across the replica transistor that may interfere with stable operation of the boost converter. Applicants have also disclosed a method of operating a DC / DC boost converter. Higher current sensing accuracy in buck mode can be achieved, which can increase transition performance between boost mode and buck mode.

[0051] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed descriptions should be construed as implying that any particular component, element, step, action or function is necessary so that it must be included within the scope of the claims. Unless explicitly stated, reference to a singular element is not intended to mean "one and only one", but "one or more". All structural and functional equivalents of the elements of the above-described embodiments known to those of ordinary skill in the art are expressly incorporated herein by reference, and are intended to be covered by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and changes within the spirit and scope of the following appended claims.

Claims

1. A current measurement linearization circuit for a DC / DC boost converter, the current measurement linearization circuit comprising: a back-gate sense transistor having a first terminal coupled to a body contact of the high-side power transistor and a second terminal coupled to a body contact of a replica transistor of a valley current sensing circuit; and A back-gate reset transistor has a first terminal configured to receive a reference voltage equal to the greater of an input voltage and an output voltage and a second terminal coupled to the body contact of the replica transistor. 2 . The current measurement linearization circuit of claim 1 , wherein during buck mode, the back gate sensing transistor is configured to be turned off when the low side power transistor is turned on and is configured to be turned on when the low side power transistor is turned off. 3 . The current measurement linearization circuit of claim 2 , wherein during the buck mode, the back-gate reset transistor is configured to be turned on when the low-side power transistor is turned on and is configured to be turned off when the low-side power transistor is turned off. 4 . The current measurement linearization circuit of claim 3 , wherein during a boost mode, the back-gate sense transistor is configured to be turned on and the back-gate reset transistor is configured to be turned off. 5 . The current measurement linearization circuit of claim 4 , wherein the first terminal of the back-gate sense transistor is further coupled to a back-gate disconnect transistor body contact. 6 . The current measurement linearization circuit of claim 5 , wherein the back-gate sensing transistor and the back-gate reset transistor are P-type metal oxide silicon transistors (PMOS transistors).

7. An integrated circuit, comprising: A DC / DC boost converter having a first terminal, a second terminal and a third terminal and comprising: a low-side power transistor coupled between the first terminal and the third terminal; a high-side power transistor coupled between the third terminal and the second terminal, the high-side power transistor having a first body contact; a back-gate turn-off transistor coupled between the first body contact and the second terminal of the high-side power transistor; and A valley current sensing circuit comprising: A comparator having an inverting input, a non-inverting input and an output, a first current sink coupled between the inverting input and a lower rail; a second current sink coupled to the non-inverting input and the lower rail; a first replica transistor coupled between the third terminal and the inverting input of the comparator, the first replica transistor having a second body contact and configured to provide a replica voltage to the inverting input, a second replica transistor coupled between a reference voltage input and the non-inverting input of the comparator and configured to provide a comparison voltage to the non-inverting input; and A current measurement linearization circuit, comprising: a back-gate sense transistor coupled between the first body contact and the second body contact of the first replica transistor; and A back-gate reset transistor is coupled between the second body contact and the reference voltage input. 8 . The integrated circuit of claim 7 , wherein during a buck mode, the back gate sense transistor is configured to be turned off when the low side power transistor is turned on and is configured to be turned on when the low side power transistor is turned off. 9 . The integrated circuit of claim 8 , wherein during the buck mode, the back-gate reset transistor is configured to be turned on when the low-side power transistor is turned on and is configured to be turned off when the low-side power transistor is turned off. 10 . The integrated circuit of claim 9 , wherein during a boost mode, the back-gate sense transistor is configured to be turned on and the back-gate reset transistor is configured to be turned off. 11 . The integrated circuit of claim 10 , wherein the first terminal of the back gate sense transistor is further coupled to a third body contact of the back gate disconnect transistor. 12 . The integrated circuit of claim 11 , wherein the third body contact of the back-gate off transistor is coupled to the first body contact of the high-side power transistor.

13. The integrated circuit of claim 12, wherein the output of the comparator is configured to enable conduction of the low-side power transistor. 14 . The integrated circuit of claim 13 , wherein the output of the comparator is further configured to initiate turn-off of the high-side power transistor.

15. The integrated circuit of claim 12, wherein the reference voltage is equal to the output voltage during boost mode and equal to the input voltage during buck mode.

16. The integrated circuit of claim 12, wherein the high-side power transistor, the back-gate disconnect transistor, the first replica transistor, the second replica transistor, the back-gate sense transistor, and the back-gate reset transistor are each P-type metal oxide silicon transistors.

17. A method of operating a DC / DC boost converter, comprising: The DC / DC boost converter implemented in an integrated circuit chip is provided, the DC / DC boost converter comprising: a low-side power transistor coupled between a first terminal and a third terminal and a high-side power transistor being a P-type metal oxide silicon transistor, i.e., a PMOS transistor, coupled between the third terminal and the second terminal, the high-side power transistor having a first body contact, the first terminal being coupled to a ground plane, the second terminal being coupled to an output capacitor and a load, and the third terminal being coupled to an inductor, a first replica transistor coupled between the third terminal and the first current sink, the first replica transistor having a second body contact, a second replica transistor coupled between the voltage input and the second current sink, receiving an input voltage via the third terminal; providing an output voltage via the second terminal; during a boost mode, connecting together the first body contact of the high-side power transistor and the second body contact of the first replica transistor, and During a buck mode, when the low-side power transistor is turned off, the first body contact and the second body contact are connected together, and During the buck mode, when the low-side power transistor is turned on, the first body contact and the second body contact are disconnected, and the second body contact is connected to the voltage input to receive a maximum reference voltage, which is equal to the larger of the input voltage and the output voltage.

18. The method of claim 17, comprising providing a back-gate disconnect transistor coupled between the high-side power transistor and the second terminal.

19. The method of claim 18, comprising providing a back gate reset transistor and a back gate sense transistor, the back gate reset transistor being coupled between the second body contact and the voltage input, the back gate sense transistor having a fourth terminal and a fifth terminal, the fourth terminal being coupled to the first body contact and a third body contact of the back gate disconnect transistor, the fifth terminal being coupled to the second body contact.

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