Integrated circuit including high reliability polysilicon components and method of manufacturing the same

Abstract

The present disclosure relates to an integrated circuit including a high reliability polysilicon component and a method for manufacturing the same. The present invention provides an electronic device, such as an integrated circuit (100). The IC includes a semiconductor substrate (101), the semiconductor substrate (101) including a first doped layer (108) of a first conductivity type. A second doped layer (132) of the first conductivity type is located within the first doped layer. The second doped layer has a first layer portion and a second layer portion (124) having a dopant concentration greater than that of the first doped layer, wherein the first layer portion and the second layer portion are laterally spaced apart relative to a surface of the substrate. The integrated circuit further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first layer portion and the second layer portion. A dielectric isolation structure (180) is located between the first layer portion and the second layer portion and directly contacts the lightly doped portion.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and, more particularly, but not exclusively, to improved reliability of polysilicon resistors and other passive integrated circuit components. Background Art

[0002] Integrated circuits contain transistors and passive components (such as resistors) fabricated on a single semiconductor substrate. Resistors may include diffused resistors formed in the substrate and polysilicon resistors formed in a layer above the substrate. The reliability of polysilicon resistors is limited by various failure modes. Such failures typically render the integrated circuit nonfunctional and may occur only after it has been put into service. Such field failures are of great concern to semiconductor manufacturers due to the inconvenience to the customer and possible safety issues. Summary of the invention

[0003] The inventors disclose various methods and apparatus that can be beneficially applied to fabricate integrated circuits (ICs) with improved resistor reliability. Although such embodiments can be expected to provide improvements in the initial and long-term reliability of such ICs, the inventions described are not required to have a particular result unless explicitly recited in a particular claim.

[0004] In particular, the present invention introduces an electronic device, such as an integrated circuit (IC). The IC includes a semiconductor substrate, the semiconductor substrate including a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has a first layer portion and a second layer portion having a greater dopant concentration than the first doped layer, wherein the first layer portion and the second layer portion are laterally spaced apart relative to a surface of the substrate. A lightly doped portion of the first doped layer is located between the first layer portion and the second layer portion. A dielectric isolation structure is located between the first layer portion and the second layer portion and directly contacts the lightly doped portion.

[0005] Other embodiments include a method of forming an IC, a method of making a photolithography mask implementing a well implant layer of the IC, and a non-transitory computer-readable storage medium having stored thereon instructions that configure a processor to implement the photolithography mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and 1B A semiconductor device (eg, an integrated circuit) according to various embodiments is schematically illustrated in plan view and in cross-sectional view, respectively;

[0007] Figure 2 illustrates examples of barrier etch defects that can compromise the reliability of semiconductor devices;

[0008] Figure 3 presenting experimental data illustrating breakdown voltage in test devices with and without implementations of the described embodiments;

[0009] Figure 4 are methods of implementing photomasks according to various embodiments;

[0010] Figures 5A to 5E The diagrams illustrate various embodiments (eg Figure 4 ), thereby generating a circuit pattern generating method of a well implantation photomask;

[0011] Figure 6 According to various embodiments, for example, Figure 5E Method for producing semiconductor devices using photomasks as described;

[0012] Figures 7A to 7E Graphical illustration of implementation Figure 6 Methods for forming integrated circuits (e.g., Figure 1A and 1B an electronic device in the progressive formation steps of a device); and

[0013] Figures 8A to 8B Schematic diagrams showing embodiments that can reduce parasitic interactions of passive components implemented using the described embodiments with neighboring components on a circuit substrate. DETAILED DESCRIPTION

[0014] The present invention is described with reference to the accompanying drawings. The figures are not drawn to scale and are provided only for the purpose of illustrating the present invention. Several aspects of the present invention are described below with reference to exemplary applications for illustration. It should be understood that numerous specific details, relationships and methods are set forth to provide an understanding of the present invention. The present invention is not limited to the illustrated order of actions or events, as some actions may occur in different orders and / or simultaneously with other actions or events. In addition, all illustrated actions or events may not be required to implement the method according to the present invention.

[0015] Some physical defects that occur during integrated circuit fabrication can create a risk of early or long-term device failure, for example by forming a conductive path between a polysilicon resistor and the circuit substrate. Such a failure may be referred to as a "polysilicon resistor short". The conductive path may be formed by dielectric breakdown between the resistor and the substrate, which is caused by high electric field strength between the defect and the resistor. Embodiments of the present invention benefit from the inventors' recognition that, while such physical defects cannot be eliminated, the impact of such physical defects on device lifetime may be mitigated by reducing the electric field strength that would otherwise cause dielectric breakdown and conductive short formation.

[0016] First go to Figure 1A and 1B , presents aspects of a semiconductor device 100 (eg, an integrated circuit) formed according to various embodiments. Figure 1A Yes Figure 1B , and Figure 1B Yes Figure 1A . These figures are described together in the following discussion, wherein Figure 1A and 1B Like reference numbers in the drawings refer to like features. The illustrated devices are exemplary and schematic in nature, showing some representative components that may aid in describing various embodiments.

[0017] Device 100 is formed in and on substrate 104, which includes a lightly doped semiconductor layer 108. Although semiconductor layer 108 can be of any type (e.g., silicon, germanium, or gallium arsenide), this discussion is non-limitingly with reference to silicon embodiments. Semiconductor layer 108 is located on top of an underlying similar material (e.g., a silicon wafer) or a different material (e.g., a buried oxide layer or a sapphire wafer). Semiconductor layer 108 can be an epitaxial layer grown on an underlying material (e.g., a heavily doped p-type wafer). Semiconductor layer 108 can further be a lightly doped p-type layer, as appropriate. Those skilled in the art of semiconductors understand "lightly doped" to mean doped to a resistivity of about 1-20 ohm-cm. As discussed further below, substrate 104 can include various doped layers or doped regions, such as wells, buried layers, and isolation structures, depending on the particular device. Without limitation, this discussion may refer to the semiconductor layer 108 as an epitaxial layer, a p-type epitaxial layer, an epi layer, or a p-epi layer 108 .

[0018] The device 100 includes an optional isolation trench 120 within the semiconductor layer 108. Described non-limitingly with respect to the semiconductor layer 108 being a p-type epi layer, the isolation trench 120 is formed by an n-type buried layer (NBL) 160, an n-type deep well 164, and isolation structures 168, 172. Although the isolation structures 168, 172 are shown as shallow trench isolation (STI) structures, in some other embodiments, thermal oxides, such as those produced in a LOCOS process, may be used. The isolation trench 120 encloses a shallow well 124 (e.g., a shallow p-well) of the same conductivity type as the semiconductor layer 108 and an enclosed portion 132 of the semiconductor layer 108. Unless otherwise stated, the enclosed portion 132 is considered to be part of the semiconductor layer 108 for purposes of this description and claims. The shallow well 128 is located outside the isolation trench 120. For purposes of this discussion and claims, the wells 124, 128 are separate and distinct from the semiconductor layer 108. Wells 124, 128 extend from the surface of substrate 104 into semiconductor layer 108. Wells 124 and 128 may be part of a default shallow p-well layer that is formed in the device 100, for example, to suppress latch-up or field FETs, in substantially the entire surface that was originally unprocessed to form implant regions and isolation structures for various devices. Parasitic effects such as latch-up and field FETs may generally be referred to herein as parasitic interactions.

[0019] A representative transistor 144 having a gate 148, a source 152, and a drain 156 is formed within the well 124. Although shown as a MOS transistor, the transistor 144 may be of any type, such as MOS, bipolar, power, or LDMOS. In various embodiments, the device 100 includes both MOS transistors and bipolar transistors. The isolation trench 120 may isolate the transistor 144 from the rest of the integrated circuit, thereby providing signal isolation and / or parasitic interaction protection. The device 100 may also include additional isolation structures, not shown, in the form of isolation rings and similar structures to provide isolation between transistors and / or wells of different conductivity types. The device 100 further includes contacts, vias, and interconnects without reference numbers embedded in the dielectric layer. These features represent interconnect levels that connect the transistor 144 to other transistors of the device 100 to implement electrical functions.

[0020] The device 100 further includes three instances of isolation structures 176, 180, and 184. The isolation structures 176, 180, and 184 may also be STI structures or LOCOS structures, and when STI is used, may be filled with silicon dioxide or another dielectric material. The isolation structures 176, 180, 184 may be formed according to design rules that enforce isolation of non-gate polysilicon features from the substrate 104. The isolation structure 176 is located within the well 124, the isolation structure 180 is located within the enclosed portion 132 but outside the well 124, and the isolation structure 184 is located outside the isolation trench 120 in the semiconductor layer 108.

[0021] Located above each of the isolation structures 176, 180, 184 are one or more gate layer structures formed from the same layer (eg, polysilicon) that forms the gate 148. Figure 1A , a passive gate level component 188 represented by a resistor is located on the isolation structure 184. Similarly, a passive gate level component 192, again represented by a resistor, is located on the isolation structure 180. It should be understood that components 188, 192 are not limited to resistors, but may each include any passive component, such as a conductive trace or a capacitor. "Gate level" means that components 188, 192 are formed by the material layer that forms gate 148. However, components 188, 192 may be processed in a different manner from gate 148. For example, gate 148 may include a silicide layer that is not present on components 188, 192. Each of passive components 188 and 192 is electrically connected within the circuit by an appropriate combination of vias, metal interconnects, and / or polysilicon interconnects that are not shown. As used herein, the term "passive component" includes any electrical component formed by a gate layer conductive / resistive material that is not part of a current switching component. Specifically, "passive components" explicitly exclude transistor gates, but include conductive traces connected to transistor gates.

[0022] Located on the isolation structure 176 are a number of dummy fill structures 196 that may be conductive. The dummy fill structures 196 may be automatically placed in the gate layer design by a pattern generation program to improve the uniformity of a dry etch process used to form gate layer features or a planarization process following the deposition of a dielectric layer over the gate level structure. The dummy fill structures 196 are not electrically connected to any circuit and are therefore electrically isolated.

[0023] The gate 148, passive components 188, 192, and dummy fill structures 196 may be formed of a gate layer material (e.g., polysilicon or a metal including Ta, Ti, or W, including silicides of these elements). When used, the polysilicon may be heavily doped to impart a relatively low resistivity. When used, the metal may have a lower resistivity than polysilicon. In either case, the gate layer material may be used to form the gates, passive components, and gate layer interconnects (sometimes referred to as "metal zeros") of MOS transistors. In this discussion, the gate 148 and the layers forming it are described as including polysilicon without limitation.

[0024] Conventionally, isolation structures such as isolation structures 176, 180, 184 are formed within a shallow doped well, such as the default p-well described earlier. In the process of forming such isolation features, a trench is typically formed in the substrate using a masked dry etching process, such as plasma etching. Such a process typically includes forming an opening in a photoresist layer to expose the portion of the substrate to be removed. Sometimes, after the opening is formed in the photoresist layer, particles may adhere to the surface of the substrate. Such particles may block etching, thereby producing a feature referred to herein as a "block etch defect."

[0025] Figure 2 Two examples of barrier etch defects are illustrated, respectively, in a lightly doped p-epi layer 205 and a p-well 210. Defect 220 is within isolation structure 230, and defect 240 is within isolation structure 250. Components 260, 270 are respectively located above isolation structures 230, 250. Components 260, 270 are illustrated as having an electrical potential relative to p-epi layer 205, representing the general case of components operating within an electrically active circuit.

[0026] The surface of the substrate adjacent to the isolation structure 230 has an associated relatively wide depletion region 280, while the surface of the substrate adjacent to the isolation structure 250 has an associated relatively narrow depletion region 290. It is believed that the depletion region is formed in response to a layer of defects at the surface of the p-epi layer 205 remaining after the trenches in which the isolation structures 230, 250 are formed are created. Such defects may, for example, include dangling bonds, which may acquire charge when electrons fill unoccupied orbitals. Without being limited by theory, it is believed that the presence of charge associated with such defects pins the Fermi level at the interior surface of the trench, thereby causing a space charge layer to form. This space charge layer, in turn, creates a depletion layer that extends into the surface of the underlying semiconductor to a depth sufficient to eliminate the space charge layer potential. This depth is determined in part by the carrier concentration in the semiconductor material, with lower carrier concentrations creating wider depletion regions.

[0027] Embodiments described herein and otherwise within the scope of the present invention benefit from the inventors' recognition that when the isolation structure is located within a lightly doped portion of the substrate (e.g., p-epi), the depletion region is wide enough to effectively eliminate charge carriers from many blocking etch defects. This has the effect of electrically passivating the defects, making them less likely to cause electric field concentrations that lead to dielectric breakdown events. In contrast, defects located in well regions (e.g., p-well 210) have carrier concentrations sufficient to allow for charge concentrations in the defects, potentially leading to dielectric breakdown over time.

[0028] Considering defect 240, the dopant concentration in p-well 210 creates a relatively shallow depletion region 290, so that there is a sufficient carrier concentration within defect 240. Therefore, under some operating conditions, a large electric field may be generated at the tip of defect 240, leading to eventual dielectric breakdown and a conductive short 295 between component 270 and the substrate.

[0029] In contrast, the carrier concentration within defect 220 is negligible due to the relatively wide depletion region 280. Thus, defect 220 behaves electrically as an insulator and specifically does not form a large electric field between defect 220 and component 260. Therefore, the presence of defect 220 near component 260 is expected to have a much smaller impact on the lifetime of the electronic device of which component 260 is a part.

[0030] Figure 3 The diagram in Figure 2 illustrates this effect. Figure 3 Device reliability as determined by testing the devices plotted on a normal probability plot is shown. Data set 310 represents breakdown voltage failures for a population of nominally identical baseline devices in which the isolation structure is formed within a substrate doped to a majority charge carrier concentration typical of a p-well. Data set 320 represents breakdown voltage failures for a population of nominally identical non-baseline devices formed according to embodiments described herein in which the isolation structure is formed within a substrate doped to a majority charge carrier concentration typical of a lightly doped p-epi layer. At a median breakdown voltage of approximately 65V, the non-baseline devices of data set 320 exhibit approximately twice the breakdown voltage of the baseline devices of data set 310. The areal density of barrier etch defects in the baseline and non-baseline devices is expected to be the same, so the significant improvement in breakdown voltage is believed to be attributable to the reduction in electric field concentration at the tip of the defect.

[0031] Return to Figure 1B, the device 100 includes a gap 136 in the p-well 124 corresponding to the isolation structure 180 and a gap 140 in the p-well 128 corresponding to the isolation structure 184. The isolation structure 180 directly contacts the underlying enclosed portion 132 of the lightly doped semiconductor layer 108 exposed by the gap 136, and the isolation structure 184 directly contacts the underlying semiconductor layer 108 exposed by the gap 140. Therefore, it is expected that the components 188, 192 have greater reliability due to the formation of the isolation structures 180, 184 directly in the lightly doped material rather than in the p-well region. Although it is expected that each blocking defect will form under some of the dummy fill structures 196, these features are generally electrically floating, so it is expected that no large electric field will be formed at any such defect. And in either case, the dummy fill structure 196 is not conductively coupled to any circuit element, so any short circuit that does form will not affect the electrical performance or reliability of the device 100.

[0032] The omission of well implants below the isolation structures 180, 184 is in contrast to conventional practice. For various reasons, conventional design practice places p-wells in most portions of the electronic device not occupied by n-wells, for example, to suppress parasitic interactions as described earlier. It is predicted in this work that such an omission will not have any significant impact on device reliability because the potential between the defect and the overlying polysilicon feature is expected to overcome the surface charge layer and pull carriers into the defect. Furthermore, there is no a priori understanding that charge depletion due to Fermi pinning in the defect will significantly exclude mobile charge carriers from the blocking etch defect. For at least these reasons, Figure 3 The doubling of the breakdown voltage of the test devices demonstrated in is a completely unexpected and clearly beneficial result.

[0033] In various embodiments, omitting the well below the passive polysilicon device is implemented by design rules that affect the placement of optical elements on a photomask used to make an electronic device, of which device 100 represents. As described earlier, design rules conventionally place shallow p-wells below passive components and dummy gate layer features. In various embodiments, shallow p-wells below passive components are excluded by using a new design barrier layer, referred to herein as PWELLBLK. The PWELLBLK layer is used to exclude the implant from areas of the circuit design that would otherwise receive a p-well implant based on the default design rules. The PWELLBLK geometry can be applied to designs that include wide area p-well implants. The PWELLBLK is tangibly implemented on a photomask that defines an open area of ​​a resist pattern for the well implant. Other embodiments may implement an n-well in an n-type substrate, in which case the barrier layer may be referred to as NWELLBLK.

[0034] Figure 4A method 400 is presented for example of producing a photomask implementing one or more of the described embodiments. In a first step 410, passive components (e.g., components 188, 192 ( Figure 1A / 1B)) of the gate level. These geometries can be determined by conventional circuit design rules. In step 420, the drawn geometries of the isolation structures corresponding to the passive components identified in the previous step (for example, corresponding to isolation structures 180 and 184) are generated. Again, these isolation features can also be determined by conventional circuit design rules. In step 430, the drawn geometries of the well implantation blocking layer (for example, the PWELLBLK layer previously described) are determined. These geometries correspond to the isolation structures determined in the previous step. "Corresponding to" means that each blocking geometry is configured so that a portion of the photoresist layer at least partially blocks the well implantation under a specific one of the isolation structures determined in the previous step. A specific blocking geometry may or may not have the same size and geometric extension as the isolation structure to which it corresponds. For example, a blocking geometry may be larger than its corresponding isolation structure in order to ensure complete overlap of the isolation structure in view of alignment tolerances. Finally, in step 440, a photomask is implemented that contains optical elements corresponding to the geometric shapes drawn in the PWELLBLK layer.

[0035] Those skilled in the art of photomask design and fabrication are familiar with the tools and procedures that can be used to implement a photomask having the desired optical elements to produce a well layer. In this method, "implementation" includes obtaining a photomask by any means, such as directly generating the photomask by the manufacturer of the apparatus 100, or obtaining the photomask through a contractual relationship with a photomask manufacturer. In addition, the optical elements corresponding to the specific geometry can be positive elements or negative elements, and can include any sub-elements required to properly reproduce the specific geometry in the desired layer of the semiconductor device, such as optical proximity correction (OPC) features. In an additional step further described below, the photomask can be used to produce a photoresist pattern that blocks the well implant process in areas of the circuit that have passive components electrically connected on corresponding isolation structures.

[0036] Figures 5A to 5E Some of the steps that may be performed to implement method 400 in the pattern generation phase of circuit design are graphically outlined. Figure 5A4 , a representative computer system 510 receives a design file 520 that includes design elements to be reproduced in the physical design of device 100. Computer system 510 includes software designed to transform the desired features to be implemented in the circuit design into several photomask levels used in the device manufacturing process. Such software may be commercially available, or may be proprietary, and may be conventional except for the steps described herein. The software may generate output files for use in generating photomasks in one of several available formats (e.g., MEBES, GDS-II, or OASIS). The computer program implementing the steps of method 400 and the resulting output files may be stored locally in a non-transitory computer-readable medium (e.g., a magnetic storage device or flash memory) in computer system 510, may be stored in a portable non-transitory computer-readable medium for transport, or may be transmitted electronically, such as via a proprietary LAN (local area network) or the Internet. In the illustrated example, the design elements include passive components 188, 192, dummy fill structures 196, transistor 144, isolation structures 176, 180 and 184, and shallow wells 124, 128. (See Figure 1A / 1B. )

[0037] Figure 5B Illustrated is a diagram of gate-level drawn geometries 530 determined by computer system 510 for device 100. These geometries correspond to electrically connected passive components (e.g., components 188 and 192) and may be represented by data structures within computer system 510. Gate 148 and dummy fill structures 196 are shown in dashed lines for reference, indicating that gate 148 and dummy fill structures 196 are excluded from the drawn geometries because they are either not passive components (e.g., gate 148) or are not electrically connected (e.g., dummy fill structures 196).

[0038] Figure 5C A diagram illustrating the isolation hierarchy of the design of device 100 is illustrated. Computer system 510 has generated isolation geometries 541, 542, 543, 544, and 545, which are collectively referred to as drawn isolation geometry 540. Drawn geometry 541 corresponds to isolation structure 184, drawn geometry 542 corresponds to isolation structure 168, drawn geometry 543 corresponds to isolation structure 180, drawn geometry 544 corresponds to isolation structure 176, and drawn geometry 545 corresponds to isolation structure 172. Drawn geometry 540 may be represented by a data structure within computer system 510.

[0039] Figure 5D188 , and PWELLBLK 552 corresponds to isolation structure 543 (and component 192 ). It can be seen that, logically, the set of PWELLBLK geometries 550 is the intersection of the set of drawn isolation geometries 540 and the set of passive components in the design. Again, the PWELLBLK geometries can be represented by a data structure within the computer system 510 .

[0040] Figure 5E The photomask 560 that may be produced by the previous steps is illustrated. The photomask 560 includes a well implant blocking geometry 570 that corresponds to the PWELLBLK geometry 550 and defines the physical extent of the area to be excluded from the well implant. The geometry 570 may be implemented, for example, by a chrome-on-glass substrate. The open areas 580 correspond to the extent of the area where the well implant is allowed to proceed. In this example, the photomask 560 is a positive mask because when used with a positive photoresist will cause the resist to remain at locations that will block exposure to light by the masked portions 570. In other embodiments, a negative mask may be produced in which the open and blocked portions of the mask are reversed.

[0041] Figure 6 A method 600 of forming a semiconductor device using the mask 560 , for example according to various embodiments, is presented. Figures 7A to 7E The semiconductor device 100 is illustrated, for example, in various stages of formation according to method 600. In the following discussion, Figure 6 and Figures 7A to 7E Describe at the same time. Fig. 7A In the illustrated optional first step 610, an isolation trench is formed in the semiconductor layer 108 surrounding the enclosed portion 132. The process, which may include conventional steps, has formed the isolation trench 120 bordering the buried layer 160 and the deep well 164.

[0042] In step 620, a dielectric isolation structure is formed in the lightly doped semiconductor layer. Figure 7B, such structures are exemplified by isolation structure 184 formed within semiconductor layer 108 and isolation structures 180 and 176 formed within enclosed portion 132 of p-epi layer. Also shown are isolation structures 168, 172, which for efficiency reasons may be formed simultaneously with isolation structures 176, 180, and / or 184 as part of an STI or LOCOS process flow.

[0043] In step 630 of method 600, well regions, such as shallow wells 124 and 128, are formed within portions of semiconductor layer 108. The well regions may be defined by open areas 580 of photomask 560. Figure 7C The diagram illustrates a photomask 560 positioned over a photoresist layer 710 and substrate 104. A photolithography process 720 exposes a portion of the photoresist layer 710 over the desired locations of the well regions (e.g., shallow wells 124 and 128). Fig.7D In the embodiment shown in FIG. 1 , the remaining portion 715 of the photoresist layer 710 prevents the substrate 104 from being exposed to an implantation process 730 that implants dopants, such as p-type dopants (eg, boron). The implantation process 730, which is typically followed by a diffusion / activation step, creates the shallow wells 124,128.

[0044] In reference Fig. 7E In further illustration, step 640, gate level passive components may be conventionally formed over one or more of the isolation structures formed in the previous steps, such as illustrated by components 188 and 192. For efficiency reasons, components 188 and 192 may be formed simultaneously with other gate level features (e.g., gate 148 and dummy fill structure 196). Subsequent processes not shown form interconnect levels to produce gates such as gate 148 and gate 196. Figure 1B The device 100 illustrated in FIG.

[0045] As described earlier, a p-well may be formed over all portions of the device substrate that are not otherwise used to reduce the risk of parasitic interactions. Conversely, removing portions of the p-well may increase the risk of forming parasitic bipolar or field FET transistors during device operation. Thus, some embodiments include one or more features that may be used instead of or in addition to the default p-well to reduce the risk of parasitic transistors in conjunction with forming passive gate level components directly over isolation structures in a lightly doped substrate.

[0046] Fig. 8A and 8B Some examples of such features shown as part of device 800 are illustrated. Fig. 8AThe diagram illustrates an embodiment in which a passive component 810 is located on an isolation structure 820 which in turn is located within a lightly doped p-epi layer. The device 800 includes a shallow p-well 830 with a blocked region marked where the p-well implant is blocked as previously described. An isolation trench is provided by an n-type deep well 840 and an n-type buried layer 850. Thus, in a manner similar to isolating active devices such as transistors, the region below the isolation structure 820 is isolated from the rest of the device 810 to prevent interaction with adjacent devices through a field FET effect in which the voltage on the component 810 can form an inversion layer below the isolation structure 820.

[0047] Figure 8B The diagram illustrates an embodiment in which the isolation structure 820 is separated from the rest of the device 810 (exemplified by the transistor and the isolation trench) by a lateral spacing D. It is expected that under many operating conditions, a minimum D of 10 μm will be sufficient to effectively isolate the component 810 from the isolation trench. In some other cases, depending on the doping level and operating voltage, a minimum spacing of 20 μm may be desirable. In addition, a p+ guard ring 860 is shown surrounding the isolation structure 820. The guard ring 860 can provide additional isolation by limiting the extent of the inversion zone under the isolation structure 820. Devices formed according to the described embodiments may include a plurality of p+ guard rings 860, depending on the design type, doping level, operating voltage, and space constraints. Fig. 8A and 8B One or both of the illustrated isolation types.

[0048] Although various embodiments of the present invention have been described above, it should be understood that the embodiments are presented by way of example only and not limitation. Numerous changes may be made to the disclosed embodiments according to the disclosure herein without departing from the spirit or scope of the present invention. Therefore, the breadth and scope of the present invention should not be limited by any of the embodiments described above. Rather, the scope of the present invention should be defined according to the appended claims and their equivalents.

Claims

1. An integrated circuit, comprising: a semiconductor substrate including a first doped layer of a first conductivity type; a second doped layer of the first conductivity type located within the first doped layer, the second doped layer having a first portion and a second portion having a dopant concentration greater than that of the first doped layer, the first portion and the second portion being laterally spaced apart by a gap relative to a surface of the substrate; The lightly doped portion of the first doped layer is located between the first portion and the second portion; a dielectric isolation structure located in the gap between the first portion and the second portion and directly contacting the lightly doped portion; and passive components, which are located directly on the dielectric isolation structure, A transistor is formed within the second doped layer, the transistor comprising a gate formed in a gate layer above the second doped layer, and the passive component is formed by the gate layer.

2. The integrated circuit of claim 1, wherein the passive component comprises a resistor.

3. The integrated circuit of claim 1, wherein the passive components comprise polysilicon. 4 . The integrated circuit of claim 1 , further comprising a doped buried layer having a second conductivity type within the substrate, wherein the lightly doped portion is located between the dielectric isolation structure and the doped buried layer.

5. The integrated circuit of claim 1, further comprising a transistor located within the second doped layer. The integrated circuit of claim 1 , wherein the first conductivity type is p-type.

7. The integrated circuit of claim 1, further comprising a second dielectric isolation structure within the second doped layer and an electrically isolated conductive structure on the second dielectric isolation structure.

8. A method of manufacturing an integrated circuit, comprising: providing a semiconductor substrate comprising a first doped layer of a first conductivity type and a first dopant concentration; forming a second doped layer of the first conductivity type within the first doped layer, the second doped layer having a first portion and a second portion having a greater dopant concentration than the first doped layer, the first portion and the second portion being laterally spaced apart by a gap relative to a surface of the substrate, wherein a lightly doped portion of the first doped layer is located between the first portion and the second portion; a dielectric isolation structure formed in the gap between the first portion and the second portion and directly contacting the lightly doped portion; and forming passive components directly on the dielectric isolation structure, Wherein the method further includes forming a transistor within the second doped layer, the transistor including a gate formed in a gate layer above the second doped layer, and the passive component is formed from the gate layer.

9. The method of claim 8, wherein the passive component comprises a resistor.

10. The method of claim 8, wherein the passive component comprises polysilicon. 11 . The method of claim 8 , further comprising forming a doped buried layer having a second conductivity type within the substrate, and the lightly doped portion is located between the dielectric isolation structure and the doped buried layer. The method of claim 8 , wherein the first doped layer is p-type. 13 . The method of claim 8 , further comprising forming a second dielectric isolation structure within the second doped layer and positioning an electrically isolated conductive structure on a second dielectric region.

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