Semiconductor Devices

Abstract

A semiconductor device is provided. More specifically, a semiconductor device including a capacitor having improved electrostatic capacitance by simplifying a process and / or a method for manufacturing the semiconductor device are provided. The semiconductor device includes: an insulating structure defining a first groove, the insulating structure being located on a substrate; a first conductive layer located in the insulating structure, a first portion of an upper surface of the first conductive layer being exposed by the first groove; a capacitor structure, the capacitor structure including a first electrode pattern located on the first conductive layer, a dielectric pattern located on the first electrode pattern, and a second electrode pattern located on the dielectric pattern, the first electrode pattern extending along the sidewall and bottom surface of the first groove and the upper surface of the insulating structure; and a first wiring pattern located on the capacitor structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0103545 filed on August 31, 2018 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor device and / or a method of manufacturing a semiconductor device. More particularly, the present inventive concept relates to a semiconductor device including a capacitor structure and a method of manufacturing the same. Background Art

[0004] With the development of industry and the development of multimedia, semiconductor devices for computers, mobile devices, etc. have been highly integrated and improved in performance. In the case of a semiconductor device including a capacitor, when the area occupied by a unit cell decreases as the degree of integration increases, it is desirable to maintain or increase the electrostatic capacitance of the capacitor.

[0005] A MIM (Metal-Insulator-Metal) capacitor using a high dielectric constant material as a dielectric film of the capacitor and using a metal material as a lower electrode and an upper electrode has been developed. Summary of the invention

[0006] Some example embodiments of the inventive concepts provide a semiconductor device including a capacitor having improved electrostatic capacity through a simplified process.

[0007] Some example embodiments of the inventive concepts also provide a method of manufacturing a semiconductor device including a capacitor having improved electrostatic capacity through a simplified process.

[0008] However, exemplary embodiments of the inventive concept are not limited to the embodiments set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept belongs by referring to the detailed description of some exemplary embodiments given below.

[0009] According to an example embodiment of the present invention, a semiconductor device includes: an insulating structure, which defines a first trench and is located on a substrate; a first conductive layer, which is located in the insulating structure, and a first portion of an upper surface of the first conductive layer is exposed by the first trench; a capacitor structure, which includes a first electrode pattern electrically connected to the first conductive layer, a dielectric pattern located on the first electrode pattern, and a second electrode pattern located on the dielectric pattern, the first electrode pattern extending along the sidewall and bottom surface of the first trench and the upper surface of the insulating structure; and a first wiring pattern, which is located on the capacitor structure.

[0010] According to an example embodiment conceived in the present invention, a semiconductor device includes: a first conductive layer, the first conductive layer is located on a substrate; an insulating structure, the insulating structure is located on the first conductive layer, the insulating structure includes a first groove and a second groove, the first groove exposes a first portion of the upper surface of the first conductive layer, the second groove exposes a second portion of the upper surface of the first conductive layer and is spaced apart from the first groove; a capacitor structure, the capacitor structure extends along the sidewall and bottom surface of the first groove; a first wiring pattern, the first wiring pattern is located on the capacitor structure and extends along the upper surface of the insulating structure; and a second wiring pattern, the second wiring pattern is spaced apart from the first wiring pattern, fills the second groove, and extends along the upper surface of the insulating structure.

[0011] According to an example embodiment of the present invention, a semiconductor device includes: an insulating structure, which defines a first trench and is located on a substrate; a first conductive layer, which is located in the insulating structure, and a first portion of an upper surface of the first conductive layer is exposed by the first trench; a first electrode pattern, which extends along the sidewalls and bottom surface of the first trench; a dielectric pattern, which covers the upper surface and sidewalls of the first electrode pattern; a second electrode pattern, which extends along the upper surface of the dielectric pattern; and a first wiring pattern, which extends along the upper surface of the second electrode pattern.

[0012] According to an example embodiment conceived in the present invention, a method for manufacturing a semiconductor device includes: forming an insulating structure defining a first trench and a first conductive layer located in the insulating structure, the first trench exposing a first portion of an upper surface of the first conductive layer; forming a first electrode pattern extending along a sidewall and a bottom surface of the first trench and an upper surface of the insulating structure; sequentially forming a dielectric pattern and a second electrode pattern on the first electrode pattern to form a capacitor structure; and forming a first wiring pattern on the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0014] Figure 1 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0015] Figure 2 and Figure 3 is a diagram showing a method according to an example embodiment Figure 1 Various enlarged views of portion "II".

[0016] Figure 4 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0017] Figure 5 and Figure 6 yes Figure 4 Various enlarged views of portion "V".

[0018] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concepts.

[0019] Figure 8 yes Figure 7 An enlarged view of portion "VIII" of FIG.

[0020] Fig. 9 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0021] Fig.10 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0022] Fig.11 are schematic cross-sectional views for explaining semiconductor devices according to some example embodiments of the inventive concepts.

[0023] Fig.12 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0024] Fig.13 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0025] Fig.14 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept.

[0026] Figures 15 to 24is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept.

[0027] Fig.25 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept, Fig.26 yes Fig.25 An enlarged view of portion “XXVI” of FIG.

[0028] Fig. 27 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept, Fig.28 yes Fig. 27 Magnified view of section "XXVIII". DETAILED DESCRIPTION

[0029] Although the term "same" is used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the one element is the same as the other element within a desired manufacturing tolerance range (e.g., ±10%).

[0030] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, the relevant numerical value is intended to include a manufacturing tolerance (e.g., ±10%) around the numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with geometric shapes, it is intended that the accuracy of the geometric shape is not required, but the degree of variation in shape is within the scope of the present disclosure.

[0031] In the following, reference will be made to Figures 1 to 14 Semiconductor devices according to some example embodiments of the inventive concepts are described.

[0032] Figure 1 is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept. Figure 2 and Figure 3 is a diagram showing some example embodiments Figure 1 Various enlarged views of portion "II".

[0033] Reference Figures 1 to 3 , a semiconductor device according to some example embodiments includes: a substrate 100; an insulating structure 200; a plurality of conductive layers 310, 320, 330, 340; a capacitor structure 400; a first wiring pattern 510; a first barrier layer 440; a second wiring pattern 520; a second barrier layer 450; and a rewiring pattern 530.

[0034] The substrate 100 may be bulk silicon or silicon on an insulating structure (SOI). In some example embodiments, the substrate 100 may be a silicon substrate, or may include, for example, but not limited to, other materials such as silicon germanium, silicon germanium on an insulating structure (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0035] Although not shown, the substrate 100 may include various internal circuit patterns. The internal circuit patterns may include, for example, transistors, diodes, and / or capacitors.

[0036] The substrate 100 may include a first region A and a second region B. The first region A and the second region B may be separated from each other or may be adjacent to each other. The first region A and the second region B may perform the same function or may perform different functions from each other. The first region A and the second region B may each be, for example, a cell region or a circuit region. For example, a memory cell may be formed in the cell region, and a peripheral circuit for driving the memory cell may be formed in the circuit region.

[0037] The insulating structure 200 may be formed on the substrate 100. The insulating structure 200 may include a plurality of insulating layers 210, 220, 230. For example, the insulating structure 200 may include first to third insulating layers 210, 220, 230 sequentially stacked on the substrate 100. Although the insulating structure 200 is shown as including only three insulating layers 210, 220, 230, this is only for ease of explanation and the present disclosure is not limited thereto.

[0038] Boundaries are shown to be formed between the first to third insulating layers 210, 220, 230, but this is only for convenience of explanation and the present disclosure is not limited thereto. For example, depending on the process of forming the insulating structure 200, boundaries between the first to third insulating layers 210, 220, 230 may not be formed.

[0039] The insulating structure 200 may include, for example, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide. The low dielectric constant material may include, but is not limited to, for example, one of the following: FOX (flowable oxide), TOSZ (Torene SilaZene), USG (undoped quartz glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (Boro Phospho Silica Glass), PETEOS (plasma enhanced tetraethyl orthosilicate), FSG (Fluoride Silicate Glass), CDO (carbon doped silicon oxide), xerogel, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), polyparaxylene (Parylene), BCB (bis-benzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0040] A plurality of conductive layers 310, 320, 330, 340 may be formed in the insulating structure 200. For example, the first conductive layer 310 may be formed in the second insulating layer 220 on the first region A, and the second conductive layer 320 may be formed in the second insulating layer 220 on the second region B. In addition, for example, the third conductive layer 330 may be formed in the first insulating layer 210 on the first region A, and the fourth conductive layer 340 may be formed in the first insulating layer 210 on the second region B.

[0041] The conductive layers 310, 320, 330, 340 may be connected to each other or may be connected to the substrate 100 through vias 325, 345. For example, the second conductive layer 320 may be connected to the fourth conductive layer 340 through a first via 325 penetrating the second insulating layer 220. In addition, for example, the fourth conductive layer 340 may be connected to the substrate 100 through a second via 345 penetrating the first insulating layer 210. Therefore, the conductive layers 310, 320, 330, 340 may be connected to various internal circuit patterns in the substrate 100.

[0042] The sidewalls of the conductive layers 310, 320, 330, 340 and the vias 325, 345 may all have a tapered shape (or may be inclined). For example, the widths of the conductive layers 310, 320, 330, 340 and the vias 325, 345 may increase as they move away from the upper surface of the substrate 100, respectively. Here, the width refers to the width in a direction parallel to the upper surface of the substrate 100. The tapered shape may be attributed to the characteristics of the etching process used to form the conductive layers 310, 320, 330, 340 and the vias 325, 345. However, the present disclosure is not limited thereto, and the sidewalls of the conductive layers 310, 320, 330, 340 and the vias 325, 345 may have various shapes.

[0043] Conductive layers 310, 320, 330, 340 and vias 325 may include, but are not limited to, for example, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), and aluminum (Al)) and / or metal nitrides (e.g., titanium nitride, tantalum nitride, and tungsten nitride).

[0044] The capacitor structure 400 may be formed on the insulating structure 200 and the first conductive layer 310. The insulating structure 200 may include a first trench TR1 exposing a portion of an upper surface of the first conductive layer 310. The first trench TR1 may be formed, for example, in the third insulating layer 230 on the first conductive layer 310. The capacitor structure 400 may extend along the sidewall and bottom surface of the first trench TR1 and the upper surface of the insulating structure 200. Therefore, the capacitor structure 400 connected to the first conductive layer 310 may be formed on the insulating structure 200.

[0045] The capacitor structure 400 may include a first electrode pattern 410, a dielectric pattern 420, and a second electrode pattern 430 sequentially stacked on the insulation structure 200 and the first conductive layer 310. The first electrode pattern 410 may extend along the sidewall and bottom surface of the first trench TR1 and the upper surface of the insulation structure 200. The first electrode pattern 410 may be electrically connected to the first conductive layer 310. The dielectric pattern 420 may extend along the contour of the upper surface of the first electrode pattern 410. The second electrode pattern 430 may extend along the contour of the upper surface of the dielectric pattern 420.

[0046] exist Figure 2, the thickness T11 of the first electrode pattern 410 is shown as thicker than the thicknesses T21 and T22 of the dielectric pattern 420, and the thicknesses T31 and T32 of the second electrode pattern 430 are shown as being the same as the thickness T11 of the first electrode pattern 410. However, this is only for ease of explanation, and the present disclosure is not limited thereto. For example, the thicknesses T21 and T22 of the dielectric pattern 420 may be thicker than the thickness T11 of the first electrode pattern 410 and the thicknesses T31 and T32 of the second electrode pattern 430. In addition, for example, the thickness T11 of the first electrode pattern 410 may be different from the thicknesses T31 and T32 of the second electrode pattern 430.

[0047] In some example embodiments, the dielectric pattern 420 may extend longer than the first electrode pattern 410. For example, a first distance D11 from one edge of the first trench TR1 to one end of the first electrode pattern 410 may be shorter than a second distance D21 from the same edge of the first trench TR1 to one end of the dielectric pattern 420.

[0048] Therefore, the dielectric pattern 420 may cover the upper surface and the sidewalls of the first electrode pattern 410. Figure 2 As shown, the dielectric pattern 420 may include a first extension 422 extending along the upper surface of the first electrode pattern 410 and a first protrusion 424 protruding from the first extension 422 and covering the sidewall of the first electrode pattern 410. The first extension 422 of the dielectric pattern 420 may overlap with the first electrode pattern 410, and the first protrusion 424 of the dielectric pattern 420 may not overlap with the first electrode pattern 410. Here, overlapping means overlapping in a direction perpendicular to the upper surface of the substrate 100. In some example embodiments, the first protrusion 424 of the dielectric pattern 420 may be in direct contact with the upper surface of the insulation structure 200. In some example embodiments, the thickness T21 of the first extension 422 may be substantially the same as the thickness T22 of the first protrusion 424.

[0049] In some example embodiments, the second electrode pattern 430 may extend longer than the first electrode pattern 410. For example, a distance from one end of the first trench TR1 to one distal end of the second electrode pattern 430 may be substantially the same as the second distance D21.

[0050] The second electrode pattern 430 may cover the upper surface of the dielectric pattern 420. For example, the second electrode pattern 430 may include a second extension portion 432 extending along the upper surface of the first extension portion 422 and a second protrusion 434 protruding from the second extension portion 432 and extending along the upper surface of the first protrusion 424. In some example embodiments, a thickness T31 of the second extension portion 432 may be the same as or substantially similar to a thickness T32 of the second protrusion 434.

[0051] For example, the first electrode pattern 410 and the second electrode pattern 430 may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof. The first electrode pattern 410 and the second electrode pattern 430 may include the same material or different materials. In the following description, it is described that both the first electrode pattern 410 and the second electrode pattern 430 include titanium nitride (TiN).

[0052] The dielectric pattern 420 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, but is not limited to, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0053] The first wiring pattern 510 may be formed on the capacitor structure 400. The first wiring pattern 510 may extend along the upper surface of the insulation structure 200. For example, the first wiring pattern 510 may extend along the upper surface of the capacitor structure 400. The first wiring pattern 510 may be electrically connected to the second electrode pattern 430 of the capacitor structure 400.

[0054] In some example embodiments, the first wiring pattern 510 may fill up the first trench TR1. In addition, in some example embodiments, sidewalls of the first wiring pattern 510 may be disposed on the same or substantially similar plane as sidewalls of the dielectric pattern 420 and the second electrode pattern 430.

[0055] The first wiring pattern 510 may include a conductive material. For example, the first wiring pattern 510 may include, but is not limited to, a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and nickel (Ni)). In the following description, it is described that the first wiring pattern 510 includes aluminum (Al).

[0056] The first barrier layer 440 may be formed on the insulation structure 200 and the first conductive layer 310. The first barrier layer 440 may be physically spaced apart from the capacitor structure 400.

[0057] The insulating structure 200 may include a second trench TR2 that is spaced apart from the first trench TR1 and exposes another portion of the upper surface of the first conductive layer 310. The second trench TR2 may be formed, for example, in the third insulating layer 230 on the first conductive layer 310. The first barrier layer 440 may extend along the sidewall and bottom surface of the second trench TR2. Therefore, the first barrier layer 440 connected to the first conductive layer 310 may be formed on the insulating structure 200. In some example embodiments, the first barrier layer 440 may also extend along the upper surface of the insulating structure 200.

[0058] The second wiring pattern 520 may be formed on the first barrier layer 440. The second wiring pattern 520 may be spaced apart from the first wiring pattern 510 and extend along the upper surface of the insulating structure 200. For example, the second wiring pattern 520 may extend along the upper surface of the first barrier layer 440. The second wiring pattern 520 may be electrically connected to the first conductive layer 310 and the first electrode pattern 410.

[0059] In some embodiments, the second wiring pattern 520 may completely fill the second trench TR2 . In addition, in some embodiments, the sidewalls of the second wiring pattern 520 may be disposed on the same or substantially similar plane as the sidewalls of the first barrier layer 440 .

[0060] Different voltages may be applied to the first wiring pattern 510 and the second wiring pattern 520. Therefore, different voltages may be applied to the first electrode pattern 410 and the second electrode pattern 430. The capacitor structure 400 may store charges in the dielectric pattern 420 by utilizing a potential difference generated between the first electrode pattern 410 and the second electrode pattern 430.

[0061] The second wiring pattern 520 may include a conductive material. For example, the second wiring pattern 520 may include, but is not limited to, a metal such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and nickel (Ni).

[0062] In some embodiments, the second wiring pattern 520 may be formed on the same layer as the first wiring pattern 510. In this specification, "the same layer" means a layer formed by the same manufacturing process. For example, the second wiring pattern 520 and the first wiring pattern 510 may include the same material. For example, the second wiring pattern 520 may include aluminum (Al).

[0063] The first barrier layer 440 may prevent a material (e.g., aluminum (Al)) included in the second wiring pattern 520 from diffusing to, for example, the insulating structure 200. The first barrier layer 440 may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof.

[0064] In some example embodiments, the first barrier layer 440 and the second electrode pattern 430 may include the same material. In this specification, "same" not only means completely the same, but also means a slight difference that may occur due to a process margin, etc. For example, the first barrier layer 440 may include titanium nitride (TiN).

[0065] In some example embodiments, the thicknesses T31 and T32 of the second electrode pattern 430 may be greater than the thickness T41 of the first barrier layer 440. This will be described later in Figure 21 to Figure 24 Describe it in the description.

[0066] The second barrier layer 450 may be formed on the insulation structure 200 and the second conductive layer 320. The second barrier layer 450 may be physically spaced apart from the capacitor structure 400 and the first barrier layer 440.

[0067] The insulating structure 200 may include a third trench TR3 exposing a portion of the upper surface of the second conductive layer 320. The third trench TR3 may be formed in the third insulating layer 230, for example, on the second conductive layer 320. The second barrier layer 450 may extend along the sidewall and bottom surface of the third trench TR3. Therefore, the second barrier layer 450 connected to the second conductive layer 320 may be formed on the insulating structure 200. In some example embodiments, the second barrier layer 450 may also extend along the upper surface of the insulating structure 200.

[0068] Each sidewall of the first to third trenches TR1, TR2, TR3 may have a gradually narrowing shape. For example, the width of the first to third trenches TR1, TR2, TR3 may increase as they move away from the upper surface of the substrate 100. Here, the width represents the width in a direction parallel to the upper surface of the substrate 100. This may be attributed to the characteristics of the etching process used to form the first to third trenches TR1, TR2, TR3. However, the present disclosure is not limited thereto, and the sidewalls of the first to third trenches TR1, TR2, TR3 may have various shapes.

[0069] The rewiring pattern 530 may be formed on the second barrier layer 450. The rewiring pattern 530 may extend along the upper surface of the insulation structure 200. For example, the rewiring pattern 530 may extend along the upper surface of the second barrier layer 450. The rewiring pattern 530 may be electrically connected to the second conductive layer 320.

[0070] In some example embodiments, the rewiring pattern 530 may completely fill the third trench TR3 . In addition, in some example embodiments, a sidewall of the rewiring pattern 530 may be disposed on the same plane as a sidewall of the second barrier layer 450 .

[0071] The rewiring pattern 530 may include a conductive material. For example, the rewiring pattern 530 may include, but is not limited to, a metal such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), and nickel (Ni).

[0072] In some embodiments, the rewiring pattern 530 may be formed at the same layer as the first wiring pattern 510 and the second wiring pattern 520. For example, the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530 may include the same material. For example, the rewiring pattern 530 may include aluminum (Al).

[0073] The second barrier layer 450 may mitigate or prevent a material (e.g., aluminum (Al)) included in the rewiring pattern 530 from diffusing into, for example, the insulating structure 200. The second barrier layer 450 may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof.

[0074] In some example embodiments, the second barrier layer 450 may be formed at the same layer as the first barrier layer 440. For example, the second barrier layer 450 and the first barrier layer 440 may include the same material. For example, the second barrier layer 450 may include titanium nitride (TiN).

[0075] In some example embodiments, the thickness T31, T32 of the second electrode pattern 430 may be thicker than the thickness T51 of the second barrier layer 450. In addition, in some example embodiments, the thickness T51 of the second barrier layer 450 may be the same as or substantially similar to the thickness T41 of the first barrier layer 440. This will be described later in Figure 21 to Figure 24 Describe it in the description.

[0076] In some example embodiments, Figure 3 As shown, the second electrode pattern 430 may include a lower electrode pattern 430a and an upper electrode pattern 430b sequentially stacked on the dielectric pattern 420. The lower electrode pattern 430a may extend along the contour of the upper surface of the dielectric pattern 420. The upper electrode pattern 430b may extend along the contour of the upper surface of the lower electrode pattern 430a. The lower electrode pattern 430a and the upper electrode pattern 430b may include the same material or different materials.

[0077] exist Figure 3, the thickness T33 of the lower electrode pattern 430a is shown to be the same as the thickness T34 of the upper electrode pattern 430b. However, this is only for convenience of explanation, and the present disclosure is not limited thereto.

[0078] In some example embodiments, the upper electrode pattern 430b may be formed at the same layer as the first barrier layer 440 and the second barrier layer 450. For example, the upper electrode pattern 430b, the first barrier layer 440 and the second barrier layer 450 may include the same material.

[0079] In some example embodiments, the thickness T34 of the upper electrode pattern 430b may be the same as or substantially similar to the thickness T41 of the first barrier layer 440 and the thickness T51 of the second barrier layer 450. This will be described later. Figure 21 to Figure 24 Describe it in the description.

[0080] In some example embodiments, a passivation layer 610 may be further formed on the insulation structure 200 .

[0081] The passivation layer 610 may be formed to cover the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530. The passivation layer 610 may protect the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530. Although not specifically shown, the passivation layer 610 may expose some of the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530 so that the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530 are connected to another wiring pattern.

[0082] The passivation layer 610 may include, but is not limited to, for example, a polymer such as photosensitive polyimide (PSPI), benzocyclobutene (BCB), or epoxy.

[0083] Since at least a portion of the capacitor structure 400 extends along the sidewall and bottom surface of the first trench TR1, the area in which the capacitor is formed in a limited space can be increased. For example, the area of ​​the capacitor structure 400 can be larger than that of a capacitor structure extending only along the upper surface of the insulating structure 200. Therefore, a semiconductor device including a capacitor having improved capacitance in a limited space can be provided.

[0084] In addition, in the capacitor structure 400, the dielectric pattern 420 may extend longer than the first electrode pattern 410 to cover the upper surface and the sidewall of the first electrode pattern 410. Therefore, a short circuit between the sidewall of the first electrode pattern 410 and the sidewall of the second electrode pattern 430 may be alleviated or prevented. Therefore, a semiconductor device including a capacitor with improved reliability may be provided.

[0085] Figure 4is a schematic cross-sectional view for explaining a semiconductor device according to an example embodiment of the inventive concept. Figure 5 and Figure 6 yes Figure 4 For ease of explanation, the description of the combined Figures 1 to 3 The repeated description section provided.

[0086] Reference Figures 4 to 6 , the second electrode pattern 430 extends to be longer than the dielectric pattern 420 .

[0087] For example, a second distance D21 from one end of the first trench TR1 to one end of the dielectric pattern 420 may be shorter than a third distance D31 from the same end of the first trench TR1 to one end of the second electrode pattern 430 .

[0088] Therefore, the second electrode pattern 430 may cover the upper surface and the sidewall of the dielectric pattern 420. Figure 5 As shown, the second electrode pattern 430 may include a third protrusion 436 protruding from the second protrusion 434 to cover the sidewall of the dielectric pattern 420. The second extension 432 and the second protrusion 434 of the second electrode pattern 430 may overlap the dielectric pattern 420, and the third protrusion 436 of the second electrode pattern 430 may not overlap the dielectric pattern 420. In some example embodiments, the third protrusion 436 of the second electrode pattern 430 may directly contact the upper surface of the insulation structure 200.

[0089] In some example embodiments, the thickness T31 of the second extension portion 432 and the thickness T32 of the second protrusion 434 may be thicker than the thickness T35 of the third protrusion 436. This will be described later. Figure 21 to Figure 24 Describe it in the description.

[0090] In some example embodiments, sidewalls of the first wiring pattern 510 may be disposed on the same or substantially similar plane as sidewalls of the third protrusion 436 .

[0091] In some example embodiments, Figure 6 As shown, the second electrode pattern 430 may include a lower electrode pattern 430a and an upper electrode pattern 430b sequentially stacked on the dielectric pattern 420. The lower electrode pattern 430a may extend along the contour of the upper surface of the dielectric pattern 420. The upper electrode pattern 430b may extend along the contour of the upper surface of the lower electrode pattern 430a. In addition, the upper electrode pattern 430b may cover the sidewalls of the dielectric pattern 420 and the sidewalls of the lower electrode pattern 430a. In some example embodiments, a portion of the upper electrode pattern 430b may be in direct contact with the upper surface of the insulating structure 200.

[0092] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concepts. Figure 8 yes Figure 7 For ease of explanation, the description of the combination will be briefly described or omitted. Figures 1 to 3 The description section that is repeated.

[0093] Reference Figure 7 and Figure 8 , the sidewalls of the first electrode pattern 410 , the sidewalls of the dielectric pattern 420 , and the sidewalls of the second electrode pattern 430 are disposed on the same plane.

[0094] For example, one end of the first electrode pattern 410 may be spaced apart from the first trench TR1 by a fourth distance D12. At this time, the distance from the first trench TR1 to one end of the dielectric pattern 420 may be the same as or substantially similar to the fourth distance D12. In addition, the distance from the first trench TR1 to one end of the second electrode pattern 430 may be the same as or substantially similar to the fourth distance D12.

[0095] In some example embodiments, sidewalls of the first wiring pattern 510 may be disposed on substantially the same plane as sidewalls of the first electrode pattern 410 , the dielectric pattern 420 , and the second electrode pattern 430 .

[0096] Fig. 9 1 is a schematic cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 3 The description section that is repeated.

[0097] Reference Fig. 9 , the voltage applied to the first electrode pattern 410 may be different from the voltage applied to the second wiring pattern 520 (see Figure 1 ).

[0098] For example, different voltages may be applied to the first wiring pattern 510 and the third conductive layer 330. The third conductive layer 330 may be electrically connected to the first conductive layer 310, for example, through the third via 315 penetrating the second insulating layer 220. Therefore, different voltages may be applied to the first electrode pattern 410 and the second electrode pattern 430.

[0099] In some example embodiments, the second barrier layer 450 and the second wiring patterns 520 may be omitted.

[0100] Fig.10 1 is a schematic cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 3 The description section that is repeated.

[0101] Reference Fig.10 , the insulation structure 200 includes a plurality of anti-etching films 215 , 225 , and 235 .

[0102] For example, the insulating structure 200 may include first to third anti-etching films 215, 225, 235. The first anti-etching film 215 may, for example, extend along the upper surface of the substrate 100. The second anti-etching film 225 may, for example, extend along the upper surface of the first insulating layer 210, the upper surface of the third conductive layer 330, and the upper surface of the fourth conductive layer 340. The third anti-etching film 235 may, for example, extend along the upper surface of the second insulating layer 220, the upper surface of the first conductive layer 310, and the upper surface of the second conductive layer 320.

[0103] In some example embodiments, the first to third trenches TR1, TR2, TR3 may penetrate the third anti-etching film 235 to expose a portion of an upper surface of the first conductive layer 310 and a portion of an upper surface of the second conductive layer 320. In some example embodiments, the first via 325 penetrates the second anti-etching film 225 and may be connected to the fourth conductive layer 340. In some example embodiments, the second via 345 penetrates the first anti-etching film 215 and may be connected to the substrate 100.

[0104] The first to third anti-etching films 215 , 225 , and 235 may include, but are not limited to, silicon nitride (SiN), for example.

[0105] Fig.11 1 is a schematic cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 3 The description section that is repeated.

[0106] Reference Fig.11 , the first conductive layer 310 and the second conductive layer 320 may be conductive pads formed on the insulation structure 200 .

[0107] The first conductive layer 310 and the second conductive layer 320 may be formed, for example, to extend along an upper surface of the second insulating layer 220 .

[0108] The sidewalls of the first conductive layer 310 and the second conductive layer 320 may both be in a tapered shape. For example, the widths of the first conductive layer 310 and the second conductive layer 320 may decrease as they move away from the upper surface of the substrate 100. Here, the width refers to the width in a direction parallel to the upper surface of the substrate 100. The tapered shape may be attributed to the characteristics of the etching process used to form the first conductive layer 310 and the second conductive layer 320. However, the present invention is not limited thereto, and the sidewalls of the first conductive layer 310 and the second conductive layer 320 may be in various shapes.

[0109] In some example embodiments, a fourth insulating layer 240 exposing a portion of an upper surface of the first conductive layer 310 and a portion of an upper surface of the second conductive layer 320 may be further formed on the first conductive layer 310 and the second conductive layer 320. The fourth insulating layer 240 may extend along contours of an upper surface and sidewalls of the first conductive layer 310, contours of an upper surface and sidewalls of the second conductive layer 320, and a contour of an upper surface of the second insulating layer 220.

[0110] The first to third trenches TR1 , TR2 , TR3 penetrate the fourth insulating layer 240 and may expose a portion of an upper surface of the first conductive layer 310 and a portion of an upper surface of the second conductive layer 320 .

[0111] Fig.12 1 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 1 to 3 The description section that is repeated.

[0112] Reference Fig.12 , the capacitor structure 400 extends along the plurality of trenches TR4 , TR5 .

[0113] For example, the insulating structure 200 may include fourth and fifth trenches TR4 and TR5. The fourth and fifth trenches TR4 and TR5 may be formed, for example, in the third insulating layer 230 on the first conductive layer 310. The fourth and fifth trenches TR4 and TR5 may be formed to be spaced apart from the third trench TR3.

[0114] The capacitor structure 400 may extend along the sidewalls and bottom surfaces of the fourth trench TR4 and the fifth trench TR5 and the upper surface of the insulating structure 200. The capacitor structure 400 is shown as extending along only two trenches TR4 and TR5, but this is only for ease of explanation and the present disclosure is not limited thereto. For example, the capacitor structure 400 may extend along three or more trenches.

[0115] The fourth trench TR4 and the fifth trench TR5 are both shown to expose the upper surface of the first conductive layer 310, but this is only for ease of description, and the inventive concept is not limited thereto. At least one of the fourth trench TR4 and the fifth trench TR5 may expose a portion of the upper surface of the first conductive layer 310. Therefore, the capacitor structure 400 connected to the first conductive layer 310 may be formed on the insulating structure 200.

[0116] Fig.13 1 is a schematic cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 3 The description section that is repeated.

[0117] Reference Fig.13 , a fourth wiring pattern 540 located on the first wiring pattern 510 , the second wiring pattern 520 , and the re-wiring pattern 530 may also be formed.

[0118] For example, a fifth insulating layer 620 may be formed to cover the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530. The fifth insulating layer 620 may include a sixth trench TR6 exposing a portion of an upper surface of the first wiring pattern 510. The fourth wiring pattern 540 may be formed in the sixth trench TR6 and may extend along an upper surface of the fifth insulating layer 620. The fourth wiring pattern 540 may be electrically connected to the first wiring pattern 510.

[0119] Only a single fourth wiring pattern 540 connected to the first wiring pattern 510 is shown on the first wiring pattern 510, but this is only for convenience of explanation and the present disclosure is not limited thereto. In some example embodiments, an additional wiring pattern 540 connected to the second wiring pattern 520 or the rewiring pattern 530 may be formed on the second wiring pattern 520 or the rewiring pattern 530.

[0120] The fourth wiring pattern 540 may include a conductive material. For example, the fourth wiring pattern 540 may include, but is not limited to, a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), or nickel (Ni)). In some example embodiments, the fourth wiring pattern 540 may include the same conductive material as the first wiring pattern 510, the second wiring pattern 520, and the redistribution pattern 530.

[0121] In some example embodiments, a third barrier layer 460 extending along the sidewalls and bottom surface of the sixth trench TR6 may be further formed. A fourth wiring pattern 540 may be formed on the third barrier layer 460 .

[0122] The third barrier layer 460 may mitigate or prevent the diffusion of the material included in the fourth wiring pattern 540 into, for example, the insulating structure 200. The third barrier layer 460 may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof. In some example embodiments, the third barrier layer 460 may include the same material as the first barrier layer 440 and the second barrier layer 450.

[0123] In some example embodiments, a sixth insulating layer 630 covering the fourth wiring patterns 540 may be further formed.

[0124] Fig.141 is a schematic cross-sectional view for explaining a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 3 The description section that is repeated.

[0125] Reference Fig.14 , solder bumps 720 located on the first wiring pattern 510 , the second wiring pattern 520 , and the re-wiring pattern 530 may also be formed.

[0126] For example, the passivation layer 610 may include a seventh trench TR7 exposing a portion of the upper surface of the first wiring pattern 510 . The solder bump 720 may be formed to fill the seventh trench TR7 . The solder bump 720 may be electrically connected to the first wiring pattern 510 .

[0127] Only one solder bump 720 connected to the first wiring pattern 510 is shown on the first wiring pattern 510, but this is only for convenience of explanation and the inventive concept is not limited thereto. For example, another solder bump 720 connected to the second wiring pattern 520 or the rewiring pattern 530 may be formed on the second wiring pattern 520 or the rewiring pattern 530.

[0128] The solder bumps 720 may be used as conductive protrusions for, for example, tape automated bonding (TAB) or flip chip bonding. In some example embodiments, the solder bumps 720 may also be used as conductive protrusions for connecting ball grid arrays (BGA) and chip scale packages (CSP) to a package substrate or the like.

[0129] In some example embodiments, a metal film 710 extending along the sidewall and bottom surface of the seventh trench TR7 may also be formed. A solder bump 720 may be formed on the metal film 710. The metal film 710 may be used as an adhesive layer, an anti-diffusion layer, and / or a wetting layer. The metal film 710 may be, for example, an under-bump metal (UBM).

[0130] For example, the metal film 710 may include, but is not limited to, at least one of chromium (Cr), copper (Cu), nickel (Ni), titanium tungsten (TiW), nickel vanadium (NiV), and combinations thereof.

[0131] In the following, reference will be made to Figures 1 to 8 and Figures 15 to 28 A method of fabricating a semiconductor device according to example embodiments of the inventive concepts is described.

[0132] Figures 15 to 24 FIG. 1 is a diagram of an intermediate stage for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Figures 1 to 14 The description section that is repeated.

[0133] Reference Fig.15 , an insulating structure 200 and a plurality of conductive layers 310 , 320 , 330 , 340 are disposed on a substrate 100 .

[0134] The insulating structure 200 may include first to third trenches TR1 , TR2 , TR3 . For example, the first to third trenches TR1 , TR2 , TR3 may be formed by etching a portion of the third insulating layer 230 .

[0135] The first trench TR1 and the second trench TR2 are spaced apart from each other and may be formed to expose a portion of an upper surface of the first conductive layer 310. The third trench TR3 may be formed to expose a portion of an upper surface of the second conductive layer 320.

[0136] Reference Fig.16 , a first electrode film 410 p is formed on the insulating structure 200 and the first conductive layer 310 .

[0137] The first electrode film 410p may be conformally formed on Fig.15 For example, the first electrode film 410p may extend along the contour of the upper surface of the insulating structure 200 and the contours of the sidewalls and bottom surfaces of the first to third trenches TR1, TR2, TR3.

[0138] The first electrode film 410p may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof. In the following description, it is described that the first electrode film 410p includes titanium nitride (TiN).

[0139] Reference Fig.17 , the first electrode film 410 p is patterned to form a first electrode pattern 410 .

[0140] The formation of the first electrode pattern 410 may be performed, for example, by a photolithography process. For example, an etching process using the first mask pattern 810 as an etching mask may be performed. The first mask pattern 810 may cover the first trench TR1 and may expose the first electrode film 410p between the first trench TR1 and the second trench TR2.

[0141] An etching process using the first mask pattern 810 as an etching mask may be performed until the upper surface of the insulation structure 200 is exposed. Thus, a first electrode pattern 410 extending along the sidewalls and bottom surfaces of the first trench TR1 and the upper surface of the insulation structure 200 may be formed.

[0142] In some example embodiments, the first mask pattern 810 may further cover the second trench TR2 and / or the third trench TR3. Thus, a sacrificial pattern 410q extending along the sidewalls and bottom surfaces of the second trench TR2 and the third trench TR3 may be formed.

[0143] After forming the first electrode pattern 410 , the first mask pattern 810 may be removed.

[0144] Reference Fig.18 , a dielectric film 420 p and a second electrode film 430 p may be formed on the first electrode pattern 410 .

[0145] The dielectric film 420p and the second electrode film 430p may be sequentially stacked on the first electrode pattern 410. In addition, the dielectric film 420p and the second electrode film 430p may be conformally formed on the first electrode pattern 410. Fig.15 For example, the dielectric film 420p and the second electrode film 430p may extend along the contour of the upper surface of the first electrode pattern 410, the contour of the upper surface of the insulation structure 200, and the contour of the upper surface of the sacrificial pattern 410q.

[0146] The dielectric film 420p may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) material having a higher dielectric constant than silicon oxide.

[0147] The second electrode film 430p may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof. The first electrode pattern 410 and the second electrode film 430p may include the same material or different materials. In the following description, it is described that both the first electrode pattern 410 and the second electrode film 430p include titanium nitride (TiN).

[0148] Reference Fig.19 and Fig. 20 , the dielectric film 420p is patterned to form a dielectric pattern 420 and a lower electrode pattern 430a. Fig. 20 yes Fig.19 An enlarged view of part "XX" is provided for reference.

[0149] The formation of the dielectric pattern 420 and the lower electrode pattern 430a may be performed, for example, by a photolithography process. For example, an etching process using the second mask pattern 820 as an etching mask may be performed. The second mask pattern 820 may cover the first trench TR1 and may expose the second electrode film 430p on the second trench TR2 and the third trench TR3.

[0150] An etching process using the second mask pattern 820 as an etching mask may be performed until the upper surface of the insulating structure 200 is exposed. Thus, the first dielectric pattern 420 and the lower electrode pattern 430a extending along the upper surface of the first electrode pattern 410 may be formed. In addition, the sacrificial pattern 410q may be removed.

[0151] In some example embodiments, the second mask pattern 820 may extend longer than the first electrode pattern 410. For example, the second mask pattern 820 may be formed to protrude from an end of the first electrode pattern 410. Thus, the dielectric pattern 420 including the first extension 422 and the first protrusion 424 may be formed.

[0152] For example, Fig. 20 As shown, a first distance D11 from one end of the first trench TR1 to one end of the first electrode pattern 410 may be shorter than a second distance D21 from the same end of the first trench TR1 to one end of the dielectric pattern 420 .

[0153] After forming the dielectric pattern 420 and the lower electrode pattern 430 a , the second mask pattern 820 may be removed.

[0154] Reference Fig.21 , a third electrode film 430q is formed on the lower electrode pattern 430a.

[0155] The third electrode film 430q may be conformally formed on Fig.19 For example, the third electrode film 430q may extend along the contour of the upper surface of the lower electrode pattern 430a, the contour of the upper surface of the insulation structure 200, and the contours of the sidewalls and bottom surfaces of the second and third trenches TR2 and TR3.

[0156] The third electrode film 430q may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), metal silicide, and combinations thereof. The lower electrode pattern 430a and the third electrode film 430q may include the same material or different materials. In the following description, it is described that both the lower electrode pattern 430a and the third electrode film 430q include titanium nitride (TiN).

[0157] Reference Fig. 22 , a wiring film 500 is formed on the third electrode film 430q.

[0158] Can be Fig.21 A wiring film 500 is formed on the resultant product. In some example embodiments, the wiring film 500 may be formed to completely fill the first to third trenches TR1, TR2, TR3.

[0159] The wiring film 500 may include a conductive material. For example, the wiring film 500 may include, but is not limited to, a metal such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), or nickel (Ni). In the following description, it is described that the wiring film 500 includes aluminum (Al).

[0160] Reference Fig.23 and Fig.24 , the wiring film 500 is patterned to form a first wiring pattern 510 , a second wiring pattern 520 , and a re-wiring pattern 530 . Fig.24 yes Fig.23 An enlarged view of part "XXIV" is provided for reference.

[0161] The formation of the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530 may be performed by, for example, a photolithography process. For example, an etching process using the third mask pattern 830 as an etching mask may be performed. The third mask pattern 830 may cover the first to third trenches TR1, TR2, TR3, and may expose the wiring film 500 between the first trench TR1 and the second trench TR2, and the wiring film 500 between the second trench TR2 and the third trench TR3.

[0162] Thus, a first wiring pattern 510 filling the first trench TR1 and extending along the upper surface of the insulation structure 200 may be formed. Furthermore, a second wiring pattern 520 filling the second trench TR2, being spaced apart from the first wiring pattern 510, and extending along the upper surface of the insulation structure 200 may be formed. Furthermore, a rewiring pattern 530 filling the third trench TR3, being spaced apart from the first wiring pattern 510 and the second wiring pattern 520, and extending along the upper surface of the insulation structure 200 may be formed.

[0163] In some example embodiments, the capacitor structure 400 may be formed together with the first wiring pattern 510, the second wiring pattern 520, and the rewiring pattern 530. For example, an etching process using the third mask pattern 830 as an etching mask may be performed until the upper surface of the insulating structure 200 is exposed. Thus, the third electrode film 430q may be patterned to form an upper electrode pattern 430b, a first barrier layer 440, and a second barrier layer 450.

[0164] In some example embodiments, the third mask pattern 830 may extend longer than the first electrode pattern 410. For example, the third mask pattern 830 may be formed to protrude from an end of the first electrode pattern 410. Fig.24 As shown, it can be formed using Figures 1 to 3 A capacitor structure 400 is depicted.

[0165] After forming the first wiring pattern 510 , the second wiring pattern 520 , the re-wiring pattern 530 , and the capacitor structure 400 , the third mask pattern 830 may be removed.

[0166] Since the capacitor structure 400 can be formed together with the process of forming the rewiring pattern 530, the capacitor structure 400 can be manufactured through a simplified process. Therefore, a semiconductor device including a capacitor having improved capacitance can be provided through a simplified process.

[0167] Fig.25 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. Fig.26 yes Fig.25 An enlarged view of section "XXVI" of FIG. Fig.25 It is used to illustrate Fig. 22 An intermediate stage diagram of the subsequent stage.

[0168] Reference Fig.25 and Fig.26 , the third mask pattern 830 may extend longer than the dielectric pattern 420. For example, the third mask pattern 830 may be formed to protrude from the end of the dielectric pattern 420. Fig.26 As shown, it can be formed Figures 4 to 6 The capacitor structure is described.

[0169] Fig. 27 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. Fig.28 yes Fig. 27 An enlarged view of section "XXVIII". In addition, Fig. 27 It is used to illustrate Fig. 22 An intermediate stage diagram of the subsequent stage.

[0170] Reference Fig. 27 and Fig.28 , the third mask pattern 830 may be extended to Fig. 22 The first electrode pattern 410 is short or Fig. 22 The third mask pattern 830 may be formed to be the same as the first electrode pattern 410. Fig. 22 The ends of the first electrode pattern 410 are the same or lead to Fig. 22 The end of the first electrode pattern 410. Fig.28 As shown, it can be formed Figure 7 and Figure 8 The capacitor structure is described.

[0171] Summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the disclosed exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the present invention are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A semiconductor device, the semiconductor device include: an insulating structure, the insulating structure being located on the substrate, the insulating structure comprising a first trench and a second trench, the second trench being spaced apart from the first trench; a first conductive layer, wherein the first conductive layer is located in the insulating structure, a first portion of an upper surface of the first conductive layer is exposed by the first groove, and a second portion of an upper surface of the first conductive layer is exposed by the second groove; a capacitor structure comprising a first electrode pattern electrically connected to the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along the sidewall and bottom surface of the first trench and the upper surface of the insulating structure; a first wiring pattern, the first wiring pattern being located on the capacitor structure, filling the first trench, and the first wiring pattern being electrically connected to the second electrode pattern of the capacitor structure; as well as A second wiring pattern is spaced apart from the first wiring pattern, fills the second trench, and extends along the upper surface of the insulating structure, and is connected to a second portion of the upper surface of the first conductive layer.

2. The semiconductor device according to claim 1, in, The dielectric pattern extends along the contour of the upper surface of the first electrode pattern, The second electrode pattern extends along a contour of an upper surface of the dielectric pattern.

3. The semiconductor device according to claim 2, in, A first distance from one end of the first trench to a terminal end of the first electrode pattern is shorter than a second distance from the one end of the first trench to a terminal end of the dielectric pattern.

4. The semiconductor device according to claim 1, further comprising: include: a barrier layer, the barrier layer being located between the first conductive layer and the second wiring pattern, The barrier layer extends along sidewalls and a bottom surface of the second trench and the upper surface of the insulation structure.

5. The semiconductor device according to claim 1, further comprising: include: a second conductive layer, the second conductive layer being spaced apart from the first conductive layer and being located in the insulating structure; as well as A rewiring pattern extends along the upper surface of the insulating structure, the rewiring pattern is spaced apart from the first wiring pattern, and the rewiring pattern is connected to the upper surface of the second conductive layer.

6. The semiconductor device according to claim 5, further comprising: include: a barrier layer, the barrier layer being located between the second conductive layer and the redistribution pattern, wherein the second groove at least exposes a portion of the upper surface of the second conductive layer, The barrier layer extends along sidewalls and a bottom surface of the second trench and along the upper surface of the insulation structure.

7. The semiconductor device according to claim 1, in, The first electrode pattern and the second electrode pattern include titanium nitride.

8. The semiconductor device according to claim 1, in, The first wiring pattern includes aluminum.

9. A semiconductor device, the semiconductor device include: a first conductive layer, the first conductive layer being located on a substrate; an insulating structure, the insulating structure being located on the first conductive layer, the insulating structure comprising a first trench and a second trench, the first trench exposing a first portion of an upper surface of the first conductive layer, the second trench exposing a second portion of an upper surface of the first conductive layer and being spaced apart from the first trench; a capacitor structure extending along the sidewalls and bottom surface of the first trench; a first wiring pattern, the first wiring pattern being located on the capacitor structure, filling the first trench, and extending along an upper surface of the insulating structure; as well as A second wiring pattern is spaced apart from the first wiring pattern, fills the second trench, and extends along the upper surface of the insulating structure, and is connected to a second portion of the upper surface of the first conductive layer.

10. The semiconductor device according to claim 9, further comprising: include: a barrier layer extending along sidewalls and a bottom surface of the second trench, Wherein, the second wiring pattern extends along the upper surface of the barrier layer.

11. The semiconductor device according to claim 10, in, The capacitor structure includes a first electrode pattern located on the first conductive layer, a dielectric pattern located on the first electrode pattern, and a second electrode pattern located on the dielectric pattern. The second electrode pattern is thicker than the barrier layer.

12. The semiconductor device according to claim 10, in, The capacitor structure includes a first electrode pattern located on the first conductive layer, a dielectric pattern located on the first electrode pattern, and a second electrode pattern located on the dielectric pattern. The barrier layer and the second electrode pattern include the same material.

13. The semiconductor device according to claim 9, in, A voltage applied to the first wiring pattern is different from a voltage applied to the second wiring pattern.

14. The semiconductor device according to claim 9, in, The first wiring pattern and the second wiring pattern include the same material.

15. The semiconductor device according to claim 9, further comprising: include: a second conductive layer, the second conductive layer being located in the insulating structure and spaced apart from the first conductive layer; as well as A rewiring pattern extends along an upper surface of the insulating structure, the rewiring pattern is spaced apart from the first wiring pattern, and the rewiring pattern is connected to an upper surface of the second conductive layer.

16. A semiconductor device, the semiconductor device include: an insulating structure, the insulating structure being located on the substrate, the insulating structure comprising a first trench and a second trench, the second trench being spaced apart from the first trench; a first conductive layer, wherein the first conductive layer is located in the insulating structure, a first portion of an upper surface of the first conductive layer is exposed by the first groove, and a second portion of the upper surface of the first conductive layer is exposed by the second groove; a first electrode pattern extending along a sidewall and a bottom surface of the first trench; a dielectric pattern, the dielectric pattern covering an upper surface and a side wall of the first electrode pattern; a second electrode pattern extending along an upper surface of the dielectric pattern; a first wiring pattern extending along an upper surface of the second electrode pattern, filling the first groove, and electrically connected to the second electrode pattern; as well as A second wiring pattern is spaced apart from the first wiring pattern, fills the second trench, and extends along an upper surface of the insulating structure, and is connected to a second portion of the upper surface of the first conductive layer.

17. The semiconductor device according to claim 16, in, The dielectric pattern includes a first extending portion extending along the upper surface of the first electrode pattern and a first protruding portion protruding from the first extending portion and covering the sidewall of the first electrode pattern.

18. The semiconductor device according to claim 17, in, The second electrode pattern includes a second extending portion extending along an upper surface of the first extending portion and a second protruding portion protruding from the second extending portion and extending along an upper surface of the first protruding portion.

19. The semiconductor device according to claim 17, in, The first protrusion is in direct contact with an upper surface of the insulation structure.

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