Semiconductor device

Abstract

Embodiments of the present disclosure relate to semiconductor devices. After the molding encapsulation process is completed, the polysilicon resistor has a large resistance change rate. To achieve high-precision fine tuning, it is desirable to achieve a resistor that is almost unaffected by the stress and temperature fluctuations generated in the substrate through the molding encapsulation process. The resistance element is formed in a plurality of wiring layers and has a repeating pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of materials.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2018-161311, filed on August 30, 2018, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device having a resistance element formed in a wiring layer. Background Art

[0004] In the case where an oscillation circuit is provided in a semiconductor device, a trimming circuit for finely adjusting the frequency characteristics of the oscillation circuit is generally provided. The trimming circuit has a resistor, and by adjusting the resistance value of the resistor, the oscillation frequency of the oscillation circuit can be set to an expected value for each semiconductor device. As a resistance element for the trimming circuit, a polysilicon resistor for forming a circuit element such as a transistor is known. The advantage of the polysilicon resistor is that the polysilicon resistor can be formed without complicating the manufacturing process of the semiconductor device, and a high resistance can be achieved with a high resistivity and a small area. However, it is known that the resistance value fluctuates after the molding encapsulation process. This is because the resistance element (polysilicon resistor) on the silicon chip is subjected to stress from the molding resin, and the resistance value changes due to shape change, piezoelectric effect, etc. Japanese Unexamined Patent Application Publication No. 2013-229509 prescribes the position for arranging the polysilicon resistor so as to minimize the stress received by the polysilicon resistor from the molding resin. Summary of the Invention

[0005] According to Japanese Unexamined Patent Application Publication No. 2013-229509, the object is to suppress the resistance change rate of the polysilicon resistor from the wafer state (i.e., the trimming completion state) of the polysilicon resistor to within about ±0.5% after the molding encapsulation process. However, in recent years, the accuracy required for the trimming circuit has been high, and it is desired to reduce the resistance change rate as much as possible. Further, in the technology disclosed in Japanese Unexamined Patent Application Publication No. 2013-229509, since the positions where the polysilicon resistor can be arranged are restricted, the degree of freedom in layout is inevitably low. In addition, the characteristic change caused by temperature change also affects the accuracy of the oscillation frequency of the oscillation circuit. For this reason, a control circuit for controlling the temperature dependence of the oscillation frequency has been conventionally provided, but this increases the circuit area and also causes an increase in the power consumption of the chip.

[0006] According to the description and drawings of the present specification, other objects and novel features will become apparent.

[0007] A resistive element is implemented, which is formed on multiple wiring layers, has a main resistance in a direction perpendicular to the surface of the semiconductor substrate, and has a main resistance composed of multiple types of materials. A resistor with a small resistance change rate and a small change in temperature characteristics can be realized after the molding encapsulation process is completed.

[0008] A resistor with a small resistance change rate and a small change in temperature characteristics can be realized after the molding encapsulation process is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a locking diagram of a semiconductor device.

[0010] Figure 2 is a circuit diagram of an oscillator circuit.

[0011] Figure 3 is a conceptual diagram of a resistive element.

[0012] Figure 4 is a diagram showing the principle of suppressing the temperature dependence of the oscillator frequency.

[0013] Figure 5 is an example of a resistive element.

[0014] Figure 6 is a circuit diagram of a resistive element.

[0015] Figure 7 is a circuit diagram of a variable resistor using a resistive element.

[0016] Figure 8 is a diagram showing an example of a resistive element.

[0017] Figure 9 is a diagram showing an example of a resistive element.

[0018] Figure 10 is a diagram showing an example of a resistive element.

[0019] Figure 11 is a diagram showing an example of a resistive element.

[0020] Figure 12 is a diagram showing an example of a resistive element.

[0021] Figure 13 is a diagram showing an example of a resistive element.

[0022] Figure 14 is a diagram showing an example of a resistive element.

[0023] Figure 15 is a diagram showing an example of a multilayer buried via.

[0024] Figure 16 This is a block diagram of a pressure sensor.

[0025] Figure 17 This is a diagram showing an example of a resistance element.

[0026] Figure 18 This is a diagram showing an example of a pressure detection circuit.

[0027] Figure 19 This is a diagram showing an example of a resistor for a pressure detection circuit. Detailed implementation

[0028] Embodiments will be described below with reference to the accompanying drawings. Figure 1 This shows a semiconductor device 1 according to the present embodiment. Active elements such as transistors and passive elements such as resistors and capacitors are formed on the substrate of the semiconductor device 1. These elements are used to form various functional blocks in the semiconductor device 1. As an example of a functional block, Figure 1 This shows a CPU (Central Processing Unit) 2, a RAM 3, a peripheral IP 4, and a non-volatile memory 5. The peripheral IP can be, for example, an A / D converter. Addresses and data are exchanged between these functional blocks via a bus 10. A clock generation circuit 7 generates a clock from the oscillation signal of an on-chip oscillator contained therein and distributes the clock to these functional clocks via the bus 10. As will be described in detail later, the on-chip oscillator has a trimming resistor. By setting the resistance value of the trimming resistor to a predetermined value, the oscillation frequency of the on-chip oscillator is adjusted to the desired value for each semiconductor device 1. The trimming code required for trimming is written into the non-volatile memory 5 or the RAM 3, and based on the trimming code read through a control register 6, the resistance value of the trimming resistor is set to a predetermined value.

[0029] Figure 2 This shows a circuit diagram of an oscillation circuit 8, which is an example of an on-chip oscillator used in the clock generation circuit 7. The oscillation circuit includes a trimming circuit 20, a constant current generation circuit 21, capacitors 22 and 23, capacitor drive circuits 24 and 25, comparators 26 and 27, and a latch circuit 28. The current flowing through the source / drain path of the PMOS transistor 35 in the constant current generation circuit 21 is Ir0, and the transistor size of the PMOS transistor 36 in the constant current generation circuit 21 is M times the transistor size of the PMOS transistor 35. Therefore, an output current M×Ir0 is output from the drain of the PMOS transistor 36.

[0030] The oscillation output of the oscillation circuit 8 is the oscillation signal Φ output from the output terminal Q of the latch circuit 28. The latch circuit 28 has an output terminal QN and the oscillation signal / Φ, and outputs from the output terminal QN an oscillation signal / Φ whose phase is opposite to that of the oscillation signal Φ. The oscillation signal Φ and the oscillation signal / Φ are input to the capacitor drive circuits 24 and 25, and the capacitors 22 and 23 are alternately charged from the discharged state to the reference potential level using the output current M×Ir0 from the PMOS transistor 36. When the charge rises to the potential VR of the reference potential point N1 of the trimming circuit 20, the outputs of the comparators 26 and 27 are inverted, and the phase of the oscillation signal Φ (oscillation signal / Φ) is inverted. By repeating this operation, the oscillation circuit 8 outputs an oscillation signal having a predetermined frequency.

[0031] In the trimming circuit 20, the resistance value R of the variable resistor is adjusted according to the trimming code stored in the control register 6 via to adjust the potential VR of the reference potential point N1. It can be understood from the following equation (1) that the oscillation frequency F of the oscillation circuit 8 (CKOUT) is determined by the capacitance values C0 and C1 of the capacitors 22 and 23, the resistance value R of the variable resistor 20a via and the mirror ratio M. Let T H be the time width of the high level, and T L be the time width of the low level in the oscillation output of the oscillation circuit 8.

[0032] [Equation]

[0033]

[0034] Figure 3 is a conceptual diagram of the resistance element used in the variable resistor 20a according to the present embodiment. The resistance element is formed in the wiring layer of the semiconductor device. The surface of the semiconductor substrate on which the semiconductor element is formed is defined as the XY plane, and the direction perpendicular to the XY plane is defined as the Z direction. The resistance element has a lower conductive layer 31 and an upper conductive layer 32 extending in the X direction or the Y direction respectively, and both ends of the resistance element are connected to the lower conductive layer 31 and the upper conductive layer 32 respectively; and has an interlayer conductive layer 33 extending in the Z direction, and the lower conductive layer 31, the interlayer conductive layer 33 and the upper conductive layer 32 are connected in series.

[0035] In this text, it is assumed that the resistance of the resistance element is R, and the k + 1 lower conductive layers 31, the k upper conductive layers 32, and the 2k interlayer conductive layers 33 of the resistance element are connected in series. The resistance value of one lower conductive layer 31 is Rxy_lower, the resistance value of one upper conductive layer 32 is Rxy_upper, and the resistance value of one interlayer conductive layer 33 is Rz. At this time, the resistance R of the resistance element is expressed as R = (k + 1)×Rxy_lower + 2k×Rz + k×Rxy_upper. This is the expression in the case where the resistance element is connected to another element in the upper conductive layer 32. Similarly, in the case where the lower conductive layer 31 is connected to another element, the resistance value R of the resistance element is expressed as R = k×Rxy_lower + 2k×Rz + (k + 1)×Rxy_upper.

[0036] In any case, it is assumed that the Z-direction component of the resistance element is the main resistance, and the relationship of Rz >> Rxy_lower + Rxy_upper is established. The resistance element of this embodiment formed in the interconnection layer and having the Z-direction component as the main resistance is hardly affected by the stress generated in the semiconductor substrate through the molding encapsulation process. Therefore, there is no limitation on the arrangement position of the resistance element of this embodiment, and the lower conductive layer 31, the interlayer conductive layer 33, and the upper conductive layer 32 can be connected in series so that the resistance element has a desired resistance, and there is no limitation on the arrangement and number of each conductive layer.

[0037] Specifically, in this embodiment, the interlayer conductive layer 33 serving as the main resistance is formed so that the resistance R of the resistance element via becomes equal to the reciprocal of the sum (C0 + C1) of the capacitances of the resistance element. At this time, as Figure 4 shown, if the product of (C0 + C1) and R via can be made a constant value regardless of temperature, then according to the relationship shown in Equation (1), the oscillation frequency F (CKOUT) of the oscillation circuit 8 can be kept constant regardless of temperature.

[0038] Specifically, for the interlayer conductive layer 33 that constitutes the main resistance of the resistance element for the variable resistor 20a, by using a plurality of buried vias of the same material, the temperature dependence of the resistance R of the resistance element via is made equal to the inverse temperature dependence of (C0 + C1). It should be noted that since the lower conductive layer 31 and the upper conductive layer 32 constituting the resistance element are wiring layers initially formed with low resistance, the influence of the lower conductive layer 31 and the upper conductive layer 32 can be reduced to a negligible level. Figure 5An installation example of a resistive element is shown. As described above, the structure of the wiring layer formed in the semiconductor device is for the resistive element. The lower conductive layer 31 is formed in the wiring layer M1, the upper conductive layer 32 is formed in the wiring layer M4, and the interlayer conductive layer 33 is formed in the vias V1 to V3 and the wiring layers M2 and M3. By using multiple conductive layers to form the interlayer conductive layer 33, the resistance value of the interlayer conductive layer 33 can be increased as much as possible, and it can be formed without complicating the process of the wiring layer. The interlayer conductive layer 33 includes vias 51 connected in series, bonding pads 52 formed in the wiring layer M2, vias 53, bonding pads 54 formed in the wiring layer M3, and vias 55. In Figure 5 the resistive element, it is assumed that the via 51 formed between the wiring layers M1 and M2 is formed of material a, the via 53 formed between the wiring layers M2 and M3 is formed of material b, and the via 55 formed between the wiring layers M3 and M4 is formed of material c.

[0039] At this time, the capacitance C (= C0 + C1), the resistance value Ra of the buried via of material a, the resistance value Rb of the buried via of material b, and the resistance value Rc of the buried via of material c can be expressed by the following equations (2) and (3), where the temperature change is ΔT. All values should reach the second approximation.

[0040] [Equation 2]

[0041] C = C0{1 + k TC1 ×ΔT + k TC2 ×ΔT 2}(2)

[0042] [Equation 3]

[0043]

[0044] It should be noted that C0, Ra0, Rb0, and Rc0 are zero-order approximation values, k TC1 , k TRa1 , k TRb1 and k TRc1 are the main temperature coefficients, and k TC2 , k TRa2 , k TRb2 and k TRc2 are the secondary temperature coefficients, respectively.

[0045] Since the resistance value R via of the resistive element can be considered as the resistance value of the interlayer conductive layer as the main resistance, the resistance value R via can be expressed as the sum of the resistance values Ra, Rb, and Rc (R via = Ra + Rb + Rc). Substituting Equation (3) into it gives Equation (4). [Equation 4]

[0046]

[0047] Further, by substituting Equation (2) and Equation (4) into the oscillation frequency F shown in Equation (1) (CKOUT) of the equation, the following relational expression (5) is obtained.

[0048] [Equation 5]

[0049]

[0050] Rvia0 = Ra0 + Rb0 + Rc0

[0051]

[0052]

[0053] In this article, since the temperature coefficient is less than 1 and the coefficient value becomes smaller as the temperature gets higher, and the influence on the temperature dependence is small, by adjusting the ratio of Ra0, Rb0, and Rc0 to R via0 such that the oscillation frequency F (CKOUT) in the first-order temperature coefficient (k TC1 + k TR1 ) and the second-order temperature coefficient (k TC2 + k TR2 + k TC1 × k TR1 ) become 0 respectively, a resistance element with extremely small temperature dependence can be obtained. This leads to solving two equations, each equation having three variables Ra0, Rb0, and Rc0 and having a first-order temperature coefficient and a second-order temperature coefficient of 0, such that a resistance element with extremely low temperature dependence can be realized. For example, in the case where the accuracy of the oscillation frequency F (CKOUT) allows the second-order temperature coefficient to be ignored, the interlayer conductive layer can be composed of two materials that are materials of the resistance element. On the contrary, in the case where the higher-order temperature coefficient is also 0, the interlayer conductive layer can be composed of multiple materials corresponding to the higher-order temperature coefficient.

[0054] Since the resistance values Ra, Rb, and Rc of each material are always positive, at least one of the materials constituting the interlayer conductive layer needs to include a material with a positive temperature coefficient and at least one material with a negative temperature coefficient. As a material with such a negative temperature coefficient, a semiconductor (polycrystalline silicon) can be used. For example, although Figure 5 shows an example where the material of the interlayer conductive layer 33 is different for each layer, titanium nitride (TiN) is used for via 51, P-type polycrystalline silicon (P-PolySi) is used for via 53, and tungsten (W) is used for via 55.

[0055] As described above, since the variable resistor 20a in the present embodiment is formed by using the structure of the wiring layer, the resistance values of the respective conductive layers constituting the resistance element are relatively low. Therefore, a desired resistance value is achieved by using a large number of conductive layers connected in series as the resistance element. Figure 6 FIG. shows a circuit diagram of the resistance element 60. Since the resistance element 60 is formed by a repeating pattern of a lower conductive layer, an interlayer conductive layer, and an upper conductive layer, one unit of the repeating pattern is pseudo-indicated as a unit resistor 61 herein.

[0056] Figure 7 FIG. shows a circuit diagram of the variable resistor 20a using the resistance element 60 of the present embodiment. The variable resistor 20a has N resistance elements 60 connected in series, and bypass switches 70-i (i = 1 to N) provided in parallel with the resistance element 60-i to bypass the resistance element 60-i (i = 1 to N). As Figure 6 shown, the resistance element 60 is composed of unit resistors 61 connected in series. The ON / OFF of the bypass switch 70-i of the variable resistor 20a is determined according to the trimming code, whereby the resistance of the variable resistor 20a is set to a desired resistance value, and a potential corresponding to the resistance value appears at the node N1. Since the resistance element 60 of the present embodiment has a large number of series elements, the yield may decrease due to defects such as non-conduction. For this reason, for the resistance element 60-i in which a manufacturing failure has occurred, the corresponding bypass switch 70-i is continuously turned on, thereby preventing the yield from decreasing.

[0057] Although Figure 5 FIG. shows an example in which buried vias of different materials are vertically stacked to form an interlayer conductive layer as the resistance element 60, the present invention is not limited thereto. Other implementation manners are as follows.

[0058] In Figure 8 , the resistance element 60 is divided into a plurality of regions, and the materials for forming the interlayer conductive layer in the respective regions are different from each other. In this example, it is separated into two regions 80 and 83. As shown in a cross-sectional view of a portion 81 of the resistance element formed in the region 80, W is used for the via 82 in the region 80, and as shown in a cross-sectional view of a portion 84 of the resistance element formed in the region 83, P-PolySi is used for the via 85 in the region 83. Figure 9A modified example is shown. In this example, the layers used to form the buried vias vary depending on the material. As shown in the cross-sectional view of part 81a of the resistor element formed in region 80, W is used for via 82 in region 80, but the W buried via is formed between wiring layer M2 and wiring layer M3 and not between wiring layer M1 and wiring layer M2. On the other hand, as shown in the cross-sectional view of part 84a of the resistor element formed in region 83, although P-PolySi is used for via 85 in region 83, the P-PolySi buried via is formed between wiring layer M1 and wiring layer M2 and not between wiring layer M2 and wiring layer M3. As described above, by using different layers for forming the buried vias according to the material, there is an advantage that the process for forming resistor element 60 can be simplified. In this example, dummy wirings 86 and 87 are provided in the wiring layer, and in this wiring layer (that is, in wiring layer M1 in region 80 and wiring layer M3 in region 83 respectively), no buried vias are formed. The dummy wirings can be omitted.

[0059] Figure 10 An example is shown in which a correction block for correcting the temperature coefficient is provided Figure 8 and a configuration example of the resistor element 60 shown in. The unit resistors configured in region 90, the unit resistors configured in region 93, and the unit resistors configured in region 94 are connected in series, and a bypass switch 97 is provided in parallel with the unit resistors connected in series in region 94. Additionally, as shown in the cross-sectional view of part 91 of the resistor element formed in region 90, W is used for via 92 in region 90, and as shown in the cross-sectional view of part 95 of the resistor element formed in regions 93 and 94, P-PolySi is used for via 96 in regions 93 and 94. According to this configuration, in the case where the thermal coefficient changes due to device variations, by switching the ON / OFF of the bypass switch 97, the variations can be suppressed and the frequency accuracy can be improved. Although this example shows an example in which a correction block having a material with a negative temperature coefficient is used as the interlayer conductive layer, a correction block having a material with a positive temperature coefficient can be provided as the interlayer conductive layer, or both a correction block having a material with a positive temperature coefficient as the interlayer conductive layer and a correction block having a material with a negative temperature coefficient as the interlayer conductive layer can be provided. The number of unit resistors connected in series in the correction block can be the same as or different from the number of series connections in other regions.

[0060] Figure 11 An example is shown in which the layers used to form the buried vias vary depending on the material, and this example is similar to the example of Figure 9 The advantage is that the process of forming resistor element 60 can be simplified.

[0061] Figure 12shows a modified example of forming an interlayer conductive layer by vertically stacking resistors of different materials. In the case where the materials used to form the interlayer conductive layer are different for each region, in addition to the inherent resistance values of the materials, by making the number of unit resistance elements connected in series in each region different, Ra0, Rb0, and Rc0 can be accurately adjusted with respect to R Figures 8 to 11 shown. via0 ratio. Figure 12 shows that the same operation can be performed even when forming an interlayer conductive layer by vertically stacking buried vias of different materials. In this embodiment, the interlayer conductive layer is formed by P-PolySi buried via 105 and W buried via 106, and the number of via 105 and the number of via 106 are different from each other.

[0062] In this example, the lower conductive layer 101 is formed in wiring layer M1 or wiring layer M2, the upper conductive layer 102 is formed in wiring layer M3, and the interlayer conductive layer 103 is formed in vias V1 to V2 and wiring layer M2. For example, the interlayer conductive layer 103a is composed of series-connected via 105, bonding pad 107 formed in wiring layer M2, and via 106, while the interlayer conductive layers 104a and 104b are composed of via 106 and are connected to the lower conductive layer 101b formed in wiring layer M2. In this example, dummy wiring 108 may or may not be provided in wiring layer M1, in which no buried via 105 is formed. This example is an example of reducing the number of P-PolySi buried vias 105, but the number of W buried vias 106 can also be reduced. Although this example is an example of buried vias having two types of materials, as Figure 5 shown, in an example of buried vias having two or more types of materials, the number of buried vias of each material can be adjusted similarly.

[0063] Figure 13 shows yet another modified example. Figure 11A plan view of the interlayer conductive layer 113 formed between wiring layers M1 to M4 and a cross-sectional view taken along line a-a' in the plan view are shown. The interlayer conductive layer 113 includes a TiN buried via 114 connected in series, a bonding pad 117 formed in the wiring layer M2, a P-PolySi buried via 115, a bonding pad 118 formed in the wiring layer M3, and a W buried via 116. In this example, the diameter of each via and the diameter of the bonding pad are different. Specifically, in the case of the diameter Wd_t of the TiN buried via 114, the diameter Wd_2 of the bonding pad 117, the diameter Wd_p of the P-PolySi buried via 115, the diameter Wd_3 of the bonding pad 118, and the diameter Wd_w of the W buried via 116 are set such that Wd_t < Wd_w < Wd_p < Wd_3 < Wd_2. In this way, by making the diameters of vias made of different materials different from each other, in addition to the resistance values inherent in the materials, the ratios of Ra0, Rb0, and Rc0 to R can be accurately adjusted. via0 Furthermore, the TiN buried via 114 and the P-PolySi buried via 115, or the P-PolySi buried via 115 and the W buried via 116 can be directly connected without using a bonding pad.

[0064] Figure 14An example is shown in which a correction block for correcting the temperature coefficient is provided for a resistive element, in which the interlayer conductive layer is formed by vertically stacking resistors of different materials. In this example, correction blocks 131 to 133 are provided, which are connected to the interlayer conductive layer 123d provided between the upper conductive layer 122b formed in the wiring layer M4 and the bonding pad 127 formed in the wiring layer M1; and bypass switches 134 to 136, which are respectively connected in parallel with the correction blocks 131 to 133. The correction blocks 131 to 133 are connected in series to the resistive element. The correction block 131 is composed of the conductive layer of the wiring layer M1, the conductive layer of the wiring layer M2, and the interlayer conductive layer 137 between the wiring layers M1 and M2, and the interlayer conductive layer 137 is made of the same material (TiN in this article) as the via 124 of the interlayer conductive layer 123. The correction block 132 is composed of the conductive layer of the wiring layer M2, the conductive layer of the wiring layer M3, and the interlayer conductive layer 138 between the wiring layers M2 and M3, and the material of the interlayer conductive layer 138 is the same as the material of the via 125 of the interlayer conductive layer 123 (P-PolySi in this article). The correction block 133 is composed of the conductive layer of the wiring layer M3, the conductive layer of the wiring layer M4, and the interlayer conductive layer 139 between the wiring layers M3 and M4, and the material of the interlayer conductive layer 139 is the same as the material of the via 126 of the interlayer conductive layer 123 (W in this article). According to this configuration, in the case where the thermal coefficient changes due to component variations, the change can be suppressed by switching the ON / OFF of the bypass switches 134 to 136, and the frequency accuracy can be improved. In this example, an example is shown in which correction blocks corresponding to all the materials of the interlayer conductive layer constituting the resistive element are provided, but correction blocks corresponding to one or two types of materials can be provided.

[0065] Although various examples of mounting the resistive element 60 have been described above, materials other than the exemplified materials can be used for these materials, and different resistive materials can be buried in multiple layers in the same via, as Figure 15 shown. The via 140 has a structure in which a TiN layer 141 is deposited and a W layer 142 is buried. In this way, a via having multiple materials can be formed between one wiring layer, rather than forming vias having different materials between wiring layers.

[0066] The formation of the resistive component in the vertical direction is not limited to the method of embedding the resistive material by drilling in the interlayer insulating film, and can be a formation method of forming the interlayer insulating film after using a mask to etch the required pattern, in order to form a conductive layer pattern on the conductive layer formed by pre-depositing the resistive material.

[0067] As described above, the resistor element of the present embodiment can suppress the influence of stress and the influence of thermal changes generated in the semiconductor substrate through the molding encapsulation process. As an application taking advantage of these characteristics, Figure 16 A pressure sensor 150 using the resistor element of the present embodiment is shown.

[0068] The pressure sensor 150 includes a control register 151, an oscillation circuit 152, and a counter 153. Based on the control signal read from the control register 151, the oscillation circuit 152 oscillates a clock having a predetermined oscillation frequency. The counter 153 counts the number of cycles of the clock from the oscillation circuit 152 within a period determined by a reference clock. The pressure sensor 150 is a pressure sensor that uses the stress change of the resistor element, which is a common type of pressure sensor. As the oscillation circuit 152, for example, an oscillation circuit as shown in Figure 2 can be used. When pressure is applied to the pressure sensor 150, the resistance value of the resistor element included in the oscillation circuit 152 changes, and the frequency of the clock from the oscillation circuit 152 changes accordingly. The counter 153 detects the pressure applied to the pressure sensor 150 based on the change in the clock frequency (that is, the change in the number of cycles to be counted). In a conventional resistor element, since the resistance value also changes according to temperature, it is necessary to add a temperature sensor and correct the change caused by the temperature change. Using the resistor element of the present embodiment eliminates the need for a thermal sensor.

[0069] Here, it is desirable that the resistor element for the pressure sensor in the oscillation circuit 152 has a large resistance value that changes due to the application of pressure to the pressure sensor 150.

[0070] Figure 17 An example of the resistor element is shown. The piezoresistive conductive layers 160a to 160c extending in the X direction of the wiring layer M1 are arranged in parallel. The piezoresistive conductive layer 160 is formed of a material whose resistivity is easily changed by the stress applied to the chip (e.g., SiCr). The piezoresistive conductive layers 160 are connected in series via the connection portion 161. The connection portion 161 is formed by using the structure of the wiring layer. The lower conductive layer 162 is formed in the wiring layer M2, the upper conductive layer 163 is formed in the wiring layer M4, and the interlayer conductive layer 164 is formed in the vias V2 to V3 and the wiring layer M3. The interlayer conductive layer 164 includes a via 165 connected in series, a bonding pad 166 formed in the wiring layer M3, and a via 167. One end of the connection portion 161 is connected to the piezoresistive conductive layer 160 at the via V1 between the wiring layers M1 and M2, and the other end is connected to the adjacent piezoresistive conductive layer 160 at the via V1 between the wiring layers M1 and M2.

[0071] In Figure 17In the resistive element, via 165 formed between wiring layers M2 and M3 is formed of material a, via 167 formed between wiring layers M3 and M4 is formed of material b, and the piezoresistive conductive layer 160 is formed of material c, and the ratios of Ra0, Rb0, and Rc0 to R via0 are adjusted such that the oscillation frequency F (CKOUT) at the first-order temperature coefficient (k TC1 + k TR1 ) and the second-order temperature coefficient (k TC2 + k TR2 + k TC1 × k TR1 ) become 0 as shown in Equation (5). As a result, in the resistive element shown in Figure 17 , a large resistance change due to stress can be obtained through the piezoresistive conductive layer 160, and on the other hand, the change in the temperature characteristics of the piezoresistive conductive layer 160 is eliminated by the connection portion 161, and the influence caused by the temperature change can be suppressed to a very small level.

[0072] In Figure 17 , the piezoresistive conductive layer 160 is formed in a wiring layer lower than the wiring layer in which the connection portion 161 is formed, but the piezoresistive conductive layer 160 can be formed in a wiring layer higher than the wiring layer in which the connection portion 161 is formed.

[0073] The pressure sensor is not limited to the Figure 16 configuration. Figure 18 shows an example of a pressure detection circuit. The A / D converter 170 detects the potential at the potential point N2 obtained by dividing the power supply voltage by the first resistor R1 and the second resistor R2. Figure 19 shows an example of the first resistor R1 and the second resistor R2 used in the pressure detection circuit in which Figure 18 is installed.

[0074] The second resistor R2 is formed in the wiring layer M1 as a piezoresistive conductive layer 171 extending in the Y direction. The material of the piezoresistive conductive layer 171 is a material that generates a piezoelectric effect on the wafer. Specifically, the crystal point group is a material (1, 2, m, 222, mm2, 4, -4, 422, 4mm, -42m, 3, 32, 3m, 6, -6, 622, 6mm, -62m, -23, -43m), for example, W can be used.

[0075] The first resistor R1 is formed by using the structure of the wiring layer. The lower conductive layer 172 is formed in the wiring layer M2, the upper conductive layer 173 is formed in the wiring layer M4, and the interlayer conductive layer 174 is formed in the vias V2 to V3 and the wiring layer M3. The interlayer conductive layer 174 includes a via 175 connected in series, a bonding pad 176 formed in the wiring layer M3, and a via 177. The first resistor R1 and the second resistor R2 are connected to the via V1 between the wiring layers M1 and M2, and the connection point corresponds to Figure 18 the potential point N2 shown in

[0076] The varistor conductive layer 171 constituting the second resistor R2 and the vias 175 and 177 of the interlayer conductive layer constituting the main resistor of the first resistor R1 are formed of the same material. As a result, the second resistor R2 is stressed to generate a piezoelectric effect, while the interlayer conductive layer 174 of the first resistor R1 is hardly affected by the stress in the XY plane. On the other hand, since the varistor conductive layer of the second resistor R2 and the interlayer conductive layer of the main resistor of the first resistor R1 are formed of the same material, the change in temperature characteristics due to temperature change is canceled out. This makes it possible to realize a pressure detection circuit in which the influence of temperature fluctuations is suppressed to a very small level.

[0077] Figure 19 The varistor conductive layer 171 in

[0078] is a conductive layer extending in the Y direction, but it can also be formed as a conductive layer extending in the X direction. Further, by providing both a pressure detection path circuit in which the conductive layer extending in the Y direction is the varistor conductive layer 171 and a pressure detection path circuit in which the conductive layer extending in the X direction is the varistor conductive layer 171 on one chip, a pressure sensor capable of detecting pressure in the biaxial direction can be realized. Figure 16 As another application of the resistance element of this embodiment, a Figure 16 circuit can be used to realize a thermal sensor. Although the base voltage (Vbe) of a bipolar transistor is usually used for a temperature sensor, since the base voltage has a second-order temperature coefficient, the INL (Integral Nonlinearity: integral nonlinearity) of the temperature sensor decreases and temperature errors are likely to occur. Therefore, in the Figure 2 circuit block, for example, the Figure 5 oscillator circuit is applied as the oscillator circuit 152, and the Figure 5 configuration is applied as its resistance element. At this time, in the via0is adjusted by a ratio such that the oscillation frequency F (CKOUT) at the second-order temperature coefficient (k TC2 + k TR2 + k TC1 × k TR1 ) becomes 0, as shown in Equation (5). Since the resistance value of the resistance element is adjusted so that the second-order temperature coefficient is 0 and only the first-order temperature coefficient remains, a temperature sensor with good INL can be achieved by counting the clock of the oscillation circuit 152. Since only the second-order temperature coefficient is set to 0, the interlayer conductive layer that is the main resistor of the resistance element can be formed of two types of materials.

[0079] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments described above, and needless to say, various modifications can be made without departing from its gist. The illustrated materials are also merely exemplary, and other materials that satisfy the requirements described in this embodiment can be used. Multiple configuration examples and multiple configuration examples and multiple configuration examples and multiple configuration examples of modification examples can be combined as long as they do not conflict with each other.

[0080] Supplementary Note 1

[0081] A semiconductor device includes

[0082] a semiconductor substrate;

[0083] a plurality of wiring layers formed on the semiconductor substrate and including a first wiring layer, a second wiring layer, and a third wiring layer; and

[0084] an A / D converter that detects the potential of a potential point obtained by resistively dividing a power supply voltage through a first resistor and a second resistor,

[0085] wherein the first resistor includes a repeating pattern that includes a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer connecting the first conductive layer and the second conductive layer,

[0086] wherein the second resistor is formed in the third wiring layer, and

[0087] wherein the material of the second resistor and the material of the interlayer conductive layer of the first resistor are materials that exhibit a piezoelectric effect with respect to the semiconductor substrate.

[0088] Supplementary Note 2

[0089] The semiconductor device according to Supplementary Note 2,

[0090] Among them, the materials include crystal point groups, which include (1, 2, m, 222, mm2, 4, -4, 422, 4mm, -42m, 3, 32, 3m, 6, -6, 622, 6mm, -62m, 23, -43m).

[0091] Supplementary Note 3

[0092] A semiconductor device according to Supplementary Note 2

[0093] Among them, the material is tungsten.

Claims

1. A semiconductor device, comprising: a semiconductor substrate; and a plurality of wiring layers formed over the semiconductor substrate in a direction perpendicular to a surface of the semiconductor substrate, and including at least a first wiring layer and a second wiring layer above the first wiring layer, wherein a resistive element is formed in the plurality of wiring layers, wherein the resistive element includes the following repeating pattern: a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer extending in the direction and connecting the first conductive layer and the second conductive layer together, and wherein the interlayer conductive layer includes a plurality of bonding pads and a plurality of vias located between the plurality of bonding pads and electrically connecting the plurality of bonding pads, the plurality of vias being formed of a plurality of materials, and the plurality of materials including at least one of a positive temperature coefficient material and a negative temperature coefficient material.

2. The semiconductor device according to claim 1, wherein the repeating pattern of the resistive element is formed in a first region and a second region, wherein the repeating pattern formed in the first region and the repeating pattern formed in the second region are serially coupled, and wherein the material of the interlayer conductive layer formed in the first region is different from the material of the interlayer conductive layer formed in the second region.

3. The semiconductor device according to claim 2, wherein the repeating pattern of the resistive element is formed in a third region, wherein the repeating pattern formed in the first region, the repeating pattern formed in the second region, and the repeating pattern formed in the third region are serially coupled, wherein the repeating pattern formed in the third region is disposed in parallel with a bypass switch, and wherein the material of the interlayer conductive layer formed in the third region is the material of the interlayer conductive layer formed in the first region, or the material of the interlayer conductive layer formed in the second region.

4. The semiconductor device according to claim 2, wherein the wiring layer includes a third wiring layer between the first wiring layer and the second wiring layer, wherein the interlayer conductive layer formed in the first region is formed between the first wiring layer and the second wiring layer and is not formed between the second wiring layer and the third wiring layer, and wherein the interlayer conductive layer formed in the second region is formed between the second wiring layer and the third wiring layer and is not formed between the first wiring layer and the second wiring layer.

5. The semiconductor device according to claim 3, wherein the wiring layer includes a third wiring layer between the first wiring layer and the second wiring layer, wherein the material of the interlayer conductive layer formed in the third region is the same as the material of the interlayer conductive layer formed in the first region, and the interlayer conductive layer formed in the third region is formed between the first wiring layer and the second wiring, and is not formed between the second wiring layer and the third wiring layer, or wherein, the material of the interlayer conductive layer formed in the third region is the same as the material of the interlayer conductive layer formed in the second region, and the interlayer conductive layer formed in the third region is formed between the second wiring layer and the third wiring layer and is not formed between the first wiring layer and the second wiring layer.

6. The semiconductor device according to claim 1, wherein the wiring layer includes a third wiring layer between the first wiring layer and the second wiring layer, and wherein the material of the interlayer conductive layer formed between the first wiring layer and the second wiring layer is different from the material of the interlayer conductive layer formed between the second wiring layer and the third wiring layer.

7. The semiconductor device according to claim 6, wherein the resistance element further includes a pattern having the first conductive layer, a third conductive layer formed on the third wiring layer, and an interlayer conductive layer connecting the first conductive layer and the third conductive layer, or a pattern having the second conductive layer, the third conductive layer, and the interlayer conductive layer connecting the second conductive layer and the third conductive layer.

8. The semiconductor device according to claim 6, wherein the interlayer conductive layer includes a bonding pad formed on the third wiring layer, a first via hole coupling the first conductive layer and the bonding pad, a second via hole coupling the second conductive layer and the bonding pad, and wherein the width of the bonding pad, the width of the first via hole, and the width of the second via hole are different from each other.

9. The semiconductor device according to claim 7, further including at least one correction block of a first correction block and a second correction block, wherein the first correction block is connected in series with the resistance element and includes a repeating pattern of: the first conductive layer, the third conductive layer formed on the third wiring layer, and an interlayer conductive layer connecting the first conductive layer and the third conductive layer, wherein the second correction block is connected in series with the resistance element and includes a repeating pattern of the second conductive layer, the third conductive layer, and an interlayer conductive layer connecting the second conductive layer and the third conductive layer, and wherein bypass switches are respectively arranged in parallel for the first correction block and the second correction block.

10. The semiconductor device according to claim 1, comprising: a trimming circuit including a plurality of the resistance elements.

11. A semiconductor device, comprising: a semiconductor substrate; a plurality of wiring layers formed on the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate, and at least including a first wiring layer and a second wiring layer above the first wiring layer; and an oscillation circuit including a capacitor and a trimming circuit having resistance elements formed on the plurality of wiring layers, wherein the oscillation frequency of the oscillation circuit is determined according to the capacitance value of the capacitor and the resistance value of the resistance elements included in the trimming circuit, wherein the resistance element has a main resistance in the direction, and the main resistance is formed of a plurality of materials, wherein the resistance element includes a repeating pattern of: a first conductive layer in the first wiring layer among the plurality of wiring layers, a second conductive layer in the second wiring layer among the plurality of wiring layers, and an interlayer conductive layer extending in the direction and connecting the first conductive layer and the second conductive layer, and The ratio of the respective resistances of the plurality of materials is determined such that the temperature coefficient of the oscillation frequency is zero, and wherein the interlayer conductive layer includes a plurality of bonding pads and a plurality of vias located between the plurality of bonding pads for electrically connecting the plurality of bonding pads, the plurality of vias are formed of a plurality of materials, and the plurality of materials include at least one of a positive temperature coefficient material and a negative temperature coefficient material.

12. The semiconductor device according to claim 11, wherein the ratio of the respective resistances of the plurality of materials is determined such that at least one of a first-order temperature coefficient and a second-order temperature coefficient is zero.

13. The semiconductor device according to claim 11, further comprising: a counter that counts the number of clocks of the oscillation circuit within a predetermined period.

14. The semiconductor device according to claim 13, wherein the predetermined period is determined by a reference clock.

15. The semiconductor device according to claim 11, wherein the wiring layer includes at least a first wiring layer and a second wiring layer, wherein the resistance element includes a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and wherein the interlayer conductive layer is formed of the plurality of materials.

16. A pressure sensor, comprising: a semiconductor substrate; a plurality of wiring layers formed above the semiconductor substrate and including a first wiring layer, a second wiring layer, and a third wiring layer; an oscillation circuit including a capacitor and a trimming circuit, the trimming circuit having a resistance element formed on the plurality of wiring layers; and a counter that counts the number of clocks of the oscillation circuit within a predetermined period, wherein the resistance element includes a plurality of piezoresistive conductive layers formed on the third wiring layer and a connector unit formed between the first wiring layer and the second wiring layer, and the plurality of piezoresistive conductive layers are connected in series via the connector unit, wherein the connector unit includes a repeating pattern having a first conductive layer formed in the first wiring layer, a second conductive layer formed in the second wiring layer, and an interlayer conductive layer connecting the first conductive layer and the second conductive layer and formed of a plurality of materials, wherein the oscillation frequency of the oscillation circuit is determined according to the capacitance value of the capacitor and the resistance value of the resistance element included in the trimming circuit, and wherein the ratio of the resistance of the material of the piezoresistive conductive layer to the respective resistances of the plurality of materials of the interlayer conductive layer is determined such that the temperature coefficient of the oscillation frequency is zero, and wherein the interlayer conductive layer includes a plurality of bonding pads and a plurality of vias located between the plurality of bonding pads for electrically connecting the plurality of bonding pads, the plurality of vias are formed of a plurality of materials, and the plurality of materials include at least one of a positive temperature coefficient material and a negative temperature coefficient material.

17. The pressure sensor according to claim 16, The ratio of the resistance of the material of the pressure-sensitive conductive layer to the corresponding resistances of the plurality of materials of the interlayer conductive layer is determined such that the first-order temperature coefficient and the second-order temperature coefficient are zero.

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