Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device, comprising: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion covering the pattern portion, the width of the plate portion being greater than the width of each pattern portion in the pattern portion and the plate portion being connected to the pattern portion; a lower structure between the first substrate and the second substrate; horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked at intervals in a direction perpendicular to the upper surface of the second substrate; and a vertical structure on the second substrate and having side surfaces opposite to the horizontal conductive patterns.

Description

[0001] Cross-reference to Related Applications

[0002] Korean Patent Application No. 10-2018-0101721, filed on August 29, 2018, entitled "Three-Dimensional Semiconductor Device", is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to three-dimensional semiconductor devices. Background Art

[0004] In order to improve the price competitiveness of products, it is necessary to continuously increase the integration degree of semiconductor devices. Summary of the Invention

[0005] Embodiments relate to a three-dimensional semiconductor device, including: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion covering the pattern portion, the width of the plate portion being greater than the width of each pattern portion in the pattern portion and the plate portion being connected to the pattern portion; a lower structure between the first substrate and the second substrate; horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked at intervals in a direction perpendicular to the upper surface of the second substrate; and a vertical structure on the second substrate having side surfaces opposite to the horizontal conductive patterns.

[0006] Embodiments also relate to a three-dimensional semiconductor device, including: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion in contact with and covering the pattern portion; a lower structure between the first substrate and the second substrate; and an upper structure on the second substrate. The lower structure may include peripheral wirings, the plate portion may include a semiconductor layer, and the width of the plate portion may be greater than the width of each pattern portion in the pattern portion.

[0007] Embodiments also relate to a three-dimensional semiconductor device, including: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion connected to and covering the pattern portion; a lower structure including peripheral wirings between the first substrate and the second substrate; horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked at intervals in a direction perpendicular to the upper surface of the second substrate; and a vertical structure on the second substrate having side surfaces opposite to the horizontal conductive patterns. The pattern portion may have a linear shape, and the plate portion may include a semiconductor layer. Brief Description of the Drawings

[0008] The features will become clear to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1A A schematic block diagram of a semiconductor device according to an exemplary embodiment is shown;

[0010] Figure 1B A conceptual circuit diagram of a memory array region of a semiconductor device according to an exemplary embodiment is shown;

[0011] Figure 2 A schematic perspective view of an example of a three-dimensional semiconductor device according to an exemplary embodiment is shown;

[0012] Figure 3A and Figure 3B A plan view of a part of a three-dimensional semiconductor device according to an exemplary embodiment is shown;

[0013] Figure 4 Shows along Figure 3A and Figure 3B A schematic cross-sectional view of the region taken along line I-I';

[0014] Figure 5 Shows along Figure 3A and Figure 3B A schematic cross-sectional view of the region taken along line II-II';

[0015] Figure 6A A partially enlarged cross-sectional view of a part of a modified example of a three-dimensional semiconductor device according to an exemplary embodiment is shown;

[0016] Figure 6B A partially enlarged cross-sectional view of a part of a modified example of a three-dimensional semiconductor device according to an exemplary embodiment is shown;

[0017] Figure 7 Shows Figure 5 A partially enlarged cross-sectional view of the enlarged region indicated by 'B' in;

[0018] Figure 8A Shows Figure 5 A partially enlarged cross-sectional view of the enlarged region indicated by 'C' in;

[0019] Figure 8B A partially enlarged cross-sectional view of a modified example of a three-dimensional semiconductor device according to an exemplary embodiment is shown;

[0020] Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C and Figure 12A and Figure 12B ShowsFigure 4 Partial enlarged cross-sectional view of a modified example of the portion indicated by 'A';

[0021] Figure 13 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0022] Figure 14A and Figure 14B Partial enlarged cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0023] Figure 15 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0024] Figure 16 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0025] Figures 17 to 21 Plan view showing various modified examples of a three-dimensional semiconductor device according to an exemplary embodiment;

[0026] Figure 22 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0027] Figure 23 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment;

[0028] Figure 24 Cross-sectional view showing a modified example of a three-dimensional semiconductor device according to an exemplary embodiment; and

[0029] Figures 25 to 29 Cross-sectional view showing an example of a method for forming a three-dimensional semiconductor device according to an exemplary embodiment. Detailed Description

[0030] Figure 1A is a schematic block diagram showing a semiconductor device according to an exemplary embodiment.

[0031] Reference Figure 1A , a semiconductor device 1 according to an exemplary embodiment may include a memory array region MA, a row decoder 3, a page buffer 4, a column decoder 5, and a control circuit 6. The memory array region MA may include memory blocks BLK.

[0032] The memory array region MA may include memory cells arranged in a plurality of rows and a plurality of columns. The memory cells included in the memory array region MA may be electrically connected to the row decoder 3 through word lines WL, at least one common source line CSL, string selection lines SSL, and at least one ground selection line GSL, and may be electrically connected to the page buffer 4 and the column decoder 5 through bit lines BL.

[0033] In an exemplary embodiment, among the memory cells, the memory cells arranged in a common row may be connected to a single word line WL, and the memory cells arranged in a common column may be connected to a single bit line BL.

[0034] The row decoder 3 may generally be connected to the memory block BLK, and may provide a driving signal to the word lines WL of the memory block BLK selected according to the block selection signal. For example, the row decoder 3 may receive address information ADDR from an external source, and may decode the received address information ADDR to determine the voltages provided to at least a part of the word lines WL, the common source line CSL, the string selection lines SSL, and the ground selection lines GSL electrically connected to the memory block BLK.

[0035] The page buffer 4 may be electrically connected to the memory array region MA through the bit lines BL. The page buffer 4 may be connected to the bit lines BL selected according to the address decoded by the column decoder 5. The page buffer 4 may temporarily store the data to be stored in the memory cells, or may sense the data stored in the memory cells according to the operation mode. For example, the page buffer 4 may operate as a write driver circuit during the programming operation mode, and may operate as a sense amplifier circuit during the read operation mode. The page buffer 4 may receive power (e.g., voltage or current) from the control logic, and may provide power to the selected bit lines BL.

[0036] The column decoder 5 may provide a data transmission path between the page buffer 4 and an external device (e.g., a memory controller). The column decoder 5 may decode the address input from an external source, and thus may select one bit line BL among the bit lines BL.

[0037] The column decoder 5 may generally be connected to the memory block BLK, and may provide data information to the bit lines BL of the memory block BLK selected according to the block selection signal.

[0038] The control circuit 6 can control the overall operation of the semiconductor device 1. The control circuit 6 can receive a control signal and an external voltage, and can operate according to the received control signal. The control circuit 6 can include: a voltage generator for generating a voltage required for internal operation (e.g., a programming voltage, a read voltage, an erase voltage, etc.) using the external voltage. The control circuit 6 can control a read operation, a write operation, and / or an erase operation in response to the control signal.

[0039] Figure 1B is a conceptual circuit diagram showing the memory array region ( Figure 1A MA in).

[0040] Referring to Figure 1A and Figure 1B , the semiconductor device according to the exemplary embodiment can include a common source line CSL, bit lines BL, and a plurality of cell strings CSTR between the common source line CSL and the bit lines BL. The common source line CSL, the bit lines BL, and the plurality of cell strings CSTR can be disposed in the memory array region MA.

[0041] The plurality of cell strings CSTR can be connected in parallel to each bit line BL. The plurality of cell strings CSTR can be commonly connected to the common source line CSL. Each cell string CSTR in the plurality of cell strings CSTR can include a lower select transistor GST, a memory cell MCT, and an upper select transistor SST connected in series.

[0042] The memory cell MCT can be connected in series between the lower select transistor GST and the upper select transistor SST. Each memory cell MCT can include a data storage region capable of storing data.

[0043] The upper select transistor SST can be electrically connected to the bit line BL, and the lower select transistor GST can be electrically connected to the common source line CSL.

[0044] The upper select transistor SST can be provided as a plurality of upper select transistors and can be controlled by a string select line SSL. The memory cell MCT can be controlled by a plurality of word lines WL.

[0045] The lower select transistor GST can be controlled by a ground select line GSL. The common source line CSL can be commonly connected to the source of the ground select transistor GST.

[0046] In the example, the upper select transistor SST can be a string select transistor, and the lower select transistor GST can be a ground select transistor.

[0047] Figure 2 is a schematic perspective view showing an example of a three-dimensional semiconductor device according to an exemplary embodiment.

[0048] Reference Figure 2 Referring to Figure 2 , the three-dimensional semiconductor device 1 according to the exemplary embodiment may include a first substrate 10, a lower structure 50 on the first substrate 10, a second substrate 60 on the lower structure 50, and an upper structure 100 on the second substrate 60.

[0049] The first substrate 10 may be a semiconductor substrate, which may be formed of a semiconductor material such as silicon. For example, the first substrate 10 may be a single-crystalline semiconductor substrate, such as a single-crystalline silicon substrate. The lower structure 50 may include at least one of a row decoder 3, a page buffer 4, and a column decoder 5 as shown in Figure 1A Figure 1A .

[0050] The second substrate 60 may include a pattern portion 70 and a plate portion 80 covering the pattern portion 70. The plate portion 80 may include a semiconductor layer, such as a polycrystalline semiconductor layer. The polycrystalline semiconductor layer may include a polysilicon layer. The upper structure 100 may include a memory array region MA as described above.

[0051] Figure 3A FIG. Figure 3A is a plan view showing a part of the three-dimensional semiconductor device according to the exemplary embodiment, Figure 3B FIG. Figure 3B is a plan view showing a part of the three-dimensional semiconductor device according to the exemplary embodiment, Figure 4 FIG. Figure 4 is a schematic cross-sectional view showing a region taken along the line I-I' of Figure 3A and Figure 3B Figure 3B , and Figure 5 FIG. Figure 5 is a schematic cross-sectional view showing a region taken along the line II-II' of Figure 3A and Figure 3B Figure 3B .

[0052] Referring to Figures 3A to 5 Figures 3A to 5 , the lower structure 50 may be on the first substrate 10. As described above, the first substrate 10 may be a single-crystalline semiconductor substrate.

[0053] The lower structure 50 may include lower insulating layers 25, 35, and 45, peripheral wirings 30 and 40, and peripheral transistors PTR. Isolation regions 15i defining peripheral active regions 15a may be provided in the first substrate 10.

[0054] The peripheral transistors PTR may include: a peripheral gate PG on the peripheral active region 15a, and peripheral source / drains S / D provided in the peripheral active region 15a on both sides of the peripheral gate PG.

[0055] The peripheral wirings 30 and 40 may include a first peripheral wiring 30 electrically connected to the peripheral transistors PTR and a second peripheral wiring 40 electrically connected to the first peripheral wiring 30.

[0056] The lower insulating layers 25, 35, and 45 may include: a first lower insulating layer 25 surrounding the side surface of the first peripheral wiring 30; a second lower insulating layer 35 on the first lower insulating layer 25 and surrounding the side surface of the second peripheral wiring 40; and a third lower insulating layer 45 on the second lower insulating layer 35. The lower insulating layers 25, 35, and 45 may include silicon oxide.

[0057] The peripheral transistors PTR and the peripheral wirings 30 and 40 may be configured as Figure 1A at least one of the peripheral circuits of the row decoder 3, page buffer 4, and column decoder 5 shown.

[0058] The second substrate 60 may be on the lower structure 50. The lower structure 50 may be between the first substrate 10 and the second substrate 60. The second substrate 60 may include a pattern portion 70 and a plate portion 80 connected to the pattern portion 70. The plate portion 80 may have a width greater than the width of each pattern portion 70 and may be connected to the pattern portion 70. The plate portion 80 may be in contact with the pattern portion 70.

[0059] In an example, the second substrate 60 may further include a connection portion ( Figure 3A 62) connecting the pattern portions 70. The pattern portions 70 may have a linear shape, and the connection portion 62 may connect the pattern portions 70 having a linear shape. The pattern portions 70 and the connection portion 62 may have an integral structure.

[0060] In an example, the third lower insulating layer 45 may have a recessed region 45r, and the pattern portion 70 may fill the recessed region 45r. Thus, the bottom surface and side surface of the pattern portion 70 may be covered by the third lower insulating layer 45.

[0061] The plate portion 80 may include a semiconductor layer. For example, the plate portion 80 may include a polysilicon layer.

[0062] The intermediate insulating layer 90 may be on the side surface of the plate portion 80.

[0063] The stacked structure 170 may be on the plate portion 80.

[0064] The stacked structure 170 may include an interlayer insulating layer 110 and a horizontal conductive pattern 160. The horizontal conductive patterns 160 may be stacked on the second substrate 60 while being spaced apart from each other in the vertical direction Z perpendicular to the upper surface 80s of the second substrate 60. The interlayer insulating layer 110 and the horizontal conductive patterns 160 may be stacked repeatedly and alternately. The interlayer insulating layer 110 may be formed of silicon oxide. The horizontal conductive pattern 160 may be a gate pattern.

[0065] The horizontal conductive pattern 160 may include a lower horizontal conductive pattern 160L, an upper horizontal conductive pattern 160U, and an intermediate horizontal conductive pattern 160M between the lower horizontal conductive pattern 160L and the upper horizontal conductive pattern 160U. The lower horizontal conductive pattern 160L may be a lower gate pattern, the upper horizontal conductive pattern 160U may be an upper gate pattern, and the intermediate horizontal conductive pattern 160M may be an intermediate horizontal gate pattern.

[0066] The horizontal conductive pattern 160 is stacked in the first region A1 on the second substrate 60 and is spaced apart from each other in the direction Z perpendicular to the upper surface 80s of the second substrate 60, and may include a pad region P that extends from the first region A1 to the inside of the second region A2 and is arranged in a stepped shape. In an exemplary embodiment, the pad region P may be modified into various forms.

[0067] In an exemplary embodiment, the first region A1 may be a memory array region ( Figure 1A and Figure 1B MA of Figure 1A and Figure 1B ), or a region where the memory array region ( Figure 1A and Figure 1B MA of

[0068] is located. Accordingly, the first region A1 may be referred to as the "memory array region MA".

[0069] In an exemplary embodiment, the second region A2 may be located on one or both sides of the first region A1. The second region A2 may be a region where the pad region P is provided, where the horizontal conductive pattern 160 extends from the first region A1 and is arranged in a stepped shape. The second region A2 may be referred to as an "extended region" or a "stepped region".

[0069] In an example, the lower horizontal conductive pattern 160L may include a ground selection line GSL as shown in Figure 1A and Figure 1B .

[0070] In an example, the upper horizontal conductive pattern 160U may include a string selection line SSL as shown in Figure 1A and Figure 1B .

[0071] In an example, the intermediate horizontal conductive pattern 160M may include a word line WL as shown in Figure 1A and Figure 1B .

[0072] The upper insulating layer 115 may be on the second substrate 60 and the intermediate insulating layer 90. The upper insulating layer 115 may cover the pad region P of the horizontal conductive pattern 160.

[0073] The first covering insulating layer 150 and the second covering insulating layer 185 may be sequentially on the stacked structure 170 and the upper insulating layer 115. The upper insulating layer 115, and the first covering insulating layer 150 and the second covering insulating layer 185 may include silicon oxide.

[0074] In the first region A1, a vertical structure 120 passing through the stacked structure 170 may be provided. The vertical structure 120 may have side surfaces opposite to the horizontal conductive pattern 160. At least a part of the vertical structure 120 may be a channel.

[0075] A separation structure 175 passing through the stacked structure 170 may be provided. The height of the upper surface of the separation structure 175 may be higher than the height of the vertical structure 120. The separation structure 175 may pass through the stacked structure 170, may extend upward, and may pass through the first covering insulating layer 150. The separation structure 175 may be provided in a separation trench 155 passing through the first covering insulating layer 150 and the stacked structure 170.

[0076] The separation structure 175 may have a linear shape extending in a first direction X. The first direction X may be a direction parallel to the upper surface 80s of the second substrate 60.

[0077] In an example, when observed in a plan view, the separation structure 175 may cross the stacked structure 170.

[0078] The bit line 195, the gate connection wiring 196, and the peripheral connection wiring 198 may be on the second covering insulating layer 185.

[0079] Between the bit line 195 and the vertical structure 120, a bit line contact plug 190 electrically connecting the bit line 195 to the vertical structure 120 may be provided.

[0080] The gate contact structure 180 electrically connected to the horizontal conductive pattern 160 may be on the pad region P of the horizontal conductive pattern 160.

[0081] Between the gate connection wiring 196 and the gate contact structure 180, a gate contact plug 192 electrically connecting the gate connection wiring 196 to the gate contact structure 180 may be provided.

[0082] The peripheral contact structure 182 may be on the peripheral contact region 40P of the second peripheral wiring 40. The peripheral contact structure 182 may pass through the third lower insulating layer 45, the intermediate insulating layer 90, the upper insulating layer 115, and the first covering insulating layer 150.

[0083] Between the peripheral connection wiring 198 and the peripheral contact structure 182, a peripheral contact plug 194 electrically connecting the peripheral connection wiring 198 to the peripheral contact structure 182 may be provided.

[0084] In the example, in the second substrate 60, the end 80' of the plate portion 80 may have a form protruding compared to the end 70' of the pattern portion 70. Various examples of the end of the plate portion 80 and the end of the pattern portion 70 will be respectively referred to Figure 6A and Figure 6B to describe various examples of the end of the plate portion 80 and the end of the pattern portion 70.

[0085] Figure 6A and Figure 6B are partial enlarged cross-sectional views showing the end of the plate portion 80 and the end of the pattern portion 70.

[0086] In a modified example, referring to Figure 6A the end 70a' of the pattern portion 70 may have a form protruding compared to the end 80' of the plate portion 80.

[0087] In a modified example, referring to Figure 6B the end 70b' of the pattern portion 70 may be vertically aligned with the end 80' of the plate portion 80.

[0088] Referring again to Figures 3A to 5 each of the above vertical structures 120 may include a vertical structure, and each of the above horizontal conductive patterns 160 may include different material layers. Examples of the above vertical structures 120 and horizontal conductive patterns 160 will be described with reference to Figure 7 Examples of the above vertical structures 120 and horizontal conductive patterns 160 will be described.

[0089] Figure 7 is a partial enlarged cross-sectional view showing the enlarged portion indicated by 'B' in Figure 5 .

[0090] Referring to Figures 3A to 5 and Figure 7 each vertical structure 120 may include a channel semiconductor layer 140 and a gate dielectric structure 130 between the channel semiconductor layer 140 and the stacked structure 170.

[0091] In the example, each vertical structure 120 may further include a semiconductor pattern 125, an insulating core pattern 145 on the semiconductor pattern 125, and a pad pattern 147 on the insulating core pattern 145.

[0092] The channel semiconductor layer 140 can be arranged to surround the outer surface of the insulating core pattern 145 while being in contact with the semiconductor pattern 125. The gate dielectric structure 130 can be arranged to surround the outer surface of the channel semiconductor layer 140. The semiconductor pattern 125 can be an epitaxial material layer that can be formed by using a selective epitaxial growth (SEG) process. The insulating core pattern 145 can be formed of an insulating material (e.g., silicon oxide, etc.). The pad pattern 147 can be formed of polysilicon having N-type conductivity and can be a drain region. The pad pattern 147 can be on a horizontal plane that is higher in height ratio than the height of the horizontal conductive pattern 160U. As described above, the pad pattern 147 of the vertical structure 120 can be in contact with the bit line contact plug 190 and can be electrically connected thereto.

[0093] In an example, the channel semiconductor layer 140 can pass through the horizontal conductive pattern 160. When the vertical structure 120 further includes the semiconductor pattern 125, the semiconductor pattern 125 can pass through the lower horizontal conductive pattern 160L, and the channel semiconductor layer 140 can pass through the intermediate horizontal conductive pattern 160M and the upper horizontal conductive pattern 160U. The channel semiconductor layer 140 can be formed of a polysilicon layer.

[0094] In an example, the semiconductor pattern 125 can be referred to as the channel semiconductor layer. For example, the semiconductor pattern 125 can be referred to as the lower channel semiconductor layer, which is located in a relatively lower portion, while the channel semiconductor layer 140 can be referred to as the upper channel semiconductor layer, which is located in a relatively upper portion.

[0095] In an example, additional dielectric 158 can also be included between the semiconductor pattern 125 and the lower horizontal conductive pattern 160L. The additional dielectric 158 can include silicon oxide.

[0096] The gate dielectric structure 130 can include a tunnel dielectric layer 136, a data storage layer 134, and a blocking dielectric layer 132. The data storage layer 134 can be between the tunnel dielectric layer 136 and the blocking dielectric layer 132. The blocking dielectric layer 132 can be between the data storage layer 134 and the stacked structure 170.

[0097] The tunnel dielectric layer 136 can be between the data storage layer 134 and the channel semiconductor layer 140. The tunnel dielectric layer 136 can include silicon oxide and / or silicon oxide doped with impurities. The blocking dielectric layer 132 can include silicon oxide and / or a high-k dielectric material. The data storage layer 134 can be formed of a material that can store data, such as silicon nitride.

[0098] The data storage layer 134 can be between the channel semiconductor layer 140 and the intermediate horizontal conductive pattern 160M (the intermediate horizontal conductive pattern 160M can include a word line WL, asFigure 1A and Figure 1B There is a region for storing data between them as shown. For example, depending on the operating conditions of a non-volatile memory device such as a flash memory device, electrons injected from the channel semiconductor layer 140 through the tunnel dielectric layer 136 into the data storage layer 134 can be captured to retain the electrons, or the electrons captured in the data storage layer 134 can be erased.

[0099] Thus, as described above, the region of the data storage layer 134 located between the intermediate-level conductive pattern 160M (which can be a word line ( Figure 1A and Figure 1B of the WL)) and the channel semiconductor layer 140 can be defined as a data storage region, and the data storage region can configure Figure 1B the memory cells ( Figure 1B of the MCT) shown.

[0100] Each horizontal conductive pattern 160 may include a first material layer 162 and a second material layer 164 that are different from each other. In an example, the first material layer 162 may be a high-k dielectric material such as alumina, while the second material layer 164 may be formed of a conductive material including, for example, one or two or more of metal nitrides (e.g., TiN or WN), metals (e.g., W), metal silicides (e.g., TiSi or WSi), and doped silicon. In another example, the first material layer 162 and the second material layer 164 may be formed of different conductive materials. The first material layer 162 may extend between the second material layer 164 and the vertical structure 120 while covering the upper and lower surfaces of the second material layer 164.

[0101] Figure 8A is a partial enlarged cross-sectional view showing the enlarged region indicated by 'C' in Figure 5 .

[0102] Referring to Figures 3A to 5 and Figure 8A , each horizontal conductive pattern 160 may include a first material layer 162 and a second material layer 164 as described with reference to Figure 7 . The first material layer 162 may cover the upper and lower surfaces of the second material layer 164, while the second material layer 164 may be in direct contact with the separation structure 175.

[0103] In an example, the separation structure 175 may be formed of an insulating material such as silicon oxide that fills the separation trench 155. Modified examples of the separation structure 175 will be described with reference to Figure 8B .

[0104] Figure 8B is a view showing Figure 5Partial enlarged cross-sectional view of the enlarged area indicated by 'C'.

[0105] In the modification example, referring to Figure 8B , each separation structure 175 may include a separation spacer 176 and a separation core pattern 178. The separation spacer 176 may include an insulating material such as silicon oxide. The separation core pattern 178 may be formed of a conductive material including, for example, one or two or more of metal nitride (e.g., TiN or WN), metal (e.g., W), metal silicide (e.g., TiSi or WSi), and doped silicon.

[0106] Referring again to Figures 3A to 5 , the plate portion 80 and the pattern portion 70 of the second substrate 60 may be in direct contact with each other and may be formed of different materials. The plate portion 80 may include a semiconductor layer, and the pattern portion 70 may be formed of one or two or more of an insulating material, a doped semiconductor material, and a metal material.

[0107] In the example, the pattern portion 70 may be formed of silicon nitride, and the plate portion 80 may be formed of a semiconductor layer.

[0108] In another example, the pattern portion 70 may be formed of polysilicon, and the plate portion 80 may be formed of a semiconductor layer that forms an interface with the pattern portion 70.

[0109] Next, referring to Figures 9A to 12B , various examples of the second substrate 60 will be described. Figures 9A to 12B shows the Figure 4 Partial enlarged cross-sectional view of the enlarged area indicated by 'A'.

[0110] In the example, referring to Figure 9A , the second substrate 60a may include a pattern portion 70a and a plate portion 80a on the pattern portion 70a. The plate portion 80a may be formed of a semiconductor layer, such as a doped polysilicon layer. For example, the plate portion 80a may be formed of a polysilicon layer having N-type conductivity.

[0111] The second substrate 60a may further include a barrier layer 64 covering the side surface and the bottom surface of the pattern portion 70a. The barrier layer 64 may be formed of a conductive barrier layer such as Ti / TiN, while the pattern portion 70a may be formed of a metal material such as tungsten, the resistance of which is lower than that of the semiconductor layer of the plate portion 80a. Therefore, the second substrate 60a may include a pattern portion 70a having a low resistance and a plate portion 80a having semiconductor characteristics. The above second substrate 60a can improve the electrical characteristics of the three-dimensional semiconductor device.

[0112] In the modification example, referring to Figure 9B, the second substrate 60b may include a pattern portion 70b, a barrier layer 64 covering side and bottom surfaces of the pattern portion 70b, and a plate portion 80b on the pattern portion 70b. The pattern portion 70b and the barrier layer 64 may be the same as the pattern portion 70a and the barrier layer 64 described with reference to Figure 9A .

[0113] The plate portion 80b may include a first plate layer 80b1 and a second plate layer 80b2 on the first plate layer 80b1.

[0114] The second plate layer 80b2 may be a semiconductor layer. For example, the second plate layer 80b2 may be formed of a doped polysilicon layer. For example, the second plate layer 8062 may be formed of a polysilicon layer having N-type conductivity.

[0115] The first plate layer 80b1 may be formed of a material capable of improving electrical characteristics by increasing adhesion between the second plate layer 80b2 and the pattern portion 70b or by reducing resistance between the second plate layer 80b2 and the pattern portion 70b. For example, the first plate layer 80b1 may include a metal silicide (e.g., WSi or TiSi) and / or a metal nitride (e.g., TiN or TiSiN).

[0116] In a modified example, with reference to Figure 9C , the second substrate 60c may include a pattern portion 70c and a plate portion 80c on the pattern portion 70c, while the pattern portion 70c and the plate portion 80c may have an integral structure. For example, the pattern portion 70c and the plate portion 80c may be formed of a semiconductor layer. For example, the pattern portion 70c and the plate portion 80c may be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

[0117] In a modified example, with reference to Figure 10A , the second substrate 60d may include a pattern portion 70d and a plate portion 80d on the pattern portion 70d. The plate portion 80d may include a first plate layer 80d1 and a second plate layer 80d2 on the first plate layer 80d1.

[0118] The first plate layer 80d1 may have an integral structure with the pattern portion 70d. Thus, the first plate layer 80d1 and the pattern portion 70d may be continuously connected to each other without a boundary and may be formed of the same material.

[0119] In an example, the first plate layer 80d1 and the pattern portion 70d may be formed of an insulating material (e.g., silicon nitride).

[0120] In another example, the first plate layer 80d1 and the pattern portion 70d may be formed of a conductive material (e.g., doped silicon or a metal material such as tungsten).

[0121] The second plate layer 80d2 may be a semiconductor layer. For example, the second plate layer 80d2 may be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

[0122] In a modified example, referring to Figure 10B , the second substrate 60e may include a pattern portion 70e and a plate portion 80e on the pattern portion 70e. The plate portion 80e may include a first plate layer 80e1 and a second plate layer 80e2 on the first plate layer 80e1.

[0123] The first plate layer 80e1 may have an integral structure with the pattern portion 70e. For example, the first plate layer 80e1 and the pattern portion 70e may be formed of a conductive material.

[0124] The second plate layer 80e2 may be formed of a semiconductor layer. For example, the second plate layer 80e2 may be formed of a semiconductor layer having N-type conductivity (e.g., polysilicon).

[0125] The second substrate 60e may further include a conduction blocking layer 65 that extends between the first plate layer 80e1 and the lower structure 50 while covering the side surface and the bottom surface of the pattern portion 70e. The conduction blocking layer 65 may be formed of a conductive material such as Ti / TiN or the like.

[0126] In a modified example, referring to Figure 10C , the second substrate 60f may include a pattern portion 70f, a plate portion 80f on the pattern portion 70f, and a blocking layer 65 that extends between the plate portion 80f and the lower structure 50 while covering the side surface and the bottom surface of the pattern portion 70f.

[0127] The plate portion 80f may include a first plate layer 80f1, a second plate layer 80f2 on the first plate layer 80f1, and an additional conductive layer 81 located between the first plate layer 80f1 and the second plate layer 80f2.

[0128] The first plate layer 80f1 and the pattern portion 70f may have an integral structure. For example, the first plate layer 80f1 and the pattern portion 70f may be formed of a conductive material such as tungsten. The second plate layer 80f2 may be formed of a semiconductor layer. The additional conductive layer 81 may be formed of a material that can increase the adhesion between the first plate layer 80f1 and the second plate layer 80f2 or improve the electrical characteristics by reducing the resistance between the first plate layer 80f1 and the second plate layer 80f2. For example, the additional conductive layer 81 may include one or two or more of metal silicides (e.g., WSi or TiSi), metal nitrides (e.g., WN, TiN, or TiSiN), and metals (e.g., Ti).

[0129] In a modified example, referring to Figure 11A, the second substrate 60g may include a pattern portion 70g and a plate portion 80g on the pattern portion 70g. Each pattern portion 70g may include a first pattern portion 70g1 and a second pattern portion 70g2 on the first pattern portion 70g1.

[0130] The plate portion 80g may have an integral structure that is continuously connected to the second pattern portion 70g2 without a boundary. Thus, the plate portion 80g and the second pattern portion 70g2 may be formed of the same material, for example, a semiconductor layer. The plate portion 80g may be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

[0131] In an example, the first pattern portion 70g1 may be formed of an insulating material (e.g., silicon nitride).

[0132] In another example, the first pattern portion 70g1 may be formed of a conductive material, such as a metal nitride such as TiN and / or a metal such as W.

[0133] In a modified example, referring to Figure 11B , the second substrate 60h may include a pattern portion 70h and a plate portion 80h on the pattern portion 70h. Each pattern portion 70h may include a first pattern portion 70h1 and a second pattern portion 70h2 on the first pattern portion 70h1.

[0134] The second substrate 60h may further include a barrier layer 64 covering the side and bottom surfaces of the first pattern portion 70h1.

[0135] The plate portion 80h may have an integral structure that is continuously connected to the second pattern portion 70h2 without a boundary. The plate portion 80h may be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

[0136] The first pattern portion 70h1 may be formed of a metal such as W, and the barrier layer 64 may be formed of a conductive material such as Ti / TiN.

[0137] In a modified example, referring to Figure 11C , the second substrate 60i may include a pattern portion 70i and a plate portion 80i on the pattern portion 70i. Each pattern portion 70i may include a first pattern portion 70i1 and a second pattern portion 70i2 on the first pattern portion 70i1.

[0138] The plate portion 80i may have an integral structure that is continuously connected to the second pattern portion 70i2 without a boundary. The plate portion 80i may be formed of a semiconductor layer having N-type conductivity or P-type conductivity.

[0139] The second substrate 60i may further include a barrier layer 64 covering side and bottom surfaces of the first pattern portion 70i1. The barrier layer 64 may be formed of a conductive material such as Ti / TiN or the like.

[0140] The second substrate 60i may further include an additional conductive layer 75 extending between the plate portion 80i and the lower structure 50 while covering side and bottom surfaces of the second pattern portion 70i2. The additional conductive layer 75 may include one or two or more of metal silicide (e.g., WSi or TiSi), metal nitride (e.g., WN, TiN, or TiSiN), and metal (e.g., Ti).

[0141] In a modified example, referring to Figure 12A , as described above, the second substrate 60 may include a pattern portion 70 and a plate portion 80 on the pattern portion 70.

[0142] The third interlayer insulating layer 45 of the lower structure 50 may include a lower insulating portion 45a and an upper insulating portion 45b. The lower insulating portion 45a may be disposed below the lower surface of the pattern portion 70, and the upper insulating portion 45b may be between side surfaces of the pattern portion 70.

[0143] In a modified example, referring to Figure 12B , the second substrate 60j may include a pattern portion 70, a plate portion 80 on the pattern portion 70, and a barrier layer 64' covering the lower surface of the pattern portion 70.

[0144] The third interlayer insulating layer 45 of the lower structure 50 may include a lower insulating portion 45a and an upper insulating portion 45b. The upper insulating portion 45b may cover side surfaces of the barrier layer 64' and the pattern portion 70 stacked in sequence, and the lower insulating portion 45a may be disposed below the barrier layer 64'.

[0145] Next, referring to Figure 13 , a modified example of a three-dimensional semiconductor device according to an exemplary embodiment will be described.

[0146] Referring to Figure 13 , as described above, the lower structure 50 may be on the first substrate 10, and the second substrate 60k may be on the lower structure 50. The first substrate 10 may be a semiconductor substrate, and the lower structure 50 may include peripheral transistors PTR, peripheral wirings 30 and 40, and first to third lower insulating layers 25, 35, and 45, as described above. On the second substrate 60k, a stacked structure 170, a vertical structure 120, and bit lines 195 described with reference to Figures 3A to 5 may be disposed.

[0147] The second substrate 60k may include a pattern portion 70k and a plate portion 80k.

[0148] In the example, the plate portion 80k can cover the upper surface and the side surface of the pattern portion 70k.

[0149] In the example, the plate portion 80k can include a polycrystalline semiconductor layer. For example, the plate portion 80k can be formed of a polysilicon layer having N-type conductivity or P-type conductivity.

[0150] In the example, the pattern portion 70k can be formed of an insulating material (e.g., silicon nitride). In another example, the pattern portion 70k can include a conductive material, such as a metal nitride such as TiN and / or a metal such as W.

[0151] As described above, reference will be made to Figure 14A and Figure 14B to describe various modified examples of the pattern portion 70k and the plate portion 80k that covers the upper surface and the side surface of the pattern portion 70k. Figures 14A to 14B is a partial enlarged cross-sectional view showing the enlarged region indicated by 'A' in Figure 13 the.

[0152] In the modified example, referring to Figure 14A , the second substrate 601 can include a pattern portion 701 and a plate portion 801. The second substrate 601 can also include a barrier layer 66 disposed below the pattern portion 701. The plate portion 801 can cover the upper surface of the pattern portion 701 while covering the side surfaces of the barrier layer 66 and the pattern portion 701 that are sequentially stacked. The barrier layer 66 can be formed of a conductive material such as Ti / TiN.

[0153] In the modified example, referring to Figure 14B , the second substrate 60m can include a pattern portion 70m and a plate portion 80m. The second substrate 60m can also include a barrier layer 66 disposed below the pattern portion 70m and an additional conductive layer 76 inserted between the pattern portion 70m and the plate portion 80m and extending between the plate portion 80m and the lower structure 50. The additional conductive layer 76 can include one or two or more of a metal silicide (e.g., WSi or TiSi), a metal nitride (e.g., WN, TiN, or TiSiN), and a metal (e.g., Ti).

[0154] Next, referring to Figure 15 and Figure 16 , modified examples of a three-dimensional semiconductor device according to an example embodiment will be described. Figure 15 and Figure 16 are schematic cross-sectional views showing a region taken along the line I-I' of Figure 3A and Figure 3B the.

[0155] In the modified example, referring toFigure 15 , the lower structure 50 may be on the first substrate 10 as described above. The second substrate 260a including the pattern portion 270a and the plate portion 280a connected to the pattern portion 270a and covering the upper surface of the pattern portion 270a may be on the lower structure 50.

[0156] The second substrate 260a may be the same as the second substrate 60 described with reference to Figures 3A to 5 . In addition, according to the various modification examples described with reference to Figures 9A to 12B , the second substrate 260a may be modified to the second substrates 60a to 60j. Therefore, the second substrate 260a may be understood to be the same as those second substrates described with reference to Figures 3A to 12B , and thus its detailed description will not be repeated.

[0157] The stacked structure 270 may be on the second substrate 260a. The stacked structure 270 may include an interlayer insulating layer 210 and a horizontal conductive pattern 260 stacked alternately and repeatedly.

[0158] The first covering insulating layer 250 and the second covering insulating layer 285 stacked in sequence may be on the stacked structure 270. The separation structure 275 may be disposed in the separation trench 255 passing through the first covering insulating layer 250 and the stacked structure 270. The separation structure 275 may be formed of an insulating material such as silicon oxide.

[0159] The vertical structure 220v passing through the stacked structure 270 may be provided.

[0160] Each vertical structure 220v may include an insulating core pattern 245 passing through the stacked structure 270, a channel semiconductor layer 240 surrounding the outer surface of the insulating core pattern 245, a gate dielectric structure 230 surrounding the outer surface of the channel semiconductor layer 240, and a pad pattern 247 on the channel semiconductor layer 240 and the insulating core pattern 245. The channel semiconductor layer 240, the insulating core pattern 245, and the pad pattern 247 may be formed of the same materials as the channel semiconductor layer 140, the insulating core pattern 145, and the pad pattern 147 described with reference to Figure 7 . In an example, the gate dielectric structure 230 may be formed of the same materials and structure as the gate dielectric structure 130 described with reference to Figure 7 .

[0161] The vertical structure 220v may include a first vertical structure 220vl and a second vertical structure 220v2 located on both sides of the separation structure 275.

[0162] A horizontal connection structure 220h can be provided, which extends from the first vertical structure 220v1 and the second vertical structure 220v2 and is provided in the plate portion 280a of the second substrate 260a located below the separation structure 275. The gate dielectric structure 230, the channel semiconductor layer 240, and the insulating core pattern 245 of the first vertical structure 220v1 and the second vertical structure 220v2 extend downward from the first vertical structure 220v1 and the second vertical structure 220v2 to below the separation structure 275, so that the horizontal connection structure 220h can be provided.

[0163] The plate portion 280a can be formed of a semiconductor layer having N-type conductivity, for example, polysilicon having N-type conductivity. The plate portion 280a can be a back gate electrode.

[0164] The source line 284 can be on the first cover insulation layer 250. A source contact plug 282 for electrically connecting the source line 284 to the second vertical structure 220v2 can be between the source line 284 and the second vertical structure 220v2.

[0165] The bit line 295 can be on the second cover insulation layer 285. A bit line contact plug 290 for electrically connecting the bit line 295 to the first vertical structure 220v1 can be between the bit line 295 and the first vertical structure 220v1.

[0166] In the modification example, referring to Figure 16 , the lower structure 50 can be on the first substrate 10, as described above. The second substrate 260b including the pattern portion 270b and the plate portion 280b connected to the pattern portion 270b and covering the upper surface and the side surface of the pattern portion 270b can be on the lower structure 50.

[0167] The second substrate 260b can be the same as the second substrate 60k described with reference to Figure 13 . In addition, according to various modification examples described with reference to Figure 14A and Figure 14B , the second substrate 260b can be modified to the second substrates 601 and 60m. Therefore, the second substrate 260b can be understood to be the same as those second substrates described with reference to Figures 13 to 14B , and thus its detailed description will not be repeated.

[0168] On the second substrate 260b, as described with reference to Figure 15 , a stacked structure 270, a separation structure 275, a vertical structure 220v, a source line 284, and a bit line 295 can be provided.

[0169] Referring again to Figures 3A to 5, as described above, in the example, the second substrate 60 may include: a pattern portion 70 extending in the first direction X; a connection portion 62 connecting the pattern portion 70 and having an integral structure with the pattern portion 70; and a plate portion 80 overlapping the pattern portion 70 and the connection portion 62.

[0170] In the example, the pattern portion 70 and the separation structure 175 may have a linear shape extending in the same direction (e.g., the first direction X). Next, referring to Figures 17 to 21 , various modified examples of the second substrate 60 will be described. Hereinafter, when referring to Figures 17 to 21 for description, the structure on the second substrate may be the same as the structure described with reference to Figures 3A to 5 for description. Therefore, reference may be made to Figures 17 to 21 for the modified examples of the second substrate described Figure 3A therein, while reference may be made to Figures 3B to 5 for the structure on the second substrate that can be modified.

[0171] In the modified example, referring to Figure 17 , Figures 3B to 5 , the second substrate 360a may include: a pattern portion 370a having a linear shape; a connection portion 362a integrally formed with the pattern portion 370a and connecting the pattern portion 370a; and a plate portion 380a covering the pattern portion 370a and the connection portion 362a.

[0172] The pattern portion 370a and the separation structure ( Figure 3B 175 of) may have linear shapes extending in directions perpendicular to each other. For example, the separation structure 175 may have a linear shape extending in the first direction X, while the pattern portion 70 may have a linear shape extending in a second direction Y perpendicular to the first direction X. At least one of the pattern portions 370a has a linear shape extending in the first direction X. At least one of the horizontal conductive patterns ( Figure 4 160 of) has a linear shape extending in the second direction Y. The pattern portion 370a and the horizontal conductive pattern ( Figure 4 160 of) may have linear shapes extending in directions perpendicular to each other.

[0173] In the modified example, referring to Figure 18 , Figures 3B to 5 , the second substrate 360b may include: a pattern portion 370b having a linear shape: a connection portion 362b integrally formed with the pattern portion 370b and connecting the pattern portion 370b; and a plate portion 380b covering the pattern portion 370b and the connection portion 362b.

[0174] The pattern portion 370b and the separation structure ( Figure 3B 175 of) may have linear shapes that cross diagonally with each other.

[0175] In the modified example, referring to Figure 19 and Figures 3B to 5 , the second substrate 360c may include: a pattern portion 370c having a linear shape; a connection portion 362c integrally formed with the pattern portion 370c and connecting the pattern portion 370c; and a plate portion 380c covering the pattern portion 370c and the connection portion 362c.

[0176] As described above, the connection portion ( Figure 17 362a) may have a linear shape continuously connected in one direction. In another example, as Figure 19 shown, the connection portion 362c may have a bar shape extending in a direction perpendicular to the pattern portion 370c. The connection portion 362c having the bar shape may be provided as a plurality of connection portions, and the plurality of connection portions 362c may be spaced apart from each other in the first direction X and may be spaced apart from each other in the second direction Y.

[0177] In the modified example, referring to Figure 20 and Figures 3B to 5 , the second substrate 360d may include: a pattern portion 370d having a linear shape; a connection portion 362d integrally formed with the pattern portion 370d and connecting the pattern portion 370d; and a plate portion 380d covering the pattern portion 370d and the connection portion 362d. The pattern portion 370d and the connection portion 362d may be arranged in a grid shape.

[0178] In the modified example, referring to Figure 21 and Figures 3B to 5 , the second substrate 360e may include: a pattern portion 370e; a connection portion 362e integrally formed with the pattern portion 370e and connecting the pattern portion 370e; and a plate portion 380e covering the pattern portion 370e and the connection portion 362e.

[0179] The above-described pattern portions 370a to 370c may have a straight shape. In another example, as Figure 21 shown, the pattern portion 370e may have a bent shape or a curved shape.

[0180] Next, referring to Figure 22 , a modified example of a three-dimensional semiconductor device according to an exemplary embodiment will be described. Figure 22 is a cross-sectional view showing a region taken along the line II-II' of Figure 3A and Figure 3B .

[0181] Referring to Figure 22 and Figure 3A and Figure 3B andFigure 4 , as described in reference Figures 3A to 5 , the lower structure 50 may be on the first substrate 10, and the second substrate 60 may be on the lower structure 50. As described with reference to Figures 3A to 5 , the lower structure 50 may include peripheral transistors PTR, peripheral wirings 30 and 40, and first to third lower insulating layers 25, 35, and 45. Further, on the second substrate 60, there may be provided a stacked structure 170, an upper insulating layer 115, a first cover insulating layer 150, and a second cover insulating layer 185, a vertical structure 120, a gate contact structure 180, a bit line contact plug 190, a gate contact plug 192, a peripheral contact plug 194, a gate connection wiring 196, and a bit line 195 described in reference Figures 3A to 5 .

[0182] In an example, the plate portion 80 may include a semiconductor layer having N-type conductivity. Thus, the plate portion 80 may be used as a common source line CSL described in reference Figure 1A and Figure 1B . A source contact structure 183 may be on the plate portion 80, which may be the above-mentioned common source line ( Figure 1A and Figure 1B CSL). A source contact plug 193 may be on the source contact structure 183. A peripheral connection wiring 198' electrically connected to the source contact plug 193 and the peripheral contact plug 194 at the same time may be on the second cover insulating layer 185.

[0183] Therefore, the plate portion 80 may be electrically connected to the peripheral wiring 40 configuring the peripheral circuit in the lower structure 50 below the second substrate 60 through the peripheral connection wiring 198'. Modification examples in which the peripheral wiring 40 configuring the peripheral circuit in the lower structure 50 and the plate portion 80 are electrically connected to each other will be described with reference to Figure 23 and Figure 24 .

[0184] Figure 23 and Figure 24 are cross-sectional views showing the region taken along the line II-II' of Figure 3A and Figure 3B .

[0185] In the modification example, with reference to Figure 23, the plate portion 80 of the second substrate 60 described above may be a semiconductor layer having N-type conductivity, and the pattern portion 70 may be formed of a conductive material (e.g., TiN, W, doped polysilicon, etc.). A contact plug 55 may be provided which is inserted between the pattern portion 70 of the second substrate 60 and the peripheral pad regions 40P' of the peripheral wirings 30 and 40, and electrically connects the pattern portion 70 to the peripheral pad regions 40P' of the peripheral wirings 30 and 40. Accordingly, the plate portion 80 of the second substrate 60 may include a semiconductor layer having N-type conductivity, and the plate portion 80 may be used as a reference Figure 1A and Figure 1B the common source line CSL described. The plate portion 80 may be electrically connected through the contact plug 55 to the peripheral wiring 40 that configures a peripheral circuit in the lower structure 50 below the second substrate 60.

[0186] In a modified example, referring to Figure 24 , the plate portion 80 of the second substrate 60 described above may be a semiconductor layer having N-type conductivity or P-type conductivity, or may include a portion having N-type conductivity or a portion having P-type conductivity, and the pattern portion 70 may be formed of a conductive material (e.g., TiN, W, doped polysilicon, etc.) or an insulating material (e.g., SiN, etc.). In this case, the separation structure 175 may include: a separation core pattern 178 formed of a conductive material; and a separation spacer 176 on a side surface of the separation core pattern 178 and separating the separation core pattern 178 from the stacked structure 170. The separation spacer 176 may be formed of an insulating material. The separation core pattern 178 in the separation structure 175 may be electrically connected to the semiconductor layer having N-type conductivity of the plate portion 80, where the plate portion 80 may be Figure 1A and Figure 1B the common source line CSL shown in.

[0187] Next, referring to Figures 25 to 29 , an example of a method of forming a three-dimensional semiconductor device according to an exemplary embodiment will be described.

[0188] Referring to Figure 25 , peripheral transistors PTR may be formed on the first substrate 10. The first substrate 10 may be a single crystal semiconductor substrate. Forming the peripheral transistors PTR may include: forming an isolation region 15i that defines a peripheral active region 15a on the first substrate 10; forming a peripheral gate PG on the peripheral active region 15a; and forming peripheral source / drain regions S / D on both sides of the peripheral gate PG in the peripheral active region 15a.

[0189] The first lower insulating layer 25 covering the peripheral transistor PTR may be formed on the first substrate 10. The first peripheral wiring 30 electrically connected to the peripheral transistor PTR may be formed in the first lower insulating layer 25. The second lower insulating layer 35 may be formed on the first lower insulating layer 25 and the first peripheral wiring 30. The second peripheral wiring 40 electrically connected to the first peripheral wiring 30 may be formed in the second lower insulating layer 35. The third lower insulating layer 45 may be formed on the second lower insulating layer 35. The peripheral transistor PTR, the first peripheral wiring 30 and the second peripheral wiring 40, and the first to third lower insulating layers 25, 35, and 45 may form a lower structure 50. Referring to Figure 26 , the third lower insulating layer 45 may be patterned, and thus a recessed area 45r may be formed.

[0190] Referring to Figure 27 , a pattern portion 70 may be formed in the recessed area 45r. A plate portion 80 may be formed on the pattern portion 70 and the third lower insulating layer 45. The pattern portion 70 and the plate portion 80 may form a second substrate 60.

[0191] Forming the second substrate 60 may include: forming a first material layer covering the third lower insulating layer 45 while filling the recessed area 45r; exposing the third lower insulating layer 45 by planarizing the first material layer; and then forming the plate portion 80 on the third lower insulating layer 45 by performing a deposition process.

[0192] In one example, the first material layer may be formed of an insulating material.

[0193] In another example, the first material layer may be formed of a metal material.

[0194] In another example, the first material layer may be formed of a doped semiconductor layer.

[0195] In another example, before forming the first material layer, it may further include forming a conduction barrier layer ( Figure 9A 64), such as Ti / TiN, etc.

[0196] In one example, the plate portion 80 may include a semiconductor layer. For example, the plate portion 80 may include an N-type semiconductor layer or a P-type semiconductor layer.

[0197] In another example, the plate portion 80 may be provided as a first plate layer ( Figure 9B 80b1) and a second plate layer ( Figure 9B 8062) stacked in sequence.

[0198] In another example, the plate portion 80 and the pattern portion 70 may have an integrated structure.

[0199] In another example, forming the second substrate 60 may include: forming a first material layer that covers the third lower insulating layer 45 while filling the recessed region 45r; planarizing the first material layer to have a constant thickness on the third lower insulating layer 45; and forming a second material layer on the first material layer. Accordingly, the first material layer may remain on the third lower insulating layer 45 while filling the recessed region 45r. Thus, the first material layer remaining in the recessed region 45r may form a pattern portion ( Figure 10A of 70d), the first material layer remaining on the third lower insulating layer 45 may form a first plate layer ( Figure 10A of 80d1) of the plate portion 80, and the second material layer may form a second plate layer ( Figure 10A of 80d2) of the plate portion 80.

[0200] In another example, when the above-described second substrate 60 is provided, before providing the first material layer that covers the third lower insulating layer 45 while filling the recessed region 45r, it may further include forming a barrier layer ( Figure 10B of 65). Further, before forming the second material layer on the first material layer remaining on the third lower insulating layer 45, it may further include forming an additional conductive layer ( Figure 10C of 81).

[0201] In another example, after providing the first material layer that partially fills the recessed region 45r, forming the second substrate 60 may include: forming a second material layer that covers the third lower insulating layer 45 while filling the remaining region of the recessed region 45r.

[0202] In another example, forming the second substrate 60 may include: forming a pattern portion ( Figure 13 of 70k) on the lower structure 50 using a deposition and etching process, and forming a plate portion ( Figure 13 of 80k) that covers the side surfaces and the upper surface of the pattern portion ( Figure 13 of 70k).

[0203] Referring to Figure 28 , a molding structure 105 may be formed on the second substrate 60. The molding structure 105 may include an interlayer insulating layer 110 and a molding layer 116 that are alternately and repeatedly stacked. The interlayer insulating layer 110 may be formed of silicon oxide, and the molding layer 116 may be formed of a material having an etching selectivity with respect to the interlayer insulating layer 110. For example, the molding layer 116 may be formed of silicon nitride.

[0204] A vertical structure 120 may be provided to pass through the molding structure 105.

[0205] In an example, the vertical structure 120 may be a reference Figure 7The described vertical structure. For example, forming the vertical structure 120 may include: forming a hole that passes through the molded structure 105 and exposes the plate portion 80 of the second substrate 60; forming a semiconductor pattern ( Figure 7 125) that epitaxially grows from the plate portion 80 exposed by the hole; forming a gate dielectric structure ( Figure 7 130) on the sidewall of the hole on the semiconductor pattern ( Figure 7 125); forming a channel semiconductor layer ( Figure 7 140) that contacts the semiconductor pattern ( Figure 7 125) while covering the gate dielectric structure 130; forming a core pattern ( Figure 7 145) that partially fills the hole on the channel semiconductor layer 140; and forming a pad pattern 147 on the channel semiconductor layer 140 and the core pattern ( Figure 7 145).

[0206] The first covering insulating layer 150 that covers the vertical structure 120 may be formed on the molded structure 105. Separation trenches 155 that pass through the first covering insulating layer 150 and the molded structure 105 may be provided.

[0207] Referring to Figure 29 , the molded layer 116 (see Figure 28 ) exposed by the separation trenches 155 is removed to form an empty space, and a horizontal conductive pattern 160 may be formed in the empty space. Then, a separation structure 175 that fills the separation trenches 155 may be provided.

[0208] Referring again to Figures 3A to 5 , a gate contact structure 180 for the pad region P of the horizontal conductive pattern 160 and a peripheral contact structure 182 on the peripheral contact region 40P of the second peripheral wiring 40 may be provided. Then, after providing the second covering insulating layer 185, contact plugs 190, 192, and 194 are formed, and bit lines 195, gate connection wirings 196, and peripheral connection wirings 198 may be provided on the contact plugs 190, 192, and 194.

[0209] In an exemplary embodiment, the second substrate 60 may include a pattern portion 70 and a plate portion 80. The plate portion 80 may include a semiconductor layer, and the pattern portion 70 may be formed of a conductor having a lower resistance than the semiconductor layer of the plate portion 80. Thus, the pattern portion 70 may improve the electrical characteristics of the second substrate 60. For example, when the plate portion 80 includes a polysilicon layer having N-type conductivity (which may be used as a common source line CSL), the pattern portion 70 formed of tungsten or the like having a lower resistance than the polysilicon layer may contribute to improving the electrical characteristics of the common source line CSL.

[0210] In an exemplary embodiment, the second substrate 60 may include a pattern portion 70 and a plate portion 80. When a three-dimensional semiconductor device according to the exemplary embodiment is provided in the form of a semiconductor chip, or when a semiconductor process is performed in the form of a semiconductor wafer, the pattern portion 70 may help prevent warping of the three-dimensional semiconductor device including the second substrate 60. For example, in the three-dimensional semiconductor device as shown in Figure 2 when stress is generated in any one direction or three-dimensionally by an upper structure ( Figure 2 100) disposed above the second substrate 60, the pattern portion 70 of the second substrate 60 may help prevent the three-dimensional semiconductor device from warping due to the upper structure 100. According to the warping shape generated by the upper structure 100, the pattern portion 70 may be selected and provided in one of various flat shapes as shown in Figure 3A and Figures 17 to 21 .

[0211] Therefore, the pattern portion 70 and various pattern portions 70a to 70m, 270a and 270b, and 370a to 370e to be modified may be referred to as "anti-warping patterns", "stress patterns", or "support patterns".

[0212] By summarizing and reviewing, in order to improve the integration of semiconductor devices, the peripheral circuits may be on the lower substrate and the upper substrate, and the memory array region may be on the upper substrate.

[0213] As described above, the peripheral circuits, the upper substrate, and the memory cell array may be sequentially disposed on the lower substrate in the vertical direction, so that warping of the semiconductor device may be reduced or prevented.

[0214] As described above, the embodiment may provide the following three-dimensional semiconductor device, which includes a lower structure on a first substrate, a second substrate on the lower structure, and an upper structure on the second substrate. The lower structure may include peripheral circuits, and the upper structure may include a memory cell array. Therefore, the embodiment may provide a three-dimensional semiconductor device with improved integration.

[0215] The embodiment may provide a three-dimensional semiconductor device capable of preventing or significantly reducing warping. The second substrate may include a pattern portion and a plate portion covering the pattern portion. The plate portion may include a semiconductor layer. The pattern portion may prevent warping of the three-dimensional semiconductor device or may significantly reduce warping. As described above, a three-dimensional semiconductor device capable of preventing warping or significantly reducing warping may be provided, so that defects generated by warping may be reduced. Therefore, productivity may be improved.

[0216] Example embodiments have been disclosed herein, and although specific terms are employed, they are used only and will be interpreted in a general descriptive sense and not for purposes of limitation. In some instances, as of the filing date of this application, it should be apparent to those of ordinary skill in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly stated. Accordingly, it will be understood by those of skill in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: A first substrate; A second substrate on the first substrate, the second substrate including a pattern portion and a plate portion covering the pattern portion, the width of the plate portion being greater than the width of each pattern portion in the pattern portion and the plate portion being directly connected to the pattern portion; A lower structure between the first substrate and the second substrate, the lower structure including peripheral wirings and an insulating layer between the peripheral wirings and the second substrate; Horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked spaced apart from each other in a direction perpendicular to the upper surface of the second substrate; And A vertical structure on the second substrate having side surfaces opposite to the horizontal conductive patterns, Wherein the pattern portion includes a pair of pattern portions adjacent to and parallel to each other, and Wherein each of the pair of pattern portions has a linear shape extending in a first direction, and Wherein the insulating layer covers side surfaces and bottom surfaces of each pattern portion in the pattern portion.

2. The three-dimensional semiconductor device according to claim 1, wherein the plate portion includes a semiconductor layer.

3. The three-dimensional semiconductor device according to claim 2, wherein the pattern portion includes a material different from the semiconductor layer of the plate portion.

4. The three-dimensional semiconductor device according to claim 3, wherein the pattern portion includes an insulating material.

5. The three-dimensional semiconductor device according to claim 1, wherein: The plate portion includes a semiconductor layer having N-type conductivity, and The pattern portion includes a conductive material having a lower resistance than the semiconductor layer.

6. The three-dimensional semiconductor device according to claim 1, wherein the horizontal conductive pattern is a gate pattern, and Wherein at least a part of the vertical structure is a channel.

7. The three-dimensional semiconductor device according to claim 6, further comprising: A source contact structure on the plate portion; A peripheral contact structure on a peripheral contact region of the peripheral wirings of the lower structure; And A peripheral connection wiring electrically connecting the source contact structure to the peripheral contact structure.

8. The three-dimensional semiconductor device according to claim 6, further comprising: A contact plug between the peripheral wirings of the lower structure and the pattern portion, the contact plug electrically connecting the peripheral wirings to the pattern portion.

9. The three-dimensional semiconductor device according to claim 1, wherein: A lower insulating layer of the lower structure covers a bottom surface and side surfaces of the pattern portion, and The plate portion is connected to an upper surface of the pattern portion.

10. The three-dimensional semiconductor device according to claim 1, wherein: The plate portion is directly connected to the pattern portion while covering an upper surface and side surfaces of the pattern portion, and A lower insulating layer of the lower structure covers a bottom surface of the pattern portion.

11. The three-dimensional semiconductor device according to claim 1, further comprising: A barrier layer between the pattern portion and the lower structure.

12. The three-dimensional semiconductor device according to claim 1, wherein the pattern portion and the plate portion have an integral structure.

13. The three-dimensional semiconductor device according to claim 1, wherein: The plate portion includes a first plate layer and a second plate layer on the first plate layer, the second plate layer includes a semiconductor layer, and the first plate layer includes a material different from that of the second plate layer.

14. The three-dimensional semiconductor device according to claim 13, further comprising: An additional conductive layer between the first plate layer and the second plate layer.

15. The three-dimensional semiconductor device according to claim 1, wherein: each pattern portion in the pattern portion includes a first pattern portion and a second pattern portion on the first pattern portion, and the first pattern portion and the second pattern portion are formed of different materials.

16. The three-dimensional semiconductor device according to claim 15, wherein the second pattern portion has an integral structure with at least a part of the plate portion.

17. The three-dimensional semiconductor device according to claim 1 further comprises: A connection portion connected to the pattern portion, wherein: the plate portion covers the connection portion, and the pattern portion and the connection portion have an integral structure.

18. The three-dimensional semiconductor device according to claim 1, wherein at least one pattern portion in the pattern portion has a linear shape extending in a first direction, and wherein at least one of the horizontal conductive patterns has a linear shape extending in a second direction perpendicular to the first direction.

19. A three-dimensional semiconductor device, comprising: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion that contacts and covers the pattern portion; a lower structure between the first substrate and the second substrate; and an upper structure on the second substrate, wherein: the lower structure includes peripheral wirings, the plate portion includes a semiconductor layer, the width of the plate portion is greater than the width of each pattern portion in the pattern portion, and the second substrate further includes a connection portion that is integrally formed with the pattern portion while connecting the pattern portions, the connection portion is in the same plane as the pattern portion, and the plate portion covers the connection portion.

20. A three-dimensional semiconductor device, comprising: a first substrate; a second substrate on the first substrate, the second substrate including a pattern portion and a plate portion that is directly connected to and covers the pattern portion; a lower structure including peripheral wirings between the first substrate and the second substrate; horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked at intervals in a direction perpendicular to the upper surface of the second substrate; and a vertical structure on the second substrate having side surfaces opposite to the horizontal conductive patterns, wherein: the pattern portion has a linear shape, the plate portion includes a semiconductor layer, and the second substrate further includes a connection portion that is integrally formed with the pattern portion while connecting the pattern portions, the connection portion is in the same plane as the pattern portion, and the plate portion covers the connection portion.

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