Semiconductor Devices

Abstract

A semiconductor device according to an example embodiment includes: a substrate extending in a first direction and a second direction intersecting each other; nanowires on the substrate and spaced apart from each other in the second direction; a gate electrode extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowire to vertically overlap with the nanowire; an external partition wall on the substrate and covering a side wall of the gate electrode on the nanowire; and an isolation layer between the gate electrodes and extending in the first direction, wherein an upper surface of the isolation layer is flush with an upper surface of the gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0103027, entitled “Semiconductor Device”, filed on August 30, 2018 in the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As electronic devices tend to become smaller and lighter, the demand for high integration of semiconductor devices continues to increase. Summary of the invention

[0005] An embodiment relates to a semiconductor device, comprising: a substrate extending in a first direction and a second direction intersecting each other; nanowires on the substrate and spaced apart from each other in the second direction; a gate electrode extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowire to vertically overlap with the nanowire; an external partition wall on the substrate and covering a sidewall of the gate electrode on the nanowire; and an isolation layer between the gate electrodes and extending in the first direction. The upper surface of the isolation layer may be flush with the upper surface of the gate electrode.

[0006] Embodiments also relate to a semiconductor device, including: a substrate extending in a first direction and a second direction intersecting each other; nanowires on the substrate and spaced apart from each other in the second direction; a gate electrode extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowire to vertically overlap with the nanowire; an external partition wall on the substrate and covering a sidewall of the gate electrode on the nanowire; and an isolation layer between the gate electrodes and extending in the first direction. The isolation layer may include a plurality of layers.

[0007] Embodiments also relate to a semiconductor device, comprising: a substrate, comprising a first region and a second region horizontally spaced apart from each other; a first nanowire in the first region and horizontally spaced apart from each other; a first gate electrode in the first region and surrounding the first nanowire; a first gate dielectric layer in the first region and between the first nanowire and the first gate electrode; a first external partition wall in contact with the first gate dielectric layer on the first nanowire; and a first isolation layer between the first gate electrodes; a second nanowire in the second region and horizontally spaced apart from each other; a second gate electrode in the second region and surrounding the second nanowire; a second gate dielectric layer in the second region and between the second nanowire and the second gate electrode; and a second external partition wall in contact with the second gate dielectric layer on the second nanowire; and a second isolation layer between the second gate electrodes. The first isolation layer may be arranged at the same height as an upper surface of the first gate electrode, and the second isolation layer may be arranged at the same height as an upper surface of the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1A A plan view for explaining a semiconductor device according to example embodiments is shown.

[0010] Figure 1B Shown along Figure 1A A cross-sectional view taken along lines 1A-1A' and 1B-1B';

[0011] Figure 1C Shown along Figure 1A A cross-sectional view taken along lines 1C-1C' and 1D-1D';

[0012] Figure 1D Shown along Figure 1A A cross-sectional view taken along lines 1E-1E′ and 1F-1F′;

[0013] Figures 2 to 4 shows a cross-sectional view of a semiconductor device according to example embodiments; and

[0014] FIG. 5A to FIG. 16 Views illustrating a semiconductor device according to example embodiments are shown. DETAILED DESCRIPTION

[0015] Figure 1A is a plan view of a semiconductor device according to example embodiments. Figure 1B is along Figure 1AA cross-sectional view taken along lines 1A-1A' and 1B-1B'. Figure 1C is along Figure 1A A cross-sectional view taken along lines 1C-1C' and 1D-1D'. Figure 1D is along Figure 1A A cross-sectional view taken along lines 1E-1E' and 1F-1F'.

[0016] exist Figures 1A to 1D In the figure, two directions parallel to the upper surface of the substrate 110 and intersecting each other are respectively defined as a first direction (X direction) and a second direction (Y direction), and a direction substantially perpendicular to the upper surface is defined as a third direction (Z direction). The first direction (X direction) and the second direction (Y direction) may be substantially perpendicular to each other. The first direction (X direction) and the second direction (Y direction) are directions substantially perpendicular to the third direction (Z direction). The direction indicated by the arrows in the drawings and the direction opposite thereto are described as the same direction. The definitions of the above directions are the same in all subsequent drawings.

[0017] refer to Figures 1A to 1D , the first region I and the second region II may be defined on the substrate 110 of the semiconductor device 100. The first region I and the second region II may be regions where different types of semiconductor devices are arranged. For example, an NMOS transistor may be arranged in the first region I, and a PMOS transistor may be arranged in the second region II.

[0018] According to example embodiments, the substrate 110 may include a silicon substrate. According to example embodiments, the substrate 110 may be a substrate for implementing a device, such as an image sensor such as a system large-scale integrated circuit (LSI), a logic circuit, a CMOS imaging sensor (CIS), a memory device such as a flash memory, a dynamic random access memory (DRAM), a static RAM (SRAM), an electrically programmable read-only memory (EPROM), an electrically erasable programmable ROM (EEPROM), or a micro-electromechanical system (MEMS).

[0019] According to example embodiments, at least one of the first nanowire 120A, the first outer partition wall 130A, the inner partition wall 140, the first source region / drain region 150A, the first source contact / drain contact 155A, the first etch stop pattern 160A, the first insulating layer 170A, the first isolation layer 180A, the first gate electrode 190A and the first gate dielectric layer 192A may be arranged in the first region I.

[0020] According to example embodiments, the first nanowire 120A may include a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. For example, the first nanowire 120A may include silicon (Si), germanium (Ge), SiGe, indium gallium arsenide (InGaAs), GaSb, InSb, or a combination thereof.

[0021] The first gate electrode 190A may include, for example, doped polysilicon, a metal, or a combination thereof. According to example embodiments, the first gate electrode 190A may include, for example, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), TiAlN, tantalum carbide nitride (TaCN), TaC, TaSiN, or a combination thereof.

[0022] According to example embodiments, the first gate dielectric layer 192A may include, for example, a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. According to example embodiments, the high-k dielectric film that may be used as the first gate dielectric layer 192A may include any one of the following: for example, hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide or HfO 2 -Alumina (Al 2 O 3 )alloy.

[0023] The first source / drain region 150A extending to both ends of the first nanowire 120A may be formed on the substrate 110 in a direction (Z direction) perpendicular to the upper surface of the substrate 110. According to example embodiments, the first source / drain region 150A may include, for example, a doped SiGe film, a doped Ge film, a doped silicon carbide (SiC) film, or a doped InGaAs film. The first source / drain region 150A may include a semiconductor layer formed from the substrate 110 and the first nanowire 120A by an epitaxial process. According to example embodiments, the first source / drain region 150A may include a material different from that of the substrate 110 and the first nanowire 120A.

[0024] According to example embodiments, the upper surface of the first source / drain region 150A may be higher than the upper surface of the first nanowire 120A. According to example embodiments, a portion of the first source / drain region 150A may be used as a source / drain region of a transistor formed in the first region I. According to example embodiments, impurity ions may be heavily doped in a portion from the bottom surface of the first source / drain region 150A to a certain height. According to another example embodiment, impurity ions may be heavily doped from a central portion of the first source / drain region 150A to a certain height. According to another example embodiment, impurity ions may be heavily doped into the entire first source / drain region 150A.

[0025] The first outer partition wall 130A may cover the sidewall of the first gate electrode 190A. The first source / drain contact 155A may be connected to the first source / drain region 150A through the first insulating layer 170A and the first etch stop pattern 160A. A metal silicide layer may be formed between the first source / drain contact 155A and the first source / drain region 150A.

[0026] The first etch stop pattern 160A may be arranged on the first source / drain region 150A and the first outer partition wall 130A. The first etch stop pattern 160A may cover a portion of the first outer partition wall 130A and the first source / drain region 150A. The first etch stop pattern 160A may include a material having a high etching selectivity to the first insulating layer 170A. According to example embodiments, the first etch stop pattern 160A may include, for example, silicon nitride.

[0027] A portion of the first gate electrode 190A may be between adjacent first nanowires 120A or between the first nanowire 120A closest to the substrate 110 and the substrate 110. A portion of the first gate electrode 190A between adjacent first nanowires 120A or between the first nanowire 120A closest to the substrate 110 and the substrate 110 may be covered by a first gate dielectric layer 192A. The first gate dielectric layer 192A may be between the first gate electrode 190A and the inner partition wall 140 and between the first gate electrode 190A and the first nanowire 120A. The first gate dielectric layer 192A may extend on the surface of the first nanowire 120A and the sidewall surface of the inner partition wall 140.

[0028] The internal partition wall 140 may be between adjacent first nanowires 120A and / or between the substrate 110 and the first nanowire 120A adjacent to the substrate 110. The internal partition wall 140 may be in contact with the first source / drain region 150A and the first gate dielectric layer 192A. The internal partition wall 140 may be between the first source / drain region 150A and the first gate dielectric layer 192A. Therefore, the first source / drain region 150A may be separated from the first gate dielectric layer 192A.

[0029] The inner partition wall 140 may include a material different from a material included in the first gate dielectric layer 192A. According to example embodiments, a dielectric constant of a material included in the inner partition wall 140 may be less than a dielectric constant of a material included in the first gate dielectric layer 192A. According to example embodiments, the inner partition wall 140 may include an oxide of a group IV semiconductor, an oxide of a group IV-V compound semiconductor, an oxide of a group III-V compound semiconductor, an oxide such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0030] According to example embodiments, the first outer partition wall 130A and the inner partition wall 140 may be arranged at different heights on the substrate 110 in the third direction (Z direction). According to example embodiments, the first outer partition wall 130A and the inner partition wall 140 may overlap each other in the third direction (Z direction). According to example embodiments, the inner partition wall 140 may include a material different from a material included in the first outer partition wall 130A. According to example embodiments, a dielectric constant of a material included in the inner partition wall 140 may be smaller than a dielectric constant of a material included in the first outer partition wall 130A.

[0031] According to example embodiments, the first isolation layer 180A may include an insulating material (e.g., silicon oxide). According to example embodiments, the first isolation layer 180A may extend in the second direction (Y direction). According to example embodiments, the first isolation layer 180A may extend in the third direction (Z direction). According to example embodiments, the upper surface of the first isolation layer 180A may be higher than the upper surface of the first source / drain region 150A, and the lower surface of the first isolation layer 180A may be lower than the lower surface of the first source / drain region 150A. According to example embodiments, the length of the first isolation layer 180A in the third direction (Z direction) may be greater than the length of the first source / drain region 150A in the third direction (Z direction). According to example embodiments, the first isolation layer 180A may be between the first external partition walls 130A. According to example embodiments, a width of the first outer partition wall 130A in contact with the first isolation layer 180A (i.e., a length in the first direction (X direction)) is smaller than a width of the first outer partition wall 130A not in contact with the first isolation layer 180A (i.e., a length in the first direction (X direction)).

[0032] According to example embodiments, an upper surface of the first isolation layer 180A may be substantially flush with an upper surface of the first insulating layer 170A. According to example embodiments, an upper surface of the first isolation layer 180A may be substantially flush with an upper surface of the first etch stop pattern 160A.

[0033] According to example embodiments, the first isolation layer 180A may be in contact with the inner partition wall 140. According to example embodiments, an upper surface of the first isolation layer 180A may be substantially flush with an upper surface of the inner partition wall 140.

[0034] At least one of the second nanowire 120B, the second external partition wall 130B, the second source region / drain region 150B, the second source contact / drain contact 155B, the second etch stop pattern 160B, the second insulating layer 170B, the second isolation layer 180B, the second gate electrode 190B and the second gate dielectric layer 192B may be arranged in the second region II.

[0035] The second gate electrode 190B and the second gate dielectric layer 192B may have features similar to those described above for the first gate electrode 190A and the first gate dielectric layer 192A. For example, the second gate electrode 190B may include doped polysilicon, metal, or a combination thereof, and the second gate dielectric layer 192B may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0036] According to example embodiments, the second gate electrode 190B and the second gate dielectric layer 192B may include, for example, the same material as the first gate electrode 190A and the first gate dielectric layer 192A, respectively. For example, the second gate electrode 190B and the second gate dielectric layer 192B may include a material different from the material of the first gate electrode 190A and the first gate dielectric layer 192A, respectively.

[0037] A second source / drain region 150B extending in a third direction (Z direction) may be formed adjacent to both ends of the second nanowire 120B on the substrate 110. The second source / drain region 150B may include a semiconductor layer regrown from the substrate 110 and the second nanowire 120B by an epitaxial process. According to example embodiments, the second source / drain region 150B may include a material different from that of the second nanowire 120B. According to example embodiments, the second source / drain region 150B may include, for example, a doped SiGe film, a doped Ge film, a doped SiC film, or a doped InGaAs film.

[0038] According to example embodiments, the second source / drain region 150B may include a material different from that of the first source / drain region 150 A. The first source / drain region 150A may include SiC, and the second source / drain region 150B may include SiGe or Ge.

[0039] The second outer partition wall 130B, the second etch stop pattern 160B, the second insulating layer 170B, the second source contact / drain contact 155B may have features similar to those described above for the first outer partition wall 130A, the first insulating layer 170A, and the first source contact / drain contact 155A. According to example embodiments, the second outer partition wall 130B, the second insulating layer 170B, and the second source contact / drain contact 155B may be formed in the same process as the process of forming the first outer partition wall 130A, the first insulating layer 170A, and the first source contact / drain contact 155A, respectively. In other embodiments, the second outer partition wall 130B may be formed in a process different from the process of forming the first insulating layer 170A. According to example embodiments, the second insulating layer 170B may be formed in a process different from the process of forming the first insulating layer 170A.

[0040] Compared to the first region I, the inner partition wall 140 may not be arranged on the second region II. Therefore, the inner partition wall 140 may not be between the substrate 110 and the second nanowire 120B. Figure 1B As shown, the second gate dielectric layer 192B may be between the second gate electrode 190B and the second source / drain region 150B. Therefore, the second gate dielectric layer 192B may extend from between the substrate 110 and the second nanowire 120B to between the second gate electrode 190B and the second source / drain region 150B. The second source / drain region 150B may contact the second gate dielectric layer 192B.

[0041] According to an example embodiment, Figure 1B As shown, the internal partition wall 140 may be formed between the first gate electrode 190A and the first source / drain region 150A, but not between the second gate electrode 190B and the second source / drain region 150B.

[0042] Since the inner partition wall 140 is formed between the first gate electrode 190A and the first source / drain region 150A, the distance between the first gate electrode 190A and the first source / drain region 150A can be increased. Therefore, the parasitic capacitance between the first source / drain region 150A can be reduced. Omitting the inner partition wall 140 (from between the second gate electrode 190B and the second source / drain region 150B) can improve the crystal quality of the second source / drain region 150B.

[0043] According to example embodiments, the second isolation layer 180B may be formed to have features and shapes similar to those of the first isolation layer 180A. In another embodiment, the second isolation layer 180B may include a material different from that of the first isolation layer 180A. Thus, the stress applied to the device formed in the second region II by the second isolation layer 180B and the stress applied to the device formed in the first region I by the first isolation layer 180A may be changed. Thus, the mobility of the carrier charge of the materials included in the first isolation layer 180A and the second isolation layer 180B may be improved.

[0044] According to example embodiments, the first isolation layer 180A may have a first width IWA, and the second isolation layer 180B may have a second width IWB. According to example embodiments, the first width IWA and the second width IWB may be the same. In another embodiment, the first width IWA and the second width IWB may be different from each other. Therefore, the width of the first external partition wall 130A in contact with the first isolation layer 180A may be different from the width of the second external partition wall 130B in contact with the second isolation layer 180B.

[0045] According to example embodiments, as described below, the first isolation layer 180A and the second isolation layer 180B may be formed after forming the first source / drain region 150A and the second source / drain region 150B. Therefore, in a process for forming the first source / drain region 150A and the second source / drain region 150B, a portion of the first isolation layer 180A and the second isolation layer 180B may be reduced or prevented from being damaged and unintended epitaxial growth may be reduced or prevented from occurring in such damaged portions.

[0046] The first cover layer 266A and the second cover layer 266B (see Fig. 13B ) and the first and second outer partition walls 130A and 130B are aligned to form the first and second isolation layers 180A and 180B. Therefore, damage to the first and second nanowires 120A and 120B adjacent to the first and second isolation layers 180A and 180B can be prevented, which can reduce or prevent short circuits between the first and second source / drain regions 150A and 150B and the first and second gate electrodes 190A and 190B.

[0047] Figures 2 to 4 1A-1A' and 1B-1B' in FIG. 1. Figures 1A to 1D The same reference numerals in the drawings denote the same elements, and thus only the differences will be mainly described.

[0048] refer to Figure 2, the first isolation layer 180A' and the second isolation layer 180B' may include a first liner 181A and a second liner 181B and a first filler 182A and a second filler 182B, respectively. According to example embodiments, the first liner 181A and the second liner 181B may be conformally formed to have a U-shaped cross section, such as Figure 2 As shown. The first filler 182A and the second filler 182B may fill the inner space defined by the first liner 181A and the second liner 181B, respectively. Therefore, the first liner 181A and the second liner 181B may cover the side surfaces and the bottom surfaces of the first filler 182A and the second filler 182B, respectively. The first liner 181A may contact the first external partition wall 130A, the first nanowire 120A, and the internal partition wall 140. The second liner 181B may contact the second external partition wall 130B, the second nanowire 120B, and the second gate dielectric layer 192B, respectively. The upper surfaces of the first liner 181A and the second liner 181B may be substantially flush with the upper surfaces of the first filler 182A and the second filler 182B, respectively.

[0049] The first filler 182A and the second filler 182B may have the same Figures 1A to 1D The first isolation layer 180A and the second isolation layer 180B are described as having the same composition. The first liner 181A and the second liner 181B may have different compositions from the first filler 182A and the second filler 182B.

[0050] refer to Figure 3 , the first isolation layer 180A" and the second isolation layer 180B" may include first liner layers 181A and 181B, first fillers 182A and 182B, and first stress control layers 183A and 183B, respectively. According to example embodiments, the first liner layer 181A and the second liner layer 181B may be respectively connected to the reference Figure 2 The first liner 181A and the second liner 181B described are substantially the same. According to example embodiments, the first filler 182A and the second filler 182B may partially fill the inner space defined by the first liner 181A and the second liner 181B, respectively. According to example embodiments, the first filler 182A and the second filler 182B may be conformally formed to have a U-shaped cross-section. According to example embodiments, the first stress control layer 183A and the second stress control layer 183B may fill the inner space defined by the first filler 182A and the second filler 182B, respectively.

[0051] According to example embodiments, the first stress control layer 183A and the second stress control layer 183B may apply different stresses to semiconductor devices formed in the first region I and the second region II, respectively. In another embodiment, the first stress control layer 183A and the second stress control layer 183B may apply substantially the same stress to semiconductor devices formed in the first region I and the second region II, respectively.

[0052] According to example embodiments, the first stress control layer 183A and the second stress control layer 183B may include, for example, different materials. In another embodiment, the first stress control layer 183A and the second stress control layer 183B may include the same material. According to example embodiments, the first stress control layer 183A and the second stress control layer 183B may include, for example, any one of Si, SiN, SiGe, SiON, or SiO.

[0053] According to example embodiments, one of the first stress control layer 183A and the second stress control layer 183B may be omitted. In this case, one of the first filler 182A and the second filler 182B may completely fill the inner space defined by the first liner 181A and the second liner 181B, respectively.

[0054] refer to Figure 4 , the first isolation layer 180A'' and the second isolation layer 180B'' may be lower than the first external partition wall 130A and the second external partition wall 130B. The upper surfaces of the first isolation layer 180A'' and the second isolation layer 180B'' may be lower than the upper surfaces of the first source / drain region 150A and the second source / drain region 150B. The dielectric constant control layers 171A and 171B may be on the first isolation layer 180A'' and the second isolation layer 180B'', respectively. Therefore, by forming the dielectric constant control layers 171A and 171B adjacent to the first gate electrode 190A and the second gate electrode 190B with a low-k dielectric material, the resistance-capacitance (RC) delay caused by parasitic capacitance can be reduced or prevented.

[0055] refer to Figure 4 , the lower surfaces of the first external partition wall 130A and the second external partition wall 130B can be flush with the upper surfaces of the first isolation layer 180A'' and the second isolation layer 180B'', respectively. In another embodiment, the lower surfaces of the first external partition wall 130A and the second external partition wall 130B can be lower or higher than the upper surfaces of the first isolation layer 180A'' and the second isolation layer 180B'', respectively.

[0056] FIG. 5A to FIG. 16 is an exemplary diagram of a method of manufacturing the semiconductor device 100 .

[0057] In more detail, Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig.11A , Fig.13A and Fig.14A is a top view showing the process sequence, Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 11B , Fig. 13B and Fig. 14B Along Figure 5A Lines 5A-5A' and 5B-5B', Fig. 6A Lines 6A-6A' and 6B-6B', Fig. 7A Lines 7A-7A' and 7B-7B', Fig. 8A Lines 8A-8A' and 8B-8B', Fig.9A Lines 9A-9A' and 9B-9B', Fig.11A Lines 11A-11A' and 11B-11B', Fig.13A The lines 13A-13A' and 13B-13B' and Fig.14A Cross-sectional views taken along lines 14A-14A' and 14B-14B'.

[0058] refer to Figure 5A and Figure 5B In an example embodiment, at least one sacrificial material layer and a channel material layer are alternately stacked on a substrate 110, and then some of them are etched to form a sacrificial layer 240L and a channel layer 120L, wherein a first region I and a second region II are defined on the substrate 110. According to an example embodiment, the sacrificial layer 240L and the channel layer 120L may be formed by an epitaxial process. According to an example embodiment, the sacrificial layer 240L and the channel layer 120L may have a certain width in the second direction (Y direction) and extend in the first direction (X direction). The sacrificial layer 240L and the channel layer 120L may be etched to have a fin shape, and the portion where the sacrificial layer 240L and the channel layer 120L are removed by etching may be an exposed portion of the upper surface of the substrate 110.

[0059] According to example embodiments, the sacrificial layer 240L and the channel layer 120L may include different materials, respectively. According to example embodiments, the sacrificial layer 240L and the channel layer 120L may include materials having different etching selectivities, respectively. According to example embodiments, each of the sacrificial layer 240L and the channel layer 120L may include a single crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. According to example embodiments, the sacrificial layer 240L may include SiGe, and the channel layer 120L may include single crystal silicon.

[0060] According to example embodiments, the epitaxial process may be a chemical vapor deposition (CVD) process (e.g., vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), etc.), molecular beam epitaxy, or a combination thereof. In the epitaxial process, as a precursor for forming the sacrificial layer 240L and the channel layer 120L, a liquid or gaseous precursor may be used.

[0061] refer to Fig. 6A and Figure 6B , the first dummy gate structure 260A and the second dummy gate structure 260B may be formed on the first region I and the second region II, respectively. The first dummy gate structure 260A and the second dummy gate structure 260B may have a certain width in the first direction (X direction) and may extend in the second direction (Y direction). The first dummy gate structure 260A and the second dummy gate structure 260B may include a first gate etch stop layer 262A and a second gate etch stop layer 262B, a first dummy gate electrode 264A and a second dummy gate electrode 264B, a first external partition wall 130A and a second external partition wall 130B, and a first external partition wall 130A and a second external partition wall 130B, respectively.

[0062] According to example embodiments, the first dummy gate electrode 264A and the second dummy gate electrode 264B may include polysilicon, and the first capping layer 266A and the second capping layer 266B may include a silicon nitride film. The first gate etch stop layer 262A and the second gate etch stop layer 262B may include a material having an etching selectivity to the first dummy gate electrode 264A and the second dummy gate electrode 264B. According to example embodiments, the first gate etch stop layer 262A and the second gate etch stop layer 262B may include at least one film selected from, for example, thermal oxide, silicon oxide, and silicon nitride, and the first outer partition wall 130A and the second outer partition wall 130B may include silicon oxide, silicon oxynitride, or silicon nitride.

[0063] refer to Fig. 7A and Figure 7B , a first protective layer 271 covering the first dummy gate structure 260A and the channel layer 120L may be formed on the first region I. Next, the channel layer 120L may be etched using the second dummy gate structure 260B on the second region II as an etching mask (see Figure 6B ) and sacrificial layer 240L (see Figure 6B ) to form the first opening OP1. Therefore, the second nanowire 120B and the sacrificial pattern 240P may be formed on the second region II.

[0064] According to example embodiments, a lower surface of the first opening OP1 may be lower than the lowermost sacrificial pattern 240P. According to example embodiments, the first opening OP1 may expose a portion of the substrate 110 .

[0065] refer to 7A to 8B , the second source / drain region 150B filling the first opening OP1 may be formed by growing a single crystal film from the substrate 110 , the plurality of second nanowires 120B, and the sacrificial layers 240P1 , 240P2 , and 240P3 in the first opening OP1 .

[0066] Each of the substrate 110, the plurality of second nanowires 120B, and the sacrificial pattern 240P exposed at the sidewall of the first opening OP1 may be a single crystalline semiconductor layer. Therefore, in the growth process of the second source / drain region 150B, dislocation or stacking fault caused by lattice mismatch may be avoided, and the second source / drain region 150B having excellent crystal quality may be formed.

[0067] Fig. 8A and Figure 8B The second source / drain region 150B is shown to be formed as a single layer. In an embodiment, the second source / drain region 150B may be formed to include multiple layers. For example, the second source / drain region 150B may have a multilayer structure including SiGe, wherein the content of Si and Ge is different for each layer. After forming the second source / drain region 150B, the first protective layer 271 may be removed.

[0068] refer to Fig.9A and Fig. 9B , a second protective layer 272 may be formed on the second region II. Next, the channel layer 120L on the first region I may be etched using the first dummy gate structure 260A on the first region I as an etching mask (see Figure 8B ) and sacrificial layer 240L (see Figure 8B ) to form the second opening OP2. Thus, the first nanowire 120A and the sacrificial pattern 240P may be formed on the first region I. The second opening OP2 may expose a portion of the upper surface of the substrate 110.

[0069] refer to Fig.10 After the sacrificial layer 240L exposed through the second opening OP2 is etched to be laterally recessed, an inner partition wall material film may be conformally deposited, and the inner partition wall 140 may be formed by performing an etch-back process again.

[0070] Next, refer to Fig.11A and Fig. 11B , the first source / drain region 150A may be connected to the reference Fig. 8A and Figure 8BThe same manner as described is formed on the first region I. The second protective layer 272 may then be removed.

[0071] refer to Fig.12 , an etch stop material film 160L, an insulating material film 170L, a hard mask film 273, and a photoresist 274 may be formed on the resulting structure formed at this time. The etch stop material film 160L may be formed in a conformal manner and may identify the end point of etching and protect the underlying layers in subsequent processes.

[0072] According to example embodiments, the etch stop material film 160L may include a material having a high etch selectivity to the insulating material film 170L. According to example embodiments, the etch stop material film 160L may include, for example, silicon nitride.

[0073] The insulating material film 170L may be etched to a certain height so that no step is formed on the upper surface of the insulating material film 170L by a planarization / etch-back process, etc. The insulating material film 170L may include silicon oxide such as Tonen SilaZene (TOSZ).

[0074] refer to Figures 12 to 13B , a hard mask pattern 273P may be formed by patterning the hard mask film 273 using a photoresist as an etching mask. Thus, the hard mask pattern 273P exposes the upper surface of the insulating material film 170L and may have an opening extending in the second direction (Y direction). The insulating material film 170L may be etched by again using the hard mask pattern 273P as an etching mask so that the upper surface of the etching stop material film 160L is exposed. The etching stop material film 160L may be overetched to expose the upper surfaces of a portion of the first source / drain region 150A and the second source / drain region 150B. Thus, an etching stop pattern 160P and an insulating pattern 170P may be formed.

[0075] refer to Fig.14A and Fig. 14B , a first isolation layer 180A and a second isolation layer 180B may be formed. The exposed first source / drain region 150A and the second source / drain region 150B and the substrate 110 under the first source / drain region 150A and the second source / drain region 150B may be etched by using the hard mask pattern 273P as an etching mask to form the first isolation layer 180A and the second isolation layer 180B. The exposed first source / drain region 150A and the second source / drain region 150B may be etched and removed. For example, a portion of the first source / drain region 150A and the second source / drain region 150B may remain on the side surfaces of the first isolation layer 180A and the second isolation layer 180B.

[0076] The first and second outer partition walls 130A and 130B exposed by the hard mask pattern 273P may be partially etched by an etching process. Therefore, the widths (i.e., the lengths in the first direction (X direction)) of the first and second outer partition walls 130A and 130B exposed by the hard mask pattern 273P may be smaller than the widths of the first and second outer partition walls 130A and 130B not exposed by the hard mask pattern 273P.

[0077] refer to Figure 1B , the first width IWA and the second width IWB (which are the widths of the first isolation layer 180A and the second isolation layer 180B) may be determined according to the etching degree of the first external partition wall 130A and the second external partition wall 130B in contact with the first isolation layer 180A and the second isolation layer 180B. For example, when the first external partition wall 130A in contact with the first isolation layer 180A is etched to have a width smaller than the width of the second external partition wall 130B in contact with the second isolation layer 180B, the first width IWA may be greater than the second width IWB. As another example, when the first external partition wall 130A in contact with the first isolation layer 180A is etched to have a width greater than the width of the second external partition wall 130B in contact with the second isolation layer 180B, the first width IWA may be less than the second width IWB.

[0078] Generally, the nanowires included in the semiconductor device and adjacent to the isolation layer may be arranged adjacent to the boundary between the isolation layer and the active region and may be susceptible to the process for forming the gate electrode described below. According to example embodiments, the first capping layer 266A and the second capping layer 266B exposed by the hard mask pattern 273P (see Fig. 13B ) and the first external partition wall 130A and the second external partition wall 130B (see Fig. 13B ) can be used together as an etching mask. Therefore, despite the tolerance of the etching process for forming the shallow trench, the first isolation layer 180A and the second isolation layer 180B can be aligned between the first external partition wall 130A and the second external partition wall 130B. In addition, a portion of the side surfaces of the first isolation layer 180A and the second isolation layer 180B can be in contact with the first external partition wall 130A and the second external partition wall 130B. Therefore, the first source / drain region 150A and the second source / drain region 150B and the first gate electrode 190A and the second gate electrode 190B (see FIG. 1 ) caused by damage to the first nanowire 120A and the second nanowire 120B during the process for forming the gate electrode described below can be reduced or prevented. Fig.16 ) A short circuit occurs between the two terminals.

[0079] Next, after the isolation material film is sufficiently provided in the trench formed by etching, the upper portion of the insulating pattern 170P and the isolation material film may be removed until the upper surfaces of the first dummy gate electrode 264A and the second dummy gate electrode 264B are exposed. Thus, the first isolation layer 180A and the second isolation layer 180B may be formed. Fig. 8A and Figure 8B It is shown that the first isolation layer 180A and the second isolation layer 180B are formed together, but after forming any one of the first isolation layer 180A and the second isolation layer 180B by forming a protective layer on any one of the first region I and the second region II, the protective layer may be removed to form the other of the first isolation layer 180A and the second isolation layer 180B. Therefore, the first isolation layer 180A and the second isolation layer 180B may include different materials.

[0080] In addition, a liner material film may be provided before providing an isolation material film, so that the conformal liner 181A may cover the first filler 182A (eg, Figure 2 In this case, the first isolation layer 180A' and the second isolation layer 180B' may be formed by, for example, an atomic layer deposition (ALD) process. In another embodiment, a liner material film, an isolation material film, and a first stress control material film and a second stress control material film may be provided in sequence. Figure 3 In this case, the first isolation layer 180A" and the second isolation layer 180B" may be formed by an ALD process. In some cases, the first isolation layer 180A" and the second isolation layer 180B" may be formed by partially removing the upper portions of the first isolation layer 180A and the second isolation layer 180B and then filling the recessed space with a dielectric material. Figure 4 The dielectric constant control layers 171A and 171B.

[0081] Generally, when forming source / drain regions, a portion of the previously formed isolation layer may be damaged, and unintentional epitaxial growth may occur near the damaged isolation layer. According to example embodiments, such unintentional epitaxial growth may be prevented by forming a portion of the isolation layer after forming the source / drain regions.

[0082] refer to Fig.15, the exposed first and second dummy gate structures 260A and 260B and the first and second gate etch stop layers 262A and 262B may be removed to form a third opening OP3. The first and second nanowires 120A and 120B may be exposed through the third opening OP3. The portion of the sacrificial pattern 240P exposed through the third opening OP3 may be selectively removed to extend the third opening OP3 to the upper surface of the substrate 110.

[0083] refer to Fig.15 and Fig.16 The first gate dielectric layer 232A and the second gate dielectric layer 232B can be conformally formed on the surfaces of the first region I and the second region II exposed by the third opening OP3, and the first gate electrode 190A and the second gate electrode 190B filling the remaining space of the third opening OP3 can be formed on the first gate dielectric layer 192A and the second gate dielectric layer 192B, respectively.

[0084] Refer to Figure 1 and Fig.16 , the first source / drain contact 155A and the second source / drain contact 155B may be formed in the first region I and the second region II, respectively, wherein the first source / drain contact 155A and the second source / drain contact 155B penetrate the etch stop pattern 160P and the insulating pattern 170P and are connected to the first source / drain contact 155A and the second source / drain contact 155B. Therefore, the first etch stop pattern 160A and the second etch stop pattern 160B and the first insulating layer 170A and the second insulating layer 170B may be formed.

[0085] By summarizing and reviewing, as the size of semiconductor devices decreases, short channel effects of transistors may occur, which may reduce the reliability of semiconductor devices. In order to reduce the short channel effects, semiconductor devices with multi-gate structures such as gate-all-around types may be considered.

[0086] As described above, embodiments relate to a semiconductor device including a multi-gate metal oxide semiconductor field effect transistor (MOSFET) and a method for manufacturing the same. Embodiments may provide a semiconductor device with improved reliability.

[0087] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a general descriptive sense only, and not for purposes of limitation. In some cases, as will be appreciated by those of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, include: a substrate extending in a first direction and a second direction intersecting each other; an isolation layer extending in the first direction, the isolation layer having gate electrodes on opposite sides thereof; nanowires spaced apart from each other on the substrate and in the second direction; as well as a gate dielectric layer between the nanowire and the gate electrode; a source / drain region spaced apart from the isolation layer, wherein the nanowire is interposed between the source / drain region and the isolation layer; a source / drain contact portion extending in a third direction perpendicular to the upper surface of the substrate and contacting the source region / drain region; and an external partition wall on said substrate, wherein: The gate electrodes extend in the first direction and are spaced apart from each other in the second direction, and surround the nanowire so that the gate electrodes are vertically overlapped with the nanowire; The external partition wall covers the sidewall of the gate electrode on the nanowire; The outer partition wall contacts the gate dielectric layer and the isolation layer on the nanowire, and The upper surface of the isolation layer is flush with the upper surface of the gate electrode, The gate electrode and the source region / drain region together form a metal oxide semiconductor MOS transistor.

2. The semiconductor device according to claim 1, in, The upper surface of the isolation layer is higher than the nanowires.

3. The semiconductor device according to claim 1, in, The source region / drain region is spaced apart from the isolation layer, and the gate electrode is located between the source region / drain region and the isolation layer. Wherein, the length of the source region / drain region in the third direction is smaller than the length of the isolation layer in the third direction.

4. The semiconductor device according to claim 3, in, The lower surface of the isolation layer is lower than the lower surface of the source / drain region, and the upper surface of the isolation layer is higher than the upper surface of the source / drain region.

5. The semiconductor device according to claim 4, further comprising: include: an etching stop pattern in contact with the upper surface of the source / drain region and the side surface of the outer partition wall, Wherein, an upper surface of the etching stop pattern is flush with an upper surface of the isolation layer.

6. The semiconductor device according to claim 3, in, In a cross section parallel to the second direction and the third direction and passing through the source / drain region, the external partition wall is higher than an upper surface of the source / drain region.

7. The semiconductor device according to claim 1, in, Some of the exterior partition walls are in contact with the insulation layer.

8. The semiconductor device according to claim 7, in, The width of the external partition wall in contact with the isolation layer in the second direction is smaller than the width of the external partition wall spaced apart from the isolation layer in the second direction.

9. The semiconductor device according to claim 7, in, The upper surface of the external partition wall is flush with the isolation layer.

10. The semiconductor device according to claim 1, in, An upper surface of the gate dielectric layer is flush with an upper surface of the isolation layer.

11. A semiconductor device, include: a substrate extending in a first direction and a second direction intersecting each other; nanowires spaced apart from each other on the substrate and in the second direction; an isolation layer extending in the first direction between gate electrodes, the gate electrodes extending in the first direction and spaced apart from each other in the second direction, and surrounding the nanowires so that the gate electrodes vertically overlap the nanowires; a source / drain region spaced apart from the isolation layer, wherein the nanowire is interposed between the source / drain region and the isolation layer; A source / drain contact portion extending in a third direction perpendicular to the upper surface of the substrate and contacting the source region / drain region; and an external partition wall on the substrate and covering the sidewall of the gate electrode on the nanowire; wherein: The isolation layer includes a plurality of layers, wherein the plurality of layers includes a liner in contact with the nanowires and the external partition walls, and the liner is conformally formed, The gate electrode and the source region / drain region together form a metal oxide semiconductor MOS transistor.

12. The semiconductor device according to claim 11, in, The plurality of layers of the isolation layer further include: A filler has a composition different from that of the lining and fills at least a portion of an inner side of the lining.

13. The semiconductor device according to claim 12, in: The filler is conformally formed, and The plurality of layers of the isolation layer further includes a stress control layer filling an inner side of the filler.

14. The semiconductor device according to claim 13, in, The upper surfaces of the liner, the filler, and the stress control layer form a coplanar surface.

15. A semiconductor device, include: a substrate including a first region and a second region horizontally spaced apart from each other; first nanowires in the first region and horizontally spaced apart from each other; a first isolation layer between first gate electrodes, the first gate electrodes being in the first region and surrounding the first nanowire, the upper surface of the first isolation layer being arranged at the same height as the upper surface of the first gate electrode; a first gate dielectric layer in the first region and between the first nanowire and the first gate electrode; a first source / drain region, spaced apart from the first isolation layer, wherein the first nanowire is inserted between the first source / drain region and the first isolation layer, and the first gate electrode and the first source / drain region together constitute a first metal oxide semiconductor (MOS) transistor; a first source / drain contact portion extending in a third direction perpendicular to the upper surface of the substrate and contacting the first source region / drain region; a first external partition wall in contact with the first gate dielectric layer and the first isolation layer on the first nanowire; second nanowires in the second region and horizontally spaced apart from each other; a second isolation layer between second gate electrodes, the second gate electrodes being in the second region and surrounding the second nanowire, the upper surface of the second isolation layer being arranged at the same height as the upper surface of the second gate electrode; a second gate dielectric layer in the second region and between the second nanowire and the second gate electrode; a second source / drain region, spaced apart from the second isolation layer, wherein the second nanowire is inserted between the second source / drain region and the second isolation layer, and the second gate electrode and the second source / drain region together constitute a second metal oxide semiconductor (MOS) transistor; a second source / drain contact portion extending in the third direction and contacting the second source region / drain region; as well as The second outer partition wall contacts the second gate dielectric layer and the second isolation layer on the second nanowire.

16. The semiconductor device according to claim 15, in, The width of the first isolation layer is different from the width of the second isolation layer.

17. The semiconductor device according to claim 15, in, Some of the first external partition walls are in contact with the first insulating layer, and some of the second external partition walls are in contact with the second insulating layer, and A width of a first external partition wall in contact with the first isolation layer is different from a width of a second external partition wall in contact with the second isolation layer.

18. The semiconductor device according to claim 15, in, Each of the first isolation layer and the second isolation layer includes a plurality of layers.

19. The semiconductor device according to claim 18, in, The first isolation layer and the second isolation layer include different materials.

20. The semiconductor device according to claim 19, in: The plurality of layers of the first isolation layer include: a first liner conformally formed to have a U-shaped cross-section; A first filler formed conformally on the first liner; and A first stress control layer fills the inner side of the first filler, The plurality of layers of the second isolation layer include: a second liner conformally formed to have a U-shaped cross section; a second filler formed conformally on the second liner; and a second stress control layer filling the inner side of the second filler, and The first stress control layer and the second stress control layer include different materials.

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