Custom leadframe from standard and printed leadframe sections

Abstract

The present application discloses a custom leadframe from standard and printed leadframe sections and discloses a packaged semiconductor device (200) including an IC die (140) flip-chip attached to a custom LF, the IC die (140) having bump (140a) features coupled to bond pads (140b). The custom LF includes a metal structure including metal leads (110b) on at least two sides and a printed metal providing a printed LF section including printed metal traces (120a) coupled to FC pads (120b), the printed metal traces (120a) connected to and extending inwardly from at least one metal lead over a dielectric support material, including at least some printed metal traces coupled to bond pads on the IC die, the FC pads (120b) configured to receive bump features. The IC die is flip-chip mounted on the printed LF section such that the bump features are connected to the FC pads.

Description

Technical Field

[0001] This disclosure relates to leadframe packages for semiconductor devices and semiconductor devices packaged as a result. Background Technology

[0002] Various semiconductor chip packages are known that provide support for integrated circuit (IC) chips or dies and associated bonding wires, provide environmental protection, and enable surface mounting of the die to and interconnection with a printed circuit board (PCB). A conventional package configuration includes a lead frame (LF) having leads on at least two sides of the die pads.

[0003] LF packaging is well-known and widely used in the electronics industry to house, mount, and interconnect various ICs. A typical LF strip is usually stamped from a flat sheet of metal (e.g., copper) and includes multiple metal leads that are temporarily held together in a planar arrangement around a central region during package manufacturing by a rectangular frame comprising multiple consuming "tie-bars." Die pads are provided for the semiconductor die supported in the central region by the "tie-bars" attached to the frame. The leads extend from a first end integral with the frame to an opposite second end adjacent to but spaced from the die pads.

[0004] Different packaged devices, mechanical stresses, heat dissipation, mold locking features, and electrical parasitic components often require custom LF designs. LFs are typically designed along with the IC die in a co-design process, involving mechanical, thermal, and electrical modeling, which is time-consuming and results in high LF design costs. Changes in target specifications can trigger another iteration of the co-design process, including changes to the bump layout on the IC die and / or changes to the LF design. Summary of the Invention

[0005] This summary is provided to present a simplified selection of the disclosed concepts, which will be further described below in a detailed description including the accompanying drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0006] This disclosure recognizes that the conventional requirement of creating a custom LF design for every new IC die design can be avoided. This requirement typically results in high development costs through the use of a standard LF and IC bump design, achieved via an additive manufacturing metalworking process that adds leads coupled to the standard LF. The printed LF portion is physically supported by a dielectric support material in the gaps between the metal structures of the standard LF and includes connections to the leads of the standard LF to provide a custom LF design that provides wiring between the leads of the standard LF and each bump feature on the IC die (e.g., solder bumps or solder-covered copper pillars). This disclosure enables the rapid digital generation of new custom LF designs and the subsequent fabrication of the actual custom LF. Furthermore, this disclosure enables the standardization of IC bump designs, which can reduce the number of die masks required, for example, by avoiding the need for a redirection layer.

[0007] The disclosed aspects include packaged semiconductor devices comprising an IC die flip-chip (FC) attached to a custom LF, the IC die having bump features coupled to bonding pads. The custom LF includes: a metal structure having metal leads on at least two sides; and printed metal providing a printed LF portion including printed metal traces coupled to the FC pads, the printed metal traces connecting to and extending inwardly over at least one metal lead above a dielectric support material, including at least some printed metal traces coupled to bonding pads on the IC die, the FC pads being configured to receive the bump features. The IC die is flip-chip mounted on the printed LF portion such that the bump features are connected to the FC pads. Attached Figure Description

[0008] Now refer to the attached diagram, which is not necessarily drawn to scale, in which:

[0009] Figure 1 A simplified example custom LF is shown according to an example embodiment, which shows its standard LF portion and a printed LF portion coupled to the standard LF portion.

[0010] Figures 2A-2F The diagram shows views of various stages in assembling a disclosed packaged semiconductor device, which includes a disclosed custom leadframe comprising a standard LF portion and a printed LF portion.

[0011] Figure 3A A top view of a standard LF section with floating leads is shown, and Figure 3B This is shown after the printed LF section that contacts the other leads of the standard LF. Figure 3A The standard LF section in [the document / document]. Detailed Implementation

[0012] Example embodiments are described with reference to the accompanying drawings, wherein the same reference numerals are used to denote similar or equivalent elements. The illustrated order of actions or events should not be considered a limitation, as some actions or events may occur in a different order and / or simultaneously with other actions or events. Furthermore, some of the illustrated actions or events may not be necessary to implement the method according to this disclosure.

[0013] Figure 1 A simplified example custom LF 100 according to an exemplary embodiment is shown, illustrating its standard LF portion 110 having leads 110b on at least two sides, and a printed LF portion 120 coupled to the leads 110b of the standard LF portion 110. Some design overlap is typically present between the traces 120a and leads 110b of the printed LF portion 120 to reflect manufacturing tolerances to ensure reliable connection. The custom LF 100 is typically part of a custom LF strip comprising multiple LFs. The printed metal may have a porosity greater than 10%.

[0014] The custom LF 100 includes a dielectric support surface 131 in the gap between the metal structures of the standard LF portion 110, which provides mechanical support for the printed LF portion 120 extending beyond the standard LF. The dielectric support surface 131 can be provided as a surface of a support 130, which typically includes a pre-molded structure in which leads 110b are embedded leads with exposed top surfaces, such that dielectric material exists between adjacent leads 110b. The pre-molded structure can include a pre-molded standard LF providing the standard LF portion 110, wherein a molding compound provides the dielectric support surface 131 and the leads 110b are exposed, or via a single-stage or multi-stage molded interconnect substrate (MIS) including a pre-molded structure comprising a MIS lead frame providing the standard LF portion 110, wherein the top dielectric layer of the MIS serves as the dielectric support surface 131 and the leads 110b are exposed. The standard LF portion 110 can also be provided or processed to have a nano-rough surface to improve the adhesion of the traces 120a and leads 110b of the printed LF portion 120.

[0015] The printed LF portion 120 is formed by additive deposition (e.g., 3D printing, i.e., inkjet printing, or screen printing) of a metal precursor (e.g., an ink or paste comprising multiple metal particles) to typically / generally deposit the printed metal precursor. Sintering or curing is typically performed after additive deposition to form the printed LF portion 120 comprising FC pads 120b and metal traces 120a, the metal traces 120a being connected to and extending inwardly from at least one metal lead 110b over and from the dielectric support surface 131. The typical thickness of the printed metal precursor is 75 μm to 150 μm. The additive deposition process may include multiple coating and sintering steps, such as a series of powder coatings followed by laser exposure.

[0016] For some devices, traces 120a may extend from one side of a custom LF 100 without any FC bonding pads 120b in the path, for example, to provide a common ground or heat dissipation path. The IC die is then flip-coupled to the FC pads 120b, which are configured to receive bump features coupled to bonding pads on the IC die to be mounted. Typically, sintering or curing of the metal precursor is performed prior to flip-chip mounting. The FC pads 120b are positioned for flip-chip mounting the IC die onto the printed metal, such that the bump features (see description below) Figure 2C The bump feature 140a) falls on the FC pad 120b. After flip-chip mounting of the IC die, the LF strip is typically heated to a temperature above the melting point of the solder material used in a conventional solder reflow process, which can improve the conductivity of the printed LF portion 120.

[0017] As is known in the printing industry, inks comprise solid materials (e.g., particulate, such as nanoparticles) or materials for solid precursors that form solids (e.g., particulates) after curing or sintering to remove their liquid carriers, including solvents and / or dispersants. For example, inks can be sinterable metallic inks or UV-curable polymers or UV-curable polymer-based mixtures. Inks can be additively deposited to their programmed desired locations via a printing press platform. Ink deposition equipment can be piezoelectric, thermal, or acoustic inkjet printers, electrostatic inkjet printers, or screen or flexographic printers.

[0018] Metal pastes can be processed, for example, after additive deposition via screen printing, involving a heating step in a reducing atmosphere followed by a vacuum sintering step, typically at a temperature of at least 200°C, to form a sintered metal coating. The metal paste can conventionally be sintered in a curing oven to remove binders and solvents (if present) and to densify to reduce the porosity of the metal material.

[0019] Figures 2A-2FThe diagram shows views of various stages of assembling a packaged semiconductor device, which includes an exposed custom leadframe comprising a standard LF portion and a printed LF portion. Figure 2A A side view of the standard LF section following the additive deposition printing of the LF section is shown, and Figure 2B The diagram shows a top view of the standard LF portion, indicated by its leads 110b and a tab 110a. The printed LF portion is shown by its metal traces 120a and FC pads 120b, supported by a dielectric support surface 131 located in the gap between the metal structures of the standard LF portion. The tab 110a secures the metal leads 110b to the frame 110c. Figure 2C A side view of a standard LF is shown after the flip-chip mounted IC die 140, and Figure 2D The top view shows the standard LF, which is shown by its lead 110b and tie 110a. The IC die 140 has a bonding pad 140b, wherein the bump feature 140a on the bonding pad 140b is on the printed LF portion, such that the bump feature 140a of the IC die falls on the FC pad 120b of the printed LF portion.

[0020] Figure 2E The image shows a side view after molding to form the molding material 150 surrounding the LF sheet. Figure 2F A side view is shown after the LF sheet is monolithically molded to form the semiconductor device 200 of the package shown.

[0021] Figure 3A A top view of a standard LF section with floating lead 110d is shown, and Figure 3B This shows the printed LF section 120' after the printed section contacts the other leads of the standard LF. Figure 3A The standard LF section in ICs. Floating leads can increase the flexibility and heat dissipation of IC package input / output (I / O) configurations and reduce mechanical stress by providing exposed pads on the back side of the package near the center of the IC. Floating lead designs are common in some commercially available existing packages (e.g., HOTROD from Texas Instruments Inc. for various power converter devices). TM Standard features in encapsulation.

[0022] The method for forming a disclosed custom LF can begin by identifying multiple preliminary candidate LF designs that also meet the device requirements of the IC die, including the number of I / Os, voltage and / or current ratings, and mechanical and / or thermal stresses. The number of preliminary candidate LFs can be narrowed down to identify the final candidate LFs by simulating them to quantify their device performance. This narrowing process creates a set of candidate LF designs that meet all the requirements of a specific IC device. The same process is repeated for other IC devices with different voltage and / or current ratings and mechanical and / or thermal stresses but somewhat similar I / O numbers and package sizes. This process creates a set of candidate custom LF designs for different IC devices with similar numbers of I / Os and die sizes.

[0023] Typically, one or more standard LFs are designed based on common features shared by two or more candidate LFs. Algorithms identify common features in the candidate custom LF designs, which together determine the standard LF design. The standard design LF is then fabricated into LF strips using conventional LF manufacturing techniques. 3D printing technology is then used to fabricate printed metal portions including printed traces that extend to contacts on top of the edges of the standard LF traces to replicate the candidate LF design. In this way, the standard LF design can be used as a candidate LF design for different devices.

[0024] Depending on how candidate LF designs are classified, there can be more than one standard LF design. Candidate LF designs can be classified based on similarities, such as the number of I / Os, package size, thermal performance, and mechanical strength.

[0025] As described above, the surface of the LF 110 may include nano-roughening. Next, a metal precursor material is additively deposited and then sintered or cured (e.g., laser-processed) to provide metal traces and FC pads, and the metal traces are connected to the leads of the standard LF for desired wiring and to meet other LF properties, such as the number of I / O pins, heat dissipation, and mechanical stress. Additive deposition may include inkjet printing using piezoelectric, thermal, or acoustic methods, or electrostatic inkjet printing, screen printing, or flexographic printing. Molding and monolithization of the LF strip typically follow.

[0026] Printed metal precursor materials may include inks, which contain solid materials or materials used as precursors for solids, which form solids after curing or sintering. Inks may include copper or silver nanoparticles. Typically, printed metals have greater porosity, lower mechanical strength, and lower electrical conductivity than the metals in the LF (Left-Installed) process.

[0027] Several standard LF options exist that can be used with the disclosed aspects. Two or more standard LFs can be combined, for example, a top leader frame on a bottom leader frame. Some leads of the standard LF can also be floating, as described above. Figure 3A and 3B As shown, this can increase the flexibility of IC package I / O configuration, such as heat dissipation and / or providing mechanical stress relief.

[0028] The advantages offered by the disclosed custom LF include reduced time and cost for LF orders, standardized LF and IC bump designs to reduce the number of masks required. Furthermore, additive manufacturing of the metal layers allows for flexible design and manufacturing of the LF.

[0029] The disclosed embodiments can be integrated into various assembly processes to form a wide variety of semiconductor integrated circuit (IC) devices and related products. Assemblies may include a single semiconductor die or multiple semiconductor dies, such as a PoP configuration comprising multiple stacked semiconductor dies. Various packaging substrates can be used. The semiconductor die may include various elements and / or include various layers thereon, including barrier layers, dielectric layers, device structures, active and passive elements, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Furthermore, the semiconductor die can be formed using various processes, including bipolar transistors, insulated-gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0030] Those skilled in the art to which this disclosure pertains will understand that many other embodiments and variations thereof are possible within the scope of the claimed invention, and that further additions, deletions, substitutions, and modifications may be made to the described embodiments without departing from the scope of this disclosure.

Claims

1. A semiconductor packaging method, comprising: A leadframe strip is provided, the leadframe strip comprising a plurality of leadframes, each leadframe comprising a metal structure and a dielectric support material, the metal structure comprising metal leads on at least two sides, and the dielectric support material being located in the gaps between the metal structures; A printed metal precursor material is additively deposited on at least a portion of the metal leads, and then sintered or cured to form a printed lead frame portion, the printed lead frame portion including printed metal traces that connect to at least one of the metal leads above the dielectric support material and extend inwardly from the metal leads, and The die is mounted upside down on the printed lead frame portion.

2. The method of claim 1, wherein the printed metal precursor material comprises ink, the ink comprising a solid material or a material for a solid precursor, the precursor forming a solid after the curing or sintering, wherein the ink comprises copper or silver nanoparticles.

3. The method according to claim 1, wherein the printed lead frame portion comprises: A flip-chip pad is connected to the metal trace and is at least partially above the dielectric support material.

4. The method according to claim 1, wherein the printed lead frame portion has a greater porosity than the metal structure of the lead frame, a lower mechanical strength than the metal structure of the lead frame, and a lower electrical conductivity than the metal structure of the lead frame.

5. The method according to claim 1 further includes molding and then monolithically forming the lead frame strip.

6. The method according to claim 1, further comprising: Multiple preliminary candidate leadframe designs are determined, which meet the requirements of the die, including the number of inputs or outputs (I / O) and the location of bump features. By simulating the initial candidate leadframes to quantify their performance, a set of candidate leadframe designs that meet the die requirements are created, thereby narrowing down the number of initial candidate leadframes to identify candidate leadframes. The determination and reduction are repeated for at least one other die that has some similarities in the number of I / Os and package size; a set of candidate custom leadframe designs are created for different integrated circuit devices including the said die and the other dies that have similar numbers of the said I / Os and die sizes; And based on common features among two or more of the candidate custom leadframe designs, a custom leadframe design including the leadframe and the printed leadframe portion is generated.

7. The method of claim 1, wherein the dielectric support material is provided by the top dielectric layer of the molded interconnect substrate, i.e., the MIS.

8. The method of claim 1, wherein the additive deposition comprises using piezoelectric, thermal, acoustic inkjet printing, or electrostatic inkjet printing, screen printing, or flexographic printing.

9. The method of claim 1, wherein the surface of the lead frame includes nano-roughening.

10. The method of claim 1, wherein the metal structure further comprises at least one floating lead isolated from the metal leads by the dielectric support material, and wherein the printed lead frame portion contacts the floating lead.

11. The method of claim 1, wherein the printed metal has a porosity greater than 10%.

12. The method of claim 1, wherein at least some of the metal leads have a first end extending away from the center of the lead frame and a second end extending toward the center of the lead frame, and wherein each printed metal trace has a first end deposited on the second end of one of the metal leads.

13. The method of claim 12, wherein each printed metal trace extends from the second end of one of the metal leads toward the center of the lead frame.

14. A packaged semiconductor device, comprising: Core; Custom leadframe, which includes: A metal structure comprising metal leads on at least two sides; A dielectric support material located in the gap between the metal leads; and A printed metal having a printed lead frame portion that is connected to and extends inwardly from at least one metal lead above the dielectric support material. The die is mounted upside down on the printed lead frame portion.

15. The packaged semiconductor device of claim 14, wherein the printed metal has a greater porosity than the metal structure, a lower mechanical strength than the metal structure, and a lower electrical conductivity than the metal structure, wherein the printed metal comprises copper or silver.

16. The packaged semiconductor device of claim 14, wherein the die includes bonding pads and the printed lead frame portion includes flip-chip pads, wherein the die is flip-mounted to the printed lead frame portion by a bump feature connecting the bonding pads and the flip-chip pads.

17. The packaged semiconductor device of claim 14, wherein the dielectric support material is provided by the top dielectric layer of the molded interconnect substrate, i.e., the MIS.

18. The packaged semiconductor device of claim 14, wherein the surface of the lead frame includes nano-roughening.

19. The packaged semiconductor device of claim 14, wherein the metal structure further comprises at least one floating lead isolated from the metal leads by the dielectric support material.

20. The packaged semiconductor device of claim 14, wherein the printed metal has a porosity greater than 10%.

21. A packaged semiconductor device, comprising: The die has bonding pads; as well as Custom leadframe, which includes: A metal structure comprising metal leads on at least two sides; Dielectric support material, which is located in the gap between the metal leads and is provided by the top dielectric layer of the molded interconnect substrate, i.e., MIS; A printed metal having a printed leadframe portion, the printed leadframe portion comprising: Printed metal traces, which are connected to and extend inwardly therefrom at least one of the metal leads above the dielectric support material; and Flip chip pads, which are connected to the metal traces, The die is flip-mounted onto the printed leadframe portion via a bump feature connecting the bonding pad and the flip-chip pad.

22. The packaged semiconductor device of claim 21, wherein the metal structure further comprises at least one floating lead, and wherein the printed metal comprises copper or silver.

23. A semiconductor packaging method, comprising: A lead frame is provided, the lead frame including metal leads on at least two sides, and the lead frame including a dielectric support material located in the gap between the metal leads; A printed lead frame portion is provided on at least a portion of the metal lead, the printed lead frame portion including printed metal traces that connect to and extend inwardly therefrom at least one of the metal leads above the dielectric support material, and The die is mounted upside down on the printed lead frame portion.

24. The method of claim 23, wherein the printed metal comprises ink, the ink comprising a solid material or a material for a precursor of a solid, the precursor forming a solid after curing or sintering.

25. The method of claim 24, wherein the ink comprises copper or silver nanoparticles.

26. The method of claim 23, wherein the printed metal has a greater porosity than the metal leads of the lead frame, a lower mechanical strength than the metal leads of the lead frame, and a lower conductivity than the metal leads of the lead frame.

27. The method of claim 23, further comprising molding the printed lead frame and the die.

28. The method of claim 23, wherein the dielectric support material is provided by the top dielectric layer of the molded interconnect substrate, i.e., the MIS.

29. The method of claim 23, wherein the metal lead frame is printed by using piezoelectric, thermal, acoustic inkjet printing, or electrostatic inkjet printing, screen printing, or flexographic printing.

30. The method of claim 23, wherein the surface of the lead frame includes nano-roughening.

31. The method of claim 23, wherein the metal lead includes at least one floating lead isolated from the metal lead by the dielectric support material, and wherein the printed lead frame portion contacts the floating lead.

32. The method of claim 23, wherein the printed metal has a porosity greater than 10%.

33. The method of claim 23, wherein one or more of the metal leads have a first end extending away from the center of the lead frame and a second end extending toward the center of the lead frame, and wherein each printed metal trace has a first end deposited on the second end of one of the metal leads.

34. The method of claim 33, wherein each printed metal trace extends from the second end of one or more of the metal leads toward the center of the lead frame.

35. A semiconductor packaging method, comprising: A lead frame is provided, the lead frame including metal leads on at least two sides, and the lead frame including a dielectric support material located in the gap between the metal leads; A printed leadframe portion is provided, the printed leadframe portion including printed metal traces and flip chip pads, the printed metal traces being connected to at least one metal lead above the dielectric support material and extending inwardly from the metal lead, the flip chip pads being connected to the metal traces and located above the dielectric support material; The die is flip-mounted onto the printed lead frame portion by means of bump features connecting the bonding pads of the die and the flip chip pads; as well as Multiple preliminary candidate leadframe designs are determined, which meet the requirements of the die, including the number of inputs or outputs (I / O) and the position of the bump features; By simulating the initial candidate leadframes to quantify their performance, a set of candidate leadframe designs that meet the die requirements are created, thereby narrowing down the number of initial candidate leadframes to identify candidate leadframes. The determination and reduction are repeated for at least one other die that has some similarities in the number of I / Os and package size; a set of candidate custom leadframe designs are created for different integrated circuit devices including the said die and the other dies that have similar numbers of the said I / Os and die sizes; And based on common features among two or more of the candidate custom leadframe designs, a custom leadframe design including the leadframe and printed leadframe portions is generated.

36. A semiconductor packaging method, comprising: A lead frame is provided, the lead frame including metal leads on at least two sides, and the lead frame including a dielectric support material located in the gap between the metal leads; Metal traces are printed on at least a portion of the metal leads and at least a portion of the dielectric support material, the metal traces being connected to at least one of the metal leads above the dielectric support material and extending inward from the metal leads; as well as The die is mounted upside down on the metal trace.

37. The method of claim 36, wherein one or more of the metal leads have a first end extending away from the center of the lead frame and a second end extending toward the center of the lead frame, and wherein each metal trace has a first end deposited on the second end of one or more of the metal leads.

38. The method of claim 37, wherein each metal trace extends from the second end of one or more of the metal leads toward the center of the lead frame.

39. A semiconductor packaging method, comprising: A lead frame is provided, the lead frame including metal leads on at least two sides, and the lead frame including a dielectric support material located in the gap between the metal leads; Metal traces are printed on at least a portion of the metal leads, the metal traces being connected to at least one of the metal leads above the dielectric support material and extending inward from the metal leads and terminating in pads configured to receive bump features on the die. as well as The die is mounted on the metal trace by means of the bump feature connected to the pad.

40. The method of claim 39, wherein one or more of the metal leads have a first end extending away from the center of the lead frame and a second end extending toward the center of the lead frame, and wherein each metal trace has a first end deposited on the second end of one or more of the metal leads.

41. The method of claim 40, wherein each metal trace extends from the second end of one or more of the metal leads toward the center of the lead frame.

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