Semiconductor device including insulating layer

Abstract

A semiconductor device includes: a trench defining an active area in a substrate; a first insulating layer on the bottom surface and side surfaces of the active area in the trench; a shielding layer on the surface of the first insulating layer, the shielding layer including a plurality of spaced-apart particles; a second insulating layer on the shielding layer, in which first charges are captured, the plurality of spaced-apart particles being configured to concentrate second charges having a polarity opposite to the first charges captured in the second insulating layer; and a gap-filling insulating layer on the second insulating layer in the trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0106106 filed on September 5, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Devices and methods according to example embodiments relate to a semiconductor device having a device isolation layer and a method of manufacturing the same. Background Art

[0004] As the integration density of semiconductor devices increases, the design rules of components of semiconductor devices have been reduced. For example, in semiconductor devices that require a large number of transistors, the gate length as a design rule standard may be reduced. Therefore, the voltage and current characteristics of highly reduced semiconductor devices may be degraded. Summary of the invention

[0005] Example embodiments of the inventive concepts are directed to providing a semiconductor device having a structure configured to reduce or prevent a hot electron induced punch-through (HEIP) phenomenon from occurring in a semiconductor device that is scaled down as the integration density of the semiconductor device increases.

[0006] Furthermore, example embodiments of the inventive concepts are directed to providing a method of manufacturing a semiconductor device, by which a structure configured to reduce or prevent the occurrence of a HEIP phenomenon can be efficiently manufactured in a semiconductor device that is shrunk as the integration density of the semiconductor device increases.

[0007] According to an example embodiment, a semiconductor device is provided, comprising: a trench defining an active area in a substrate; a first insulating layer on a bottom surface and a side surface of the trench within the trench; a shielding layer on a surface of the first insulating layer, the shielding layer comprising a plurality of spaced-apart particles; a second insulating layer on the shielding layer; and a gap-filling insulating layer on the second insulating layer in the trench.

[0008] According to an example embodiment, a semiconductor device is provided, including: a trench defining an active region in a substrate; a first insulating layer on a bottom surface and a side surface of the trench in the trench; a shielding layer on a surface of the first insulating layer, the shielding layer exposing a portion of the surface of the first insulating layer; a second insulating layer on the shielding layer; and a gap-filling insulating layer on the second insulating layer in the trench. The first insulating layer includes a protrusion formed in at least a portion of its surface.

[0009] According to an example embodiment, a semiconductor device is provided, comprising: an active region in a substrate; a device isolation layer defining the active region; a gate structure extending along a first direction disposed on the active region and the device isolation layer; a bit line structure extending along a second direction intersecting the first direction on the gate structure; and a storage node contact portion adjacent to the bit line structure at an end of the active region. The device isolation layer comprises a first insulating layer contacting the active region, a shielding layer comprising a plurality of particles on the first insulating layer, and a second insulating layer on the shielding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A are cross-sectional views of some components of semiconductor devices according to some embodiments of the inventive concept.

[0011] Figure 1B It is shown in Figure 1A Schematic cross-sectional view of the phenomenon that holes and electrons are filled in the region shown in part A of FIG.

[0012] Figure 1C is a cross-sectional view showing a semiconductor device according to some embodiments of the inventive concept, as shown in FIG. Figure 1A An example for comparison.

[0013] Figure 1D are cross-sectional views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0014] Figure 1E and 1F are cross-sectional views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0015] Figures 1G to 1I According to some embodiments of the present invention Figure 1E An enlarged view of portion B.

[0016] Figure 1J and 1K are cross-sectional views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0017] Figure 2A are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0018] Figure 2B Shown along Figure 2A Cross-sectional views taken along lines II′, II-II′ and III-III′.

[0019] Figure 3 is along Figure 2A A cross-sectional view taken along line IV-IV'.

[0020] Figure 4 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0021] Figure 5 Shown along Figure 4 Cross-sectional views taken along lines II', II-II' and III-III'.

[0022] Figure 6 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0023] Figure 7 Shown along Figure 6 Cross-sectional views taken along lines II', II-II' and III-III'.

[0024] Figure 8 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept.

[0025] Fig. 9 Shown along Figure 8 Cross-sectional views taken along lines II', II-II' and III-III'.

[0026] Fig.10 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0027] Fig.11 Shown along Fig.10 Cross-sectional views taken along lines II', II-II' and III-III'.

[0028] Fig.12 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0029] Fig.13 Shown along Fig.12 Cross-sectional views taken along lines II', II-II' and III-III'.

[0030] Fig.14 , 16 18 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0031] Fig.15 , 17 and 19 respectively show the Fig.14 , 16 and cross-sectional views taken along lines II′, II-II′ and III-III′ of FIG. 18 .

[0032] Fig. 20A layout of a first region of a semiconductor device according to some embodiments of the inventive concept is shown.

[0033] Fig.21 Shown along Fig. 20 Cross-sectional views taken along lines V-V', VI-VI' and VII-VII'.

[0034] Fig. 22 are plan views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0035] Fig.23 is along Fig. 22 A cross-sectional view taken along line VIII-VIII'.

[0036] Figures 24 to 29 are diagrams illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0037] Fig.30 is a cross-sectional view of a semiconductor device according to another embodiment of the inventive concept. DETAILED DESCRIPTION

[0038] The inventive concept will now be described more fully with reference to the accompanying drawings in which example embodiments of the inventive concept are shown. Throughout this application, the same reference numerals may refer to the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items. It should be noted that the various aspects described for one embodiment may be incorporated into different embodiments, although not specifically described in this regard. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0039] Figure 1A are cross-sectional views of some components of semiconductor devices according to some embodiments of the inventive concept. Figure 1B It is shown in Figure 1A Schematic cross-sectional view of the phenomenon that holes and electrons are filled in the region shown in part A of FIG. Figure 1C is a cross-sectional view showing a semiconductor device according to some embodiments of the inventive concept, as shown in FIG. Figure 1A An example for comparison. Figure 1D are cross-sectional views of some components of semiconductor devices according to further embodiments of the inventive concept.

[0040] refer to Figure 1A, the semiconductor device may include a substrate 101 and a device isolation layer 20. A trench 107 defining an active region 102 may be formed in the substrate 101, and the device isolation layer 20 may be disposed in the trench 107. The device isolation layer 20 may have, for example, a shallow trench isolation (STI) structure, which generally has a smaller width and generally has better isolation characteristics.

[0041] In some embodiments, the device isolation layer 20 may include a first insulating layer 22 disposed on the surface of the trench 107, a shielding layer 24 disposed on the first insulating layer 22, a second insulating layer 26 disposed on the shielding layer 24, and a gap-filling insulating layer 28 disposed on the second insulating layer 26. The gap-filling insulating layer 28 may be formed in the trench 107 so as to at least partially fill the trench 107. The first insulating layer 22 and the gap-filling insulating layer 28 may be formed of oxide, and the second insulating layer 26 may be formed of nitride. The shielding layer 24 may include, for example, polysilicon doped with impurities, tungsten, and / or titanium nitride. The shielding layer 24 may include polysilicon doped with oxygen, nitrogen, and / or carbon. However, the embodiments of the inventive concept are not limited thereto.

[0042] Semiconductor device (wherein according to some embodiments Figure 1A The structure shown may be expanded) may be a transistor semiconductor device, which may further include a gate structure (eg, Fig. 20 and Fig.21 Of these, 130 Fig. 22 and Fig.23 140 of them, and Fig.30 For example, when the gate structure constitutes a portion of a p-type metal oxide semiconductor (pMOS) field effect transistor (pMOSFET), electrons may be trapped in a portion of the device isolation layer 20, and holes h+ may be charged on the opposite side of the portion of the device isolation layer 20.

[0043] refer to Figure 1A and Figure 1B As semiconductor devices shrink dramatically, the electric field between channels may increase rapidly and many hot electrons may be generated. For example, in a pMOS transistor, holes as carriers may collide with the lattice of the drain region where a high electric field is applied, which may generate electron-hole pairs and generate many hot electrons.

[0044] Hot electrons may penetrate the device isolation layer and be trapped in the nitride layer. That is, because the second insulating layer 26 formed of nitride is provided between the first insulating layer 22 as an oxide layer and the gap-filling insulating layer 28, a potential difference may occur in the second insulating layer 26, so that electrons may be trapped in the second insulating layer 26.

[0045] The electrons trapped due to the potential difference may be trapped not only in the nitride layer (i.e., the second insulating layer 26) but also at the interface between the conductive shielding layer 24 (e.g., polysilicon doped with impurities) and the second insulating layer 26. For example, the position of the trapped electrons may correspond to internal lattice defects of the second insulating layer 26 and / or defects present at the interface between the shielding layer 24 and the second insulating layer 26.

[0046] The trapped electrons may attract holes h+ having an opposite type of charge due to electrical attraction, and the holes h+ may be mainly concentrated and charged into the shielding layer 24. That is, due to the presence of the shielding layer 24, the ability of the trapped electrons to attract holes h+ into the active region 102 of the semiconductor substrate 101 may be reduced. Therefore, even if the electrons are trapped in the device isolation layer 20, the holes h+ may not be concentrated in the active region 102 of the semiconductor substrate 101 adjacent to the device isolation layer 20.

[0047] Since the holes h+ are not concentrated in the active region 102 of the semiconductor substrate 101 adjacent to the device isolation layer 20, the length of the effective channel formed in the active region 102 may not change, and thus the possibility of abnormal operation of the semiconductor device may be reduced or prevented.

[0048] In some embodiments, the shielding layer 24 may include particles spaced apart from each other. Although the particles are shown as being spaced apart from each other at regular intervals, the distribution of the particles is not limited thereto, and the particles may be spaced apart from each other at irregular intervals. According to various embodiments of the inventive concept, the plurality of particles may have different sizes and shapes.

[0049] A conductive structure (eg, Fig.21 Therefore, when the top end of the shielding layer 24 is exposed on the top surface of the semiconductor substrate 101, that is, when the top end of the shielding layer 24 is at the same height as the top surface of the semiconductor substrate 101, the conductive structure may contact the shielding layer 24, thereby degrading one or more operating capabilities of the device.

[0050] In order to reduce the possibility of the above phenomenon or prevent the above phenomenon, according to some embodiments of the present invention, the shielding layer 24 can be formed by a plurality of particles spaced apart from each other to obtain separation between the plurality of particles. Therefore, the contact between the shielding layer 24 and the conductive structure can be reduced or prevented. In addition, even if the particles of the shielding layer 24 are in contact with the conductive structure, the operation of the device will not be affected. Therefore, the shielding layer 24 including a plurality of particles can reduce the possibility of the hot electron induced punch-through (HEIP) phenomenon or prevent the hot electron induced punch-through (HEIP) phenomenon, and can also reduce or prevent device defects caused by the conductive structure.

[0051] refer to Figure 1C ,and Figure 1A Different, the semiconductor device may not include the shielding layer 24. As the semiconductor device is drastically reduced, the electric field between the channels may be greatly increased, and many hot electrons may be generated. The hot electrons may penetrate the device isolation layer 20 and be captured in the second insulating layer 26 formed of nitride. That is, because the second insulating layer 26 formed of nitride is disposed between the first insulating layer 22 formed of oxide and the gap-filling insulating layer 28, a potential difference may be generated in the second insulating layer 26, so that the electrons e- may be captured in the second insulating layer 26. The electrons e- captured due to the potential difference may not only be captured in the second insulating layer 26, but may also be captured at the interface between the first insulating layer 22 and the second insulating layer 26.

[0052] The trapped electrons e- can attract holes h+ with opposite type of charge due to electrical attraction. The holes h+ can be concentrated and charged into the active region 102 of the semiconductor substrate 101 adjacent to the device isolation layer 20. When the holes h+ are concentrated into the active region 102 adjacent to the device isolation layer 20, the length of the effective channel can be less than the original length. Therefore, even when no voltage is applied to the gate, current may flow, the threshold voltage may be reduced, and the leakage current may increase. This may lead to one or more device defects. This phenomenon may be referred to as hot electron induced punch-through (HEIP). In a pMOS region where holes h+ are the main carriers and Vpp is applied at a high voltage, the HEIP phenomenon may be problematic. However, as described above, because Figure 1A As shown, the shielding layer 24 exists, the holes h+ are neither concentrated nor filled into the active region 102 of the semiconductor substrate 101, and the HEIP phenomenon can be alleviated or prevented.

[0053] refer to Figure 1D The device isolation layer 30 may include a first insulating layer 32 , a shielding layer 34 , a second insulating layer 36 , and a gap-filling insulating layer 38 .

[0054] In some embodiments of the present inventive concept, the shielding layer 34 may include a liner 34a and a plurality of particles 34b. The liner 34a may extend along the side surface and the bottom surface of the first insulating layer 32. The liner 34a may at least partially cover the lower side surface of the first insulating layer 32, and may not cover or expose the upper side surface of the first insulating layer 32. The top end of the liner 34a may be formed at a height lower than the top surface of the semiconductor substrate 101 so as to be located in the recessed area thereof, and may be spaced apart from the top surface of the semiconductor substrate 101 by a predetermined depth. When the predetermined depth is too small, device defects may occur due to contact between the conductive structure and the liner 34a. Therefore, the predetermined depth may be appropriately controlled based on the characteristics of the semiconductor device.

[0055] A plurality of particles 34b may be disposed on the first insulating layer 32 and spaced apart from the liner 34a. The plurality of particles 34b may be disposed separately from each other. As described above, the plurality of particles 34b may be spaced apart so that the HEIP phenomenon may be mitigated or prevented, and device defects due to contact with the conductive structure may also be prevented or the influence thereof may be reduced.

[0056] Figure 1E and 1F are cross-sectional views of some components of semiconductor devices according to some embodiments of the inventive concept. Figures 1G to 1I According to some embodiments Figure 1E An enlarged view of section B. Figures 1A to 1I In the figure, the same reference numerals represent the same elements. Figures 1A to 1D The same description is given for the embodiments of the present invention.

[0057] refer to Figure 1E and 1G , the device isolation layer 40 may include a first insulating layer 42, a shielding layer 44, a second insulating layer 46, and a gap-filling insulating layer 48. In some embodiments, the first insulating layer 42 may include a liner unit 42a and a protrusion 42b, the liner unit 42a being conformally formed in the groove 107, and the protrusion 42b protruding from the liner unit 42a into the groove 107. The surface of the first insulating layer 42 on which the protrusion 42b is formed may have a rough or irregular shape. The protrusion 42b may be disposed in the upper portion of the groove 107. For example, the protrusion 42b may be disposed at a depth d1 of about 100 mm from the top of the first insulating layer 42 (or the top of the groove 107). The protrusion 42b may be provided separately from the shielding layer 44. The protrusion 42b may be formed by oxidizing a portion of the shielding layer 44 due to a subsequent heat treatment process or the like performed after forming the device isolation layer 40.

[0058] refer to Figure 1E and1H , a portion of the protrusion 42b may be in contact with the shielding layer 44. Since a subsequent process performed after forming the device isolation layer 40 acts on the device isolation layer 40, when the shielding layer 44 is disposed on a higher portion of the trench 107, an oxidation process may easily occur due to the subsequent process. Therefore, some of the plurality of particles of the shielding layer 44 may not be completely oxidized, but only the upper portion of the particles of the shielding layer 44 may be oxidized, and the unoxidized portion of the shielding layer 44 may be in contact with the oxidized portion thereof. The oxidized portion of the shielding layer 44 may form the protrusion 42b of the first insulating layer 42.

[0059] refer to Figure 1E and 1I , some of the particles of the shielding layer 44 may be disposed on the protrusion 42b. The portion of the shielding layer 44 in contact with the first insulating layer 42 may be oxidized, and the oxidized portion of the shielding layer 44 may form the protrusion 42b of the first insulating layer 42. Although not shown, according to different embodiments Figure 1H and Fig. 1I The shielding layer 44 and the first insulating layer 42 shown in FIG. 4 may be integrated into the first insulating layer.

[0060] refer to Figure 1F , the shielding layer 44 may include a liner 44a and a plurality of particles 44b. Figure 1F Part C can correspond to Figures 1G to 1I Any one of .

[0061] Figure 1J and 1K 1 is a cross-sectional view of some components of a semiconductor device according to some embodiments of the present inventive concept. Figures 1A to 1K In the figure, the same reference numerals represent the same elements. Figures 1A to 1I The same description is given for the embodiments of the present invention.

[0062] refer to Figure 1J , the shielding layer 44 may be formed as a liner type and conformally cover a portion of the first insulating layer 42. The liner type shielding layer 44 may be spaced apart from the protrusions 42b provided on the first insulating layer 42 and at least partially cover the lower sidewall and bottom surface of the first insulating layer 42.

[0063] refer to Figure 1K , the top end of the liner type shielding layer 44 may contact the lower end of the protrusion 42b. The protrusion 42b of the first insulating layer 42 may be formed by oxidizing not only the grains of the shielding layer 44 but also the top end of the liner layer.

[0064] Figure 2A are plan views of some components of semiconductor devices according to some embodiments of the inventive concept. Figure 2B Shown along Figure 2A Cross-sectional views taken along lines II′, II-II′ and III-III′. Figure 3 is along Figure 2A A cross-sectional view taken along line IV-IV'.

[0065] refer to Figure 2A and 2B , a semiconductor device according to some embodiments of the inventive concept may include a substrate 101 having a first region Cell and a second region Core / Peri, the first region Cell and the second region Core / Peri having corresponding active regions of different densities.

[0066] The substrate 101 may be a semiconductor substrate 101, such as a silicon wafer. The substrate 101 may include, but is not limited to, single crystal silicon, polycrystalline silicon, or amorphous silicon. The substrate 101 may include at least one material selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 101 may include a conductive region.

[0067] The first region Cell may be a high-density region including an active region of relatively high density, and the second region Core / Peri may be a low-density region including an active region of relatively low density.

[0068] The first region Cell may be a cell array region of a semiconductor memory device. For example, a volatile memory cell array such as a dynamic random access memory (DRAM) may be formed in the first region Cell. Alternatively, a nonvolatile memory cell array such as a flash memory may be formed in the first region Cell.

[0069] A peripheral circuit electrically connected to the cell array formed in the first region Cell may be formed in the second region Core / Peri. The second region Core / Peri may include an area (e.g., a core area) where the cell array is not formed. Hereinafter, a "peripheral circuit area" may refer to an area or a core area in which the above-mentioned peripheral circuit is formed.

[0070] The semiconductor device may include a cell active region 104 and a cell device isolation layer 110 in the first region Cell. The cell device isolation layer 110 may define the cell active region 104.

[0071] Each unit active region 104 may include a top surface having a short axis S along the first direction and a long axis L along the second direction. Each unit active region 104 may include a short sidewall S1 having the same or similar width as the short axis S and a long sidewall L1 parallel to the long axis L.

[0072] A plurality of unit active regions 104 may be formed. The plurality of unit active regions 104 may be spaced apart from each other by a first width P1 in the first direction. In addition, the plurality of unit active regions 104 may be spaced apart from each other by a second width P2 in the second direction, and the second width P2 may be greater than the first width P1.

[0073] The plurality of unit active regions 104 may be repeatedly and regularly arranged in the first direction and the second direction. The plurality of unit active regions 104 may be arranged in a zigzag configuration and may only partially overlap each other in the first direction. The plurality of unit active regions 104 may be arranged in a row in the second direction.

[0074] In some embodiments, the cell device isolation layer 110 may include a first insulating layer 112 , a cell shielding layer 114 , and a second insulating layer 116 .

[0075] The first insulating layer 112 may at least partially surround each of the plurality of unit active regions 104 between the plurality of unit active regions 104 spaced apart from each other. For example, the first insulating layer 112 may contact the long sidewalls L1 of the unit active regions 104 and extend in the second direction, and also contact the short sidewalls S1 of the unit active regions 104 and extend in the first direction.

[0076] In some embodiments of the present inventive concept, the thickness of the first insulating layer 112 may be less than half of the first width P1. Therefore, a residual space may be formed between the first insulating layers 112, and the residual space extends continuously in the first direction and the second direction. In some embodiments, the first insulating layer 112 may be formed of oxide.

[0077] The unit shielding layer 114 may include a plurality of particles and is disposed on the first insulating layer 112. The plurality of particles may be spaced apart from each other, and the surface of the first insulating layer 112 may be exposed between the spaced apart particles. Although the particles are shown as being spaced apart from each other by a constant distance, embodiments of the inventive concept are not limited thereto, and the particles may be spaced apart from each other by an irregular or varying distance. The plurality of particles may have different sizes and shapes. The unit shielding layer 114 may include, for example, one or more materials, including but not limited to polysilicon, tungsten, or titanium nitride doped with impurities.

[0078] The second insulating layer 116 may be disposed on the unit shielding layer 114. In some embodiments, the second insulating layer 116 may extend continuously in the first direction and the second direction. The second insulating layer 116 may at least partially cover the particles of the unit shielding layer 114 and contact the surface of the first insulating layer 112 exposed between the particles. The second insulating layer 116 may at least partially cover both the inner wall of the first insulating layer 112 and the unit shielding layer 114. The second insulating layer 116 may be disposed in the remaining space formed between the first insulating layers 112 to partially fill or substantially completely fill the remaining space formed between the first insulating layers 112. The side surface and the bottom surface of the second insulating layer 116 may be at least partially surrounded by the first insulating layer 112. In some embodiments, the second insulating layer 116 may be formed of nitride.

[0079] The semiconductor device according to some embodiments of the present inventive concept may include a peripheral active region 106 and a peripheral device isolation layer 120 in the second region Core / Peri. A plurality of peripheral active regions 106 may be formed. The peripheral device isolation layer 120 may define the peripheral active region 106 and have a third width P3 greater than the first width P1 of the cell device isolation layer 110.

[0080] In some embodiments of the present inventive concept, the peripheral device isolation layer 120 may include a first insulating liner 122 , a peripheral shielding layer 124 , a second insulating liner 126 , and a gap-filling insulating layer 128 .

[0081] The first insulating liner 122 may contact the sidewalls of the peripheral active regions 106 between the plurality of peripheral active regions 106 spaced apart from each other. For example, the thickness of the first insulating liner 122 may be similar to or equal to the thickness of the first insulating layer 112. In some embodiments of the present inventive concept, the first insulating liner 122 may be formed of the same material as the first insulating layer 112. In some embodiments, the first insulating liner 122 may include an oxide.

[0082] The peripheral shielding layer 124 may be disposed on the first insulating liner 122 and include a plurality of particles. The plurality of particles may be spaced apart from each other, and the surface of the first insulating liner 122 may be exposed between the spaced apart particles. Although the particles are shown as being spaced apart from each other by a constant distance, embodiments of the inventive concept are not limited thereto, and the particles may be spaced apart from each other by an irregular or varying distance. The plurality of particles may have different sizes and shapes. In some embodiments, the peripheral shielding layer 124 may include a material similar to or the same material as the unit shielding layer 114. The peripheral shielding layer 124 may include, for example, one or more materials, including but not limited to polysilicon doped with impurities, tungsten, and titanium nitride.

[0083] The second insulating liner 126 may be disposed on the peripheral shielding layer 124. The second insulating layer 126 may at least partially cover the particles of the peripheral shielding layer 124 and contact the surface of the first insulating liner 122 exposed between the particles. The second insulating liner 126 may at least partially cover both the inner wall of the first insulating liner 122 and the peripheral shielding layer 124. A residual space may be formed between the second insulating liners 126. The side surface and the bottom surface of the second insulating liner 126 may be at least partially surrounded by the first insulating liner 122. In some embodiments of the present inventive concept, the second insulating liner 126 may be formed of a material similar to or the same material as the second insulating layer 116. In some embodiments, the second insulating liner 126 may be formed of a nitride.

[0084] A gap-filling insulating layer 128 may be disposed on the second insulating liners 126. The gap-filling insulating layer 128 may be disposed in a remaining space formed between the second insulating liners 126 to partially fill or substantially completely fill the remaining space formed between the second insulating liners 126. In some embodiments, the gap-filling insulating layer 128 may include oxide.

[0085] refer to Figure 3 , the peripheral shielding layer 124 may include a plurality of particles, the surfaces of which are at least partially surrounded by the second insulating liner 126. The plurality of particles may be spaced apart from each other on the same plane. In some embodiments of the present inventive concept, the plurality of particles may have different sizes and shapes. For example, in some embodiments, the particles may have a size of about to about and in other embodiments, the particles may have a thickness of about to about The thickness of the present invention is not limited thereto. For example, according to various embodiments of the present invention, the plurality of particles 124a may have a shape such as a sphere or a hemispherical shape. The plurality of particles 124a, 124b, 124c, 124d, and 124e may have a shape formed by combining spherical or hemispherical particles.

[0086] Figure 4 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Figure 5 Shown along Figure 4 The cross-sectional view taken along the lines I-I', II-II' and III-III'. Figures 1A to 5 In the figure, the same reference numerals represent the same elements. Figures 1A to 3 The same description is given for the embodiments of the present invention.

[0087] refer to Figure 4 and Figure 5 , the cell device isolation layer 110 according to some embodiments of the inventive concept may include a first insulating layer 112 , a cell shielding layer 114 , and a second insulating layer 116 , and further include a third insulating layer 118 .

[0088] The sum of the thickness of the second insulating layer 116 and the thickness of the first insulating layer 112 may be greater than half of the first width P1 but less than half of the second width P2 .

[0089] The third insulating layer 118 may be disposed between the plurality of unit active regions 104 spaced apart from each other by the second width P2 in the second direction. The third insulating layer 118 may be formed on the second insulating layer 116. The side surface and the bottom surface of the third insulating layer 118 may be at least partially surrounded by the second insulating layer 116. In some embodiments, the third insulating layer 118 may be formed of a material similar to or the same as the gap-filling insulating layer 128. In some embodiments, the third insulating layer 118 may be formed of an oxide.

[0090] The peripheral device isolation layer 120 may include a first insulating liner 122, a peripheral shielding layer 124, a second insulating liner 126, and a gap-filling insulating layer 128. In some embodiments of the present inventive concept, the sum of the thickness of the first insulating liner 122 and the thickness of the second insulating liner 126 may be greater than half of the first width P1 but less than half of the second width P2.

[0091] Figure 6 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Figure 7 Shown along Figure 6 The cross-sectional view taken along the lines I-I', II-II' and III-III'. Figures 1A to 7 In the figure, the same reference numerals represent the same elements. Figures 1A to 5 The same description is given for the embodiments of the present invention.

[0092] refer to Figure 6 and Figure 7 , a semiconductor device according to some embodiments of the inventive concept may include a cell device isolation layer 110 in a cell region and a peripheral device isolation layer 120 in a peripheral region. The cell device isolation layer 110 may define a cell active region 104, and the peripheral device isolation layer 120 may define a peripheral active region 106.

[0093] In some embodiments, the cell device isolation layer 110 may include a first insulating layer 112. The first insulating layer 112 may be in contact with the sidewalls of the plurality of cell active regions 104 between the plurality of cell active regions 104. In some embodiments of the present inventive concept, the first insulating layer 112 may be in contact with the long sidewalls L1 of the cell active regions 104 and extend continuously in the second direction. The first insulating layer 112 may be in contact with the short sidewalls S1 of the cell active regions 104 and extend continuously in the first direction. The first insulating layer 112 may be disposed in the space between the plurality of cell active regions 104 so as to partially fill or substantially completely fill the space between the plurality of cell active regions 104.

[0094] Figure 6 and 7 An example is shown in which the cell device isolation layer 110 includes only the first insulating layer 112. However, the embodiments of the inventive concept are not limited thereto, and according to various embodiments of the inventive concept, the cell device isolation layer 110 may include the first insulating layer 112 and other elements. For example, the cell device isolation layer 110 may include a void region formed inside and / or around the first insulating layer 112.

[0095] The peripheral device isolation layer 120 may include a first insulating liner 122, a peripheral shielding layer 124, a second insulating liner 126, and a gap-filling insulating layer 128. In some embodiments of the present inventive concept, the thickness of the first insulating liner 122 may be equal to or greater than half of the second width P2 corresponding to a separation distance between the cell active regions 104 in the second direction when viewed in a plan view of the semiconductor device.

[0096] Figure 8 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Fig. 9 Shown along Figure 8 The cross-sectional view taken along the lines I-I', II-II' and III-III'. Figures 1A to 8 In the figure, the same reference numerals represent the same elements. Figures 1A to 7 The same description is given for the embodiments of the present invention.

[0097] refer to Figure 8 and Fig. 9 , the cell device isolation layer 110 may include a first insulating layer 112 and a second insulating layer 116 .

[0098] The first insulating layer 112 may be formed between a plurality of unit active regions 104 spaced apart from each other, and in contact with the sidewalls of the plurality of unit active regions 104. The first insulating layer 112 may extend continuously in the first direction and the second direction without interruption. The thickness of the first insulating layer 112 may be greater than half of the first width P1 (corresponding to the separation distance between adjacent unit active regions 104 in the first direction when viewed in a plan view of the semiconductor device) but less than half of the second width P2 (corresponding to the separation distance between adjacent unit active regions 104 in the second direction when viewed in a plan view of the semiconductor device). The first insulating layer 112 may form a recess between the unit active regions 104 spaced apart from each other in the second direction.

[0099] The second insulating layer 116 may be disposed between the plurality of unit active regions 104 spaced apart from each other along a straight line in the second direction. The second insulating layer 116 may be disposed on the first insulating layer 112. The side surface and the bottom surface of the second insulating layer 116 may be at least partially surrounded by the first insulating layer 112. The second insulating layer 116 may be disposed in a recess having the first insulating layer 112 as a sidewall so as to partially fill or substantially completely fill the recess having the first insulating layer 112 as a sidewall.

[0100] The peripheral device isolation layer 120 may include a first insulating liner 122, a peripheral shielding layer 124, a second insulating liner 126, and a gap-filling insulating layer 128. The thickness of the first insulating liner 122 may be greater than half of the first width P1 and less than half of the second width P2. The sum of the thickness of the first insulating liner 122 and the thickness of the second insulating liner 126 may be greater than half of the second width P2 and less than half of the third width P3.

[0101] Fig.10 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Fig.11 Shown along Fig.10 The cross-sectional view taken along the lines I-I', II-II' and III-III'. Figures 1A to 10 In the figure, the same reference numerals represent the same elements. Figures 1A to 9 The same description is given for the embodiments of the present invention.

[0102] refer to Fig.10 and Fig.11 The cell device isolation layer 110 may include a first insulating layer 112 , a cell shielding layer 114 , and a second insulating layer 116 . The peripheral device isolation layer 120 may include a first insulating liner 122 , a peripheral shielding layer 124 , a second insulating liner 126 , and a gap-filling insulating layer 128 .

[0103] The first insulating layer 112 may be formed between a plurality of unit active regions 104 spaced apart from each other, and contact the sidewalls of the plurality of unit active regions 104. The first insulating layer 112 may extend continuously in the first direction and the second direction without interruption. The thickness of the first insulating layer 112 may be greater than half of the first width P1 (corresponding to the separation distance between adjacent unit active regions 104 in the first direction when viewed in a plan view of the semiconductor device) but less than half of the second width P2 (corresponding to the separation distance between adjacent unit active regions 104 in the second direction when viewed in a plan view of the semiconductor device). The first insulating layer 112 may define a recess between a plurality of unit active regions 104 spaced apart from each other in the second direction.

[0104] The cell shielding layer 114 may include a plurality of particles. The plurality of particles may be disposed on the first insulating layer 112 and disposed in a recess having the first insulating layer 112 as a sidewall. In some embodiments of the present inventive concept, although the plurality of particles are not disposed between the cell active regions 104 spaced apart from each other by a first width P1, the plurality of particles may be disposed between the cell active regions 104 spaced apart from each other by a second width P2.

[0105] The second insulating layer 116 may be disposed between a plurality of unit active regions 104 spaced apart from each other along a straight line in the second direction. The second insulating layer 116 may be disposed on the first insulating layer 112. The second insulating layer 116 may at least partially cover particles of the unit shielding layer 114 and contact the surface of the first insulating layer 112 exposed between the particles. The second insulating layer 116 may at least partially cover both the inner wall of the first insulating layer 112 and the unit shielding layer 114. The second insulating layer 116 may be disposed in a recess having the first insulating layer 112 as a side wall so as to partially fill or substantially completely fill the recess having the first insulating layer 112 as a side wall. The side surface and the bottom surface of the second insulating layer 116 may be at least partially surrounded by the first insulating layer 112.

[0106] Fig.12 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Fig.13 Shown along Fig.12 The cross-sectional view taken along the lines I-I', II-II' and III-III'. Figures 1A to 13 In the figure, the same reference numerals represent the same elements. Figures 1A to 11 The same description is given for the embodiments of the present invention.

[0107] refer to Fig.12 and Fig.13The cell device isolation layer 110 may include a first insulating layer 112 , a cell shielding layer 114 , and a second insulating layer 116 . The peripheral device isolation layer 120 may include a first insulating liner 122 , a peripheral shielding layer 124 , a second insulating liner 126 , and a gap-filling insulating layer 128 .

[0108] The first insulating layer 112 may be elongated in the second direction. When viewed from above in a plan view of the semiconductor device, the first insulating layer 112 may extend parallel to the long sidewalls L1 of the cell active region 104, and a plurality of first insulating layers 112 may be spaced apart from each other in the first direction.

[0109] The first insulating layer 112 may at least partially surround the cell active region 104. The first insulating layer 112 may contact the short sidewalls S1 of the cell active regions 104 disposed adjacent to each other in the second direction, and may be disposed in the space between these cell active regions 104 so as to partially fill or substantially completely fill the space between the cell active regions 104 spaced apart from each other by a second width P2 (corresponding to the separation distance between the adjacent cell active regions 104 in the second direction when viewed in a plan view of the semiconductor device). The first insulating layer 112 may contact the long sidewalls L1 of the cell active regions 104 and extend continuously in the second direction without interruption. The thickness of the portion of the first insulating layer 112 in contact with the short sidewalls S1 may be greater than or equal to half of the second width P2. The thickness of the portion of the first insulating layer 112 in contact with the long sidewalls L1 may be less than half of the first width P1 (corresponding to the separation distance between the adjacent cell active regions 104 in the first direction when viewed in a plan view of the semiconductor device). The first insulating layer 112 may define a trench that may be elongated in the second direction between the cell active regions 104 spaced apart from each other in the first direction.

[0110] The unit shielding layer 114 may be disposed between the unit active regions 104 spaced apart from each other in the first direction, and may not be disposed between the unit active regions 104 spaced apart from each other in the second direction. The unit shielding layer 114 may include a plurality of particles. The plurality of particles may be disposed on the sidewall and / or the bottom surface of the first insulating layer 112. When viewed from above in a plan view of the semiconductor device, the plurality of particles disposed on one sidewall of the first insulating layer 112 elongated in the second direction may be spaced apart from each other in the second direction. When viewed from above in a plan view of the semiconductor device, the plurality of particles may be disposed in a straight line in the second direction.

[0111] The thickness of the first insulating liner 122 may be greater than half of the second width P2. The first insulating liner 122 may be formed simultaneously or uniformly with a portion of the first insulating layer 112 in contact with the short sidewall S1 of the cell active region 104. The first insulating liner 122 may be formed during a different process operation than a portion of the first insulating layer 112 in contact with the long sidewall L1 of the cell active region 104.

[0112] Fig.14 , 16 18 are plan views of some components of semiconductor devices according to some embodiments of the inventive concept. Fig.15 , 17 and 19 respectively show the Fig.14 , 16 and 18 along the lines II′, II-II′ and III-III′. Figures 1A to 18 In the figure, the same reference numerals represent the same elements. Figures 1A to 13 The same description is given for the embodiments of the present invention.

[0113] refer to Fig.14 and Fig.15 The unit device isolation layer 210 may include a first insulating layer 212 , a unit shielding layer 214 , and a second insulating layer 216 . The peripheral device isolation layer 220 may include a first insulating liner 222 , a peripheral shielding layer 224 , and a second insulating liner 226 .

[0114] The cell shielding layer 214 may be disposed on the first insulating layer 212. The cell shielding layer 214 may be a liner formed along the side surface and the bottom surface of the first insulating layer 212. The liner may extend from the bottom surface of the first insulating layer 212 to the side surface of the first insulating layer 212. The cell shielding layer 214 may include, for example, one or more materials including, but not limited to, polysilicon doped with impurities, tungsten, or titanium nitride.

[0115] The second insulating layer 216 may be disposed on the cell shielding layer 214, and the side surface and the bottom surface of the second insulating layer 216 may be at least partially surrounded by the cell shielding layer 214. In some embodiments of the present inventive concept, the second insulating layer 216 may extend continuously in the first direction and the second direction. The second insulating layer 216 may be disposed in the remaining space left after the first insulating layer 212 and the cell shielding layer 214 are formed between the cell active regions 104, so as to partially fill or substantially completely fill the remaining space left after the first insulating layer 212 and the cell shielding layer 214 are formed between the cell active regions 104. For example, the second insulating layer 216 may be formed of nitride.

[0116] The peripheral shielding layer 224 may be disposed on the first insulating liner 222. The peripheral shielding layer 224 may be or correspond to a liner formed along the side surface and the bottom surface (relative to the semiconductor substrate 101 as a bottom reference point on which other structures are formed) of the first insulating liner 222. The liner may extend from the bottom surface of the first insulating liner 222 to the side surface of the first insulating liner 222. The peripheral shielding layer 224 may include, for example, one or more materials, including but not limited to polysilicon doped with impurities, tungsten, or titanium nitride.

[0117] The second insulating liner 226 may be disposed on the peripheral shielding layer 224. The gap-filling insulating layer 228 may be disposed on the second insulating liner 226 and may be disposed in a remaining space left after the first insulating liner 222, the peripheral shielding layer 224, and the second insulating liner 226 are formed between the peripheral active regions 106, so as to partially fill or substantially completely fill the remaining space left after the first insulating liner 222, the peripheral shielding layer 224, and the second insulating liner 226 are formed between the peripheral active regions 106.

[0118] refer to Fig.16 and 17 , the unit shielding layer 214 may include a liner 214a and a plurality of particles 214b. The liner 214a may extend along the side surface and the bottom surface of the first insulating layer 212 (relative to the semiconductor substrate 101 as described above). The liner 214a may at least partially cover the lower side surface of the first insulating layer 212, and may not cover or may expose the upper side surface of the first insulating layer 212. The top of the liner 214a may be formed at a height lower than the top surface of the semiconductor substrate and spaced apart from the top surface of the semiconductor substrate by a predetermined depth. When the predetermined depth is too small, device defects may easily occur due to the contact of the conductive structure with the liner 214a. Therefore, the predetermined depth may be appropriately controlled based on the characteristics of the semiconductor device to reduce defects.

[0119] The plurality of particles 214b may be disposed on the first insulating layer 212 and spaced apart from the liner 214a. The plurality of particles 214b may contact an upper side surface of the first insulating layer 212 where the liner 214a is not formed. The plurality of particles 214b may be disposed separately from each other.

[0120] The liner 214a and the plurality of particles 214b may be formed of a conductive material. For example, the liner 214a and the plurality of particles 214b may include one or more materials, including but not limited to polysilicon, tungsten, or titanium nitride doped with impurities. The liner 214a and the plurality of particles 214b may be formed of the same element or material.

[0121] The peripheral shielding layer 224 may have a configuration similar to or the same as the unit shielding layer 214. For example, the peripheral shielding layer 224 may include a liner 224a that may at least partially cover the sidewalls and the bottom surface of the first insulating liner 222 (as described above relative to the semiconductor substrate 101) and a plurality of particles 224b that are disposed on the first insulating liner 222 and spaced apart from the liner 224a.

[0122] refer to Fig.18 and Fig.19 In the cell region Cell, a plurality of particles 214c may be spaced apart from each other and disposed on the side surface and the bottom surface (as described above relative to the semiconductor substrate 101) of the first insulating layer 212. The plurality of particles 214c may be disposed only on the lower side surface of the first insulating layer 212, and may not be disposed on the upper side surface of the first insulating layer 212.

[0123] The liner 214d may be disposed on the first insulating layer 212 and spaced apart from the plurality of particles 214c. The liner 214d may be disposed on the upper side surface of the first insulating layer 212, but may not be disposed on the lower side surface of the first insulating layer 212 on which the plurality of particles 214c are disposed, or the lower side surface of the first insulating layer 212 on which the plurality of particles 214c are disposed may be exposed. In the peripheral region Core / Peri, the plurality of particles 224c may be spaced apart from each other and disposed on the side surface and the bottom surface (as described above relative to the semiconductor substrate 101) of the first insulating liner 222. The liner 224d may be spaced apart from the plurality of particles 224c and disposed on the upper side surface of the first insulating liner 222.

[0124] Fig. 20 A layout of a first region of a semiconductor device according to some embodiments of the inventive concept is shown. Fig.21 Shown along Fig. 20 The cross-sectional view taken along the lines V-V', VI-VI' and VII-VII'. Figures 1A to 21 In the figure, the same reference numerals represent the same elements. Figures 1A to 19 The same description is given for the embodiments of the present invention.

[0125] refer to Fig. 20 and 21 , a cell active region 104 may be defined by a cell device isolation layer 110 in a first region CELL of a semiconductor device. The cell active region 104 may be arranged in a zigzag configuration along a first direction and arranged in a row along a second direction. As described above, the cell device isolation layer 110 may include a first insulating layer 112, a cell shielding layer 114, and a second insulating layer 116.

[0126] The word line WL may be arranged across the cell active area 104 and extend in the X-axis direction. The word lines WL may be arranged parallel to each other in the Y-axis direction. The bit lines BL may extend on the word lines WL along the Y-axis direction and be arranged parallel to each other in the X-axis direction. The bit lines BL may be connected to the cell active area 104 through a direct contact portion DC. The direct contact portion DC is referred to as a first contact plug DC.

[0127] The storage node contacts BC may be formed between adjacent pairs of the bit lines BL. The storage node contacts BC may be arranged in a row in the X-axis direction and the Y-axis direction. The storage node contacts BC may be referred to as second contact plugs BC.

[0128] A recessed region R for forming a transistor TR may be formed on a substrate 101 of a semiconductor device. The recessed region R may be formed as a linear pattern having a substantially constant width and extending in the X-axis direction. The recessed region R may be formed across the cell active region 104 and the cell device isolation layer 110 to be parallel to each other in the X-axis direction. The recessed region R may be formed in both edge portions of the cell active region 104.

[0129] The transistor TR may be formed in the cell active region 104. Each transistor TR may include a gate structure 130 including a gate insulating film 131, a gate electrode 132, and a gate capping film 133, and each transistor TR may further include a first impurity region 104a and a second impurity region 104b.

[0130] The gate insulating film 131 may be formed on the inner side surface of the recessed region R. The gate insulating film 131 may be formed between the cell active region 104 and the gate electrode 132. For example, the gate insulating film 131 may include one or more materials including but not limited to a thermal oxide film, a silicon oxide film, a silicon oxynitride film, and a high-k material.

[0131] The gate electrode 132 may be disposed on the gate insulating film 131. The cell device isolation layer 110 and the cell active region 104 may face the gate electrode 132, with the gate insulating film 131 therebetween. The top surface of the first insulating layer 112 may be in contact with the bottom surface of the gate insulating film 131 (as described above with respect to the semiconductor substrate 101). The top surface of the second insulating layer 116 may be in contact with the bottom surface of the gate insulating film 131 (as described above with respect to the semiconductor substrate 101). The shielding layer 114 may include a plurality of particles spaced apart from each other, and may not be in contact with the gate insulating film 131.

[0132] The gate electrode 132 may be disposed to partially fill or substantially completely fill a lower portion of the recessed region R. The gate electrode 132 may be formed of a conductive material. In some embodiments, the gate electrode 132 may form a word line.

[0133] The gate covering film 133 may be formed on the gate electrode 132 to at least partially cover the gate electrode 132. The gate covering film 133 may be disposed to partially fill or substantially completely fill an upper portion of the recessed region R. A top surface of the gate covering film 133 may be disposed at the same height as a top surface of the cell active region 104 (relative to the semiconductor substrate 101 as described above). The gate covering film 133 may include an insulating material.

[0134] The first impurity region 104a may be disposed in the cell active region 104 disposed between the pair of gate electrodes 132. The second impurity region 104b may be formed in the cell active region 104 located between the pair of gate electrodes 132. The first impurity region 104a and the second impurity region 104b may be doped with n-type impurities. The first impurity region 104a and the second impurity region 104b may function as a source region and / or a drain region.

[0135] A buffer insulating film pattern 150 may be formed on the cell active region 104 and the cell device isolation layer 110. For example, the buffer insulating film pattern 150 may be formed of one or more materials, including but not limited to silicon oxide, silicon nitride, or a combination thereof. The buffer insulating film pattern 150 may include a single layer or a multilayer structure.

[0136] The bit line structure 160 may include bit lines 161 and 162 and a bit line capping pattern 165. The bit lines 161 and 162 may extend across the word lines WL in the Y-axis direction and be disposed parallel to each other in the X-axis direction. The bit lines 161 and 162 may be connected to the cell active region 104 through a first contact plug DC.

[0137] The bit lines 161 and 162 may include a conductive pattern 161 and a metal containing layer 162. The bit lines 161 and 162 may include a metal containing layer 162 formed on the conductive pattern 161. The bit lines 161 and 162 may have a multi-layer stack structure including the conductive pattern 161 and the metal containing layer 162.

[0138] For example, the conductive pattern 161 may include a polysilicon layer doped with impurities. The metal-containing layer 162 may include one or more metals, such as but not limited to tungsten, titanium, tantalum, etc., or one or more conductive metal nitrides, such as but not limited to nitrides of tungsten, titanium, tantalum, etc. According to various embodiments of the inventive concept, the conductive pattern 161 and the metal-containing layer 162 are not limited to the above materials.

[0139] The bit line capping pattern 165 may be formed on the bit lines 161 and 162. The bit line capping pattern 165 may include the above-described insulating material.

[0140] The first contact plug DC may be disposed to partially fill or substantially completely fill the first contact hole DCH exposing a portion of the cell active region 104, and be electrically connected to the cell active region 104. The first contact hole DCH may pass through the first impurity region 104a of the cell active region 104, the cell device isolation layer 110 adjacent to the first impurity region 104a, and a portion of the gate capping film 133, so that the lower end of the first contact hole DCH may be disposed at a height lower than the top surface (relative to the semiconductor substrate 101 as described above) of the cell active region 104. The first contact plug DC may form a direct contact portion DC configured to connect the bit lines 161 and 162 to the cell active region 104.

[0141] A lower end of the first contact plug DC may be insulated from the gate electrode 132 by the gate capping film 133. In some embodiments, the first contact plug DC may be formed of a conductive material.

[0142] The insulating partition wall 170 may be disposed between the inner side surface of the first contact hole DCH and the first contact plug DC. The insulating partition wall 170 may include an insulating material that is disposed to partially fill or substantially completely fill the inside of the first contact hole DCH and may at least partially surround the side surface of the first contact plug DC. The insulating partition wall 170 may insulate the first contact plug DC from a second contact plug BC adjacent to the first contact plug DC. For example, the insulating partition wall 170 may include a plurality of stacked structures 171 and 172 sequentially stacked on both side surfaces of the bit line structure.

[0143] The second contact plug BC may be disposed to partially fill or substantially completely fill the second contact hole BCH formed between two adjacent bit lines 161 and 162. The second contact plug BC may extend to upper portions of the two adjacent bit lines 161 and 162. The second contact plug BC may form a storage node contact BC.

[0144] In some embodiments, the second contact plug BC may be disposed to partially fill or substantially completely fill the second contact hole BCH, so that a portion of the second contact plug BC may contact the device isolation layer 110. For example, the second contact plug BC may contact the first insulating layer 112 and the second insulating layer 116. In contrast, because the grains of the shielding layer 114 are disposed separately from each other, the second contact plug BC may be disposed in the space between the grains and may not contact the shielding layer 114. However, embodiments of the inventive concept are not limited thereto, and some grains of the shielding layer 114 may contact the second contact plug BC.

[0145] The blocking film 175 may conformally at least partially cover the insulating partition wall 170 , the second contact plug BC, and the bit line capping pattern 165 .

[0146] The landing pad LP may be disposed on the barrier film 175. The landing pad LP may be formed of a metal-containing material. The landing pad LP and the second contact plug BC may be used to connect the lower electrode BE of the capacitor formed on the bit lines 161 and 162 with the cell active region 104. The landing pad LP may be disposed to at least partially overlap the second contact plug BC.

[0147] The landing pad isolation pattern 180 may isolate the landing pads LP from each other in the X-axis direction and the Y-axis direction. The lower electrode BE may be disposed on the landing pad LP.

[0148] The first insulating layer 112 may have a protrusion formed in at least a portion of its surface as described above, although not particularly shown herein. For example, the protrusion may be formed at the top of the first insulating layer 112. The at least a portion of the surface of the first insulating layer 112 where the protrusion is formed (for example, near the top, i.e., adjacent to the gate structure, the bit line structure, or the storage node contact portion) may have a rough or irregular shape.

[0149] Fig. 22 are plan views illustrating some components of a semiconductor device according to some embodiments of the inventive concept. Fig.23 is along Fig. 22 A cross-sectional view taken along line VIII-VIII'. Figures 1A to 23 In the figure, the same reference numerals represent the same elements. Figures 1A to 21 The same description is given for the embodiments of the present invention.

[0150] refer to Fig. 22 and Fig.23 , the semiconductor device may include an active region 106 (in Fig. 22 104, and the like. The active region 106 may be defined by the device isolation layer 120. The active region 106 may include a source region (eg, Fig. 22 SD1 in), drain region (e.g., Fig. 22 The device isolation layer 120 may include a first insulating liner 122, a shielding layer 124, a second insulating liner 126 and a gap-filling insulating layer 128.

[0151] The gate structure 140 may be formed on the active region 106. The gate structure 140 may include a gate insulating layer 141, a gate electrode 142 (in Fig. 22The gate structure 140 may include a gate insulating layer 141 and a gate electrode 142. The gate structure 140 may include a gate capping layer 143. In addition, the gate structure 140 may include a partition wall 144 disposed on both side surfaces of the gate insulating layer 141 and the gate electrode 142. The lower end of the gate structure 140 may contact the device isolation layer 120. The gate structure 140 may contact the first insulating liner 122 and the second insulating liner 126, and may contact some particles included in the shielding layer 124.

[0152] Figures 24 to 29 1 is a diagram showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figures 24 to 29 In the figure, lines II′, II-II′ and III-III′ correspond to Figure 2A Lines II′, II-II′ and III-III′ in FIG.

[0153] refer to Fig.24 , a cell trench 105 defining a cell active region 104 may be formed in the first region Cell of the substrate 101, and a peripheral trench 107 defining a peripheral active region 106 may be formed in the second region Core / Peri. Due to a loading effect and / or reactive ion etching (RIE) lag, the cell trench 105 may be formed to have a depth less than that of the peripheral trench 107 of the second region Core / Peri.

[0154] The cell trench 105 may include a first cell trench 105a having a relatively small width P1 and a second cell trench 105b having a relatively large width P2. For example, the cell trench 105 may include a first cell trench 105a having a depth different from that of the second cell trench 105b. For example, due to RIE hysteresis, the depth of the second cell trench 105b may be greater than the depth of the first cell trench 105a.

[0155] The peripheral trench 107 may have a third width P3 greater than the first width P1. Although the third width P3 is shown as greater than the second width P2, embodiments of the inventive concept are not limited thereto and may be less than or equal to the second width P2 in other embodiments.

[0156] refer to Fig.25, a first insulating layer 312 may be formed on the surfaces of the cell trench 105 and the peripheral trench 107 in the first region Cell and the second region Core / Peri. In some embodiments, the thickness of the first insulating layer 312 may be less than half of the first width P1. However, embodiments of the inventive concept are not limited thereto, and according to other embodiments of the inventive concept, the first insulating layer 312 may be formed to different thicknesses. The first insulating layer 312 may conformally at least partially cover the inner walls of the cell trench 105 and the peripheral trench 107. For example, the first insulating layer 312 may be used to reduce the consumption of the cell active area 104 due to oxidation during a subsequent oxidation process, obtain a cell active area 104 of a desired area, and improve the switching characteristics of the cell transistor.

[0157] For example, the first insulating layer 312 may include a silicon oxide film. The first insulating layer 312 may be formed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a radical oxidation process, a natural oxidation process, or the like.

[0158] refer to Fig.26 , a shielding layer 314 may be formed on the first insulating layer 312 in the first region Cell and the second region Core / Peri. In some embodiments of the present inventive concept, the shielding layer 314 may be formed of a plurality of particles.

[0159] For example, the plurality of particles can be formed using a CVD process or an epitaxial growth process. In some embodiments, hexachlorodisilane (HCD, Si 2 Cl 6 ), dichlorosilane (DCS, SiH 2 Cl 2 ), silane or disilane may be used as a source gas for a process for forming the plurality of particles. The plurality of particles may be formed using a process for forming particles on the first insulating layer 312, and may be formed by omitting an operation of forming a seed layer on the first insulating layer 312. That is, the plurality of particles spaced apart from each other may be formed by performing a fine particle formation process directly on the first insulating layer 312 without using a precursor (e.g., a fine metal film) used as a seed on the first insulating layer 312. For example, the shielding layer 314 including the plurality of particles may be formed using an ALD process or a CVD process.

[0160] refer to Fig. 27 , a second insulating layer 316 may be formed to at least partially cover the first insulating layer 312 and the shielding layer 314. In some embodiments of the present inventive concept, a sum of a thickness of the second insulating layer 316 and a thickness of the first insulating layer 312 may be less than half of the third width P3, so that a remaining space may be left in the peripheral trench 107.

[0161] For example, the second insulating layer 316 may include a silicon nitride film. The second insulating layer 316 may be formed using an ALD process. In other embodiments, the second insulating layer 316 may be formed using a CVD process or the like.

[0162] refer to Fig.28 , a third insulating layer 318 may be formed on the second insulating layer 316. The third insulating layer 318 may be formed to a sufficient thickness to partially fill or substantially completely fill a remaining space of the peripheral trench 107. However, embodiments of the inventive concept are not limited thereto.

[0163] As an example, the gap filling insulating layer may be formed of an oxide film. The gap filling insulating layer may be formed of one or more materials, including but not limited to: Tonen SilaZen (TOSN), high density plasma (HDP) oxide, flowable oxide (FOX), spin-on glass (SOG), undoped silicon glass (USG), tetraethyl orthosilicate (TEOS) and low temperature oxide (LTO).

[0164] refer to Fig.29 The planarization process may be performed until the top surfaces of the cell active region 104 and the peripheral active region 106 are exposed. Due to the planarization process, the top surface of the cell device isolation layer 110 may be at the same height as the top surface of the peripheral device isolation layer 120, thereby being substantially coplanar.

[0165] Fig.30 is a cross-sectional view of a semiconductor device according to some embodiments of the inventive concept.

[0166] refer to Fig.30 The semiconductor device may include an active region 501 formed on a semiconductor substrate, a device isolation layer 510 , a gate structure 560 , a first interlayer insulating layer ILD, a stacked structure SS, a second interlayer insulating layer IMD, and a vertical structure 530 .

[0167] The device isolation layer 510 may define the active region 501. In some embodiments of the present inventive concept, the device isolation layer 510 may include a first insulating layer, a shielding layer, and a second insulating layer, as described above with reference to Figure 1A , 1D and as described in 1E to 1K.

[0168] The gate structure 560 may be disposed on the active region 501, and the first interlayer insulating layer ILD and the stacked structure SS may be disposed on the gate structure 560. The stacked structure SS may include a plurality of insulating layers IL and a plurality of semiconductor layers ML that are alternately and repeatedly stacked. For example, the insulating layer IL may include one or more materials, including but not limited to a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a carbon-containing silicon nitride film, and a carbon-containing silicon oxynitride film. The semiconductor layer ML may include a semiconductor material. The semiconductor material may be an amorphous semiconductor material or a polycrystalline semiconductor material.

[0169] According to various embodiments of the inventive concept, the stack structure SS may include Fig.30 In the cross-sectional view of the semiconductor device, a relatively lower end of the stacked structure SS may extend further in the lateral direction than a relatively higher end of the stacked structure SS (relative to the semiconductor substrate as described above).

[0170] A through hole may be formed to vertically pass through the stacked structure SS. The vertical structure 530 may be arranged to partially fill or substantially completely fill the through hole. The vertical structure 530 may include a conductive wire 531, an insulating wire 532, and a vertical pattern 533, which extend in a substantially vertical direction in a cross-sectional view of the semiconductor device. The conductive wire 531 may include a conductive material, which may be any one or more of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. The conductive wire 531 may constitute a word line WL.

[0171] According to an example embodiment of the inventive concept, in a semiconductor device, a device isolation layer may include a shielding layer having conductivity. The HEIP phenomenon may be mitigated or prevented by the shielding layer. A potential well for electrons e- and holes h+ may be formed in the nitride pattern, so that the accumulation of charges may be suppressed. As a result, the characteristics of the transistor may be maintained or the characteristic variation of the transistor may be suppressed. In addition, the shielding layer may include a plurality of particles spaced apart from each other so that a conductive structure disposed across the device isolation layer may contact the shielding layer, thereby reducing or preventing degradation of device operation.

[0172] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing the basic features. Therefore, the above embodiments should be considered as merely illustrative and not for limiting purposes.

Claims

1. A semiconductor device, comprising: a trench in the substrate defining an active region; a first insulating layer on a bottom surface and a side surface of the trench within the trench; a shielding layer on a surface of the first insulating layer, the shielding layer comprising a plurality of particles spaced apart from each other; a second insulating layer on the shielding layer; as well as filling the gap on the second insulating layer in the trench with an insulating layer, The plurality of particles of the shielding layer are formed on a surface of the first insulating layer and are spaced apart from the gap-filling insulating layer by the second insulating layer.

2. The semiconductor device according to claim 1, wherein The second insulating layer is in contact with the first insulating layer between the plurality of particles.

3. The semiconductor device according to claim 1, wherein The shielding layer includes tungsten, titanium nitride, or polysilicon doped with impurities, or a combination thereof.

4. The semiconductor device according to claim 1, wherein: The shielding layer further comprises a lining layer on the bottom surface and the side surface of the first insulating layer, The plurality of particles are spaced apart from the liner and are located on the upper surface of the first insulating layer.

5. The semiconductor device according to claim 1, wherein The shielding layer further comprises a lining layer on the upper side surface of the first insulating layer, The plurality of particles are spaced apart from the liner and are located on a bottom surface and a side surface of the first insulating layer.

6. The semiconductor device according to claim 1, further comprising: A gate structure extending along a first direction on the active area; A bit line structure extending on the gate structure along a second direction intersecting the first direction; as well as A storage node contact is formed at an end of the active region and is adjacent to the bit line structure.

7. The semiconductor device according to claim 1, further comprising a gate structure on the active region, The gate structure forms a P-type metal oxide semiconductor field effect transistor.

8. A semiconductor device comprising: a trench in the substrate defining an active region; a first insulating layer on a bottom surface and a side surface of the trench within the trench; a shielding layer on the first insulating layer, the shielding layer comprising a plurality of particles spaced apart from each other, with a portion of a surface of the first insulating layer exposed between the plurality of particles; a second insulating layer on the shielding layer; as well as filling the gap on the second insulating layer in the trench with an insulating layer, wherein the plurality of particles of the shielding layer are formed on a surface of the first insulating layer and are separated from the gap-filling insulating layer by the second insulating layer, and The first insulating layer includes a protrusion in at least a portion of its surface.

9. The semiconductor device according to claim 8, wherein: The protrusion is located at a depth of 100Å or less from the top of the groove facing away from the substrate.

10. The semiconductor device according to claim 8, wherein Some of the plurality of particles are in contact with the protrusions.

11. The semiconductor device according to claim 8, wherein The shielding layer further includes a liner layer conformally formed on the first insulating layer, The liner is spaced apart from the plurality of particles.

12. The semiconductor device according to claim 8, wherein The shielding layer includes a liner layer conformally formed on the first insulating layer and spaced apart from the protrusion.

13. The semiconductor device according to claim 8, wherein: The shielding layer includes a liner conformally formed on the first insulating layer, and a top end of the shielding layer facing away from the substrate contacts the protrusion.

14. A semiconductor device comprising: an active region in a substrate; A device isolation layer defining the active area; A gate structure disposed on the active region and the device isolation layer and extending along a first direction; A bit line structure extending on the gate structure along a second direction intersecting the first direction; and a storage node contact portion adjacent to the bit line structure at an end of the active region, The device isolation layer includes a first insulating layer in contact with the active area, a shielding layer on the first insulating layer, a second insulating layer on the shielding layer, and a gap-filling insulating layer on the second insulating layer. The shielding layer includes a plurality of particles formed on a surface of the first insulating layer and spaced apart from the gap-filling insulating layer by the second insulating layer.

15. The semiconductor device according to claim 14, wherein: The plurality of particles are spaced apart from the storage node contacts and the gate structure.

16. The semiconductor device according to claim 14, wherein: Some of the plurality of particles are in contact with the storage node contacts.

17. The semiconductor device according to claim 14, wherein: Some of the plurality of particles are in contact with the gate structure.

18. The semiconductor device according to claim 14, wherein: The shielding layer further includes a liner on a bottom surface and sidewalls of the first insulating layer, the liner being separated from the plurality of particles on the first insulating layer.

19. The semiconductor device according to claim 14, wherein: The first insulating layer includes oxide, the second insulating layer includes nitride, and the shielding layer includes polysilicon doped with oxygen, carbon, or nitrogen.

20. The semiconductor device according to claim 14, wherein A surface of the first insulating layer has an irregular shape at a position adjacent to the gate structure, the bit line structure, or the storage node contact portion.

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