semiconductor devices

Abstract

A semiconductor device includes: a first active fin protruding from a substrate; a first gate pattern covering the side and top surfaces of the first active fin; and first source / drain patterns located on opposite sides of the first gate pattern. Each of the first source / drain patterns includes a first lower side and a second lower side spaced apart from each other, a first upper side extending from the first lower side, and a second upper side extending from the second lower side. The first lower side may be inclined at a first angle relative to the top surface of the substrate, and the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2018-0105788 and No. 10-2019-0037884, filed on September 5, 2018 and April 1, 2019, respectively, with the Korean Intellectual Property Office are hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and in particular to a semiconductor device including a fin field-effect transistor. Background Art

[0004] Semiconductor devices are considered important components in the electronics industry due to their small size, multifunctionality, and / or low cost. Semiconductor devices are classified into memory devices for storing data, logic devices for processing data, and hybrid devices including both memory and logic elements. In order to meet the increasing demand for electronic devices with high speed and / or low power consumption, it is necessary to realize semiconductor devices with high reliability, high performance, and / or multifunctionality.

[0005] To meet these technological requirements, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0006] According to some embodiments, a semiconductor device may include: a first active fin protruding from a substrate; a first gate pattern covering side surfaces and a top surface of the first active fin; and first source / drain patterns located on opposite sides of the first gate pattern, wherein each of the first source / drain patterns includes a first lower side and a second lower side spaced apart from each other, a first upper side extending from the first lower side, and a second upper side extending from the second lower side. The first lower side may be inclined at a first angle relative to the top surface of the substrate, and the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

[0007] According to some embodiments, a semiconductor device may include: a substrate including a first region and a second region; a first active fin protruding from the substrate on the first region; a first source

[0008] A source / drain pattern is provided on the first active fin; a second active fin protruding from the substrate on the second region; and a second source / drain pattern is provided on the second active fin. A maximum width of the first source / drain pattern in the first direction may be different from a maximum width of the second source / drain pattern in the first direction.

[0009] According to some embodiments, a semiconductor device may include: a substrate including a first region and a second region; a first active fin protruding from the substrate on the first region; a first source

[0010] The substrate includes a first active fin and a second active fin protruding from the substrate in the second region; a second source / drain pattern disposed on the second active fin. The first source / drain pattern may have the same shape as the second source / drain pattern, and the first source / drain pattern may have a different size from the second source / drain pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various features will become readily apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0012] Figure 1 A plan view of a semiconductor device according to an embodiment is shown.

[0013] Figure 2 Shown Figure 1 A perspective view of a semiconductor device.

[0014] Figure 3 and Figure 4 Shown are respectively along Figure 1 A cross-sectional view taken along line AA' and line BB'.

[0015] Figure 5 Shown along Figure 1 An enlarged cross-sectional view taken along line CC'.

[0016] Figure 6 、 Figure 7 、 Figure 8A 、 Figure 9 and Figure 10 shows cross-sectional views of various stages in the process of manufacturing a semiconductor device having Figures 3 to 5 The vertical section shown in .

[0017] Figure 8B shows the semiconductor device in Figure 8A Graph showing the change in surface profile of a portion indicated by “P1” in FIG.

[0018] Figures 11 to 14 Each of the semiconductor devices according to the embodiment is shown Figure 1 Various cross-sectional views taken along line CC'.

[0019] Figure 15 A perspective view of a semiconductor device according to an embodiment is shown.

[0020] Figure 16 Shown along Figure 15 A cross-sectional view taken along line AA'.

[0021] Figure 17 Shown along Figure 15 A cross-sectional view taken along line CC'.

[0022] Figure 18 A plan view of a semiconductor device according to an embodiment is shown.

[0023] Figure 19 Shown along Figure 18 Cross-sectional view of the vertical cross-section taken along line AA', line BB' and line CC'.

[0024] Figure 20 Shown along Figure 18 A sectional view of a vertical section taken along line DD' and line EE'.

[0025] Figure 21 Shown along Figure 18 An enlarged cross-sectional view taken along line FF'.

[0026] Figures 22 to 25 Each of the semiconductor devices according to the embodiment is shown Figure 18 Various cross-sectional views taken along line FF'.

[0027] Figure 26 The semiconductor device according to the embodiment is shown along Figure 18 An enlarged cross-sectional view taken along line FF'.

[0028] Figure 27 A plan view of a semiconductor device according to an embodiment is shown.

[0029] Figure 28 Shown along Figure 27 A cross-sectional view taken along line G-G'.

[0030] Figure 29 Shown along Figure 27 A cross-sectional view taken along line H-H'.

[0031] Figure 30 An equivalent circuit diagram of an SRAM cell according to an embodiment is shown.

[0032] Figure 31 A semiconductor device (eg, including Figure 30 A plan view of an SRAM cell).

[0033] Figures 32 to 35 Shown are respectively along Figure 31 Cross-sectional views taken along line II', line JJ', line KK' and line LL'.

[0034] Figure 36 is a cross-sectional view of a semiconductor device including a source / drain pattern according to an embodiment.

[0035] Figure 37 is a cross-sectional view of a semiconductor device including a source / drain pattern according to an embodiment. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0037] Figure 1 is a plan view showing a semiconductor device according to an embodiment. Figure 2 It shows Figure 1 A perspective view of a semiconductor device. Figure 3 and Figure 4 are along Figure 1 A cross-sectional view taken along line AA' and line BB'. Figure 5 It is along Figure 1 An enlarged cross-sectional view taken along line CC'.

[0038] refer to Figures 1 to 5 , a substrate 1 and an active fin AF protruding from the substrate 1 may be provided. A device isolation layer 3 may be provided on the substrate 1 to surround the active fin AF. The active fin AF may have a top surface and an upper side surface located at a higher level than the top surface of the device isolation layer 3. The substrate 1 may be a single crystal silicon wafer or a silicon on insulator (SOI) substrate. The device isolation layer 3 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include at least one of the above materials, and may have a single-layer or multi-layer structure. The active fin AF may be a strip or line pattern extending along the first direction X. The gate electrode GE may be provided to intersect the active fin AF along the second direction Y. The gate electrode GE may include a work function pattern and a metal line pattern.

[0039] The above-mentioned work function pattern may be an n-type work function pattern or a p-type work function pattern. The n-type work function pattern may include, for example, at least one of lanthanum (La), lanthanum oxide (LaO), tantalum (Ta), tantalum nitride (TaN), niobium (Nb), and titanium nitride (TiN). The p-type work function pattern may include, for example, aluminum (Al), aluminum oxide (AlO x ), titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide (RuO2). The metal line pattern may include, for example, at least one of tungsten, copper, and aluminum. The gate electrode GE may further include a diffusion barrier pattern located between the work function pattern and the metal line pattern. The diffusion barrier pattern may include a metal nitride layer (e.g., a titanium nitride layer, a tantalum nitride layer, and a tungsten nitride layer).

[0040] A gate capping pattern GCP may be provided on the gate electrode GE. A gate spacer GSP may be provided to cover the side surface of the gate electrode GE and the side surface of the gate capping pattern GCP. The gate capping pattern GCP may be formed of, for example, a silicon nitride layer or include, for example, a silicon nitride layer. The gate spacer GSP may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include at least one of the above materials, and may have a single-layer or multi-layer structure. A gate insulating layer Gox may be inserted between the active fin AF and the gate electrode GE. The gate insulating layer Gox may be inserted between the gate spacer GSP and the gate electrode GE. The gate insulating layer Gox may include, for example, a silicon oxide layer. In some embodiments, the gate insulating layer Gox may also include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. The high-k dielectric material may include, for example, at least one of hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O3), tantalum oxide (Ta2O3) and lead scandium tantalum oxide (PbScTaO).

[0041] A recessed region R1 may be formed in the active fin AF, adjacent to the gate spacer GSP. A source / drain pattern SD may be disposed in the recessed region R1. The source / drain pattern SD may be an epitaxial layer formed from the same material as the substrate 1. For example, the source / drain pattern SD may be a silicon epitaxial layer. The source / drain pattern SD may also include a material different from that of the substrate 1. For example, the source / drain pattern SD may be a silicon germanium epitaxial layer. The source / drain pattern SD may be doped with n-type or p-type impurities. For example, the source / drain pattern SD may be doped with phosphorus or boron. The source / drain pattern SD may be covered by an interlayer insulating layer 50. The interlayer insulating layer 50 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulating material, and may have a single-layer or multi-layer structure.

[0042] In the following, reference will be made to Figure 5 The source / drain pattern SD is described in more detail. The source / drain pattern SD may include a first lower side 41 and a second lower side 42 spaced apart from each other, a first upper side 43 extending from a top end of the first lower side 41, and a second upper side 44 extending from the second lower side 42. For example, Figure 5As shown, the cross section of the source / drain pattern SD may have a pentagonal shape having a flat bottom located at the top surface of the active fin AF, a first lower side 41 and a second lower side 42 extending upward from the flat bottom and away from each other, and a first upper side 43 and a second upper side 44 extending upward from the first lower side 41 and the second lower side 42, respectively, to contact each other. Figure 5 As shown, the pentagonal shape of the source / drain pattern SD may be symmetrical with respect to its central axis along the Z direction. Figure 5 As shown, the height of the pentagonal shape may be asymmetric, and thus the top of the source / drain pattern SD may be uneven, ie, have sharp edges pointing upward and away from the substrate 1 .

[0043] In detail, the first lower side 41 may be inclined at a first angle θ1 relative to a first line SL1 that connects the bottom end of the first lower side 41 and the bottom end of the second lower side 42 and extends outward. Hereinafter, the point where the first lower side 41 and the first upper side 43 intersect will be referred to as a first point C1, and the point where the second lower side 42 and the second upper side 44 intersect will be referred to as a second point C2. A second line segment SL2 (or second line SL2) connecting the first point C1 to the second point C2 ( Figure 5 The dashed horizontal line in FIG) may be, for example, parallel to the top surface of the substrate 1 and at a second angle θ2 relative to the second upper side 44. Figure 5 As shown, the second line segment SL2 (i.e., the distance connecting the first point C1 and the second point C2) can be the widest portion of the source / drain pattern SD along the Y direction. That is, the distance along the Y direction between the first lower side 41 and the second lower side 42 can decrease as the distance from the second line segment SL2 increases. Similarly, the distance along the Y direction between the first upper side 43 and the second upper side 44 can decrease as the distance from the second line segment SL2 increases.

[0044] The first angle θ1 may be defined as the inclination of the first lower side 41 relative to the top surface of the substrate 1. Figure 5 As shown, the first lower side 41 and the second lower side 42 may be inclined away from each other, and thus the first angle θ1 may be an acute angle. The second angle θ2 may be defined as the slope of the second upper side 44 relative to the top surface of the substrate 1. Here, the first angle θ1 may be greater than the second angle θ2. In some embodiments, the first angle θ1 may be in a range of about 55° to about 65°.

[0045] The first line SL1 and the second line SL2 may be parallel to each other. The first line SL1 and the second line SL2 may be parallel to the top surface 1a of the substrate 1. The first angle θ1 may correspond to the angle between the extension line 41e of the first lower side 41 and the seventh line SL7, which is an extension line of the top surface 1a of the substrate 1. In other words, the first angle θ1 may correspond to the angle between the first lower side 41 and the top surface 1a of the substrate 1. The second angle θ2 may correspond to the angle between the extension line 44e of the second upper side 44 and the first line SL1. The second angle θ2 may correspond to the angle between the extension line 44e of the second upper side 44 and the seventh line SL7. In other words, the second angle θ2 may correspond to the angle between the second upper side 44 and the top surface 1a of the substrate 1.

[0046] Specifically, the second line segment SL2 may have a first length L1, for example, in the Y direction. The first upper side 43 and the second upper side 44, facing each other, may be inclined toward each other and intersect at a third point C3. The extension line 41e of the first lower side 41 may intersect the extension line 42e of the second lower side 42 at a fourth point C4, and the fourth point C4 and the third point C3 may be connected by a third line segment SL3 (or third line SL3). The third line segment SL3 may have a second length L2, for example, in the Z direction. The second line segment SL2 and the third line segment SL3 may intersect each other at a fifth point C5, which is located, for example, at a higher level than the center point of the third line segment SL3 relative to the top surface of the substrate 1 in the Z direction. Therefore, the distance L3 from the third point C3 to the fifth point C5 (hereinafter also referred to as the third length) is shorter than half of the second length L2. For example, the distance L3 may be approximately 0.2 times to approximately 0.45 times the second length L2.

[0047] As the integration density of semiconductor devices increases, the distance between the source / drain patterns of adjacent PMOS and NMOS transistors decreases, thereby increasing the risk of bridging or shorting between the adjacent PMOS and NMOS transistors. However, according to some embodiments, because the first angle θ1 is greater than the second angle θ2, the source / drain pattern SD can have a relatively small width (e.g., a first length L1) in the second direction Y. Therefore, the risk of bridging or shorting between different types of source / drain patterns arranged adjacent to each other can be reduced.

[0048] Figure 6 、 Figure 7 、 Figure 8A 、 Figure 9 and Figure 10 is a cross-sectional view illustrating a process for manufacturing a semiconductor device having Figure 3 、 Figure 4 and Figure 5 The vertical section shown in . Figure 8B is a diagram showing a method according to some embodiments Figure 8A Graph showing the change in surface profile of portion “P1”.

[0049] refer to Figure 1 and Figure 6 , the substrate 1 may be patterned to form the active fins AF. A device isolation layer 3 may be formed on the substrate 1 and etched to expose the top surface and upper side surfaces of the active fins AF. For example, the device isolation layer 3 may be etched to have a top surface lower than the top surface of the active fins AF. The substrate 1 may be a single crystal silicon wafer or an SOI substrate. The device isolation layer 3 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, or include at least one of the foregoing materials, and may have a single-layer or multi-layer structure.

[0050] refer to Figure 1 and Figure 7 , a dummy gate pattern DGP may be formed to intersect the active fin AF. The dummy gate pattern DGP may be formed by sequentially stacking a dummy gate insulating layer 5, a dummy gate layer 7, and a dummy gate capping layer 9 and patterning them. The dummy gate pattern DGP may be formed at Figure 1 The active fin AF may be exposed on both sides of the dummy gate pattern DGP. A spacer layer may be conformally formed on the substrate 1 and anisotropically etched to form a gate spacer GSP. In some embodiments, the gate spacer GSP may be formed to cover the side surfaces of the active fin AF exposed from both sides of the dummy gate pattern DGP. The dummy gate insulating layer 5 may be formed of, for example, or include, a silicon oxide layer. The dummy gate layer 7 may be formed of, for example, a polysilicon layer or include, for example, a polysilicon layer. The dummy gate cap layer 9 may be formed of, for example, a silicon nitride layer or include, for example, a silicon nitride layer.

[0051] refer to Figure 1 、 Figure 7 、 Figure 8A and Figure 8B , an etching process may be performed to partially remove the active fins AF exposed on both sides of the dummy gate pattern DGP, and as a result, a recessed region R1 may be formed in the active fin AF. Here, the gate spacer GSP covering the side surface of the active fin AF may also be etched. The etching process may be an anisotropic etching process. The anisotropic etching process may cause the roughness of the surface SF1 of the recessed region R1 to increase. According to some embodiments, the rough surface SF1 of the recessed region R1 may be changed into a smooth surface SF2. This surface treatment may be achieved by additionally performing an isotropic etching process or a cleaning process and / or by depositing an epitaxial seed layer for forming a source / drain pattern. The epitaxial seed layer may be, for example, a silicon epitaxial layer.

[0052] refer to Figure 5 、 Figure 8A 、 Figure 8B and Figure 9 After the surface treatment for realizing the smooth surface SF2 of the recessed region R1, the source / drain pattern SD may be formed using, for example, a selective epitaxial growth (SEG) process. The source / drain pattern SD grown on the smooth surface SF2 may have a (111) plane and have an area equal to Figure 5 In other words, the first angle θ1 may be in the range of about 55° to about 65°. Therefore, the source / drain pattern SD may have a similar growth angle to the reference electrode. Figure 5 The shape described is the same shape.

[0053] refer to Figure 9 and Figure 10 An interlayer insulating layer 50 may be formed on the substrate 1, and then a chemical mechanical polishing (CMP) process may be performed to expose the top surface of the dummy gate pattern DGP. Next, the dummy gate pattern DGP may be removed, and as a result, a groove 12 may be formed between the inner side surfaces of the gate spacers GSP to expose the active fin AF.

[0054] See also Figures 3 to 5 and Figure 10 , a gate insulating layer Gox and a gate electrode layer may be sequentially formed on the substrate 1 to fill the trench 12, and then, an etch-back process may be performed to form the gate electrode GE in the trench 12. Thereafter, a gate capping pattern GCP may be formed on the gate electrode GE.

[0055] Figures 11 to 14 is a cross-sectional view, each cross-sectional view is taken along Figure 1 1 and 2 are taken along line CC' to illustrate the semiconductor device according to the embodiment.

[0056] refer to Figure 11 , when viewed in the CC' cross-sectional view, the top surface of the device isolation layer 3 may be concave. Figure 8A Compared with the embodiment in FIG. 1 , the upper portion of the device isolation layer 3 can be etched to form a recessed top surface (rather than a surface flush with the bottom of the recessed region R1). Here, the source / drain pattern SD can have the same Figure 5 The shape described is the same shape.

[0057] refer to Figure 12, when viewed in the CC' cross-sectional view, a portion of the gate spacer GSP may remain on the side surface of the active fin AF. For example, the side surface of the active fin AF below the recessed region R1 may be covered by the remaining gate spacer GSPr. The bottom surface of the recessed region R1 may be higher than the top surface of the device isolation layer 3. The top end of the remaining gate spacer GSPr may be located at the same level as the bottom surface of the recessed region R1. Here, the source / drain pattern SD may be formed to have the same Figure 5 However, the third point C3 of the source / drain pattern SD may be higher than Figure 5 In this case, bottom ends of the first and second lower sides 41 and 42 of the source / drain pattern SD may be located at the same level as top ends of the remaining gate spacers GSPr.

[0058] In certain embodiments, as Figure 13 As shown, the top end of the remaining gate spacer GSPr may be lower than the bottom surface of the recessed region R1. The side surface of the active fin AF below the bottom surface of the recessed region R1 may be partially covered by the source / drain pattern SD. The bottom ends of the first lower side 41 and the second lower side 42 of the source / drain pattern SD may be located at the same level as the top end of the remaining gate spacer GSPr. The active fin AF may include a portion extending or inserted into the source / drain pattern SD. Other elements may be connected to the active fin AF. Figure 12 The components are basically the same.

[0059] In certain embodiments, as Figure 14 As shown, the top end of the reserved gate spacer GSPr may be higher than the bottom surface of the recessed region R1. The source / drain pattern SD may include a lower portion that extends between the reserved gate spacers GSPr and contacts the active fin AF. The lower portion of the source / drain pattern SD may be covered by the reserved gate spacer GSPr. In this embodiment, the bottom ends of the first lower side 41 and the second lower side 42 of the source / drain pattern SD may be located at the same level as the top end of the reserved gate spacer GSPr. Other elements may be connected to the Figure 12 The components are basically the same.

[0060] Figure 15 is a perspective view showing a semiconductor device according to an embodiment. Figure 16 It is along Figure 15 A cross-sectional view of a semiconductor device according to an embodiment is shown, taken along line AA′. Figure 17 It is along Figure 15 A cross-sectional view of a semiconductor device according to an embodiment is shown, taken along line CC'.

[0061] refer to Figures 15 to 17 , can be found in the reference Figures 2 to 5A contact plug CT is formed on the semiconductor device described above. The formation of the contact plug CT may include removing the upper portion of the interlayer insulating layer 50 and the upper portion of the source / drain pattern SD to form a contact hole, and filling the contact hole with a conductive layer. Here, the bottom surface of the contact plug CT may be higher than the fifth point C5. During the formation of the contact plug CT, the top portions of the first upper side 43 and the second upper side 44 of the source / drain pattern SD may be partially removed. In this case, as shown in FIG. Figure 17 As shown, the third point C3 may be located at a point where an extension line 43e of the remaining portion of the first upper side 43 intersects an extension line 44e of the remaining portion of the second upper side 44. The width of the contact plug CT in the first direction X may be smaller than the width of the source / drain pattern SD in the first direction X. Therefore, the highest point of the source / drain pattern SD (e.g., Figure 5 The third point C3) may be located beside the contact plug CT, for example, at a point where the first upper side 43 and the second upper side 44 of the source / drain pattern SD outside the contact plug CT intersect ( Figure 15 ). Other components can be Figure 5 The components are basically the same.

[0062] Figure 18 is a plan view showing a semiconductor device according to an embodiment. Figure 19 is shown along Figure 18 Cross-sectional view of the vertical cross-section taken along line AA', line BB' and line CC'. Figure 20 is shown along Figure 18 A sectional view of a vertical section taken along line DD' and line EE'. Figure 21 It is along Figure 18 An enlarged cross-sectional view taken along line FF'.

[0063] refer to Figures 18 to 21 , the substrate 1 may include a first area AR1 and a second area AR2. The first area AR1 may be an NMOS transistor area. A first active fin AF1 protruding from the substrate 1 may be provided in the first area AR1. A first gate electrode GE1 may be provided on the first active fin AF1. A first gate capping pattern GCP1 may be provided on the first gate electrode GE1. The side surface of the first gate electrode GE1 and the side surface of the first gate capping pattern GCP1 may be covered by a first gate spacer GSP1. A first gate insulating layer Gox1 may be inserted between the first gate electrode GE1 and the first active fin AF1. The first gate insulating layer Gox1 may be inserted between the first gate electrode GE1 and the first gate spacer GSP1. A first recessed area R1 may be provided on the first active fin AF1 and on both sides of the first gate electrode GE1. A first source / drain pattern SD1 may be provided in the first recessed area R1. The first source / drain pattern SD1 may have a reference Figure 5The first source / drain pattern SD1 may have a shape as described above. Figures 11 to 14 One of the shapes described.

[0064] The second region AR2 may be a PMOS transistor region. A second active fin AF2 protruding from the substrate 1 may be provided in the second region AR2. A second gate electrode GE2 may be provided on the second active fin AF2. A second gate capping pattern GCP2 may be provided on the second gate electrode GE2. The side surfaces of the second gate electrode GE2 and the side surfaces of the second gate capping pattern GCP2 may be covered by a second gate spacer GSP2. A second gate insulating layer Gox2 may be interposed between the second gate electrode GE2 and the second active fin AF2. The second gate insulating layer Gox2 may be interposed between the second gate electrode GE2 and the second gate spacer GSP2. A second recessed region R2 may be provided on the second active fin AF2 and on both sides of the second gate electrode GE2. A second source / drain pattern SD2 may be provided in the second recessed region R2.

[0065] exist Figure 20 In the D-D' cross section of FIG. 1 , the second active fin AF2 below the second gate electrode GE2 may have a non-uniform width. For example, below the second gate electrode GE2, the width of the top surface of the second active fin AF2 may be greater than the width of the middle portion of the second active fin AF2. Furthermore, the width of the second active fin AF2 at the bottom level of the second recessed region R2 may be greater than the width of the middle portion of the second active fin AF2. In other words, the side surface of the second active fin AF2 below the second gate electrode GE2 may be recessed to have a concave shape.

[0066] refer to Figure 21 , the second source / drain pattern SD2 may include a third lower side 81 and a fourth lower side 82 spaced apart from each other, a third upper side 83 extending from the top end of the third lower side 81, and a fourth upper side 84 extending from the fourth lower side 82. The third lower side 81 may be inclined at a third angle θ3 relative to the fourth line SL4. The fourth line SL4 connects the lower end of the third lower side 81 to the lower end of the fourth lower side 82 and extends outward. Hereinafter, the point where the third lower side 81 and the third upper side 83 intersect will be referred to as the sixth point C6, and the point where the fourth lower side 82 and the fourth upper side 84 intersect will be referred to as the seventh point C7. The fourth upper side 84 may be inclined at a fourth angle θ4 relative to the fifth line segment SL5 (or the fifth line SL5) connecting the sixth point C6 to the seventh point C7. Here, the third angle θ3 may be less than Figure 3 The third angle θ3 may be substantially equal to the fourth angle θ4. In some embodiments, the third angle θ3 may be approximately 54.2°.

[0067] The fourth line SL4 and the fifth line SL5 may be parallel to each other. The fourth line SL4 and the fifth line SL5 may be parallel to the top surface 1a of the substrate 1. The third angle θ3 may correspond to the angle between the third lower side 81 and the top surface 1a of the substrate 1. The fourth angle θ4 may correspond to the angle between the fourth upper side 84 and the top surface 1a of the substrate 1.

[0068] The fifth line segment SL5 may have a fourth length L4. The third upper side 83 and the fourth upper side 84 facing each other may be inclined to each other and intersect at an eighth point C8. The extension line 81e of the third lower side 81 may intersect with the extension line 82e of the fourth lower side 82 at a ninth point C9, and the ninth point C9 and the eighth point C8 may be connected by a sixth line segment SL6 (or sixth line SL6). The sixth line segment SL6 may have a fifth length L5. The fifth line segment SL5 and the sixth line segment SL6 may intersect each other at a tenth point C10, which is substantially located at the midpoint of the sixth line segment SL6. The distance L6 from the eighth point C8 to the tenth point C10 (hereinafter referred to as the sixth length) may be approximately 0.5 times the fifth length L5.

[0069] In this embodiment, the third angle θ3 may be less than Figure 5 The fourth length L4 may be greater than the first length L1. Therefore, although the first source / drain pattern SD1 and the second source / drain pattern SD2 may have the same shape, their sizes (e.g., widths) may be different. That is, when measured in the first direction X, the maximum width of the first source / drain pattern SD1 on the first area AR1 may be smaller than the maximum width of the second source / drain pattern SD2 on the second area AR2.

[0070] Figures 18 to 21 The semiconductor device can be used similar to the reference Figures 6 to 10 The method described above is used for manufacturing. However, when forming the first recessed region R1 and the first source / drain pattern SD1 on the first region AR1, the second region AR2 may be covered with a mask pattern. The first recessed region R1 may be formed by an anisotropic etching process. The first source / drain pattern SD1 may be formed, for example, from a silicon epitaxial layer. During the formation of the first source / drain pattern SD1, the first source / drain pattern SD1 may be in-situ doped with, for example, phosphorus. In some embodiments, after forming the first source / drain pattern SD1, an ion implantation process may be further performed to implant a dopant (e.g., phosphorus) into the first source / drain pattern SD1.

[0071] Alternatively, when forming the second recessed region R2 and the second source / drain pattern SD2 on the second region AR2, the first region AR1 may be covered with a mask pattern. The second recessed region R2 may be formed by an isotropic etching process. In some embodiments, the side surface of the second active fin AF2 below the second gate electrode GE2 may be recessed in a direction intersecting the second gate electrode GE2 (e.g., the first direction X). The second source / drain pattern SD2 may be formed, for example, of a silicon germanium epitaxial layer. During the formation of the second source / drain pattern SD2, the second source / drain pattern SD2 may be in-situ doped with boron. In some embodiments, after forming the second source / drain pattern SD2, an ion implantation process may be further performed to implant a dopant (e.g., boron) into the second source / drain pattern SD2.

[0072] Figures 22 to 25 is a cross-sectional view, each cross-sectional view is taken along Figure 18 , taken along line FF' to illustrate a semiconductor device according to an embodiment.

[0073] refer to Figure 22 , when viewed in the FF' cross section, the top surface of the device isolation layer 3 may be recessed. For example, when forming the second recessed region R2, the upper portion of the device isolation layer 3 may be etched to form a recessed top surface. Here, the second source / drain pattern SD2 may have the same shape as the reference pattern. Figure 21 The shape described is the same shape.

[0074] In certain embodiments, as Figure 23 As shown, the side surface of the second active fin AF2 below the second recessed region R2 may be covered by the second reserved gate spacer GSP2r. The bottom surface of the second recessed region R2 may be higher than the top surface of the device isolation layer 3. The top end of the second reserved gate spacer GSP2r may be located at the same level as the bottom surface of the second recessed region R2. Here, the second source / drain pattern SD2 may have the same Figure 21 However, the eighth point C8 of the second source / drain pattern SD2 may be located at a position smaller than Figure 21 In this case, bottom ends of the third and fourth lower sides 81 and 82 of the second source / drain pattern SD2 may be located at the same level as top ends of the second reservation gate spacers GSP2r.

[0075] In certain embodiments, as Figure 24As shown, the top end of the second retention gate spacer GSP2r may be lower than the bottom surface of the second recessed region R2. The side surface of the second active fin AF2 below the bottom surface of the second recessed region R2 may be partially covered by the second source / drain pattern SD2. The bottom ends of the third lower side 81 and the fourth lower side 82 of the second source / drain pattern SD2 may be located at the same level as the top end of the second retention gate spacer GSP2r. Other elements may be the same as Figure 23 The other components are basically the same.

[0076] In certain embodiments, as Figure 25 As shown, the top end of the second retention gate spacer GSP2r may be higher than the bottom surface of the second recessed region R2. The second source / drain pattern SD2 may include a lower portion extending between the second retention gate spacers GSP2r and in contact with the second active fin AF2. The lower portion of the second source / drain pattern SD2 may be covered by the second retention gate spacer GSP2r. The bottom ends of the third lower side 81 and the fourth lower side 82 of the second source / drain pattern SD2 may be located at the same level as the top end of the second retention gate spacer GSP2r. Other elements may be connected to the second source / drain pattern SD2. Figure 23 The components are basically the same.

[0077] Figure 26 FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. Figure 18 An enlarged cross-sectional view taken along line FF'. Figure 26 Shown along Figure 18 Another example of a cross section taken along line F-F'. Figure 18 When the semiconductor device according to the present embodiment is cut along the lines AA', BB', CC', DD' and EE', the semiconductor device may have the same Figure 19 and Figure 20 The cross section is the same as the cross section, and its description will be omitted.

[0078] refer to Figure 26 , the side surface of the second active fin AF2 below the second recessed region R2 may be covered by the second reserved gate spacer GSP2r. The bottom surface of the second recessed region R2 may be higher than the top surface of the device isolation layer 3. The second source / drain pattern SD2 may be similar in shape to the reference fin AF2, for example. Figure 5 The source / drain pattern SD described above may be different in size (e.g., width). In other words, the third angle θ3 may be greater than the fourth angle θ4. The tenth point C10 may be located at a higher level than the center point of the sixth segment SL6. The sixth length L6 may be about 0.2 times to about 0.45 times the fifth length L5. In this embodiment, the height from the top surface of the device isolation layer 3 to the eighth point C8 may be substantially equal to the height at the eighth point C8. Figure 19 or Figure 5The height from the top surface of the device isolation layer 3 to the third point C3 in the CC' section. Here, the fourth length L4 may be less than the first length L1. That is, in the range including Figure 19 (e.g., as shown in section C-C') or Figure 5 The first source / drain pattern SD1 and Figure 26 In a semiconductor device having both the first source / drain pattern SD1 and the second source / drain pattern SD2, the first source / drain pattern SD1 and the second source / drain pattern SD2 may have top ends located at the same height from the top surface of the device isolation layer 3, and the maximum width of the first source / drain pattern SD1 in the first direction X may be greater than the maximum width of the second source / drain pattern SD2 in the first direction X.

[0079] Figure 27 is a plan view showing a semiconductor device according to an embodiment. Figure 28 is a semiconductor device according to an embodiment of the present invention. Figure 27 A cross-sectional view taken along line G-G'. Figure 29 is a semiconductor device according to an embodiment of the present invention. Figure 27 A cross-sectional view taken along line H-H'.

[0080] refer to Figures 27 to 29 A plurality of first active fins AF1 protruding from the substrate 1 may be provided on the first area AR1. A plurality of second active fins AF2 protruding from the substrate 1 may be provided on the second area AR2. The first area AR1 may be, for example, an NMOS transistor area. The second area AR2 may be, for example, a PMOS transistor area. When viewed in plan, the first and second active fins AF1 and AF2 may be stripe-shaped or linear patterns extending in a first direction X. The first and second active fins AF1 and AF2 may be spaced apart from each other at a specific interval in a second direction Y intersecting the first direction X. The first gate electrode GE1 may intersect the first active fin AF1 along the second direction Y. The second gate electrode GE2 may intersect the second active fin AF2 along the second direction Y. A first source / drain pattern SD1 may be provided on the exposed portions of the first active fins AF1 between the first gate electrodes GE1. The first source / drain pattern SD1 may function as the source / drain electrodes of the NMOS transistor. The first source / drain pattern SD1 may include a silicon epitaxial pattern doped with phosphorus. The second source / drain pattern SD2 may be disposed on the exposed portion of the second active fin AF2 between the second gate electrode GE2. The second source / drain pattern SD2 may serve as a source / drain electrode of the PMOS transistor. The second source / drain pattern SD2 may include a silicon germanium epitaxial pattern doped with boron.

[0081] exist Figure 28, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be similar in shape to the reference Figure 5 The source / drain pattern SD described above is as follows. Figure 28 As shown, although the shapes of the first source / drain patterns SD1 and the second source / drain patterns SD2 may be the same, their sizes (e.g., heights along the Z direction) may be different. When measured in the second direction Y, the maximum width of each first source / drain pattern SD1 may be substantially equal to the maximum width of each second source / drain pattern SD2. Adjacent first source / drain patterns SD1 may contact each other. In the case where the first source / drain patterns SD1 are disposed adjacent to each other, it may be difficult to determine the maximum width for each first source / drain pattern SD1. Figure 5 In this case, the extension lines of the first lower side 41, the second lower side 42, the first upper side 43 and the second upper side 44 can be used to estimate the position of the first point C1 and / or the second point C2. Figure 5 The position of the first point C1 and / or the second point C2.

[0082] exist Figure 28 In the embodiment, adjacent second source / drain patterns SD2 may contact each other. In the case where the second source / drain patterns SD2 are disposed adjacent to each other, it may be difficult to determine the electrode width for each second source / drain pattern SD2. Figure 21 In this case, the extension lines of the third lower side 81, the fourth lower side 82, the third upper side 83 and the fourth upper side 84 can be used to estimate the position of the sixth point C6 and / or the seventh point C7. Figure 21 The position of the sixth point C6 and / or the seventh point C7.

[0083] and Figure 28 Unlike, adjacent first source / drain patterns SD1 may not contact each other or may be spaced apart from each other. In addition, adjacent second source / drain patterns SD2 may not contact each other or may be spaced apart from each other.

[0084] An upper side surface of the second active fin AF2 under the second source / drain pattern SD2 may protrude from the top surface of the device isolation layer 3 and may be covered by the second reserved gate spacer GSP2r. Figure 28 , a first height H1 from a top end of the device isolation layer 3 to a top end of the first source / drain pattern SD1 may be smaller than a second height H2 from a top end of the device isolation layer 3 to a top end of the second source / drain pattern SD2. The difference between the second height H2 and the first height H1 may correspond to a vertical length of the second reserved gate spacer GSP2r.

[0085] See also Figure 27 and Figure 29A first contact plug CT1 may be disposed on the first source / drain pattern SD1. A second contact plug CT2 may be disposed on the second source / drain pattern SD2. When measured from the top of the device isolation layer 3, a third height H3 of the bottom surface of the first contact plug CT1 may be less than a fourth height H4 of the bottom surface of the second contact plug CT2. The width of the first contact plug CT1 in the second direction Y may be less than the sum of the maximum widths of the first source / drain patterns SD1 in the second direction Y. The width of the second contact plug CT2 in the second direction Y may be less than the sum of the maximum widths of the second source / drain patterns SD2 in the second direction Y. A first empty space or first air gap region AG1 may be formed between the lower sides of the first source / drain patterns SD1. A second empty space or second air gap region AG2 may be formed between the lower sides of the second source / drain patterns SD2. Other elements may be substantially the same as or similar to those described above.

[0086] exist Figure 29 It may be difficult to determine the thickness of each first source / drain pattern SD1. Figure 5 In this case, the first lower side 41 and the first upper side 43 of the leftmost first source / drain pattern in the first source / drain pattern SD1 can be used to estimate the position of the first point C1, and the second lower side 42 and the second upper side 44 of the rightmost first source / drain pattern in the first source / drain pattern SD1 can be used to estimate the position of the second point C2. The positions of the first point C1 and the second point C2 can be used to calculate the first angle and the second angle.

[0087] exist Figure 29 It may be difficult to determine the second source / drain pattern SD2. Figure 26 The positions of the sixth point C6 and / or the seventh point C7 in the second source / drain pattern SD2 can be estimated. In this case, the third lower side 81 and the third upper side 83 of the leftmost second source / drain pattern in the second source / drain pattern SD2 can be used to estimate the position of the sixth point C6, and the fourth lower side 82 and the fourth upper side 84 of the rightmost second source / drain pattern in the second source / drain pattern SD2 can be used to estimate the position of the seventh point C7. The positions of the sixth point C6 and the seventh point C7 can be used to calculate the third angle and the fourth angle.

[0088] Figure 30 is an equivalent circuit diagram of a static random access memory (SRAM) cell according to an embodiment.

[0089] refer to Figure 30According to an embodiment, an SRAM cell may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA2. The first pull-up transistor TU1 and the second pull-up transistor TU2 may be PMOS transistors. The first pull-down transistor TD1, the second pull-down transistor TD2, and the first access transistor TA1 and the second access transistor TA2 may be NMOS transistors.

[0090] The first source / drain of the first pull-up transistor TU1 and the first source / drain of the first pull-down transistor TD1 can be connected to the first node N1. The second source / drain of the first pull-up transistor TU1 can be connected to the power supply line VDD, and the second source / drain of the first pull-down transistor TD1 can be connected to the ground line VSS. The gate of the first pull-up transistor TU1 and the gate of the first pull-down transistor TD1 can be electrically connected to each other. The first pull-up transistor TU1 and the first pull-down transistor TD1 can constitute a first inverter. The connected gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 can correspond to the input terminal of the first inverter, and the first node N1 can correspond to the output terminal of the first inverter.

[0091] The first source / drain of the second pull-up transistor TU2 and the first source / drain of the second pull-down transistor TD2 can be connected to the second node N2. The second source / drain of the second pull-up transistor TU2 can be connected to the power supply line VDD, and the second source / drain of the second pull-down transistor TD2 can be connected to the ground line VSS. The gate of the second pull-up transistor TU2 and the gate of the second pull-down transistor TD2 can be electrically connected to each other. The second pull-up transistor TU2 and the second pull-down transistor TD2 can constitute a second inverter. The connected gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 can correspond to the input terminal of the second inverter, and the second node N2 can correspond to the output terminal of the second inverter.

[0092] The first inverter and the second inverter can be combined to form a latch structure. In other words, the gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to the second node N2, and the gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to the first node N1. The first source / drain of the first access transistor TA1 can be connected to the first node N1, and the second source / drain of the first access transistor TA1 can be connected to the first bit line BL1. The first source / drain of the second access transistor TA2 can be connected to the second node N2, and the second source / drain of the second access transistor TA2 can be connected to the second bit line BL2. The gates of the first access transistor TA1 and the second access transistor TA2 can be electrically coupled to the word line WL. This structure is merely an example of an SRAM cell according to an embodiment, and the SRAM cell according to an embodiment is not limited to this example.

[0093] Figure 31 FIG. 1 is a diagram showing a semiconductor device (eg, including Figure 30 A plan view of an SRAM cell). Figures 32 to 35 are along Figure 31 Cross-sectional views taken along line II', line JJ', line KK' and line LL'.

[0094] refer to Figures 31 to 35 At least one SRAM cell may be provided on a substrate 1. A device isolation layer 3 may be provided on the substrate 1. The device isolation layer 3 may be provided to define first active fins AF1 and second active fins AF2. A first source / drain pattern SD1 may be provided on each of the first active fins AF1. A second source / drain pattern SD2 may be provided on each of the second active fins AF2. The first source / drain pattern SD1 may serve as a source / drain electrode for an NMOS transistor. The first source / drain pattern SD1 may be doped with n-type impurities. For example, the first source / drain pattern SD1 may include a silicon epitaxial pattern doped with phosphorus. The second source / drain pattern SD2 may serve as a source / drain electrode for a PMOS transistor. The second source / drain pattern SD2 may be doped with p-type impurities. For example, the second source / drain pattern SD2 may include a silicon germanium epitaxial pattern doped with boron.

[0095] The first to fourth gate electrodes GE1 to GE4 may be provided to intersect the first and second active fins AF1 and AF2 and extend in the second direction Y. The second gate electrode GE2 and the fourth gate electrode GE4 may be aligned with each other in the first direction X. A separation pattern SP may be inserted between the second gate electrode GE2 and the fourth gate electrode GE4 to separate the second gate electrode GE2 and the fourth gate electrode GE4 from each other. The first gate electrode GE1 and the third gate electrode GE3 may be aligned with each other in the first direction X. A separation pattern SP may be inserted between the first gate electrode GE1 and the third gate electrode GE3 to separate the first gate electrode GE1 and the third gate electrode GE3 from each other.

[0096] First to eighth active contacts AC1 to AC8 may be provided on both sides of each of the first to fourth gate electrodes GE1 to GE4. The first to eighth active contacts AC1 to AC8 may penetrate the upper portion of the interlayer insulating layer 50 and may be coupled to the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surfaces of the first to eighth active contacts AC1 to AC8 may be coplanar with the top surface of the interlayer insulating layer 50. The first to eighth active contacts AC1 to AC8 may be formed of or include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0097] The first to fourth gate electrodes GE1 to GE4 and first and second source / drain patterns SD1 and SD2 disposed adjacent thereto on the first and second active fins AF1 and AF2 , respectively, may constitute a memory transistor. Figure 31 The memory transistor shown in FIG may include the previously referenced Figure 30 A first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA2 are described.

[0098] Reference again Figure 35The first source / drain pattern SD1 of the first pull-down transistor TD1 and the second source / drain pattern SD2 of the first pull-up transistor TU1 may be spaced apart from each other in the second direction Y, and their top surfaces may be in contact with the second active contact AC2. The second source / drain pattern SD2 of the first pull-up transistor TU1 and the second source / drain pattern SD2 of the second pull-up transistor TU2 may be spaced apart from each other in the second direction Y. The second source / drain pattern SD2 of the second pull-up transistor TU2 and the first source / drain pattern SD1 of the second pull-down transistor TD2 may be spaced apart from each other in the second direction Y, and their top surfaces may be in contact with the fifth active contact AC5. The width of each of the second active contact AC2 and the fifth active contact AC5 in the second direction Y may be greater than the maximum width of the widest of the first and second source / drain patterns SD1 and SD2 in the second direction Y.

[0099] In this embodiment, each of the first source / drain patterns SD1 may be similar in shape to the reference Figure 5 However, the first source / drain pattern SD1 may have the same Figures 11 to 14 The second source / drain patterns SD2 may have the same or similar structure as one of the source / drain patterns SD described above. Each of the second source / drain patterns SD2 may be similar in shape to the reference Figure 23 However, the second source / drain pattern SD2 may have the same Figure 21 、 Figure 22 and Figures 24 to 26 The second source / drain pattern SD2 described or reference Figures 11 to 14 The first source / drain pattern SD1 and the second source / drain pattern SD2 may have the same or similar structure as one of the source / drain patterns SD described above. Adjacent patterns in the first source / drain pattern SD1 and the second source / drain pattern SD2 may be spaced apart from each other. According to some embodiments, at least the first source / drain pattern SD1 may have Figure 5 In this case, the maximum width in the second direction Y can be reduced. Therefore, the distance between the first source / drain pattern SD1 and the second source / drain pattern SD2 can be increased, thereby preventing bridge or short circuit problems between the first source / drain pattern SD1 and the second source / drain pattern SD2. This effect becomes increasingly important as the integration density of semiconductor devices increases.

[0100] Figure 36 is a cross-sectional view of a semiconductor device including a source / drain pattern according to an embodiment. Figure 36 Shown Figure 5 A variant embodiment of .

[0101] refer to Figure 36According to an embodiment, the sides and top of the source / drain pattern SD may have a rounded shape. In other words, the first point C1 may correspond to the point where the lower extension line 43e1 of the first upper side 43 intersects the upper extension line 41eu of the first lower side 41. The second point C2 may correspond to the point where the lower extension line 44e1 of the second upper side 44 intersects the upper extension line 42eu of the second lower side 42. The third point C3 may correspond to the point where the upper extension line 43eu of the first upper side 43 intersects the upper extension line 44eu of the second upper side 44. The fourth point C4 may correspond to the point where the lower extension line 41e1 of the first lower side 41 intersects the lower extension line 42e1 of the second lower side 42. The first to fourth points C1, C2, C3, and C4 may not be located above or within the source / drain pattern SD. The laterally most protruding point of the source / drain pattern SD may be spaced apart from the first point C1 and the second point C2. The highest point of the source / drain pattern SD may be lower than the third point C3.

[0102] In this embodiment, the first angle θ1 may be the angle between a first line SL1 and the first lower side 41, the first line SL1 connecting the bottom end of the first lower side 41 and the bottom end of the second lower side 42 and extending outward. The first line SL1 may be parallel to a seventh line SL7, which is an extension of the top surface 1a of the substrate 1. The first angle θ1 may correspond to the angle between the lower extension line 41e1 of the first lower side 41 and the seventh line SL7. In other words, the first angle θ1 may correspond to the angle between the first lower side 41 and the top surface 1a of the substrate 1.

[0103] In the present embodiment, the second angle θ2 may correspond to the angle between the second line segment SL2 connecting the first point C1 and the second point C2 and the second upper side 44 or the lower extension line 44el of the second upper side 44. The first line SL1 may be parallel to the second line segment SL2. The second angle θ2 may correspond to the angle between the first line SL1 and the lower extension line 44el of the second upper side 44. In some embodiments, the second angle θ2 may correspond to the angle between the seventh line SL7 and the lower extension line 44el of the second upper side 44. The second angle θ2 may correspond to the angle between the second upper side 44 and the top surface 1a of the substrate 1. In addition to the above differences, Figure 36 The embodiments can be compared with the reference Figure 5 The embodiments described are the same or similar.

[0104] Figure 37 is a cross-sectional view of a semiconductor device including a source / drain pattern according to an embodiment. Figure 37 Shown Figure 17 A variant embodiment of .

[0105] refer to Figure 37 , can be found from the reference Figure 36In the described semiconductor device, the interlayer insulating layer 50 and the upper portion of the source / drain pattern SD are removed to form a contact hole, and then, a contact plug CT may be formed by filling the contact hole with a conductive layer. Here, the bottom surface of the contact plug CT may be higher than the fifth point C5. The top of the first upper side 43 and the second upper side 44 of the source / drain pattern SD may be removed during the formation of the contact plug CT. The first contact point CS1 may be defined as the point where the contact plug CT intersects the first upper side 43, and the second contact point CS2 may be defined as the point where the contact plug CT intersects the second upper side 44. The upper extension line 43eu and the lower extension line 43el of the first upper side 43 may be referred to as tangent lines 43eu and 43el at the first contact point CS1. In addition, the upper extension line 44eu and the lower extension line 44el of the second upper side 44 may be referred to as tangent lines 44eu and 44el at the second contact point CS2. In addition to the above differences, Figure 37 Examples and references Figure 36 and Figure 17 The embodiments described are the same or similar.

[0106] According to some embodiments, the source / drain pattern may have a bottom angle of about 55° to about 65° relative to the top surface of the substrate and a top centerline that occupies about 20%-45% of the total centerline length. Thus, the semiconductor device may have sufficient (e.g., increased) separation margin, thereby allowing adjacent source / drain patterns to be spaced apart from each other. This may enable a semiconductor device with improved electrical characteristics and increased integration density.

[0107] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be readily appreciated by one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with a particular embodiment as submitted herein may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device comprising: a first active fin protruding from the substrate; a second active fin protruding from the substrate; a device isolation layer located on the substrate, the device isolation layer surrounding the first active fin and the second active fin, and directly contacting the first active fin and the second active fin; a first gate pattern intersecting both the first active fin and the second active fin; a first source / drain pattern of a first conductivity type; a second source / drain pattern of a second conductivity type different from the first conductivity type; as well as a contact plug in direct contact with the first source / drain pattern of the first conductivity type and the second source / drain pattern of the second conductivity type, the entire bottom surface of the contact plug being flat, Wherein, each of the first source / drain patterns comprises: a first lower side and a second lower side spaced apart from each other, a first upper side extending from said first lower side, and a second upper side extending from said second lower side, Wherein, each of the second source / drain patterns includes: a third lower side and a fourth lower side spaced apart from each other, a third upper side extending from the third lower side, and a fourth upper side extending from the fourth lower side, wherein the first lower side is inclined at a first angle relative to the top surface of the substrate, the second upper side is inclined at a second angle relative to the top surface of the substrate, the third lower side is inclined at a third angle relative to the top surface of the substrate, and the first angle is greater than the second angle and the third angle, wherein the horizontal height of the intersection of the first upper side and the first lower side is higher than the horizontal height of the intersection of the third upper side and the third lower side, and the width of the first source / drain pattern at the intersection of the first upper side and the first lower side is smaller than the width of the second source / drain pattern at the intersection of the third upper side and the third lower side, the first source / drain pattern is doped with n-type impurities, and the second source / drain pattern is doped with p-type impurities, and The top surfaces of the first source / drain pattern and the second source / drain pattern are coplanar with each other, and the top surfaces of the first source / drain pattern and the second source / drain pattern are in direct contact with the bottom surface of the contact plug. 2 . The semiconductor device according to claim 1 , wherein the first angle is within a range from 55 degrees to 65 degrees.

3. The semiconductor device according to claim 1 , further comprising: a first point, wherein the first lower side intersects with the first upper side at the first point or an extension line of the first lower side intersects with an extension line of the first upper side at the first point; a second point, wherein the second lower side intersects with the second upper side at the second point or an extension line of the second lower side intersects with an extension line of the second upper side at the second point; a first dummy line segment connecting the first point and the second point to each other along each of the first source / drain patterns; a third point, at which the first upper side and the second upper side intersect or an extension line of the first upper side and an extension line of the second upper side intersect; a fourth point, an extension line of the first lower side and an extension line of the second lower side intersecting at the fourth point; a second dummy line segment connecting the third point and the fourth point along each of the first source / drain patterns; as well as A fifth point, at which the first imaginary line segment and the second imaginary line segment intersect, and the fifth point is higher than a midpoint of the second imaginary line segment. 4 . The semiconductor device according to claim 3 , wherein a first distance from the third point to the fifth point is shorter than a distance from the fifth point to a level at which the first lower side and the second lower side extend.

5. The semiconductor device according to claim 1, in, The contact plug is in contact with both the first upper side and the second upper side; The semiconductor device further includes: a first contact point at which the contact plug and the first upper side intersect; a second contact point at which the contact plug and the second upper side intersect; a first tangent line at the first contact point; a second tangent line at the second contact point; a first point, wherein the first tangent line intersects an extension line of the first lower side at the first point; a second point, wherein the second tangent line intersects an extension line of the second lower side at the second point; a first dummy line segment connecting the first point and the second point to each other along each of the first source / drain patterns; a third point, wherein the first tangent line and the second tangent line intersect at the third point; a fourth point, an extension line of the first lower side and an extension line of the second lower side intersecting at the fourth point; a second dummy line segment connecting the third point and the fourth point to each other along each of the first source / drain patterns; and A fifth point, at which the first imaginary line segment and the second imaginary line segment intersect, and the fifth point is higher than the center of the second imaginary line segment. 6 . The semiconductor device according to claim 5 , wherein a first distance from the third point to the fifth point is 0.2 times to 0.45 times the length of the second dummy line segment. 7 . The semiconductor device according to claim 1 , wherein a width of the second source / drain pattern is greater than a width of the first source / drain pattern. 8 . The semiconductor device according to claim 7 , wherein the fourth upper side is inclined at a third angle with respect to an imaginary line segment connecting a bottom end of the third upper side and a bottom end of the fourth upper side, and the second angle is equal to the third angle.

9. The semiconductor device according to claim 7, wherein The first source / drain pattern and the first gate pattern constitute an NMOS transistor, and the second source / drain pattern and the first gate pattern constitute a PMOS transistor.

10. The semiconductor device according to claim 1, further comprising: A spacer is located under each of the second source / drain patterns to cover side surfaces of the second active fin.

11. The semiconductor device according to claim 10, in, A height of a top end of the first source / drain pattern is equal to a height of a top end of the second source / drain pattern.

12. The semiconductor device according to claim 11, in, The fourth upper side is inclined at a fourth angle relative to a second imaginary line segment connecting the third point and the fourth point, and Wherein, the third angle is greater than the fourth angle.

13. The semiconductor device according to claim 1, wherein the first source / drain pattern further comprises: a first circular edge located between the first upper side and the first lower side, and A second rounded edge is located between the second upper side and the second lower side.

14. The semiconductor device according to claim 1, in, The device isolation layer exposes an upper sidewall of the second active fin; The semiconductor device further includes a spacer covering an upper sidewall of the second active fin.

15. A semiconductor device comprising: substrate; a first active fin protruding from the substrate; a first source / drain pattern of a first conductivity type on the first active fin; a second active fin protruding from the substrate; a first gate pattern intersecting both the first active fin and the second active fin; a second source / drain pattern on the second active fin having a second conductivity type different from the first conductivity type; as well as a contact plug in direct contact with the first source / drain pattern of the first conductivity type and the second source / drain pattern of the second conductivity type, the entire bottom surface of the contact plug being flat, Wherein, the first source / drain pattern includes: a first lower side and a second lower side spaced apart from each other, a first upper side extending from the first lower side, a second upper side extending from the second lower side, Wherein, each of the second source / drain patterns includes: a third lower side and a fourth lower side spaced apart from each other, a third upper side extending from the third lower side, and a fourth upper side extending from the fourth lower side, wherein the first lower side is inclined at a first angle relative to the top surface of the substrate, the second upper side is inclined at a second angle relative to the top surface of the substrate, and the third lower side is inclined at a third angle relative to the top surface of the substrate, and the first angle is greater than the second angle and the third angle. wherein the horizontal height of the intersection of the first upper side and the first lower side is higher than the horizontal height of the intersection of the third upper side and the third lower side, and the width of the first source / drain pattern at the intersection of the first upper side and the first lower side is smaller than the width of the second source / drain pattern at the intersection of the third upper side and the third lower side, the first source / drain pattern is doped with n-type impurities, and the second source / drain pattern is doped with p-type impurities, and The top surfaces of the first source / drain pattern and the second source / drain pattern are coplanar with each other, and the top surfaces of the first source / drain pattern and the second source / drain pattern are in direct contact with the bottom surface of the contact plug.

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