Semiconductor Devices

Abstract

The embodiments of the present disclosure provide a semiconductor device, belonging to the field of semiconductor technology. The semiconductor device includes: a plurality of main interconnection elements configured to provide a plurality of signal transmission channels; a redundant interconnection element; and a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection element if any two or more of the main interconnection elements fail.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device. Background Art

[0002] In order to achieve higher transistor integration, existing semiconductor design technology uses Figure 1 The stacked semiconductor chips shown in FIG. Figure 1 In the embodiment, semiconductor chips 101, 102 and 103 are stacked sequentially from bottom to top on a semiconductor substrate 100, and wire bonding elements ( Figure 1 In the semiconductor chip 102 and the semiconductor chip 101, the metal interconnection wires in the semiconductor chip and the wire bonding elements are connected through silicon vias (TSVs) 104, thereby achieving the following: Figure 1 The communication between chips in each layer of a stacked semiconductor chip is shown.

[0003] However, after a certain period of use, the performance of the through silicon vias inside the stacked semiconductor chip will degrade, and the degradation will cause the stacked semiconductor chip to fail.

[0004] Since the manufacturing cost of a stacked semiconductor chip having a plurality of TSVs is very high, it is very necessary to prevent the failure of the entire stacked semiconductor chip due to the failure of one of the plurality of TSVs.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device, comprising: a plurality of main interconnection elements configured to provide a plurality of signal transmission channels; a redundant interconnection element; and a logic control circuit configured to provide signal transmission channels through the redundant interconnection elements to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail.

[0007] In an exemplary embodiment of the present disclosure, the multiple main interconnection elements include: a first main interconnection element, configured to provide a first signal transmission channel between a first input signal and a first output signal in a normal state; and a second main interconnection element, configured to provide a second signal transmission channel between a second input signal and a second output signal in a normal state.

[0008] In an exemplary embodiment of the present disclosure, the logic control circuit includes: an input conversion circuit, configured to generate a voltage signal to the redundant interconnection element according to the first input signal and the second input signal if the first main interconnection element and the second main interconnection element fail at the same time; and an output conversion circuit, configured to generate the first output signal and the second output signal according to the voltage signal if the first main interconnection element and the second main interconnection element fail at the same time.

[0009] In an exemplary embodiment of the present disclosure, the voltage signal includes a first voltage signal, a second voltage signal, a third voltage signal and a fourth voltage signal; wherein the input conversion circuit includes: a control subcircuit, configured to generate a first selection signal, a second selection signal, a third selection signal and a fourth selection signal according to the first input signal and the second input signal; a voltage divider subcircuit, configured to select any one of the first to fourth voltage signals to be output to the redundant interconnection element according to the first selection signal, the second selection signal, the third selection signal and the fourth selection signal.

[0010] In an exemplary embodiment of the present disclosure, the control subcircuit includes: an OR gate, wherein the first input end of the OR gate is used to receive the first input signal, and the second input end of the OR gate is used to receive the second input signal; a first NOT gate, wherein the input end of the first NOT gate is electrically connected to the output end of the OR gate, and the output end of the first NOT gate is used to output the first selection signal; a second NOT gate, wherein the input end of the second NOT gate is used to receive the second input signal; an XOR gate, wherein the first input end of the XOR gate is used to receive the first input signal, and the second input end of the XOR gate is used to receive the second input signal; and a first AND gate, wherein the first input end of the first AND gate is electrically connected to the output end of the second NOT gate. , the second input end of the first AND gate is electrically connected to the output end of the XOR gate, and the output end of the first AND gate is used to output the second selection signal; a third NOT gate, the input end of the third NOT gate is used to receive the first input signal; a second AND gate, the first input end of the second AND gate is electrically connected to the output end of the third NOT gate, the second input end of the second AND gate is electrically connected to the output end of the XOR gate, and the output end of the second AND gate is used to output the third selection signal; a third AND gate, the first input end of the third AND gate is used to receive the first input signal, the second input end of the third AND gate is used to receive the second input signal, and the output end of the third AND gate is used to output the fourth selection signal.

[0011] In an exemplary embodiment of the present disclosure, the voltage divider subcircuit includes: a first transistor, the control end of the first transistor is used to receive the first selection signal, the first end of the first transistor is electrically connected to the first voltage dividing node, and the second end of the first transistor is used to output the first voltage signal; a second transistor, the control end of the second transistor is used to receive the second selection signal, the first end of the second transistor is electrically connected to the second voltage dividing node, and the second end of the second transistor is used to output the second voltage signal; a third transistor, the control end of the third transistor is used to receive the third selection signal, the first end of the third transistor is electrically connected to the third voltage dividing node, and the second end of the third transistor is used to output the third voltage signal; a fourth transistor, the control end of the fourth transistor is used to receive the fourth selection signal, the first end of the fourth transistor is electrically connected to the fourth voltage dividing node, and the second end of the fourth transistor is used to output the fourth voltage signal.

[0012] In an exemplary embodiment of the present disclosure, the output conversion circuit includes: a comparison subcircuit, configured to receive the voltage signal output by the redundant interconnection element, and compare the voltage signal with a first reference signal, a second reference signal and a third reference signal, respectively, to output a first comparison signal, a second comparison signal and a third comparison signal, respectively; and a sampling subcircuit, configured to generate the first output signal and the second output signal according to the first comparison signal, the second comparison signal and the third comparison signal.

[0013] In an exemplary embodiment of the present disclosure, the comparison subcircuit includes: a first comparator, wherein a positive input terminal of the first comparator is used to receive the voltage signal, an inverting input terminal of the first comparator is used to receive the first reference signal, and an output terminal of the first comparator is used to output the first comparison signal; a second comparator, wherein a positive input terminal of the second comparator is used to receive the voltage signal, an inverting input terminal of the second comparator is used to receive the second reference signal, and an output terminal of the second comparator is used to output the second comparison signal; and a third comparator, wherein a positive input terminal of the third comparator is used to receive the voltage signal, an inverting input terminal of the third comparator is used to receive the third reference signal, and an output terminal of the third comparator is used to output the third comparison signal.

[0014] In an exemplary embodiment of the present disclosure, the sampling subcircuit includes: a fourth NOT gate, an input end of the fourth NOT gate is electrically connected to the output end of the first comparator, and the output end of the fourth NOT gate is used to output the second output signal; an XOR gate, a first input end of the XOR gate is electrically connected to the output end of the first comparator, a second input end of the XOR gate is electrically connected to the output end of the second comparator, a third input end of the XOR gate is electrically connected to the output end of the third comparator, and the output end of the XOR gate is used to output the first output signal.

[0015] In an exemplary embodiment of the present disclosure, it also includes: a first input multiplexer and a second input multiplexer, configured to receive the first input signal and the second input signal respectively, and when the first main interconnection element and the second main interconnection element fail at the same time, respectively input the first input signal and the second input signal to the input conversion circuit.

[0016] In an exemplary embodiment of the present disclosure, the first input multiplexer and the second input multiplexer are further configured to input the first input signal and the second input signal to the first main interconnection element and the second main interconnection element respectively if neither the first main interconnection element nor the second main interconnection element fails.

[0017] In an exemplary embodiment of the present disclosure, the first input multiplexer and the second input multiplexer are further configured to input an input signal corresponding to the failed main interconnection element to the redundant interconnection element if one of the first main interconnection element and the second main interconnection element fails, and input an input signal corresponding to another main interconnection element that has not failed to the other main interconnection element.

[0018] In an exemplary embodiment of the present disclosure, it also includes: a first output multiplexer and a second output multiplexer, configured to respectively receive and output the first output signal and the second output signal of the output conversion circuit if the first main interconnection element and the second main interconnection element fail at the same time.

[0019] In an exemplary embodiment of the present disclosure, the first output multiplexer and the second output multiplexer are further configured to receive and output the first output signal and the second output signal of the first main interconnection element and the second main interconnection element respectively if neither the first main interconnection element nor the second main interconnection element fails.

[0020] In an exemplary embodiment of the present disclosure, the first output multiplexer and the second output multiplexer are further configured to, if one of the first main interconnection element and the second main interconnection element fails, receive the output signal corresponding to the failed main interconnection element through the redundant interconnection element, and receive the output signal corresponding to the other main interconnection element that has not failed through the other main interconnection element.

[0021] In an exemplary embodiment of the present disclosure, the redundant interconnection element is disposed between the plurality of main interconnection elements.

[0022] In an exemplary embodiment of the present disclosure, the plurality of primary interconnection elements and the redundant interconnection element are through silicon vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Various objects, features and advantages of the present disclosure will become more apparent by considering the following detailed description of preferred embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0024] Figure 1 It is a structural schematic diagram of a stacked semiconductor chip in the related art;

[0025] Figure 2 It is a schematic diagram of a semiconductor device in the related art;

[0026] Figure 3 is a schematic diagram of another semiconductor device in the related art;

[0027] Figure 4 is a schematic diagram of another semiconductor device in the related art;

[0028] Figure 5 is a schematic diagram showing a semiconductor device according to an embodiment of the present disclosure;

[0029] Figure 6 is a circuit schematic diagram showing a control subcircuit according to an embodiment of the present disclosure;

[0030] Figure 7 is a circuit schematic diagram showing a voltage divider subcircuit according to an embodiment of the present disclosure;

[0031] Figure 8 is a circuit diagram showing an output conversion circuit according to an embodiment of the present disclosure;

[0032] Fig. 9 is a schematic diagram showing a signal level of a comparison subcircuit according to an embodiment of the present disclosure;

[0033] Fig.10 is a schematic diagram showing a control subcircuit according to an embodiment of the present disclosure;

[0034] Fig.11 is a schematic diagram showing a voltage divider subcircuit according to an embodiment of the present disclosure;

[0035] Fig.12 is a schematic diagram showing an output conversion circuit according to an embodiment of the present disclosure;

[0036] Fig.13 is a schematic diagram showing a state of a semiconductor device according to an embodiment of the present disclosure;

[0037] Fig.14 is a schematic diagram showing a state of another semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various changes in different embodiments without departing from the scope of the present disclosure, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present disclosure.

[0039] In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which are shown by way of example various exemplary structures, systems and steps that can implement various aspects of the present disclosure. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure.

[0040] In stacked 3D integrated circuits, such as stacked memory 3D integrated circuits, through silicon vias (TSVs) are usually used to interconnect and communicate with other stacked layers. The possibility of TSV failure during the manufacturing and bonding process is very high, so most of them use TSV redundancy mechanisms (Redundant TSV) to shield faulty TSVs. The TSV redundancy mechanisms in related technologies are mainly as follows: Figure 2-4 Among several.

[0041] Figure 2 It is a schematic diagram of a semiconductor device in the related art.

[0042] like Figure 2 As shown, under normal conditions, four input signals IN0-IN3 and corresponding four output signals OUT0-OUT3 are transmitted through four transmission channels formed by TSV0-TSV3. When any two of TSV0-TSV3 fail, rerouting (Reroutereconfiguration) can be used to replace the corresponding failed TSVs with two Red.TSVs (i.e., redundant TSVs).

[0043] Figure 3 It is a schematic diagram of another semiconductor device in the related art.

[0044] like Figure 3 As shown, in a normal state, three input signals IN1-IN3 and corresponding three output signals OUT1-OUT3 pass through each other. TSV0-TSV5 form five transmission channels. Figure 3 In the embodiment, TSV0-TSV5 can be each other's redundant TSVs, but the control circuit is very complicated to implement.

[0045] Figure 4 It is a schematic diagram of another semiconductor device in the related art.

[0046] like Figure 4As shown, under normal conditions, four input signals IN0-IN3 and corresponding four output signals OUT0-OUT3 are transmitted through four transmission channels formed by TSV0-TSV3. When any one of TSV0-TSV3 fails, self-redundancy reconfiguration can be used to replace the corresponding failed TSV with a Red.TSV.

[0047] However, most of the TSV redundancy mechanisms in the above-mentioned related technologies require more hardware control overhead, and when a TSV fails, the redundant TSV is set next to it, which will increase the transmission path delay and reduce the reliability of signal transmission.

[0048] Figure 5 is a schematic diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0049] like Figure 5 As shown, the semiconductor device 500 provided by the embodiment of the present invention may include at least one group of interconnection elements, which is assumed to be N groups in the figure, where N is a positive integer greater than or equal to 1.

[0050] Here, the first group of interconnection elements 1 is taken as an example for description.

[0051] In an exemplary embodiment, the first group of interconnection elements 1 may include: a plurality of main interconnection elements, which may be configured to provide a plurality of signal transmission channels; a redundant interconnection element Red.TSV; and a logic control circuit, which may be configured to provide a signal transmission channel through the redundant interconnection element Red.TSV to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail.

[0052] In an exemplary embodiment, the plurality of main interconnection elements and the redundant interconnection element may all be through silicon vias. In the embodiment of the present invention, the first group of interconnection elements 1 includes two main interconnection elements (the first main interconnection element TSV0 and the second main interconnection element TSV1 in the figure) as an example for illustration, but the present invention is not limited thereto. The number of main interconnection elements included in each group of interconnection elements can be determined according to the specific application scenario.

[0053] The first master interconnection element TSV0 may be configured to provide a first signal transmission channel between the first input signal IN1 and the first output signal OUT1 in a normal state (ie, TSV0 is not faulty).

[0054] The second main interconnection element TSV1 may be configured to provide a second signal transmission channel between the second input signal IN2 and the second output signal OUT2 in a normal state (ie, TSV1 is not faulty).

[0055] Continue to refer Figure 5 In the illustrated embodiment, the logic control circuit may include an input conversion circuit 501 and an output conversion circuit 502 .

[0056] The input conversion circuit 501 may be configured to generate a voltage signal Vout to the redundant interconnection element Red.TSV according to the first input signal IN1 and the second input signal IN2 if the first main interconnection element TSV0 and the second main interconnection element TSV1 fail simultaneously.

[0057] The output conversion circuit 502 may be configured to generate the first output signal OUT1 and the second output signal OUT2 according to the voltage signal Vout if the first master interconnection element TSV0 and the second master interconnection element TSV1 fail simultaneously.

[0058] like Figure 5 As shown, the semiconductor device 500 may further include a first input multiplexer 503 and a second input multiplexer 504. The first input multiplexer 503 and the second input multiplexer 504 may be configured to input the first input signal IN1 and the second input signal IN2 to the first main interconnection element TSV0 and the second main interconnection element TSV1, respectively, if neither the first main interconnection element TSV0 nor the second main interconnection element TSV1 fails.

[0059] Continue to refer Figure 5 The semiconductor device 500 may further include a first output multiplexer 505 and a second output multiplexer 506. The first output multiplexer 505 and the second output multiplexer 506 may be configured to receive and output a first output signal OUT1 and a second output signal OUT2 of the first master interconnection element TSV0 and the second master interconnection element TSV1, respectively, if neither the first master interconnection element TSV0 nor the second master interconnection element TSV1 fails.

[0060] In an exemplary embodiment, the redundant interconnection element Red.TSV may be disposed between the plurality of main interconnection elements.

[0061] For example, Figure 5In the embodiment, the redundant interconnection element Red.TSV can be arranged between the first main interconnection element TSV0 and the second main interconnection element TSV1, so that when any one of the first main interconnection element TSV0 and the second main interconnection element TSV1 fails, or both fail at the same time, when the two input signals IN1 and IN2 are transmitted through the redundant interconnection element Red.TSV, the transmission path delay can be reduced and the reliability of signal transmission can be increased.

[0062] In an exemplary embodiment, the voltage signal Vout may include a first voltage signal Vout0 , a second voltage signal Vout1 , a third voltage signal Vout2 , and a fourth voltage signal Vout3 .

[0063] The input conversion circuit 501 may further include: a control subcircuit, which may be configured to generate a first selection signal S0, a second selection signal S1, a third selection signal S2, and a fourth selection signal S3 according to the first input signal IN1 and the second input signal IN2; and a voltage dividing subcircuit, which may be configured to select any one of the first to fourth voltage signals Vout0-Vout3 to be output to the redundant interconnection element Red.TSV according to the first selection signal S0, the second selection signal S1, the third selection signal S2, and the fourth selection signal S3. For a detailed description, please refer to the following embodiments.

[0064] In an exemplary embodiment, the output conversion circuit 502 may further include: a comparison subcircuit, which may be configured to receive the voltage signal Vout output by the redundant interconnection element Red.TSV, and compare the voltage signal Vout with the first reference signal Vref_1 / 2, the second reference signal Vref_upper and the third reference signal Vref_lower to output the first comparison signal C1, the second comparison signal C2 and the third comparison signal C3 respectively; a sampling subcircuit, which is configured to generate the first output signal OUT1 and the second output signal OUT2 according to the first comparison signal C1, the second comparison signal C2 and the third comparison signal C3. For a detailed description, please refer to the following embodiments.

[0065] In an exemplary embodiment, the semiconductor device may be a stacked memory device, which may include multiple layers of semiconductor chips stacked in sequence along a vertical direction, and the semiconductor chip may be, for example, a DRAM (Dynamic Random Access Memory) chip, but the present invention is not limited thereto. The DRAM chips of each layer may communicate with each other through TSV interconnections.

[0066] The semiconductor device provided by the embodiment of the present invention can, through a logic control circuit, provide a signal transmission channel through a redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection elements when any two or more main interconnection elements among a plurality of main interconnection elements fail. On the one hand, the hardware control overhead of the entire semiconductor device can be reduced; on the other hand, the area of ​​the semiconductor device occupied by the redundant TSV can be reduced, and the production cost can be reduced.

[0067] In other embodiments, redundant TSVs are arranged between main TSVs, such as a symmetrical TSV redundancy mechanism architecture to shield faulty main TSVs, and in conjunction with a logic control circuit, two adjacent TSVs can be allowed to fail simultaneously. When applied to stacked memory 3D integrated circuits, the signal transmission path can be reduced and the reliability of signal transmission can be increased.

[0068] Figure 6 is a circuit diagram showing a control subcircuit according to an embodiment of the present disclosure.

[0069] like Figure 6As shown, the control subcircuit 600 may include: an OR gate 601, wherein the first input terminal of the OR gate 601 may be used to receive the first input signal IN1, and the second input terminal of the OR gate 601 may be used to receive the second input signal IN2; a first NOT gate 602, wherein the input terminal of the first NOT gate 602 may be electrically connected to the output terminal of the OR gate 601, and the output terminal of the first NOT gate 602 may be used to output the first selection signal S0; a second NOT gate 603, wherein the input terminal of the second NOT gate 603 may be used to receive the second input signal IN2; an XOR gate 604, wherein the first input terminal of the XOR gate 604 may be used to receive the first input signal IN1, and the second input terminal of the XOR gate 604 may be used to receive the second input signal IN2; a first AND gate 605, wherein the first input terminal of the first AND gate 605 may be electrically connected to the output terminal of the second NOT gate 603, and the output terminal of the first The second input terminal of the first AND gate 605 can be electrically connected to the output terminal of the XOR gate 604, and the output terminal of the first AND gate 605 can be used to output the second selection signal S1; the third NOT gate 606, the input terminal of the third NOT gate 606 can be used to receive the first input signal IN1; the second AND gate 607, the first input terminal of the second AND gate 607 can be electrically connected to the output terminal of the third NOT gate 606, the second input terminal of the second AND gate 607 can be electrically connected to the output terminal of the XOR gate 604, and the output terminal of the second AND gate 607 can be used to output the third selection signal S2; the third AND gate 608, the first input terminal of the third AND gate 608 can be used to receive the first input signal IN1, the second input terminal of the third AND gate 608 can be used to receive the second input signal IN2, and the output terminal of the third AND gate can be used to output the fourth selection signal S3.

[0070] That is, in the embodiment of the present invention:

[0071] S0=NOT(IN2ORIN1)

[0072] S1=NOT(IN2)AND(IN2XORIN1)

[0073] S2=NOT(IN1)AND(IN2XORIN1)

[0074] S3=IN2ANDIN1

[0075] Among them, NOT represents NOT gate, OR represents OR gate, AND represents AND gate, and XOR represents XOR gate.

[0076] Figure 7 is a circuit diagram showing a voltage divider subcircuit according to an embodiment of the present disclosure.

[0077] like Figure 7As shown, the voltage divider subcircuit 700 may include: a first transistor 701, the control end of the first transistor 701 may be used to receive the first selection signal S0, the first end of the first transistor 701 may be electrically connected to the first voltage division node n1, and the second end of the first transistor 701 may be used to output the first voltage signal Vout0; a second transistor 702, the control end of the second transistor 702 may be used to receive the second selection signal S1, the first end of the second transistor 702 may be electrically connected to the second voltage division node n2, and the second end of the second transistor 702 may be used to output the second voltage signal Vout0. voltage signal Vout1; a third transistor 703, the control end of the third transistor 703 can be used to receive the third selection signal S2, the first end of the third transistor 703 can be electrically connected to the third voltage dividing node n3, and the second end of the third transistor 703 can be used to output the third voltage signal Vout2; a fourth transistor 704, the control end of the fourth transistor 704 can be used to receive the fourth selection signal S3, the first end of the fourth transistor 704 can be electrically connected to the fourth voltage dividing node n4, and the second end of the fourth transistor 704 can be used to output the fourth voltage signal Vout3.

[0078] Continue to refer Figure 7 The voltage divider subcircuit 700 may further include a power supply voltage Vdd and voltage divider resistors R1-R5 connected in series, wherein a first end of the resistor R1 may be electrically connected to the power supply voltage Vdd, a second end of the resistor R1 and a first end of the resistor R2 may be connected to a first voltage divider node n1, a second end of the resistor R2 and a first end of the resistor R3 may be connected to a second voltage divider node n2, a second end of the resistor R3 and a first end of the resistor R4 may be connected to a third voltage divider node n3, a second end of the resistor R4 and a first end of the resistor R5 may be connected to a fourth voltage divider node n4, and a second end of the resistor R5 may be grounded.

[0079] In the embodiment of the present invention, according to the voltage division formula, it can be known that:

[0080] Vout0=Vdd*(R2+R3+R4+R5) / (R1+R2+R3+R4+R5)

[0081] Vout1=Vdd*(R3+R4+R5) / (R1+R2+R3+R4+R5)

[0082] Vout2=Vdd*(R4+R5) / (R1+R2+R3+R4+R5)

[0083] Vout3=Vdd*R5 / (R1+R2+R3+R4+R5)

[0084] It can be seen from the above formula that the first voltage signal Vout0 is greater than the second voltage signal Vout1, the second voltage signal Vout1 is greater than the third voltage signal Vout2, and the third voltage signal Vout2 is greater than the fourth voltage signal Vout3, that is, Vout0>Vout1>Vout2>Vout3. The specific resistance values ​​of each voltage divider resistor and the size of the power supply voltage can be determined according to the application scenario.

[0085] In the embodiment of the present invention, the first transistor to the fourth transistor 701-704 can all be NMOS transistors, which are turned on at a high level. However, the present invention is not limited to this. In other embodiments, the first transistor to the fourth transistor 701-704 can also be PMOS transistors, which are turned on at a low level, and the circuit structure of the control subcircuit can be changed accordingly. Alternatively, in some embodiments, some of the first transistor to the fourth transistor 701-704 are NMOS transistors and some are PMOS transistors.

[0086] When the first to fourth transistors 701-704 are all NMOS transistors, the control end of each NMOS transistor can be the gate of the corresponding transistor, the first end can be the source of the corresponding transistor, and the second end can be the drain of the corresponding transistor; or, the first end can be the drain of the corresponding transistor, and the second end can be the source of the corresponding transistor.

[0087] Figure 8 is a circuit diagram showing an output conversion circuit according to an embodiment of the present disclosure.

[0088] like Figure 8 As shown, the output conversion circuit 800 may include: a comparison subcircuit 810, which can be configured to receive the voltage signal Vout (one of Vout0-Vout3) output by the redundant interconnection element Red.TSV as its input voltage Vin, and compare the voltage signal Vout with the first reference signal Vref_1 / 2, the second reference signal Vref_upper and the third reference signal Vref_lower to output the first comparison signal C1, the second comparison signal C2 and the third comparison signal C3 respectively; a sampling subcircuit 820, which can be configured to generate the first output signal OUT1 and the second output signal OUT2 according to the first comparison signal C1, the second comparison signal C2 and the third comparison signal C3.

[0089] Continue to refer Figure 8, the comparison subcircuit 810 may further include: a first comparator 811, a non-inverting input terminal of the first comparator 811 may be used to receive the voltage signal Vout, an inverting input terminal of the first comparator 811 may be used to receive the first reference signal Vref_1 / 2, and an output terminal of the first comparator 811 may be used to output the first comparison signal C1; a second comparator 812, a non-inverting input terminal of the second comparator 812 may be used to receive the voltage signal Vout, an inverting input terminal of the second comparator 812 may be used to receive the second reference signal Vref_upper, and an output terminal of the second comparator 812 may be used to output the second comparison signal C2; a third comparator 813, a non-inverting input terminal of the third comparator 813 may be used to receive the voltage signal, an inverting input terminal of the third comparator 813 may be used to receive the third reference signal Vref_lower, and an output terminal of the third comparator 813 may be used to output the third comparison signal C3.

[0090] In the embodiment of the present invention, the second reference signal Vref_upper is greater than the first reference signal Vref_1 / 2, and the first reference signal Vref_1 / 2 is greater than the third reference signal Vref_lower, that is, Vref_upper>Vref_1 / 2>Vref_lower.

[0091] Among them, for each comparator, if the voltage of the non-inverting input terminal is greater than the voltage of the inverting input terminal, the output is a high level; conversely, if the voltage of the non-inverting input terminal is less than the voltage of the inverting input terminal, the output is a low level.

[0092] exist Figure 8 In the illustrated embodiment, the sampling subcircuit 820 may further include: a fourth NOT gate 821, an input end of the fourth NOT gate 821 may be electrically connected to the output end of the first comparator 811, and the output end of the fourth NOT gate 821 may be used to output the second output signal OUT2; an X-NOR gate 822, a first input end of the X-NOR gate 822 may be electrically connected to the output end of the first comparator 811, a second input end of the X-NOR gate 822 may be electrically connected to the output end of the second comparator 812, a third input end of the X-NOR gate 822 may be electrically connected to the output end of the third comparator 813, and the output end of the X-NOR gate 822 may be used to output the first output signal OUT1.

[0093] That is, in the embodiment of the present invention:

[0094] OUT2=NOT(C1)

[0095] OUT1=NOT(C1XOR C2XOR C3)

[0096] Among them, NOT represents a NOT gate, and XOR represents an exclusive OR gate.

[0097] Fig. 9 It is a signal level schematic diagram showing a comparison sub-circuit according to an embodiment of the present disclosure.

[0098] As Fig. 9 shown, assume that when the outputs of the first comparator to the third comparator 811-813 are high level VH, it is 1.2V, and when the outputs are low level VL, it is 0V. Also assume that the second reference signal Vref_upper = 0.9V, the first reference signal Vref_1 / 2 = 0.6V, and the third reference signal Vref_lower = 0.3V.

[0099] At the same time, assume that Vout0 > 0.9V, 0.6V < Vout1 < 0.9V, 0.3V < Vout2 < 0.6V, and Vout3 < 0.3V. Then, the input-output relationship of the control sub-circuit as described in Table 1 below can be obtained:

[0100] Table 1

[0101]

[0102]

[0103] Similarly, the input-output relationship of the voltage dividing sub-circuit as described in Table 2 below can be obtained:

[0104] Table 2

[0105] S0 S1 S2 S3 Vout 1 0 0 0 Vout0 0 1 0 0 Vout1 0 0 1 0 Vout2 0 0 0 1 Vout3

[0106] The input-output relationship of the comparison sub-circuit as described in Table 3 below can also be obtained:

[0107] Table 3

[0108] Vin C1 C2 C3 Vout0 1 1 1 Vout1 1 0 1 Vout2 0 0 1 Vout3 0 0 0

[0109] By the same token, the input-output relationship of the sampling sub-circuit as described in Table 4 below can be obtained:

[0110] Table 4

[0111] C1 C2 C3 OUT2 OUT1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1

[0112] As can be seen from the above tables, the semiconductor device provided by the embodiment of the present invention can ensure the correct transmission of data.

[0113] It should be noted that in the embodiment of the present invention, 1 represents that the input or output is high level, and 0 represents that the input or output is low level. However, the present invention is not limited thereto.

[0114] Figure 10-12 The control subcircuit, voltage dividing subcircuit and output conversion circuit are described by taking a specific example. Assuming that the first main interconnection element TSV0 and the second main interconnection element TSV1 in the first group of interconnection elements fail at the same time, the input conversion circuit and the output conversion circuit are started.

[0115] For example, IN1=0, IN2=1, S2 of the control subcircuit is at a high level, thereby turning on the third NMOS of the voltage divider subcircuit, and outputting Vout2 to Red.TSV. Red.TSV inputs Vout2 to Vin of the comparison subcircuit, and compares and grades Vout2 through three comparators, and finally restores it to two bits (OUT1, OUT2) through the sampling subcircuit.

[0116] Fig.13 is a schematic diagram showing a state of a semiconductor device according to an embodiment of the present disclosure.

[0117] like Fig.13 As shown, Figure 5 Compared with the illustrated embodiment, the difference lies in that the first input multiplexer 503 and the second input multiplexer 504 of the first group of interconnection elements 1 can also be configured to receive the first input signal IN1 and the second input signal IN2, respectively, and when the first main interconnection element TSV0 and the second main interconnection element TSV1 fail at the same time, the first input signal IN1 and the second input signal IN2 are respectively input to the input conversion circuit 501.

[0118] Continue to refer Fig.13 The first output multiplexer 505 and the second output multiplexer 506 of the first group interconnection element 1 can also be configured to receive and output the first output signal OUT1 and the second output signal OUT2 of the output conversion circuit 502 respectively if the first master interconnection element TSV0 and the second master interconnection element TSV1 fail at the same time.

[0119] Fig.14 is a schematic diagram showing a state of another semiconductor device according to an embodiment of the present disclosure.

[0120] like Fig.14 As shown, Figure 5Compared with the illustrated embodiment, the difference lies in that the first input multiplexer 503 and the second input multiplexer 504 can also be configured so that if one of the first main interconnection element TSV0 and the second main interconnection element TSV1 fails, the input signal corresponding to the failed main interconnection element is input to the redundant interconnection element, and the input signal corresponding to the other main interconnection element that has not failed is input to the other main interconnection element.

[0121] Continue to refer Fig.14 The first output multiplexer 505 and the second output multiplexer 506 can also be configured such that if one of the first main interconnection element TSV0 and the second main interconnection element TSV1 fails, the output signal corresponding to the failed main interconnection element is received through the redundant interconnection element, and the output signal corresponding to the other main interconnection element that has not failed is received through the other main interconnection element.

[0122] For example, assuming that the first main interconnection element TSV0 of the first group of interconnection elements 1 fails (indicated by "X" in the figure), the first input multiplexer 503 inputs the first input signal IN1 to the redundant interconnection element Red.TSV, and transmits it to the first output multiplexer 505 through the redundant interconnection element Red.TSV, thereby outputting the first output signal OUT1.

[0123] For another example, assuming that the second main interconnection element TSV1 of the Nth group of interconnection elements N fails (indicated by "X" in the figure), the second input multiplexer 504 inputs the second input signal IN2 to the redundant interconnection element Red.TSV, and transmits it to the second output multiplexer 506 through the redundant interconnection element Red.TSV, thereby outputting the second output signal OUT2.

[0124] That is, if only one main interconnection element fails in a group of interconnection elements, the input signal corresponding to the main interconnection element without failure is transmitted through the original main interconnection element, and the input signal corresponding to the faulty main interconnection element is transmitted through the middle redundant interconnection element. The input and output conversion circuit can be bypassed here, that is, the input and output conversion circuit is used when two or more main interconnection elements fail at the same time.

[0125] It should be noted that, in the above embodiments, a group of interconnection elements including two main interconnection elements is used as an example for explanation, but the present invention is not limited thereto. A group of interconnection elements may also include more than two main interconnection elements. For example, assuming that a group of interconnection elements includes three main interconnection elements, and three signals IN1-IN3 are input at this time, the control subcircuit in the input conversion circuit may output eight selection signals S0-S7 according to the input IN1-IN3. The high levels of the eight selection signals correspond to the input states of IN1-IN3 one by one. According to the high levels of the eight selection signals S0-S7, the voltage divider subcircuit in the input conversion circuit may be turned on accordingly, and any one of the eight voltage signals Vout0-Vout7 may be selected to the redundant interconnection element. The redundant interconnection element inputs the selected voltage signal to the comparison subcircuit. Comparators with corresponding levels may compare the eight voltage signals in different levels, and finally restore them to 3 bits (OUT1, OUT2, OUT3) through corresponding sampling subcircuits.

[0126] In addition, the input conversion circuit and the output conversion circuit given in the above embodiments are only used for illustration, and any structural deformation may be made thereto as long as the purpose of the present invention can be achieved.

[0127] The exemplary embodiments of the semiconductor device proposed in the present disclosure are described and / or illustrated in detail above. However, the embodiments of the present disclosure are not limited to the specific embodiments described herein. On the contrary, the components and / or steps of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of an embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "one", "one" and "above" are used to indicate the presence of one or more elements / components / etc. The terms "comprising", "including" and "having" are used to indicate the meaning of open inclusion and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc. In addition, the terms "first" and "second" in the claims and the specification are used only as marks and are not numerical restrictions on their objects.

[0128] Although the semiconductor device presented in the present disclosure has been described in terms of various specific embodiments, those skilled in the art will recognize that the disclosure can be practiced with modification within the spirit and scope of the claims.

Claims

1. A semiconductor device, It is characterized in that include: a plurality of primary interconnect elements configured to provide a plurality of signal transmission channels; redundant interconnect elements; as well as a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail; The plurality of primary interconnect elements include: A first main interconnection element, configured to provide a first signal transmission channel between a first input signal and a first output signal in a normal state; a second main interconnection element, configured to provide a second signal transmission channel between a second input signal and a second output signal in a normal state; The logic control circuit comprises: an input conversion circuit configured to generate a voltage signal to the redundant interconnection element according to the first input signal and the second input signal if the first primary interconnection element and the second primary interconnection element fail simultaneously; an output conversion circuit configured to generate the first output signal and the second output signal according to the voltage signal if the first main interconnection element and the second main interconnection element fail simultaneously; The voltage signal includes a first voltage signal, a second voltage signal, a third voltage signal and a fourth voltage signal; wherein the input conversion circuit includes: a control subcircuit configured to generate a first gating signal, a second gating signal, a third gating signal and a fourth gating signal according to the first input signal and the second input signal; The voltage dividing sub-circuit is configured to select any one of the first to fourth voltage signals to be output to the redundant interconnection element according to the first selection signal, the second selection signal, the third selection signal and the fourth selection signal.

2. The semiconductor device according to claim 1, It is characterized in that The control subcircuit comprises: An OR gate, wherein a first input terminal of the OR gate is used to receive the first input signal, and a second input terminal of the OR gate is used to receive the second input signal; a first NOT gate, wherein an input end of the first NOT gate is electrically connected to an output end of the OR gate, and an output end of the first NOT gate is used to output the first selection signal; A second NOT gate, wherein an input end of the second NOT gate is used to receive the second input signal; an XOR gate, wherein a first input terminal of the XOR gate is used to receive the first input signal, and a second input terminal of the XOR gate is used to receive the second input signal; a first AND gate, wherein a first input terminal of the first AND gate is electrically connected to an output terminal of the second NOT gate, a second input terminal of the first AND gate is electrically connected to an output terminal of the XOR gate, and an output terminal of the first AND gate is used to output the second selection signal; a third NOT gate, wherein an input end of the third NOT gate is used to receive the first input signal; a second AND gate, wherein a first input terminal of the second AND gate is electrically connected to an output terminal of the third NOT gate, a second input terminal of the second AND gate is electrically connected to an output terminal of the XOR gate, and an output terminal of the second AND gate is used to output the third selection signal; A third AND gate, wherein the first input terminal of the third AND gate is used to receive the first input signal, the second input terminal of the third AND gate is used to receive the second input signal, and the output terminal of the third AND gate is used to output the fourth selection signal.

3. The semiconductor device according to claim 1, It is characterized in that The voltage divider subcircuit comprises: a first transistor, wherein a control terminal of the first transistor is used to receive the first selection signal, a first terminal of the first transistor is electrically connected to a first voltage dividing node, and a second terminal of the first transistor is used to output the first voltage signal; a second transistor, wherein a control terminal of the second transistor is used to receive the second selection signal, a first terminal of the second transistor is electrically connected to a second voltage dividing node, and a second terminal of the second transistor is used to output the second voltage signal; a third transistor, wherein a control terminal of the third transistor is used to receive the third selection signal, a first terminal of the third transistor is electrically connected to a third voltage dividing node, and a second terminal of the third transistor is used to output the third voltage signal; A fourth transistor, wherein the control end of the fourth transistor is used to receive the fourth selection signal, the first end of the fourth transistor is electrically connected to a fourth voltage dividing node, and the second end of the fourth transistor is used to output the fourth voltage signal.

4. A semiconductor device, It is characterized in that include: a plurality of primary interconnect elements configured to provide a plurality of signal transmission channels; redundant interconnect elements; as well as a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail; The plurality of primary interconnect elements include: A first main interconnection element, configured to provide a first signal transmission channel between a first input signal and a first output signal in a normal state; a second main interconnection element, configured to provide a second signal transmission channel between a second input signal and a second output signal in a normal state; The logic control circuit comprises: an input conversion circuit configured to generate a voltage signal to the redundant interconnection element according to the first input signal and the second input signal if the first primary interconnection element and the second primary interconnection element fail simultaneously; an output conversion circuit configured to generate the first output signal and the second output signal according to the voltage signal if the first main interconnection element and the second main interconnection element fail simultaneously; The output conversion circuit comprises: a comparison subcircuit configured to receive the voltage signal output by the redundant interconnection element, and compare the voltage signal with a first reference signal, a second reference signal, and a third reference signal, respectively, to output a first comparison signal, a second comparison signal, and a third comparison signal, respectively; The sampling subcircuit is configured to generate the first output signal and the second output signal according to the first comparison signal, the second comparison signal and the third comparison signal.

5. The semiconductor device according to claim 4, It is characterized in that The comparison subcircuit comprises: A first comparator, wherein a non-inverting input terminal of the first comparator is used to receive the voltage signal, an inverting input terminal of the first comparator is used to receive the first reference signal, and an output terminal of the first comparator is used to output the first comparison signal; a second comparator, wherein a non-inverting input terminal of the second comparator is used to receive the voltage signal, an inverting input terminal of the second comparator is used to receive the second reference signal, and an output terminal of the second comparator is used to output the second comparison signal; A third comparator, wherein the non-inverting input terminal of the third comparator is used to receive the voltage signal, the inverting input terminal of the third comparator is used to receive the third reference signal, and the output terminal of the third comparator is used to output the third comparison signal.

6. The semiconductor device according to claim 5, It is characterized in that The sampling subcircuit comprises: a fourth NOT gate, wherein an input end of the fourth NOT gate is electrically connected to an output end of the first comparator, and an output end of the fourth NOT gate is used to output the second output signal; An XNOR gate, wherein a first input terminal of the XNOR gate is electrically connected to an output terminal of the first comparator, a second input terminal of the XNOR gate is electrically connected to an output terminal of the second comparator, a third input terminal of the XNOR gate is electrically connected to an output terminal of the third comparator, and an output terminal of the XNOR gate is used to output the first output signal.

7. A semiconductor device, It is characterized in that include: a plurality of primary interconnect elements configured to provide a plurality of signal transmission channels; redundant interconnect elements; as well as a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail; The plurality of primary interconnect elements include: A first main interconnection element, configured to provide a first signal transmission channel between a first input signal and a first output signal in a normal state; a second main interconnection element, configured to provide a second signal transmission channel between a second input signal and a second output signal in a normal state; The logic control circuit comprises: an input conversion circuit configured to generate a voltage signal to the redundant interconnection element according to the first input signal and the second input signal if the first primary interconnection element and the second primary interconnection element fail simultaneously; an output conversion circuit configured to generate the first output signal and the second output signal according to the voltage signal if the first main interconnection element and the second main interconnection element fail simultaneously; Also includes: The first input multiplexer and the second input multiplexer are configured to receive the first input signal and the second input signal respectively, and input the first input signal and the second input signal to the input conversion circuit respectively when the first main interconnection element and the second main interconnection element fail at the same time.

8. The semiconductor device according to claim 7, It is characterized in that The first input multiplexer and the second input multiplexer are further configured to input the first input signal and the second input signal to the first master interconnection element and the second master interconnection element, respectively, if neither the first master interconnection element nor the second master interconnection element fails.

9. The semiconductor device according to claim 7, It is characterized in that The first input multiplexer and the second input multiplexer are further configured to input an input signal corresponding to the failed main interconnection element to the redundant interconnection element if one of the first main interconnection element and the second main interconnection element fails, and input an input signal corresponding to another main interconnection element that has not failed to the other main interconnection element.

10. A semiconductor device, It is characterized in that include: a plurality of primary interconnect elements configured to provide a plurality of signal transmission channels; redundant interconnect elements; as well as a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection elements if any two or more of the plurality of main interconnection elements fail; The plurality of primary interconnect elements include: A first main interconnection element, configured to provide a first signal transmission channel between a first input signal and a first output signal in a normal state; a second main interconnection element, configured to provide a second signal transmission channel between a second input signal and a second output signal in a normal state; The logic control circuit comprises: an input conversion circuit configured to generate a voltage signal to the redundant interconnection element according to the first input signal and the second input signal if the first primary interconnection element and the second primary interconnection element fail simultaneously; an output conversion circuit configured to generate the first output signal and the second output signal according to the voltage signal if the first main interconnection element and the second main interconnection element fail simultaneously; Also includes: The first output multiplexer and the second output multiplexer are configured to respectively receive and output a first output signal and a second output signal of the output conversion circuit if the first master interconnection element and the second master interconnection element fail simultaneously.

11. The semiconductor device according to claim 10, It is characterized in that The first output multiplexer and the second output multiplexer are further configured to receive and output the first output signal and the second output signal of the first master interconnection element and the second master interconnection element, respectively, if neither the first master interconnection element nor the second master interconnection element fails.

12. The semiconductor device according to claim 10, It is characterized in that The first output multiplexer and the second output multiplexer are further configured to receive an output signal corresponding to the failed main interconnection element through the redundant interconnection element if one of the first main interconnection element and the second main interconnection element fails, and receive an output signal corresponding to another main interconnection element that has not failed through the other main interconnection element.

13. The semiconductor device according to claim 10, It is characterized in that The redundant interconnection element is disposed between the plurality of primary interconnection elements.

14. The semiconductor device according to claim 10, It is characterized in that The plurality of primary interconnect elements and the redundant interconnect element are through silicon vias.

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