Neural network processing system

Abstract

A neural network processing system includes a first front-end module, a second front-end module, a first back-end module, and a second back-end module. The first front-end module performs a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first back-end module receives the first operation result provided by the first front-end module and the fourth operation result provided by the second front-end module via a second bridge, and sums the first operation result and the fourth operation result. The second back-end module receives the third operation result provided by the second front-end module and the second operation result provided by the first front-end module via a first bridge, and sums the third operation result and the second operation result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority from Korean Patent Application No. 10-2018-0106917 filed in the Korean Intellectual Property Office on September 7, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a neural network processing system. Background Art

[0004] Deep learning refers to a type of operation based on a deep learning architecture using an algorithm set, which attempts to model high-level abstractions of input data using a deep graph with multiple processing levels in a hierarchy. Generally speaking, a deep learning architecture may include multiple neuron hierarchies and parameters. Convolutional Neural Networks (CNNs) in deep learning architectures are widely used in many artificial intelligence and machine learning applications, such as image classification, image caption creation, visual question response, and automated driving vehicles.

[0005] Since CNN systems include many parameters and require many operations, such as for image classification, CNN systems are highly complex. Therefore, the cost of hardware resources becomes an issue for implementing CNN systems, as does the amount of power consumed by the hardware resources. Specifically, in the case of CNNs implemented in recent mobile systems (e.g., mobile communication devices), an architecture that can implement artificial intelligence while maintaining low cost and power consumption is required. Summary of the Invention

[0006] Various aspects of the present disclosure provide a neural network system capable of implementing artificial intelligence while having low cost and low power consumption.

[0007] However, the various aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a neural processing system includes a first front-end module, a second front-end module, a first back-end module, and a second back-end module. The first front-end module performs a feature extraction operation using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first back-end module receives an input of the first operation result provided from the first front-end module and the fourth operation result provided from the second front-end module through a second bridge, so as to sum the first operation result and the fourth operation result. The second back-end module receives an input of the third operation result provided from the second front-end module and the second operation result provided from the first front-end module through a first bridge, so as to sum the third operation result and the second operation result.

[0009] According to another aspect of the present disclosure, a neural processing system includes a first neural processing unit, a bridge unit, and a second neural processing unit. The first neural processing unit includes a first front-end module and a first back-end module. The bridge unit is electrically connected to the first neural processing unit. The second neural processing unit operates in a clock domain different from that of the first neural processing unit. The first front-end module provides a portion of a first operation result obtained by performing a feature extraction operation using a first feature map and a first weight to the first back-end module. The bridge unit provides a portion of a second operation result performed in the second neural processing unit to the first back-end module. The first back-end module sums the portion of the first operation result and the portion of the second operation result.

[0010] According to another aspect of the present disclosure, a neural processing system includes a first neural processing unit, a second neural processing unit, and a workload manager. The first neural processing unit includes a first front-end module and a first back-end module. The second neural processing unit includes a second front-end module and a second back-end module. The workload manager allocates first data in the data used for performing feature extraction to the first neural processing unit, and allocates second data in the data to the second neural processing unit. The first front-end module performs a feature extraction operation on the first data using a first feature map and a first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation on the second data using a second feature map and a second weight, and outputs a third operation result and a fourth operation result. The first back-end module sums the first operation result and the fourth operation result. The second back-end module sums the third operation result and the second operation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram illustrating a computing system according to an embodiment of the present disclosure.

[0013] Figure 2 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

[0014] Figure 3 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

[0015] Figure 4 and Figure 5 is a block diagram illustrating a front-end module of a neural processing system according to an embodiment of the present disclosure.

[0016] Figure 6 is a block diagram illustrating a backend module of a neural processing system according to an embodiment of the present disclosure.

[0017] Figure 7 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure.

[0018] Figure 8 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure.

[0019] Figure 9 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0020] Figure 10 is a block diagram illustrating a neural processing system according to yet another embodiment of the present disclosure.

[0021] Figure 11 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0022] Figure 12 and Figure 13 is a block diagram illustrating a neural processing system according to yet another embodiment of the present disclosure.

[0023] Figure 14 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0024] Figure 15 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0025] Figure 16 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0026] [Explanation of Symbols]

[0027] 1, 2, 3, 4, 5, 6, 7: computing system;

[0028] 10: Neural processing system;

[0029] 20: Clock Management Unit (CMU);

[0030] 30: processor;

[0031] 40: memory;

[0032] 50: Power Management Unit (PMU);

[0033] 60: Storage;

[0034] 70: Display;

[0035] 80: Camera;

[0036] 90: bus;

[0037] 100a: first neural processing unit;

[0038] 100b: second neural processing unit;

[0039] 100c: third neural processing unit;

[0040] 100d: fourth neural processing unit;

[0041] 102a: first front-end module;

[0042] 102b: second front-end module;

[0043] 102c: third front-end module;

[0044] 102d: fourth front-end module;

[0045] 104a: first backend module;

[0046] 104b: second backend module;

[0047] 104c: third backend module;

[0048] 104d: fourth backend module;

[0049] 110: bridge unit;

[0050] 111: first bridge;

[0051] 112: second bridge;

[0052] 120: workload manager;

[0053] 1021a, 1022a: first internal memory;

[0054] 1021b, 1022b: second internal memory;

[0055] 1023a, 1024a: first extraction unit;

[0056] 1023b, 1024b: second extraction unit;

[0057] 1025a, 1026a: first dispatch unit;

[0058] 1025b, 1026b: second dispatch unit;

[0059] 1027a: first MAC array;

[0060] 1027b: Second MAC array;

[0061] 1041a: first summing unit;

[0062] 1041b: second summing unit;

[0063] 1043a: first activation unit;

[0064] 1043b: second activation unit;

[0065] 1045a: first write-back unit;

[0066] 1045b: second write-back unit;

[0067] 1112, 1113, 1114, 1122, 1123, 1124: bridge;

[0068] CLK1: first clock signal;

[0069] CLK2: second clock signal;

[0070] CLK3: the third clock signal;

[0071] CLK4: fourth clock signal;

[0072] DATA, DATA3, DATA4, DATA11, DATA12, DATA21, DATA22: data;

[0073] DATA1: first data;

[0074] DATA2: second data;

[0075] DATA3: the third data;

[0076] DATA4: the fourth data;

[0077] PG1: first power gating signal;

[0078] PG2: second power gating signal;

[0079] PG3: third power gating signal;

[0080] PG4: fourth power gating signal;

[0081] R11: first operation result;

[0082] R12: Second operation result / intermediate result;

[0083] R13, R14: intermediate results;

[0084] R21: result of the third operation;

[0085] R22: fourth operation result / intermediate result;

[0086] R33, R44: intermediate results;

[0087] WB DATA1: first write-back data;

[0088] WB DATA2: Second write-back data. DETAILED DESCRIPTION

[0089] Figure 1 is a schematic diagram illustrating a computing system according to an embodiment of the present disclosure.

[0090] Reference Figure 1According to an embodiment of the present disclosure, a computing system 1 includes a neural processing system 10, a clock management unit 20 (CMU), a processor 30, and a memory 40. The neural processing system 10, the processor 30, and the memory 40 can transmit and receive data via a bus 90. The neural processing system 10 may be or may include one or more neural network processors, which may, for example, implement a convolutional neural network (CNN) by executing instructions and processing data. However, the present disclosure is not limited thereto. That is, the neural processing system 10 may alternatively be implemented by a processor that processes arbitrary vector operations, matrix operations, and the like. The neural processing system 10 may also include instructions stored therein, or may execute instructions stored in the memory 40 or dynamically received from an external source. The neural processing system 10 may also include a memory that is dynamically updated during the learning process described herein to update the learning content and thereby dynamically update new learning. An example of a neural network processor is a graphics processing unit (GPU), but the neural processing system 10 may be implemented using more than one processor (e.g., multiple graphics processors). Thus, as used herein, neural processing system 10 includes at least a neural network processor, but may also be considered to include functionally separable but interdependent software modules, functionally separable but interdependent circuit modules of individual circuit components, data and memory specific to each module and / or unit, and other elements described herein. Figure 1 The neural processing system 10 is shown in FIG. Figure 1 Neural processing system 10 is described as being separate from clock management unit 20 , processor 30 , and memory 40 , but the functions implemented by neural processing system 10 may be implemented in part by or using resources of clock management unit 20 , processor 30 , and memory 40 .

[0091] in addition, Figure 1 The computing system 1 in the embodiment of the present invention may be a computer system comprising one or more computing devices, each of which comprises one or more processors. The processor of the computing system 1 is tangible and non-transitory. The term "non-transitory" expressly disclaims transient characteristics, such as carrier waves or signals or other forms of characteristics that exist only temporarily at any time and at any place. The processor is an article of manufacture and / or machine component. Figure 1The processor of the neural processing system 10 or the computer system of other embodiments herein is configured to execute software instructions to implement the functions described in various embodiments herein. The processor of the computer system can be a general-purpose processor, a part of an application specific integrated circuit (ASIC), a microprocessor, a microcomputer, a processor chip, a controller, a microcontroller, a digital signal processor (DSP), a state machine, or a programmable logic device. The processor of the computer system can also be a logic circuit including a programmable gate array (PGA) (for example, a field programmable gate array (FPGA)) or another type of circuit including discrete gates and / or transistor logic. The processor can also be a central processing unit (CPU), a graphics processing unit (GPU), or both. In addition, any processor described herein may include multiple processors, parallel processors, or may include both. Multiple processors may be included in a single device or multiple devices or coupled to a single device or multiple devices.

[0092] Implementation Figure 1 The computer system of the computing system 1 in the embodiment of the present invention can implement all or part of the methods described herein. For example, the functions such as feature extraction, summation and activation described herein can be implemented by a computer system executing software instructions through one or more processors described herein.

[0093] In the present embodiment, the neural processing system 10 may implement and / or process a neural network comprising a plurality of layers (e.g., a feature extraction layer and a feature classification layer). Here, the feature extraction layer corresponds to the initial layer of the neural network and may, for example, be used to extract low-level features such as edges and gradients from an input image. On the other hand, the feature classification layer corresponds to a secondary layer of the neural network and may, for example, be used to extract more complex and high-level features such as a face, eyes, and nose from an input image. To explain, the feature extraction layer may be viewed as extracting low-level features before the feature classification layer extracts more complex and high-level features. The feature classification layer corresponds to a fully-connected layer.

[0094] To extract features from an input image, neural processing system 10 may use filters or kernels to compute the input image or feature map. For example, neural processing system 10 may use convolution filters or kernels to perform a convolution operation on the input image or feature map. Furthermore, neural processing system 10 may utilize weights corresponding to the feature map to perform the operation, with the weights being determined based on the specific implementation.

[0095] In the present embodiment, it should be particularly noted that the neural processing system 10 includes a plurality of neural processing units, including a first neural processing unit 100a and a second neural processing unit 100b. The first neural processing unit 100a and the second neural processing unit 100b may be implemented by physically separated neural network processors as described above, and / or by logically and / or functionally separated software modules executed by the same or different physically separated neural network processors. For ease of explanation, in the present embodiment, the neural processing system 10 is shown as including a first neural processing unit 100a and a second neural processing unit 100b, but the scope of the present disclosure is not limited thereto. Depending on the purpose of the specific embodiment, the neural processing system 10 may include n (here, n is a natural number of 2 or greater than 2) neural processing units.

[0096] Using multiple neural processing units, such as the first neural processing unit 100a and the second neural processing unit 100b described herein, provides several practical opportunities to reduce cost and / or power consumption.

[0097] The clock management unit 20 generates a first clock signal CLK1 and a second clock signal CLK2 for driving the neural processing system 10. The clock management unit 20 provides the first clock signal CLK1 and the second clock signal CLK2 to each of the first neural processing unit 100a and the second neural processing unit 100b. Therefore, the first neural processing unit 100a is driven according to the first clock signal CLK1. The second neural processing unit 100b is driven according to the second clock signal CLK2. As explained herein, for different neural processing units, such as the first neural processing unit 100a and the second neural processing unit 100b, different clocks can be selectively controlled in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed.

[0098] In some embodiments of the present disclosure, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be different from each other. In other words, the clock domain in which the first neural processing unit 100a operates may be different from the clock domain in which the second neural processing unit 100b operates.

[0099] The clock management unit 20 can control the frequency of the first clock signal CLK1 and the second clock signal CLK2 as needed. In addition, the clock management unit 20 can also perform clock gating on the first clock signal CLK1 and the second clock signal CLK2 as needed.

[0100] Processor 30 is a processor that performs general arithmetic operations, which are different from artificial intelligence operations, vector operations, matrix operations, etc., which are processed by neural processing system 10. Processor 30 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), etc., but the scope of the present disclosure is not limited thereto. In this embodiment, processor 30 generally controls computing system 1.

[0101] Memory 40 can store data used by processor 30 when executing applications or controlling computing system 1. Memory 40 can also be used to store data for neural processing system 10, but neural processing system 10 may include its own memory to store instructions and data. Memory 40 can be, for example, dynamic random access memory (DRAM), but the scope of this disclosure is not limited thereto. In this embodiment, image data processed by neural processing system 10 using, for example, a CNN can be stored in memory 40.

[0102] Figure 2 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

[0103] Reference Figure 2 , a neural processing system 10 according to an embodiment of the present disclosure includes a first neural processing unit 100a and a second neural processing unit 100b. A bridge unit 110 is provided between the first neural processing unit 100a and the second neural processing unit 100b. As described above, the first neural processing unit 100a and the second neural processing unit 100b can be physically separated and functionally separated. As explained herein, for example, the use of one or more bridges in the bridge unit 110 enhances the practical ability to selectively control the first neural processing unit 100a and the second neural processing unit 100b in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed.

[0104] First, the bridge unit 110 includes a first bridge 111 and a second bridge 112. The first bridge 111 is used to transmit the intermediate results generated by the operation of the first neural processing unit 100a to the second neural processing unit 100b. The second bridge 112 is used to transmit the intermediate results generated by the operation of the second neural processing unit 100b to the first neural processing unit 100a.

[0105] To this end, the first neural processing unit 100a and the second neural processing unit 100b can operate in different clock domains. In this case, the bridge unit 110 can be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in a clock domain different from the first neural processing unit 100a.

[0106] Therefore, when the first neural processing unit 100a and the second neural processing unit 100b operate in different clock domains, the first bridge 111 and the second bridge 112 included in the bridge unit 110 are implemented as asynchronous bridges to enable data to be transmitted between the different clock domains.

[0107] In this embodiment, the first neural processing unit 100a includes a first front-end module 102a and a first back-end module 104a. The second neural processing unit 100b includes a second front-end module 102b and a second back-end module 104b. The first neural processing unit 100a can process the first data DATA1 in the data to be processed by the neural processing system 10. The second neural processing unit 100b can process the second data DATA2 in the data to be processed by the neural processing system 10. Specifically, the first front-end module 102a performs a feature extraction operation on the first data DATA1 using the first feature map and the first weight, and outputs a first operation result R11 and a second operation result R12. In addition, the second front-end module 102b performs a feature extraction operation on the second data DATA2 using the second feature map and the second weight, and outputs a third operation result R21 and a fourth operation result R22.

[0108] The first back-end module 104a receives the first computation result R11 provided by the first front-end module 102a and the fourth computation result R22 provided by the second front-end module 102b via the second bridge 112. The first back-end module 104a sums the first computation result R11 and the fourth computation result R22. Meanwhile, the second back-end module 104b receives the third computation result R21 provided by the second front-end module 102b and the second computation result R12 provided by the first front-end module 102a via the first bridge 111. The second back-end module 104b sums the third computation result R21 and the second computation result R12.

[0109] In some embodiments of the present disclosure, the first front-end module 102a and the first back-end module 104a are driven by a first clock signal CLK1, and the second front-end module 102b and the second back-end module 104b are driven by a second clock signal CLK2 having a frequency different from that of the first clock signal CLK1. In other words, the first front-end module 102a and the first back-end module 104a can operate in a different clock domain than the second front-end module 102b and the second back-end module 104b.

[0110] On the other hand, in this embodiment, the first back-end module 104a can provide the first write-back data WB DATA1 to the first front-end module 102a, and the second back-end module 104b can provide the second write-back data WB DATA2 to the second front-end module 102b. The first write-back data WB DATA1 and the second write-back data WB DATA2 are input to each of the first front-end module 102a and the second front-end module 102b to allow repeated feature extraction operations.

[0111] Now refer to Figure 3 , a more detailed structure of the neural processing system 10 according to an embodiment of the present disclosure will be explained.

[0112] Figure 3 is a block diagram illustrating a neural processing system according to an embodiment of the present disclosure.

[0113] Reference Figure 3 According to an embodiment of the present disclosure, the first front-end module 102a included in the first neural processing unit 100a of the neural processing system 10 includes multiple first internal memories 1021a and 1022a, multiple first extraction units 1023a and 1024a, multiple first dispatch units 1025a and 1026a, and a first MAC array 1027a (multiplication and accumulation array).

[0114] The first internal memories 1021a and 1022a can store the first feature map and first weight used by the first front-end module 102a to perform feature extraction operations on the data DATA11 and DATA12. In this embodiment, the first internal memories 1021a and 1022a can be implemented as static random-access memories (SRAMs), but the scope of the present disclosure is not limited thereto.

[0115] The first extraction units 1023a and 1024a extract the first feature map and the first weight from each of the first internal memories 1021a and 1022a and transfer the first feature map and the first weight to the first dispatching units 1025a and 1026a.

[0116] The first dispatching units 1025a and 1026a transmit the extracted first feature map and first weight for each channel to the first MAC array 1027a. For example, the first dispatching units 1025a and 1026a select a weight and a corresponding feature map for each of k (where k is a natural number) channels and transmit the weight and the corresponding feature map to the first MAC array 1027a.

[0117] The first MAC array 1027a performs a multiplication-accumulation operation on the data transmitted from the first dispatch units 1025a and 1026a. For example, the first MAC array 1027a performs a multiplication-accumulation operation on the data for each of the k channels. In addition, the first MAC array 1027a outputs a first operation result R11 and a second operation result R12.

[0118] Then, as described above, the first operation result R11 is provided to the first backend module 104 a , and the second operation result R12 may be provided to the second backend module 104 b of the second neural processing unit 100 b through the first bridge 111 .

[0119] On the other hand, the first backend module 104a included in the first neural processing unit 100a of the neural processing system 10 according to an embodiment of the present disclosure includes a first summing unit 1041a, a first activation unit 1043a, and a first write-back unit 1045a.

[0120] The first summing unit 1041a performs a summing operation on the first operation result R11 and the fourth operation result R22 to generate a summing result. Here, the fourth operation result R22 may be provided from the second front-end module 102b of the second neural processing unit 100b via the second bridge 112.

[0121] The first activation unit 1043a may perform an activation operation on the result of the summation operation to generate an activation result. In some embodiments of the present disclosure, the activation operation may include an operation using an activation function (e.g., a rectified linear unit (ReLU), a sigmoid function, and a hyperbolic tangent function (tanh)), but the scope of the present disclosure is not limited thereto.

[0122] The first write-back unit 1045a performs a write-back operation to provide the execution result of the activation operation to the first front-end module 102a. Specifically, the first write-back unit 1045a can store the execution result of the activation operation in the first internal memory 1021a and 1022a.

[0123] On the other hand, the second front-end module 102b included in the second neural processing unit 100b of the neural processing system 10 according to an embodiment of the present disclosure includes multiple second internal memories 1021b and 1022b, multiple second extraction units 1023b and 1024b, multiple second dispatch units 1025b and 1026b, and a second MAC array 1027b.

[0124] The second internal memories 1021b and 1022b can store the second feature maps and second weights used by the second front-end module 102b to perform feature extraction operations on the data DATA21 and DATA22. In this embodiment, the second internal memories 1021b and 1022b can be implemented as SRAM, but the scope of the present disclosure is not limited thereto.

[0125] The second extraction units 1023b and 1024b extract the second feature map and the second weight from each of the second internal memories 1021b and 1022b and transfer the second feature map and the second weight to the second allocation units 1025b and 1026b.

[0126] The second dispatching units 1025b and 1026b transmit the extracted second feature map and second weight for each channel to the second MAC array 1027b. For example, the second dispatching units 1025b and 1026b select a weight and a corresponding feature map for each of k (where k is a natural number) channels and transmit the weight and the corresponding feature map to the second MAC array 1027b.

[0127] The second MAC array 1027b performs a multiplication-accumulation operation on the data transmitted from the second dispatch units 1025b and 1026b. For example, the second MAC array 1027b performs a multiplication-accumulation operation on the data for each of the k channels. In addition, the second MAC array 1027b outputs a third operation result R21 and a fourth operation result R22.

[0128] Then, as described above, the third operation result R21 is provided to the second backend module 104b, and the fourth operation result R22 can be provided to the first backend module 104a of the first neural processing unit 100a through the second bridge 112.

[0129] On the other hand, the second backend module 104b included in the second neural processing unit 100b of the neural processing system 10 according to an embodiment of the present disclosure includes a second summing unit 1041b, a second activation unit 1043b, and a second write-back unit 1045b.

[0130] The second summing unit 1041b performs a summing operation on the third operation result R21 and the second operation result R12 to generate a summing result. Here, the second operation result R12 may be provided from the first front-end module 102a of the first neural processing unit 100a via the first bridge 111.

[0131] The second activation unit 1043b may perform an activation operation on the execution result of the summation operation to generate an execution result. In some embodiments of the present disclosure, the activation operation may include an operation using an activation function (e.g., a rectified linear unit (ReLU), a sigmoid function, and a hyperbolic tangent function (tanh)), but the scope of the present disclosure is not limited thereto.

[0132] The second write-back unit 1045b performs a write-back operation for providing the execution result of the activation operation to the second front-end module 102b. Specifically, the second write-back unit 1045b can store the execution result of the activation operation in the second internal memory 1021b and 1022b.

[0133] Figure 4 and Figure 5 is a block diagram illustrating a front-end module of a neural processing system according to an embodiment of the present disclosure.

[0134] Reference Figure 4 Each of the first internal memories 1021a and 1022a stores a first feature map and a first weight for performing a feature extraction operation on the data DATA11 and the data DATA12. The first extraction units 1023a and 1024a extract the first feature map and the first weight from each of the first internal memories 1021a and 1022a and transmit the first feature map and the first weight to the first dispatching units 1025a and 1026a.

[0135] The first dispatch unit 1025a selects a weight and a corresponding feature map for each of the six channels of data DATA11 and transmits the weight and the corresponding feature map to the first MAC array 1027a. The first dispatch unit 1026a selects a weight and a corresponding feature map for each of the six channels of data DATA12 and transmits the weight and the corresponding feature map to the first MAC array 1027a.

[0136] The first MAC array 1027a performs a multiplication-accumulation operation on data transmitted from the first dispatch units 1025a and 1026a for each of the six channels.

[0137] In this embodiment, among the operation results outputted from the first MAC array 1027a, the first operation result R11 corresponds to the result of the multiplication-accumulation operation on the first, third, and sixth channels, and the second operation result R12 corresponds to the result of the multiplication-accumulation operation on the second, fourth, and fifth channels.

[0138] The first operation result R11 is provided to the first summing unit 1041a of the first backend module 104a, and the second operation result R12 is provided to the first bridge 111 for transmission to the second neural processing unit 100b operating in a different clock domain. Meanwhile, the first summing unit 1041a of the first backend module 104a receives the operation result of the second neural processing unit 100b operating in a different clock domain, such as the fourth operation result R22, through the second bridge 112.

[0139] Next, refer to Figure 5 Each of the second internal memories 1021b and 1022b stores a second feature map and a second weight for performing a feature extraction operation on the data DATA21 and the data DATA22. The second extraction units 1023b and 1024b extract the second feature map and the second weight from each of the second internal memories 1021b and 1022b and transmit the second feature map and the second weight to the second dispatching units 1025b and 1026b.

[0140] The second dispatch unit 1025b selects a weight and a corresponding feature map for each of the six channels of data DATA21 and transmits the selected weight and corresponding feature map to the second MAC array 1027b. The second dispatch unit 1026b selects a weight and a corresponding feature map for each of the six channels of data DATA22 and transmits the selected weight and corresponding feature map to the second MAC array 1027b.

[0141] The second MAC array 1027b performs a multiplication-accumulation operation on data transmitted from the second dispatch units 1025b and 1026b for each of the six channels.

[0142] In this embodiment, the third operation result R21 among the operation results output from the second MAC array 1027b corresponds to the result of the multiplication-accumulation operation on the second, fourth, and fifth channels, and the fourth operation result R22 corresponds to the result of the multiplication-accumulation operation on the first, third, and sixth channels.

[0143] The third operation result R21 is provided to the second summing unit 1041b of the second backend module 104b, and the fourth operation result R22 is provided to the second bridge 112 for transmission to the first neural processing unit 100a operating in a different clock domain. Meanwhile, the second summing unit 1041b of the second backend module 104b receives the operation results of the first neural processing unit 100a operating in a different clock domain, such as the second operation result R12, through the first bridge 111.

[0144] Figure 6 is a block diagram illustrating a backend module of a neural processing system according to an embodiment of the present disclosure.

[0145] Reference Figure 6 , the first summing unit 1041a performs a summing operation on the first operation result R11 and the fourth operation result R22 for each channel to generate a summing result. Figure 4 and Figure 5 In the example, since the total first operation result R11 includes values ​​of three channels among the six channels, and the fourth operation result R22 also includes values ​​of three channels, summation of each of them is performed with respect to the three channels.

[0146] Subsequently, the first activation unit 1043a performs an activation operation on the execution result of the summation operation for each channel to generate an activation result, and the first write-back unit 1045a performs a write-back operation for each channel to provide the execution result of the activation operation to the first front-end module 102a. For example, the first write-back unit 1045a may write back the data corresponding to the first channel in the execution result of the activation operation to the first internal memory 1021a, and may write back the data corresponding to the second and third channels to the first internal memory 1022a.

[0147] On the other hand, the second summing unit 1041b also performs a summing operation on the third operation result R21 and the second operation result R12 for each channel to generate a summing result. Figure 4 and Figure 5 In the example, since the total third operation result R21 includes values ​​of three channels among the six channels, and the second operation result R12 also includes values ​​of three channels, summation of each of them is performed with respect to the three channels.

[0148] Subsequently, the second activation unit 1043b performs an activation operation on the execution result of the summation operation for each channel to generate an activation result. The second write-back unit 1045b performs a write-back operation for each channel to provide the execution result of the activation operation to the second front-end module 102b. For example, the second write-back unit 1045b may write back the data corresponding to the first channel in the execution result of the activation operation to the second internal memory 1021b, and may write back the data corresponding to the second and third channels to the second internal memory 1022b.

[0149] Figure 7 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure, and Figure 8 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure.

[0150] Reference Figure 7 and Figure 8 , different from Figure 1 In the illustrated embodiment, neural processing system 10 of computing system 2 according to this embodiment further includes workload manager 120. As explained herein, the use of a workload manager such as workload manager 120 enhances the practical ability to selectively control individual neural processing units of the plurality of neural processing units in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed.

[0151] The workload manager 120 distributes the first data DATA1 in the data DATA for performing feature extraction to the first neural processing unit 100a. The workload manager 120 distributes the second data DATA2 in the data DATA to the second neural processing unit 100b. Specifically, the workload manager 120 distributes the first data DATA1 in the data DATA for performing feature extraction to the first front-end module 102a, and distributes the second data DATA2 in the data DATA to the second front-end module 102b.

[0152] Therefore, the first front-end module 102a performs a feature extraction operation on the first data DATA1 using the first feature map and the first weight, and the second front-end module 102b performs a feature extraction operation on the second data DATA2 using the second feature map and the second weight.

[0153] Specifically, in some embodiments of the present disclosure, the amount of the first data DATA1 and the amount of the second data DATA2 may be different from each other.

[0154] Clock management unit 20 controls the frequency of at least one of first clock signal CLK1 and second clock signal CLK2, and can control the performance and power of first neural processing unit 100a and second neural processing unit 100b according to the allocation operation of workload manager 120. For example, clock management unit 20 can perform clock gating on at least one of first front-end module 102a, first back-end module 104a, second front-end module 102b, and second back-end module 104b according to the allocation operation of workload manager 120.

[0155] In this way, the neural processing system 10 according to various embodiments of the present disclosure can control the clock signals of multiple first neural processing units 100a and second neural processing units 100b therein to control performance or power consumption. For example, in order to improve the performance of the first neural processing unit 100a and reduce the power consumption of the second neural processing unit 100b, the clock management unit 20 can increase the frequency of the first clock signal CLK1 used to drive the first neural processing unit 100a and can reduce the frequency of the second clock signal CLK2 used to drive the second neural processing unit 100b. As another example, in a specific case in which only the first neural processing unit 100a is used and the second neural processing unit 100b is not used, clock gating can be performed by controlling the second clock signal CLK2 used to drive the second neural processing unit 100b. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be achieved while reducing cost and power consumption.

[0156] Figure 9 is a schematic diagram illustrating a computing system according to yet another embodiment of the present disclosure, and Figure 10 is a block diagram illustrating a neural processing system according to another embodiment of the present disclosure.

[0157] Reference Figure 9 and Figure 10 , different from Figure 7 and Figure 8 In the illustrated embodiment, computing system 3 according to this embodiment further includes a power management unit (PMU) 50. As explained herein, the use of a PMU such as PMU 50 enhances the practical ability to selectively control the power of individual neural processing units in a plurality of neural processing units in a manner that reduces power consumption, increases power consumption, reduces processing speed, or increases processing speed.

[0158] As described above, the workload manager 120 distributes the first data DATA1 for performing feature extraction among the data DATA to the first front-end module 102 a and distributes the second data DATA2 among the data DATA to the second front-end module 102 b .

[0159] Therefore, the first front-end module 102a can perform a feature extraction operation on the first data DATA1 using the first feature map and the first weight, and the second front-end module 102b can perform a feature extraction operation on the second data DATA2 using the second feature map and the second weight.

[0160] The power management unit 50 provides a first power gating signal PG1 to the first neural processing unit 100a and a second power gating signal PG2 to the second neural processing unit 100b. Specifically, the power management unit 50 may provide the first power gating signal PG1 to the first front-end module 102a and the first back-end module 104a. The power management unit 50 may provide the second power gating signal PG2 to the second front-end module 102b and the second back-end module 104b.

[0161] The power management unit 50 may control at least one value of the first power gating signal PG1 and the second power gating signal PG2 to thereby perform power control on the first neural processing unit 100a and the second neural processing unit 100b in response to the allocation operation of the workload manager 120. For example, the power management unit 50 may perform power gating on at least one of the first front-end module 102a, the first back-end module 104a, the second front-end module 102b, and the second back-end module 104b.

[0162] In this way, the neural processing system 10 according to various embodiments of the present disclosure can perform power gating on at least a portion of the first neural processing unit 100a and the second neural processing unit 100b as needed, thereby reducing the power consumption of the neural processing system 10. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be achieved while reducing cost and power consumption.

[0163] Figure 11 is a schematic diagram illustrating a computing system according to another embodiment of the present disclosure.

[0164] Reference Figure 11 According to this embodiment, the computing system 4 includes a first neural processing unit 100a, a second neural processing unit 100b, a third neural processing unit 100c, and a fourth neural processing unit 100d. For ease of explanation, in this embodiment, the neural processing system 10 is shown as including the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d, but the scope of the present disclosure is not limited thereto.

[0165] The clock management unit 20 generates a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4 for driving the neural processing system 10. The clock management unit 20 provides a clock signal to each of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d. Therefore, the first neural processing unit 100a is driven according to the first clock signal CLK1. The second neural processing unit 100b is driven according to the second clock signal CLK2. The third neural processing unit 100c is driven according to the third clock signal CLK3. The fourth neural processing unit 100d is driven according to the fourth clock signal CLK4.

[0166] In some embodiments of the present disclosure, the frequencies of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 may not all be the same. In other words, the clock domains in which the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d operate may not all be the same.

[0167] The clock management unit 20 can control the frequency of each of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 as needed. Furthermore, the clock management unit 20 can also perform clock gating on at least one of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 as needed.

[0168] Figure 12 and Figure 13 is a block diagram illustrating a neural processing system according to yet another embodiment of the present disclosure.

[0169] Reference Figure 12 According to this embodiment, the neural processing system 10 includes a first neural processing unit 100a to a fourth neural processing unit 100d. One or more bridges 1112, 1113, and 1114 are provided between the first neural processing unit 100a to the fourth neural processing unit 100d.

[0170] In this embodiment, the third neural processing unit 100c includes a third front-end module 102c and a third back-end module 104c. The fourth neural processing unit 100d includes a fourth front-end module 102d and a fourth back-end module 104d. The third neural processing unit 100c can process third data DATA3 among the data to be processed by the neural processing system 10. The fourth neural processing unit 100d can process fourth data DATA4 among the data to be processed by the neural processing system 10.

[0171] Bridge 1112 transmits the intermediate result R12 generated by the operation of first neural processing unit 100a to second neural processing unit 100b. Bridge 1113 transmits the intermediate result R13 generated by the operation of first neural processing unit 100a to third neural processing unit 100c. In addition, bridge 1114 transmits the intermediate result R14 generated by the operation of first neural processing unit 100a to fourth neural processing unit 100d.

[0172] To this end, the first neural processing unit 100a and the second neural processing unit 100b can operate in different clock domains. In this case, the bridge 1112 can be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in a clock domain different from the first neural processing unit 100a. Similarly, the bridge 1113 can be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in a clock domain different from the first neural processing unit 100a. The bridge 1114 can be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in a clock domain different from the first neural processing unit 100a.

[0173] Therefore, the bridges 1112 , 1113 , and 1114 are implemented as asynchronous bridges to enable data transfer between different clock domains.

[0174] Then, refer to Figure 13 One or more bridges 1122, 1123 and 1124 are provided between the first neural processing unit 100a and the fourth neural processing unit 100d.

[0175] Bridge 1122 transmits the intermediate result R22 generated by the operation of the second neural processing unit 100b to the first neural processing unit 100a. Bridge 1123 transmits the intermediate result R33 generated by the operation of the third neural processing unit 100c to the first neural processing unit 100a. In addition, bridge 1124 transmits the intermediate result R44 generated by the operation of the fourth neural processing unit 100d to the first neural processing unit 100a.

[0176] To this end, the first neural processing unit 100a and the second neural processing unit 100b can operate in different clock domains. In this case, the bridge 1122 can be electrically connected to the first neural processing unit 100a and the second neural processing unit 100b operating in a clock domain different from the first neural processing unit 100a. Similarly, the bridge 1123 can be electrically connected to the first neural processing unit 100a and the third neural processing unit 100c operating in a clock domain different from the first neural processing unit 100a. The bridge 1124 can be electrically connected to the first neural processing unit 100a and the fourth neural processing unit 100d operating in a clock domain different from the first neural processing unit 100a.

[0177] Therefore, the bridges 1122 , 1123 , and 1124 are implemented as asynchronous bridges to enable data transfer between different clock domains.

[0178] exist Figure 12 and Figure 13 In the illustrated embodiment, a bridge is described between the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d, which are different from the first neural processing unit 100a, but the scope of the present disclosure is not limited thereto, and the content may also be similarly applied between the third neural processing unit 100c and the fourth neural processing unit 100d, which are different from the second neural processing unit 100b, and between the third neural processing unit 100c and the fourth neural processing unit 100d.

[0179] Figure 14 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0180] Reference Figure 14 , the neural processing system 10 of the computing system 5 according to this embodiment further includes a workload manager 120. Figure 7 and Figure 8 As described above, workload manager 120 may distribute and allocate data DATA used to perform feature extraction to first neural processing unit 100a, second neural processing unit 100b, third neural processing unit 100c, and fourth neural processing unit 100d. In addition, the amount of data distributed from first neural processing unit 100a to fourth neural processing unit 100d may not be the same.

[0181] The clock management unit 20 can be connected to the reference Figure 7 and Figure 8The frequency of at least one of the first to fourth clock signals CLK1 to CLK4 is controlled in the same manner as explained to control the performance and power of the first to fourth neural processing units 100 a to 100 d in response to the allocation operation of the workload manager 120 .

[0182] In this way, the neural processing system 10 according to various embodiments of the present disclosure can control the clock signals of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d, thereby controlling performance or power consumption. For example, in order to improve the performance of the first neural processing unit 100a, the second neural processing unit 100b, and the third neural processing unit 100c and reduce the power consumption of the fourth neural processing unit 100d, the clock management unit 20 can increase the frequency of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 used to drive the first neural processing unit 100a to the third neural processing unit 100c and can reduce the frequency of the fourth clock signal CLK4 used to drive the fourth neural processing unit 100d. As another example, when only the first and second neural processing units 100a, 100b are used and the third and fourth neural processing units 100c, 100d are not used, clock gating can be performed by controlling the third clock signal CLK3 and the fourth clock signal CLK4 used to drive the third and fourth neural processing units 100c, 100d. Therefore, according to a computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be achieved while reducing cost and power consumption.

[0183] Figure 15 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0184] Reference Figure 15 , different from Figure 14 In the illustrated embodiment, the neural processing system 10 of the computing system 6 according to this embodiment further includes a power management unit 50 (PMU).

[0185] As described above, the workload manager 120 allocates and distributes the data DATA for performing feature extraction to the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d.

[0186] The power management unit 50 provides a first power gating signal PG1, a second power gating signal PG2, a third power gating signal PG3 and a fourth power gating signal PG4 to the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c and the fourth neural processing unit 100d.

[0187] The power management unit 50 can be used with reference to Figure 9 and Figure 10 At least one value of the first power gating signal PG1, the second power gating signal PG2, the third power gating signal PG3 and the fourth power gating signal PG4 is controlled in the same manner, thereby performing power control of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c and the fourth neural processing unit 100d in response to the allocation operation of the workload manager 120.

[0188] In this way, the neural processing system 10 according to various embodiments of the present disclosure can reduce the power consumption of the neural processing system 10 by performing power gating on one or more of the first neural processing unit 100a, the second neural processing unit 100b, the third neural processing unit 100c, and the fourth neural processing unit 100d as needed. Therefore, according to the computing system including the neural processing system 10 according to various embodiments of the present disclosure, artificial intelligence can be implemented while reducing cost and power consumption.

[0189] Figure 16 is a block diagram illustrating a computing system according to yet another embodiment of the present disclosure.

[0190] Reference Figure 16 The computing system 7 according to this embodiment may be a computing system including a neural processing system 10, a clock management unit 20, a processor 30, a memory 40, a power management unit 50, a storage 60, a display 70, and a camera 80. The neural processing system 10, the clock management unit 20, the processor 30, the memory 40, the power management unit 50, the storage 60, the display 70, and the camera 80 may transmit and receive data via a bus 90.

[0191] In some embodiments of the present invention, the computing system 7 may be a mobile computing system. For example, the computing system 7 may be a computing system including a smart phone, a tablet computer, a laptop computer, etc. Of course, the scope of the present disclosure is not limited thereto.

[0192] The neural processing system 10 according to various embodiments of the present disclosure as explained so far is capable of performing a feature extraction operation on image data generated by the camera 80 or image data stored in the storage 60 using a CNN with low cost and low power.

[0193] As described above, the neural processing system 10 adopts an architecture including a plurality of neural processing units capable of individual clock and power control, thereby faithfully implementing and executing artificial intelligence while reducing cost and power consumption.

[0194] By summarizing the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the preferred embodiment without actually departing from the principles of the present disclosure. Therefore, the preferred embodiments disclosed by the present invention are only for general and illustrative purposes and not for limiting purposes.

Claims

1. A neural network processing system comprising: A first front-end module performs a feature extraction operation using the first feature map and the first weight, and outputs a first operation result and a second operation result; A second front-end module performs the feature extraction operation using the second feature map and the second weight, and outputs a third operation result and a fourth operation result; a first back-end module receiving the first operation result provided by the first front-end module and the fourth operation result provided by the second front-end module via the second bridge, and calculating a sum of the first operation result and the fourth operation result; as well as a second back-end module receiving the third operation result provided by the second front-end module and the second operation result provided by the first front-end module via the first bridge, so as to sum the third operation result and the second operation result, wherein the first front-end module and the first back-end module are driven according to the first clock signal, and The second front-end module and the second back-end module are driven by a second clock signal having a frequency different from that of the first clock signal.

2. The neural network processing system according to claim 1, wherein the first bridge and the second bridge are asynchronous bridges.

3. The neural network processing system according to claim 1 , wherein the first back-end module provides first write-back data to the first front-end module, and The second back-end module provides second write-back data to the second front-end module.

4. The neural network processing system according to claim 1 , wherein the first front-end module comprises: a plurality of first internal memories for storing the first feature maps and the first weights, A plurality of first extraction units extracting the first feature map and the first weight from each of the plurality of first internal memories, a plurality of first dispatching units transmitting the extracted first feature maps and the first weights to a first multiplication and accumulation array for each channel, and The first multiplication and accumulation array performs a multiplication and accumulation operation on data transmitted from the plurality of first dispatch units.

5. The neural network processing system of claim 4 , wherein the first multiply and accumulate array outputs the first operation result and the second operation result, The first operation result is provided to the first backend module, and The second operation result is provided to the second backend module through the first bridge.

6. The neural network processing system of claim 1 , wherein the second front-end module comprises: a plurality of second internal memories for storing the second feature maps and the second weights, a plurality of second extraction units, extracting the second feature map and the second weight from each of the plurality of second internal memories, a plurality of second dispatching units transmitting the extracted second feature maps and the second weights to a second multiplication and accumulation array for each channel, and The second multiplication and accumulation array performs a multiplication and accumulation operation on the data transmitted from the plurality of second dispatch units.

7. The neural network processing system according to claim 1, further comprising: A workload manager allocates first data from among data for performing feature extraction to the first front-end module and allocates second data from among the data to the second front-end module, the data including an input image. The first front-end module performs the feature extraction operation on the first data using the first feature map and the first weight, and The second front-end module performs the feature extraction operation on the second data using the second feature map and the second weight.

8. The neural network processing system according to claim 7, wherein an amount of the first data and an amount of the second data are different from each other.

9. The neural network processing system according to claim 7, further comprising: a clock management unit, providing a first clock signal to the first front-end module and the first back-end module, and providing a second clock signal to the second front-end module and the second back-end module, The clock management unit controls the frequency of at least one of the first clock signal and the second clock signal to perform clock gating on at least one of the first front-end module, the first back-end module, the second front-end module and the second back-end module according to the allocation operation of the workload manager.

10. The neural network processing system according to claim 7, further comprising: a power management unit, providing a first power gating signal to the first front-end module and the first back-end module, and providing a second power gating signal to the second front-end module and the second back-end module, The power management unit controls at least one value of the first power gating signal and the second power gating signal to perform power gating on at least one of the first front-end module, the first back-end module, the second front-end module, and the second back-end module according to the allocation operation of the workload manager.

11. A neural network processing system comprising: A first neural processing unit, comprising a first front-end module and a first back-end module; as well as a bridge unit electrically connected to the first neural processing unit, and a second neural processing unit operating in a different clock domain than the first neural processing unit, The first front-end module provides a portion of a first operation result obtained by performing a feature extraction operation using the first feature map and the first weight to the first back-end module, The bridge unit provides a portion of the second operation result executed in the second neural processing unit to the first backend module, and The first backend module sums the portion of the first operation result and the portion of the second operation result.

12. The neural network processing system of claim 11 , wherein the bridge is electrically connected to a third neural processing unit, the third neural processing unit operating in a different clock domain than the first neural processing unit, The first front-end module provides another part of the first operation result to the bridge unit, and The bridge unit provides the other part of the first operation result to the third neural processing unit.

13. The neural network processing system of claim 11 , wherein the first front-end module comprises: a plurality of first internal memories for storing the first feature maps and the first weights, A plurality of first extraction units extracting the first feature map and the first weight from each of the plurality of first internal memories, a plurality of first dispatching units transmitting the extracted first feature maps and the first weights to a first multiplication and accumulation array for each channel, and The first multiplication and accumulation array performs a multiplication and accumulation operation on the data transmitted from the plurality of first dispatch units and outputs the first operation result.

14. A neural network processing system comprising: A first neural processing unit, comprising a first front-end module and a first back-end module; A second neural processing unit, comprising a second front-end module and a second back-end module; as well as a workload manager that allocates first data from among the data for performing feature extraction to the first neural processing unit and allocates second data from among the data to the second neural processing unit, The first front-end module performs a feature extraction operation on the first data using the first feature map and the first weight, and outputs a first operation result and a second operation result. The second front-end module performs the feature extraction operation on the second data using the second feature map and the second weight, and outputs a third operation result and a fourth operation result, and The first back-end module calculates the sum of the first operation result and the fourth operation result, and the second back-end module calculates the sum of the third operation result and the second operation result, wherein the first neural processing unit is driven according to a first clock signal, and The second neural processing unit is driven according to a second clock signal having a frequency different from that of the first clock signal.

15. The neural network processing system according to claim 14, further comprising: a clock management unit, providing the first clock signal to the first front-end module and the first back-end module, and providing the second clock signal to the second front-end module and the second back-end module, The clock management unit controls the frequency of at least one of the first clock signal and the second clock signal to perform clock gating on at least one of the first front-end module, the first back-end module, the second front-end module and the second back-end module according to the allocation operation of the workload manager.

16. The neural network processing system according to claim 14, further comprising: a power management unit, providing a first power gating signal to the first front-end module and the first back-end module, and providing a second power gating signal to the second front-end module and the second back-end module, The power management unit controls at least one value of the first power gating signal and the second power gating signal to perform power gating on at least one of the first front-end module, the first back-end module, the second front-end module, and the second back-end module according to the allocation operation of the workload manager.

17. The neural network processing system of claim 14, wherein the first front-end module comprises: a plurality of first internal memories for storing the first feature maps and the first weights, A plurality of first extraction units extracting the first feature map and the first weight from each of the plurality of first internal memories, a plurality of first dispatching units transmitting the extracted first feature maps and the first weights to a first multiplication and accumulation array for each channel, and The first multiplication and accumulation array performs a multiplication and accumulation operation on data transmitted from the plurality of first dispatch units.

18. The neural network processing system of claim 14, wherein the second front-end module comprises: a plurality of second internal memories for storing the second feature maps and the second weights, a plurality of second extraction units, extracting the second feature map and the second weight from each of the plurality of second internal memories, a plurality of second dispatching units transmitting the extracted second feature maps and the second weights to a second multiplication and accumulation array for each channel, and The second multiplication and accumulation array performs a multiplication and accumulation operation on the data transmitted from the plurality of second dispatch units.

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