Semiconductor device package

Abstract

A semiconductor device package includes a carrier and a encapsulant disposed on the carrier. At least a portion of the encapsulant is spaced apart from the carrier by a space.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 728,720, filed September 7, 2018, the contents of which are incorporated by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to, among other things, semiconductor device packages and semiconductor device packages having regions or spaces free of encapsulation material. BACKGROUND

[0004] The molding process is a packaging technique used for semiconductor packages for protecting the substrate and components on the substrate. However, in some embodiments, not the entire area of the substrate should be covered by the encapsulation material (also referred to as molding compound), for example, in an antenna on package (AoP) embodiment, where impedance matching of the path from the components to the antenna can need to be performed. Thus, the semiconductor device package can have a non-molded region or space (a region or space free of encapsulation material), and the user can easily adjust the impedance matching by adjusting the surface mount technology (SMT) passive components after the molding process. SUMMARY

[0005] According to one example embodiment of the present disclosure, a semiconductor device package includes a carrier and an encapsulant disposed on the carrier. In addition, at least a portion of the encapsulant is spaced apart from the carrier by a space.

[0006] According to another example embodiment of the present disclosure, a semiconductor device package includes a carrier including a first surface and a second surface adjacent to the first surface, and an encapsulant disposed on the first surface of the carrier. In addition, a roughness of the second surface of the carrier is greater than a roughness of the first surface of the carrier.

[0007] According to another example embodiment of the present disclosure, a method of manufacturing a semiconductor device package includes a) providing a carrier having a surface; b) forming a sacrificial layer on the surface of the carrier; c) encapsulating the carrier and the sacrificial layer by an encapsulant; d) removing a portion of the encapsulant to expose a portion of the sacrificial layer such that the encapsulant is divided into a first portion and a second portion, wherein the first portion of the encapsulant is attached to the carrier and the second portion of the encapsulant is attached to the sacrificial layer; and e) removing the sacrificial layer and the second portion of the encapsulant.

[0008] For a further understanding of the present disclosure, the following examples and illustrations are provided to facilitate an understanding of the present disclosure; however, the accompanying drawings are provided solely for purposes of reference and illustration and do not limit the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a cross-sectional view of a semiconductor device package according to an embodiment of the present application.

[0010] Figure 2A , Figure 2B , Figure 2C and Figure 2D show a method of manufacturing a semiconductor device package according to an embodiment of the present application.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0015] Figure 7A , Figure 7B , Figure 7C , Figure 7D and Figure 7E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0016] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0017] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E show a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0018] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D and Figure 10E shows a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0019] Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D and Figure 11E shows a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0020] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E and Figure 12F shows a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0021] Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 13E and Figure 13F shows a method of manufacturing a semiconductor device package according to another embodiment of the present application.

[0022] Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E shows a method of manufacturing a semiconductor device package according to another embodiment of the present application. DETAILED DESCRIPTION

[0023] The foregoing description and the following detailed description are examples for the purpose of illustrating the application.

[0024] Figure 1 A semiconductor device package 1 according to an embodiment of the present application is shown. In particular, the semiconductor device package 1 has two asymmetric non-molded regions 13 and 15. As used herein, the term "non-molded region" can refer to a region (e.g., of a substrate) or space that is substantially free of mold material. Referring to Figure 1 The semiconductor device package 1 includes a carrier 10. The carrier 10 has an upper surface 11 and a lower surface 12 opposite the upper surface 11. An encapsulation material 20 is disposed on the upper surface 11 of the carrier 10. A die 101 and components 102, 103 (e.g., electronic components, e.g., passive electronic components) are disposed on the upper surface 11 of the carrier 10 and are covered by the encapsulation material 20. As used herein, the term "component" can refer to a passive electronic component, an active electronic component, or a combination thereof. Figure 1As shown in FIG. 1, one or more regions of the upper surface 11 of the carrier 10 are exposed from the encapsulation material 20 (e.g., substantially free of the encapsulation material 20). The upper surface 11 of the carrier 10 has a non-molded region 13. In the non-molded region 13, substantially no encapsulation material 20 is disposed on the upper surface 11 of the carrier 10, and the dies 104 and the components 105 disposed on the upper surface 11 of the carrier 10 are not covered by the encapsulation material 20 and thus are exposed. In addition, the encapsulation material 21 is disposed on the lower surface 12 of the carrier 10. The dies 106 and the electrical contacts 107 are disposed on the lower surface 12 of the carrier 10 and are covered by the encapsulation material 21. In addition, the substrate 19 is disposed on the encapsulation material 21. In addition, one or more regions of the lower surface 12 of the carrier 10 are exposed from the encapsulation material 21 (e.g., substantially free of the encapsulation material 21). The lower surface 12 of the carrier 10 has a non-molded region 15. In the non-molded region 15, substantially no encapsulation material 21 is disposed on the lower surface 12 of the carrier 10, and the components 108 and 109 disposed on the lower surface 12 of the carrier 10 are not covered by the encapsulation material 21 and thus are exposed.

[0025] Furthermore, with reference to Figure 1 , the non-molded regions 13 and 15 are different from each other and their locations do not correspond to each other (e.g., are not disposed relative to each other). The non-molded region 13 on the upper surface 11 of the carrier 10 and the non-molded region 15 on the lower surface 12 of the carrier 10 are not symmetrical to each other.

[0026] Figure 2A , Figure 2B , Figure 2C and Figure 2D shows a method of manufacturing a semiconductor device package 110 according to an embodiment of the present application. As shown in Figure 2A , at least one electronic component 112 is disposed on the upper surface 1111 of the carrier 111. In addition, in some embodiments, a glue is dispensed on the upper surface 1111 of the carrier 111 so as to form a removable / sacrificial layer 1117 on the upper surface 1111 of the carrier 111. In some embodiments, the removable / sacrificial layer 1117 can include a tape adhered or pasted on the upper surface 1111 of the carrier 111 or another removable binding material coated or printed on the upper surface 1111 of the carrier 111.

[0027] With reference to Figure 2B , an encapsulation material 113 is disposed on the carrier 111 and encapsulates the at least one electronic component 112 and the removable / sacrificial layer 1117. The encapsulation material 113 covers the at least one electronic component 112, the upper surface 111 of the carrier 11, and the removable / sacrificial layer 1117.

[0028] With reference to Figure 2CA portion of the encapsulation material 113 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1117. As a result, the encapsulation material 113 is divided into two portions 1130 and 1139, where a portion of the encapsulation material 1130 is attached to the upper surface 1111 of the carrier 111 and the removable / sacrificial layer 1117, and a portion of the encapsulation material 1139 is attached to the removable / sacrificial layer 1117.

[0029] Referring to Figure 2D The removable / sacrificial layer 1117 is removed by a physical or chemical method, for example, a water rinsing process. In addition, the portion of the encapsulation material 1139 attached to the removable / sacrificial layer 1117 is also removed (e.g., when the removable / sacrificial layer 1117 is removed). After the removable / sacrificial layer 1117 and the portion of the encapsulation material 1139 are removed, the portion of the encapsulation material 1130 remains on the carrier 111 and a portion of the upper surface 1111 of the carrier 111 is exposed. The portion of the encapsulation material 1130 is disposed on the upper surface 1111 of the carrier. The portion of the encapsulation material 1130 has an upper surface 1131 and a lower surface 1132 opposite the upper surface 1131 and attached to the upper surface 1111 of the carrier 111. In addition, the portion of the encapsulation material 1130 further has a surface 1133 at a height between the upper surface 1131 and the lower surface 1132, where the surface 1133 is spaced apart from the upper surface 1111 of the carrier 111. There is a space between the surface 1133 and the upper surface 1111. The surface 1133 can be substantially parallel to either or each of the upper surface 1131 and the lower surface 1132.

[0030] Further, the portion of the encapsulation material 1130 has a side surface 1136. The side surface 1136 can connect the surface 1133 and the upper surface 1131. An angle A between the side surface 1136 and the upper surface 1131 is in a range from about 90 degrees to about 110 degrees.

[0031] Figure 3A Figure 3B Figure 3C Figure 3D Figure 3E A method of manufacturing a semiconductor device package 120 according to another embodiment of the present application is shown. As shown in Figure 3A The carrier 121 has an upper surface 1211 and a recess 1210 formed in the upper surface 1211. The carrier 121 has a recessed surface 1212 (e.g., which defines a bottom of the recess 1210) recessed with respect to the upper surface 1211. At least one electronic component 122 is disposed on the upper surface 1211 of the carrier 121.

[0032] In addition, referring to Figure 3B ​​​​The adhesive is dispensed on the upper surface 1211 of the carrier 121, where a portion of the adhesive flows into the recess 1210. Thus, the removable / sacrificial layer 1217 is formed on the upper surface 1211 and the recessed surface 1212 of the carrier 121.

[0033] Referring to Figure 3C The encapsulation material 123 is disposed on the carrier 121 and encapsulates the at least one electronic component 122 and the removable / sacrificial layer 1217. The encapsulation material 123 covers the at least one electronic component 122, the upper surface 1211 of the carrier 121, and the removable / sacrificial layer 1217.

[0034] Referring to Figure 3D A portion of the encapsulation material 123 is removed by a laser process and thus a portion of the removable / sacrificial layer 1217 is exposed. As a result, the encapsulation material 123 is divided into two portions 1230 and 1239, where a portion of the encapsulation material 1230 is attached to the upper surface 1211 of the carrier 121 and the removable / sacrificial layer 1217, and a portion of the encapsulation material 1239 is attached to the removable / sacrificial layer 1217.

[0035] Referring to Figure 3E The removable / sacrificial layer 1217 is removed by a physical or chemical method, for example, a water washing process. The portion of the encapsulation material 1239 attached to the removable / sacrificial layer 1217 is removed (e.g., when the removable / sacrificial layer 1217 is removed). After the removable / sacrificial layer 1217 and the portion of the encapsulation material 1239 are removed, the portion of the encapsulation material 1230 remains on the carrier 121 and a portion of the upper surface 1211 and the recessed surface 1212 of the carrier 121 are exposed. The portion of the encapsulation material 1230 is disposed on the upper surface 1211 of the carrier 121. The portion of the encapsulation material 1230 has an upper surface 1231 and a lower surface 1232 opposite the upper surface 1231. In addition, a portion of the lower surface 1232 is spaced apart from (e.g., spaced apart from and disposed on) the recessed surface 1212 of the carrier 121 and a portion of the lower surface 1232 is attached to the upper surface 1211 of the carrier 121. There is a space between the lower surface 1232 and the recessed surface 1212.

[0036] In addition, the portion of the encapsulation material 1230 has a side surface 1236. An angle B between the side surface 1236 and the upper surface 1231 is in a range from about 90 degrees to about 110 degrees.

[0037] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4EA method of manufacturing a semiconductor device package 130 according to another embodiment of the present application is shown. As shown in Figure 4A the carrier 131 has an upper surface 1311 and a recess 1310 formed in the upper surface 1311. The carrier 131 further has a recessed surface 1312 (e.g., which defines a bottom of the recess 1310) recessed with respect to the upper surface 1311. The at least one electronic component 132 is disposed on the upper surface 1311 of the carrier 131.

[0038] Additionally, referring to Figure 4B , an adhesive is dispensed on the upper surface 1311 of the carrier 131, where a portion of the adhesive flows into the recess 1310. Thus, a removable / sacrificial layer 1317 is formed on the upper surface 1311 and the recessed surface 1312 of the carrier 131. The removable / sacrificial layer 1317 has an upper surface 1318 that is higher than the upper surface 1311 of the carrier 131. Further, the removable / sacrificial layer 1317 has a side surface 1319 that is substantially coplanar with the side surface 1315 of the recess 1310.

[0039] Referring to Figure 4C , an encapsulation material 133 is disposed on the carrier 131 and encapsulates the at least one electronic component 132 and the removable / sacrificial layer 1317. The encapsulation material 133 covers the at least one electronic component 132, the upper surface 1311 of the carrier 131, and the removable / sacrificial layer 1317.

[0040] Referring to Figure 4D , a portion of the encapsulation material 133 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1317. As a result, the encapsulation material 133 is divided into two portions 1330 and 1339, where a portion of the encapsulation material 1330 is attached to the upper surface 1311 of the carrier 131 and the removable / sacrificial layer 1317, and a portion of the encapsulation material 1339 is attached to the removable / sacrificial layer 1317.

[0041] Referring to Figure 4EThe removable / sacrificial layer 1317 is removed by a physical or chemical method, for example, a water rinsing process. In addition, a portion of the encapsulation material 1339 attached to the removable / sacrificial layer 1317 is removed (e.g., when the removable / sacrificial layer 1317 is removed). After the removable / sacrificial layer 1317 and the portion of the encapsulation material 1339 are removed, a portion of the encapsulation material 1330 remains on the carrier 131 and a portion of the upper surface 1311 and the recessed surface 1312 of the carrier 131 are exposed. The portion of the encapsulation material 1330 is disposed on the upper surface 1311 of the carrier 131. The portion of the encapsulation material 1330 has an upper surface 1331 and a lower surface 1332 opposite the upper surface 1331. In addition, the portion of the encapsulation material 1330 further has a surface 1333 at a height between the heights of the upper surface 1331 and the lower surface 1332, where the surface 1333 is spaced apart from and disposed on the recessed surface 1312 of the carrier 131. There is a space between the surface 1333 and the recessed surface 1312. Moreover, the portion of the encapsulation material 1330 has a side surface 1335 connected to the lower surface 1332 and the surface 1333. The side surface 1335 is substantially coplanar with the side surface 1313 of the recess 1310.

[0042] Furthermore, the portion of the encapsulation material 1330 has a side surface 1336. An angle C between the side surface 1336 and the upper surface 1331 is in a range from about 90 degrees to about 110 degrees.

[0043] Figure 5A Figure 5B Figure 5C Figure 5D Figure 5E A method of manufacturing a semiconductor device package 140 according to another embodiment of the present application is shown. As shown in Figure 5A The carrier 141 has an upper surface 1411 and a recess 1410 formed in the upper surface 1411. The carrier 141 further has a recessed surface 1412 (e.g., which defines a bottom of the recess 1410) recessed with respect to the upper surface 1411. At least one electronic component 142 is disposed on the upper surface 1411 of the carrier 141.

[0044] In addition, referring to Figure 5B , adhesive is dispensed on the upper surface 1411 of the carrier 141, where a portion of the adhesive flows into the recess 1410. As a result, a removable / sacrificial layer 1417 is formed on the upper surface 1411 and the recessed surface 1412 of the carrier 141. The removable / sacrificial layer 1417 has an upper surface 1418 higher than the upper surface 1411 of the carrier 141. Moreover, because the adhesive overflows the recess 1410, the removable / sacrificial layer 1417 extends across the recess 1410 and has a side surface 1419 on the upper surface 1411 of the carrier 141.​​​​

[0045] Referring to Figure 5C The encapsulation material 143 is disposed on the carrier 141 and encapsulates the at least one electronic component 142 and the removable / sacrificial layer 1417. The encapsulation material 143 covers the at least one electronic component 142, the upper surface 1411 of the carrier 141, and the removable / sacrificial layer 1417.

[0046] Referring to Figure 5D A portion of the encapsulation material 143 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1417. As such, the encapsulation material 143 is divided into two portions 1430 and 1439, where a portion of the encapsulation material 1430 is attached to the upper surface 1411 of the carrier 141 and the removable / sacrificial layer 1417, and a portion of the encapsulation material 1439 is attached to the removable / sacrificial layer 1417.

[0047] Referring to Figure 5E The removable / sacrificial layer 1417 is removed by a physical or chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 1439 attached to the removable / sacrificial layer 1417 is removed (e.g., when the removable / sacrificial layer 1417 is removed). After the removable / sacrificial layer 1417 and the portion of the encapsulation material 1439 are removed, the portion of the encapsulation material 1430 remains on the carrier 141 and a portion of the upper surface 1411 and the recessed surface 1412 of the carrier 141 are exposed. The portion of the encapsulation material 1430 is disposed on the upper surface 1411 of the carrier 141. The portion of the encapsulation material 1430 has an upper surface 1431 and a lower surface 1432 opposite the upper surface 1431. In addition, the portion of the encapsulation material 1430 further has a surface 1433 at a height between the upper surface 1431 and the lower surface 1432, where the surface 1433 is spaced apart from the upper surface 1411 and the recessed surface 1412 of the carrier 141. There is a space between the surface 1433 and the upper surface 1411, the recessed surface 1412. In addition, the portion of the encapsulation material 1430 further has a side surface 1434 connected to the lower surface 1432 and the surface 1433. The side surface 1434 is disposed on the upper surface 1411 of the carrier 141 and is not coplanar with the side surface 1415 of the recess 1410. The side surface of the recess 1410 can be disposed below the surface 1433.

[0048] In addition, the portion of the encapsulation material 1430 has a side surface 1436. An angle D between the side surface 1436 and the upper surface 1431 is in a range from about 90 degrees to about 110 degrees.

[0049] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D andFigure 6E A method of manufacturing a semiconductor device package 150 according to another embodiment of the present application is shown. As shown in Figure 6A , a carrier 151 has an upper surface 1511 and a recess 1510 formed in the upper surface 1511. The carrier 151 further has a recessed surface 1512 (e.g., which defines a bottom of the recess 1510) recessed with respect to the upper surface 1511. At least one electronic component 152 is disposed on the upper surface 1511 of the carrier 151.

[0050] Additionally, referring to Figure 6B , a glue is dispensed on the upper surface 1511 of the carrier 151, where a portion of the glue flows into the recess 1510. Thus, a removable / sacrificial layer 1517 is formed on the upper surface 1511 and the recessed surface 1512 of the carrier 151. The removable / sacrificial layer 1517 has an upper surface 1518 that is higher than the upper surface 1511 of the carrier 151. Moreover, because the glue overflowed the recess 1510, the removable / sacrificial layer 157 has an overhang portion 1515 that extends from the upper surface 1518 of the removable / sacrificial layer 1517. The overhang portion 1515 has a side surface 1516 that is substantially coplanar with a side surface 1519 of the recess 1510.

[0051] Referring to Figure 6C , an encapsulation material 153 is disposed on the carrier 151 and encapsulates the at least one electronic component 152 and the removable / sacrificial layer 1517. The encapsulation material 153 covers the at least one electronic component 152, the upper surface 1511 of the carrier 151, and the removable / sacrificial layer 1517.

[0052] Referring to Figure 6D , a portion of the encapsulation material 153 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1517. As a result, the encapsulation material 153 is divided into two portions 1530 and 1539, where a portion of the encapsulation material 1530 is attached to the upper surface 1511 of the carrier 151 and the removable / sacrificial layer 1517, and a portion of the encapsulation material 1539 is attached to the removable / sacrificial layer 1517.

[0053] Referring to Figure 6EThe removable / sacrificial layer 1517 is removed by a physical or chemical method, for example, a water rinsing process. In addition, portions of the encapsulation material 1539 attached to the removable / sacrificial layer 1517 are removed (e.g., when the removable / sacrificial layer 1517 is removed). After the removable / sacrificial layer 1517 and the portions of the encapsulation material 1539 are removed, portions of the encapsulation material 1530 remain on the carrier 151 and a portion of the upper surface 1511 and the recessed surface 1512 of the carrier 151 are exposed. The portions of the encapsulation material 1530 are disposed on the upper surface 1511 of the carrier 151. The portions of the encapsulation material 1530 have an upper surface 1531 and a lower surface 1532 opposite the upper surface 1131. The portions of the encapsulation material 1530 further have a surface 1533 at a height between the heights of the upper surface 1531 and the lower surface 1532, where the surface 1533 is spaced apart from the upper surface 1511 and the recessed surface 1512 of the carrier 151. The surface 1533 is disposed on the recessed surface 1512 of the carrier 151. In addition, the portions of the encapsulation material 1530 further have a surface 1534 adjacent to and lower than the surface 1533. The surface 1534 is spaced apart from (and, for example, disposed on) the recessed surface 1512 of the carrier 151. The surface 1534 can be substantially parallel to the surface 1533. There is a space between the surfaces 1533, 1534 and the recessed surface 1512. In addition, the portions of the encapsulation material 1530 further have a side surface 1535 connected to the lower surface 1532 and the surface 1533. The side surface 1535 is substantially coplanar with the side surface 1519 of the recess 1510.

[0054] In addition, the portions of the encapsulation material 1530 have a side surface 1536. An angle E between the side surface 1536 and the upper surface 1531 is in a range from about 90 degrees to about 110 degrees.

[0055] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D and Figure 7E A method of manufacturing a semiconductor device package 160 according to another embodiment of the present application is shown. As shown in Figure 7A The carrier 161 has an upper surface 1611 and a recess 1610 formed in the upper surface 1611. The carrier 161 further has a recessed surface 1612 (e.g., which defines a bottom of the recess 1610) recessed with respect to the upper surface 1611. At least one electronic component 162 is disposed on the upper surface 1611 of the carrier 161.

[0056] In addition, reference is made to Figure 7B, the glue is distributed on the upper surface 1611 of the carrier 161, where a portion of the glue flows into the recess 1610. Thus, the removable / sacrificial layer 1617 is formed on the upper surface 1611 and the recessed surface 1612 of the carrier 161. The removable / sacrificial layer 1617 has an upper surface 1618 higher than the upper surface 1611 of the carrier 161. Further, because the glue overflows the recess 1610, the removable / sacrificial layer 1617 has an overhanging portion 1615 that overhangs from the upper surface 1618 of the removable / sacrificial layer 1617 and extends to the upper surface 1611 of the carrier 161. The overhanging portion 1615 has a side surface 1616 that is disposed on the upper surface 1611 of the carrier 161.

[0057] Referring to Figure 7C , the encapsulation material 163 is disposed on the carrier 161 and encapsulates the at least one electronic component 162 and the removable / sacrificial layer 1617. The encapsulation material 163 covers the at least one electronic component 162, the upper surface 1611 of the carrier 161, and the removable / sacrificial layer 1617.

[0058] Referring to Figure 7D , a portion of the encapsulation material 163 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1617. As a result, the encapsulation material 163 is divided into two portions 1630 and 1639, where the portion of the encapsulation material 1630 is attached to the upper surface 1611 of the carrier 161 and the removable / sacrificial layer 1617, and the portion of the encapsulation material 1639 is attached to the removable / sacrificial layer 1617.

[0059] Referring to Figure 7EThe removable / sacrificial layer 1617 is removed by a physical or chemical method, for example, a water rinsing process. In addition, portions of the encapsulation material 1639 attached to the removable / sacrificial layer 1617 are removed (e.g., when the removable / sacrificial layer 1617 is removed). After the removable / sacrificial layer 1617 and the portions of the encapsulation material 1639 are removed, portions of the encapsulation material 1630 remain on the carrier 161 and a portion of the upper surface 1611 and the recessed surface 1612 of the carrier 161 are exposed. The portions of the encapsulation material 1630 are disposed on the upper surface 1611 of the carrier 161. The portions of the encapsulation material 1630 have an upper surface 1631 and a lower surface 1632 opposite the upper surface 1631. The portions of the encapsulation material 1630 further have a surface 1633 at a height between the heights of the upper surface 1631 and the lower surface 1632, where the surface 1633 is spaced apart from the upper surface 1611 and the recessed surface 1612 of the carrier 161. At least a portion of the surface 1633 is disposed on the recessed surface 1612 of the carrier 161. In addition, the portions of the encapsulation material 1630 further have a surface 1634 adjacent to and lower than the surface 1633. The surface 1634 is spaced apart from the recessed surface 1612 of the carrier 161. The surface 1634 can be substantially parallel to the surface 1633. There is a space between the surfaces 1633, 1634 and the upper surface 1611 and the recessed surface 1612. In addition, the portions of the encapsulation material 1630 further have a side surface 1635 connected to the lower surface 1632 and the surface 1633. The side surface 1635 is disposed on the upper surface 1611 of the carrier 161 and is not coplanar with the side surface 1615 of the recess 1610.

[0060] In addition, the portions of the encapsulation material 1630 have a side surface 1636. An angle F between the side surface 1636 and the upper surface 1631 is in a range from about 90 degrees to about 110 degrees.

[0061] Figure 8A Figure 8B Figure 8C Figure 8D Figure 8E A method of manufacturing a semiconductor device package 170 according to another embodiment of the present application is shown. As shown in Figure 8A The carrier 171 has an upper surface 1711 and a protruding portion 1710 formed on the upper surface 1711. The carrier 171 further has a protruding surface 1712 protruding with respect to the upper surface 1711. At least one electronic component 172 is disposed on the upper surface 1711 of the carrier 171.

[0062] In addition, reference is made to Figure 8B ​​​​glue is not allowed to flow over the overhanging portion 1710. Thus, a removable / sacrificial layer 1717 is formed on the upper surface 1711. Further, the removable / sacrificial layer 1717 has an upper surface 1718 that is substantially coplanar with the overhanging surface 1712.

[0063] Referring to Figure 8C The encapsulation material 173 is disposed on the carrier 171 and encapsulates the at least one electronic component 172 and the removable / sacrificial layer 1717. The encapsulation material 173 covers the at least one electronic component 172, the upper surface 1711 and the overhanging surface 1712 of the carrier 171, and the removable / sacrificial layer 1717.

[0064] Referring to Figure 8D A portion of the encapsulation material 173 is removed by a laser process and thus a portion of the removable / sacrificial layer 1717 is exposed. As a result, the encapsulation material 173 is divided into two portions 1730 and 1739, wherein the portion of the encapsulation material 1730 is attached to the upper surface 1711 and the overhanging surface 1712 of the carrier 171 and the removable / sacrificial layer 1717, and the portion of the encapsulation material 1739 is attached to the removable / sacrificial layer 1717.

[0065] Referring to Figure 8E The removable / sacrificial layer 1717 is removed by a physical or chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 1739 attached to the removable / sacrificial layer 1717 is removed (e.g., when the removable / sacrificial layer 1717 is removed). After the removable / sacrificial layer 1717 and the portion of the encapsulation material 1739 are removed, the portion of the encapsulation material 1730 remains on the carrier 171 and a portion of the upper surface 1711 of the carrier 171 is exposed. The portion of the encapsulation material 1730 is disposed on the upper surface 1711 of the carrier 171. The portion of the encapsulation material 1730 has an upper surface 1731 and a lower surface 1732 opposite the upper surface 1731. In addition, the portion of the encapsulation material 1730 further has a surface 1733 at a height between the height of the upper surface 1731 and the lower surface 1732, wherein a portion of the surface 1733 is attached to the overhanging surface 1712 of the carrier 171 and a portion of the surface 1733 is spaced apart from the upper surface 1711 of the carrier 171. There is a space between the surface 1733 and the upper surface 1711.

[0066] Further, the portion of the encapsulation material 1730 has a side surface 1736. An angle G between the side surface 1736 and the upper surface 1731 is in a range from about 90 degrees to about 110 degrees.

[0067] Figure 9A , Figure 9B , Figure 9C ,Figure 9D and Figure 9E A method of manufacturing a semiconductor device package 180 according to another embodiment of the present application is shown. As shown in Figure 9A , a carrier 181 has an upper surface 1811 and an overhang 1810 formed on the upper surface 1811. The carrier 181 further has an overhang surface 1812 that overhangs relative to the upper surface 1811. At least one electronic component 182 is disposed on the upper surface 1811 of the carrier 181.

[0068] Further, referring to Figure 9B , an adhesive is dispensed on the upper surface 1811 of the carrier 181, wherein the adhesive does not flow over the overhang 1810. Thus, a removable / sacrificial layer 1817 is formed on the upper surface 1811. In addition, the removable / sacrificial layer 1817 has an upper surface 1818 that is lower than the overhang surface 1812.

[0069] Referring to Figure 9C , an encapsulation material 183 is disposed on the carrier 181 and encapsulates the at least one electronic component 182 and the removable / sacrificial layer 1817. The encapsulation material 183 covers the at least one electronic component 182, the upper surface 1811 and the overhang surface 1812 of the carrier 181, and the removable / sacrificial layer 1817.

[0070] Referring to Figure 9D , a portion of the encapsulation material 183 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1817. As a result, the encapsulation material 183 is divided into two portions 1830 and 1839, wherein a portion of the encapsulation material 1830 is attached to the upper surface 1811 and the overhang surface 1812 of the carrier 181 and the removable / sacrificial layer 1817, and a portion of the encapsulation material 1839 is attached to the removable / sacrificial layer 1817.

[0071] Referring to Figure 9EThe removable / sacrificial layer 1817 is removed by a physical or chemical method, for example, a water rinsing process. In addition, portions of the encapsulation material 1839 attached to the removable / sacrificial layer 1817 are removed (e.g., when the removable / sacrificial layer 1817 is removed). After the removable / sacrificial layer 1817 and the portions of the encapsulation material 1839 are removed, portions of the encapsulation material 1830 remain on the carrier 181 and a portion of the upper surface 1811 of the carrier 181 is exposed. The portions of the encapsulation material 1830 are disposed on the upper surface 1811 of the carrier 181. The portions of the encapsulation material 1830 have an upper surface 1831 and a lower surface 1832 opposite the upper surface 1831. In addition, the portions of the encapsulation material 1830 further have a surface 1833 at a height between the heights of the upper surface 1831 and the lower surface 1832, where the surface 1833 is attached to the overhanging surface 1812 of the carrier 181. Moreover, the portions of the encapsulation material 1830 further have a surface 1834 adjacent to and lower than the surface 1833. The surface 1834 can be substantially parallel to the surface 1833. The surface 1834 is spaced apart from the upper surface 1811 of the carrier 181. There is a space between the surface 1834 and the upper surface 1811.

[0072] In addition, the portions of the encapsulation material 1830 have a side surface 1836. An angle H between the side surface 1836 and the upper surface 1831 is in a range from about 90 degrees to about 110 degrees.

[0073] Figure 10A Figure 10B Figure 10C Figure 10D Figure 10E A method of manufacturing a semiconductor device package 190 according to another embodiment of the present application is shown. As shown in Figure 10A The carrier 191 has an upper surface 1911 and an overhanging portion 1910 formed on the upper surface 1911. The carrier 191 further has an overhanging surface 1912 that is overhanging with respect to the upper surface 1911. At least one electronic component 192 is disposed on the upper surface 1911 of the carrier 191.

[0074] In addition, referring to Figure 10B A glue is dispensed on the upper surface 1911 of the carrier 191, where the glue extends on the overhanging surface 1912 but does not flow over the overhanging portion 1910. Thus, a removable / sacrificial layer 1917 is formed on the upper surface 1911 and the overhanging surface 1912. Moreover, the removable / sacrificial layer 1917 has a substantially flat upper surface 1918.

[0075] Referring to Figure 10C ​​​​The encapsulation material 193 is disposed on the carrier 191 and encapsulates the at least one electronic component 192 and the removable / sacrificial layer 1917. The encapsulation material 193 covers the at least one electronic component 192, the upper surface 1911 of the carrier 191, and the removable / sacrificial layer 1917.

[0076] Referring to Figure 10D A portion of the encapsulation material 193 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 1917. As a result, the encapsulation material 193 is divided into two portions 1930 and 1939, where a portion of the encapsulation material 1930 is attached to the upper surface 1911 of the carrier 191 and the removable / sacrificial layer 1917, and a portion of the encapsulation material 1939 is attached to the removable / sacrificial layer 1917.

[0077] Referring to Figure 10E The removable / sacrificial layer 1917 is removed by a physical or chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 1939 attached to the removable / sacrificial layer 1917 is removed (e.g., when the removable / sacrificial layer 1917 is removed). After the removable / sacrificial layer 1917 and the portion of the encapsulation material 1939 are removed, the portion of the encapsulation material 1930 remains on the carrier 191 and a portion of the upper surface 1911 of the carrier 191 is exposed. The portion of the encapsulation material 1930 is disposed on the upper surface 1911 of the carrier 191. The portion of the encapsulation material 1930 has an upper surface 1931 and a lower surface 1932 opposite the upper surface 1931. In addition, the portion of the encapsulation material 1930 further has a surface 1933 at a height between the heights of the upper surface 1931 and the lower surface 1932, where the surface 1933 is spaced apart from the upper surface 1911 and the overhanging surface 1912 of the carrier 191. There is a space between the surface 1933 and the upper surface 1911 and the overhanging surface 1912. The surface 1933 can be disposed above the overhanging surface 1912.

[0078] Further, the portion of the encapsulation material 1930 has a side surface 1936. An angle I between the side surface 1936 and the upper surface 1931 is in a range from about 90 degrees to about 110 degrees.

[0079] Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D and Figure 11E A method of manufacturing a semiconductor device package 200 according to another embodiment of the present application is shown. As Figure 11AAs shown in FIG. 1, a carrier 201 has an upper surface 2011 and an overhang 2010 formed on the upper surface 2011. The carrier 201 further has an overhang surface 2012 that overhangs relative to the upper surface 2011. At least one electronic component 202 is disposed on the upper surface 2011 of the carrier 201.

[0080] Further, referring to FIG. 2, a glue is dispensed on the upper surface 2011 of the carrier 201, where the glue extends on the overhang surface 2012 but does not flow over the overhang 2010. Thus, a removable / sacrificial layer 2017 is formed on the upper surface 2011 and the overhang surface 2012. In addition, the removable / sacrificial layer 2017 has a non-uniform upper surface 2018. Figure 11B Further, referring to FIG. 3, an encapsulation material 203 is disposed on the carrier 201 and encapsulates the at least one electronic component 202 and the removable / sacrificial layer 2017. The encapsulation material 203 covers the at least one electronic component 202, the upper surface 2011 of the carrier 201, and the removable / sacrificial layer 2017.

[0081] Figure 11C Further, referring to FIG. 4, a portion of the encapsulation material 203 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 2017. As a result, the encapsulation material 203 is divided into two portions 2030 and 2039, where a portion of the encapsulation material 2030 is attached to the upper surface 2011 of the carrier 201 and the removable / sacrificial layer 2017, and a portion of the encapsulation material 2039 is attached to the removable / sacrificial layer 2017.

[0082] Further, referring to FIG. 5, the removable / sacrificial layer 2017 is removed by a laser process and thus exposes a portion of the encapsulation material 2030. As a result, the encapsulation material 2030 is divided into two portions 2030a and 2030b, where a portion of the encapsulation material 2030a is attached to the upper surface 2011 of the carrier 201 and a portion of the encapsulation material 2030b is attached to the encapsulation material 2039. Figure 11D Further, referring to FIG. 6, the encapsulation material 2030b is removed by a laser process and thus exposes a portion of the encapsulation material 2039. As a result, the encapsulation material 2039 is divided into two portions 2039a and 2039b, where a portion of the encapsulation material 2039a is attached to the encapsulation material 2030a and a portion of the encapsulation material 2039b is attached to the encapsulation material 2030b.

[0083] Figure 11E ​​The removable / sacrificial layer 2017 is removed by a physical or chemical method, for example, a water rinsing process. In addition, a portion of the encapsulation material 2039 attached to the removable / sacrificial layer 2017 is removed (e.g., when the removable / sacrificial layer 2017 is removed). After the removable / sacrificial layer 2017 and the portion of the encapsulation material 2039 are removed, a portion of the encapsulation material 2030 remains on the carrier 201 and a portion of the upper surface 2011 of the carrier 201 is exposed. The portion of the encapsulation material 2030 is disposed on the upper surface 2011 of the carrier 201. The portion of the encapsulation material 2030 has an upper surface 2031 and a lower surface 2032 opposite the upper surface 2031. In addition, the portion of the encapsulation material 2030 further has a surface 2033 at a height between the heights of the upper surface 2031 and the lower surface 2032. The surface 2033 is spaced apart from (and, for example, disposed on) the overhanging surface 2012 of the carrier 201. Moreover, the portion of the encapsulation material 2030 further has a surface 2034 adjacent to and lower than the surface 2033. The surface 2034 can be substantially parallel to the surface 2033. The surface 2034 is spaced apart from the upper surface 2011 of the carrier 201. There is a space between the surfaces 2033, 2034 and the upper surface 2011 and the overhanging surface 2012.

[0084] Moreover, the portion of the encapsulation material 2030 has a side surface 2036. An angle J between the side surface 2036 and the upper surface 2031 is in a range from about 90 degrees to about 110 degrees.

[0085] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F shows a method of manufacturing a semiconductor device package 210 according to another embodiment of the present application. As shown in Figure 12A , a carrier 211 has an upper surface 2111 and a recess 2110 formed in the upper surface 2111. The carrier 211 further has a recessed surface 2112 recessed with respect to the upper surface 2110 (e.g., which defines a bottom of the recess 2110). At least one electronic component 212 is disposed on the upper surface 2111 of the carrier 211. In addition, a conductive layer 215 is disposed on the recessed surface 2112.

[0086] In addition, referring to Figure 12B , a glue is dispensed on the upper surface 2111 of the carrier 211, where a portion of the glue flows into the recess 2110. Accordingly, a removable / sacrificial layer 2117 is formed on the upper surface 2111 and the recessed surface 2112 of the carrier 211 and the conductive layer 215.

[0087] Referring to Figure 12CThe encapsulation material 213 is disposed on the carrier 211 and encapsulates the at least one electronic component 212 and the removable / sacrificial layer 2117. The encapsulation material 213 covers the at least one electronic component 212, the upper surface 2111 of the carrier 211, and the removable / sacrificial layer 2117.

[0088] Referring to Figure 12D A portion of the encapsulation material 213 is removed by a laser process and thus exposes a portion of the removable / sacrificial layer 2117. The cut gap formed by the laser is substantially aligned with the location of the conductive layer 215. The encapsulation material 213 is divided into two portions 2130 and 2139, where the portion of the encapsulation material 2130 is attached to the upper surface 2111 of the carrier 211 and the removable / sacrificial layer 2117, and the portion of the encapsulation material 2139 is attached to the removable / sacrificial layer 2117.

[0089] Referring to Figure 12E The removable / sacrificial layer 2117 is removed by a physical or chemical method, for example, a water washing process. In addition, the portion of the encapsulation material 2139 attached to the removable / sacrificial layer 2117 is removed (e.g., when the removable / sacrificial layer 2117 is removed). After the removable / sacrificial layer 2117 and the portion of the encapsulation material 2139 are removed, the portion of the encapsulation material 2130 remains on the carrier 211, and a portion of the upper surface 2111 and the recessed surface 2112 of the carrier 211 and the conductive layer 215 are exposed. The portion of the encapsulation material 2130 is disposed on the upper surface 2111 of the carrier 211. The portion of the encapsulation material 2130 has an upper surface 2131 and a lower surface 2132 opposite the upper surface 2131. In addition, a portion of the lower surface 2132 is spaced apart from (and, for example, disposed on) the recessed surface 2112 of the carrier 211, and a portion of the lower surface 2132 is attached to the upper surface 2111 of the carrier 211. There is a space between the lower surface 2132 and the recessed surface 2112.

[0090] Further, the portion of the encapsulation material 2130 has a side surface 2136. An angle K between the side surface 2136 and the upper surface 2131 is in a range from about 90 degrees to about 110 degrees.

[0091] Referring to Figure 12F A shielding layer 217 is formed on the conductive layer 215 and the portion of the encapsulation material 2130.

[0092] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F shows a method of manufacturing a semiconductor device package 220 according to another embodiment of the present application. As Figure 13AAs shown in FIG. 2, the carrier 221 has an upper surface 2211 and a conductive layer 225. A portion of the top surface of the conductive layer 255 is exposed and recessed with respect to the upper surface 2211 of the carrier 221.

[0093] In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225. Figure 13B In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225.

[0094] Figure 13C In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225.

[0095] In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225. Figure 13D In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225.

[0096] Figure 13E In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225.

[0097] In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225.

[0098] In addition, referring to FIG. 2, a portion of the encapsulation material 223 is disposed on the upper surface 2211 of the carrier 211 and the conductive layer 225. Thus, the removable / sacrificial layer 2217 is formed on the upper surface 2211 and the carrier 221 and the conductive layer 225. Figure 13F ​​The shielding layer 227 is formed on a portion of the conductive layer 225 and the encapsulation material 2230.

[0099] Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E shows a method of manufacturing a semiconductor device package 230 according to another embodiment of the present application. As shown in Figure 14A , the carrier 231 has an upper surface 2311 and includes a conductive layer 235. A portion of a top surface of the conductive layer 235 is exposed and recessed with respect to the upper surface 2311 of the carrier 231. In addition, because a portion of the top surface of the conductive layer 235 is exposed and recessed with respect to the upper surface 2311 of the carrier 231, the carrier 231 further has side surfaces 2313, 2314 disposed on the conductive layer 225 and angled (e.g., at about 90 degrees) with respect to the upper surface 2311 of the carrier 231.

[0100] In addition, referring to Figure 14B , a die is dispensed on the upper surface 2311 of the carrier 231 and on the conductive layer 235. Thus, a removable / sacrificial layer 2317 is formed on the upper surface 2311 and the carrier 231 and on the conductive layer 235.

[0101] Referring to Figure 14C , an encapsulation material 233 is disposed on the carrier 231 and encapsulates the at least one electronic component 232 and the removable / sacrificial layer 2317. The encapsulation material 233 covers the at least one electronic component 232, the upper surface 2311 of the carrier 231, and the removable / sacrificial layer 2317.

[0102] Referring to Figure 14D , a portion of the encapsulation material 233 is removed by a laser process and thus a portion of the removable / sacrificial layer 2317 and a portion of the upper surface 2311 of the carrier 231 are exposed. In addition, when a laser is used to cut the encapsulation material 233, the laser contacts the portion of the removable / sacrificial layer 2317 and the portion of the upper surface 2311 of the carrier 231 that are exposed after the portion of the encapsulation material 233 has been removed. The portion of the upper surface 2311 of the carrier 231 that is contacted by the laser can be roughened by the laser. The encapsulation material 233 is divided into two portions 2330 and 2339, where a portion of the encapsulation material 2330 is attached to the upper surface 2311 of the carrier 231 and a portion of the encapsulation material 2339 is attached to the removable / sacrificial layer 2317.

[0103] Referring to Figure 14EThe removable / sacrificial layer 2317 is removed by a physical or chemical method, for example, a water rinsing process. In addition, portions of the encapsulation material 2339 attached to the removable / sacrificial layer 2317 are removed (e.g., when the removable / sacrificial layer 2317 is removed). After the removable / sacrificial layer 2317 and the portions of the encapsulation material 2339 are removed, portions of the encapsulation material 2330 remain on the carrier 231 and a portion of the upper surface 2311 of the carrier 231 and the conductive layer 235 are exposed. As noted above, the laser directly contacts the portion of the upper surface 2311 when cutting the encapsulation material 233. Thus, the surface 2312 of the carrier 231 between the portions of the encapsulation material 2330 and the conductive layer 235 has a roughness that is greater than another portion of the upper surface 2311 of the carrier 231 and greater than the roughness of the side surfaces 2313, 2314 of the carrier 231 (e.g., by a factor of about 1.3 or greater, by a factor of about 1.5 or greater, by a factor of about 2 or greater, or by a greater factor).

[0104] In addition, the portions of the encapsulation material 2330 have side surfaces 2336. An angle M between the side surfaces 2336 and the upper surface 2331 is in a range from about 90 degrees to about 110 degrees.

[0105] In the present disclosure, references to a first feature being formed or positioned above or on a second feature can include embodiments in which the first and second features are formed or disposed in direct contact, and can also include embodiments in which additional features can be formed or disposed between the first and second features such that the first and second features can not be in direct contact.

[0106] As used herein, the terms "approximately," "substantially," "virtually," and "about" are used to describe and account for small variations. When used in connection with a quantity, the terms can refer to the exact value of the quantity as well as a range of values that are close to the exact value. For example, when used in connection with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0107] For example, substantially parallel can refer to an angular variation of less than or equal to ±10°, e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°, relative to 0°. For example, substantially perpendicular can refer to an angular variation of less than or equal to ±10°, e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°, relative to 90°.

[0108] Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no greater than 5 pm, no greater than 2 pm, no greater than 1 pm, or no greater than 0.5 pm. A surface can be considered substantially flat if the displacement between the highest point and the lowest point of the surface is no greater than 5 pm, no greater than 2 pm, no greater than 1 pm, or no greater than 0.5 pm.

[0109] As used herein, the singular terms "a," "an," and "the" can encompass the plural unless the context clearly dictates otherwise.

[0110] Additionally, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and should be taken as a literal disclosure of each and every subcombi nation within the range, not limiting specifically merely to the "to" value of the range. It is therefore merely for convenience and brevity to describe a numerical upper limit along with a numerical lower limit. The numerical upper limit is therefore "open-ended." This means that the numerical upper limit is not to be implicitly understood as the "to" value of the range.

[0111] While the application has been described and illustrated with reference to specific embodiments thereof, those skilled in the art will appreciate that various adaptations, changes, modifications, substitutions, deletions, or the like can be made without departing from the true spirit and scope of the application as defined by the appended claims. The description is not intended to be in any way limited, and it is therefore contemplated that any and all modifications, alterations, or variations that fall within the spirit and scope of the application should be considered as falling within the scope of the application. The specification and drawings should be considered merely as illustrative of the principles of the application. The dimensions and other specific numerical data can vary somewhat from that depicted in the drawings depending upon the desires of the particular situation, material, and / or manufacturing processes, or the like. Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. For example, the methods disclosed herein can be described and illustrated with reference to specific operations performed in a particular order. Those skilled in the art will appreciate that these operations can be combined, subdivided, or reordered without departing from the teachings of the presently disclosed methods. Accordingly, unless specifically indicated otherwise, the order and grouping of operations is not a limitation of the application.

Claims

1. A semiconductor device package comprising: a carrier having a first surface and a second surface recessed relative to the first surface; and an encapsulant disposed on the first surface of the carrier, the encapsulant having a first surface, a second surface opposite the first surface of the encapsulant and attached to the carrier, a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and a fourth surface adjacent to the third surface, wherein at least one portion of the encapsulant is spaced apart from the carrier by a space, wherein the third surface of the encapsulant and the fourth surface of the encapsulant are each spaced apart from the second surface of the carrier.

2. The semiconductor device package of claim 1, wherein the third surface of the encapsulant is spaced apart from the first surface of the carrier.

3. The semiconductor device package of claim 1, wherein the carrier has a third surface connecting the first surface and the second surface of the carrier, and the fourth surface of the encapsulant is substantially coplanar with the third surface of the carrier.

4. The semiconductor device package of claim 3, further comprising a conductive layer disposed on the second surface of the carrier.

5. The semiconductor device package of claim 1, wherein the carrier has a third surface connecting the first surface and the second surface of the carrier, the third surface of the encapsulant is spaced apart from the first surface of the carrier, the fourth surface of the encapsulant is connected to the second surface of the encapsulant and the third surface of the encapsulant, and the fourth surface of the encapsulant is disposed on the first surface of the carrier and is not coplanar with the third surface of the carrier, and the third surface of the carrier is disposed below the third surface of the encapsulant.

6. The semiconductor device package of claim 5, wherein the encapsulant further has: a fifth surface adjacent to the third surface of the encapsulant and spaced apart from the second surface of the carrier, and a sixth surface connecting the first surface of the encapsulant and the fifth surface of the encapsulant.

7. A semiconductor device package comprising: a carrier having a first surface and a second surface protruding relative to the first surface; and an encapsulant disposed on the first surface of the carrier, the encapsulant having a first surface, a second surface opposite the first surface of the encapsulant and attached to the carrier, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, a first portion of the third surface of the encapsulant being spaced apart from the first surface of the carrier and a second portion of the third surface of the encapsulant being attached to the second surface of the carrier.

8. A semiconductor device package comprising: a carrier having a first surface and a second surface protruding relative to the first surface; and an encapsulant disposed on the first surface of the carrier, the encapsulant having a first surface, a second surface opposite the first surface of the encapsulant and attached to the carrier, and a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, a first portion of the third surface of the encapsulant being spaced apart from the first surface of the carrier and a second portion of the third surface of the encapsulant being attached to the second surface of the carrier. an encapsulant disposed on the first surface of the carrier, the encapsulant having a first surface, a second surface opposite the first surface of the encapsulant and attached to the second surface of the carrier, a third surface at a height between a height of the first surface of the encapsulant and a height of the second surface of the encapsulant, and a fourth surface adjacent to the third surface of the encapsulant and at a height lower than the height of the third surface of the encapsulant, the third surface of the encapsulant is attached to the second surface of the carrier and the fourth surface of the encapsulant is spaced apart from the first surface of the carrier.

9. The semiconductor device package of claim 8, wherein the fourth surface of the encapsulant is substantially parallel to the third surface of the encapsulant.

10. The semiconductor device package of claim 9, wherein the encapsulant further has a fifth surface connecting the first surface of the encapsulant and the fourth surface of the encapsulant.

11. The semiconductor device package of claim 10, wherein an angle between the fifth surface of the encapsulant and the first surface of the encapsulant is in a range from 90 degrees to 110 degrees.

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