Detection Method for Integrated Circuit Chip and Fuse

Abstract

The present disclosure relates to a method for detecting an integrated circuit chip and a fuse, including a substrate, multiple conductive layers, a fuse, a dielectric layer, and a latch circuit; wherein, a dielectric layer is provided between adjacent conductive layers, a dielectric layer is provided between the substrate and the adjacent conductive layer, and contact holes are provided on the dielectric layer; the fuse is located in the contact holes on the first dielectric layer, and the first dielectric layer is any one of the multiple dielectric layers; the latch circuit is provided on the substrate and is connected to the fuse. During the testing of the integrated circuit chip, the latch-up effect is triggered, so that the current in the latch circuit continuously increases until the fuse is blown, realizing the fusing during the testing of the fuse. And when testing multiple fuses, it is only necessary to sequentially trigger the latch circuits of each fuse, which improves the testing efficiency and saves the testing time.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and more particularly, to an integrated circuit chip and a method for detecting a fuse. Background Art

[0002] With the development and progress of technology, integrated circuits are increasingly widely used, and a large number of fuses are often included in integrated circuits.

[0003] Currently, the fuses used in integrated circuits are usually gate oxide fuses. The gate oxide fuses are in an open state before fusing, and a large voltage difference needs to be applied between the conductive gate and the heavily doped layer to fuse the fuse during fusing.

[0004] When performing integrated circuit testing, it is necessary to perform a fusing test on the fuse. The low fusing efficiency of the gate oxide fuse results in a long test time and low test efficiency.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present disclosure is to provide an integrated circuit chip and a method for detecting a fuse, thereby at least to some extent overcoming the problems of long integrated circuit test time and low test efficiency caused by the limitations and defects of related technologies.

[0007] According to one aspect of the present disclosure, there is provided an integrated circuit chip, comprising:

[0008] A substrate;

[0009] A multi-layer conductive layer, wherein a dielectric layer is provided between adjacent conductive layers, a dielectric layer is provided between the substrate and the adjacent conductive layer, and contact holes are provided on the dielectric layer;

[0010] A fuse located in a contact hole in a first dielectric layer, the first dielectric layer being any one of the multi-layer dielectric layers;

[0011] A latch circuit provided in the substrate and connected to the fuse.

[0012] According to an embodiment of the present disclosure, the first dielectric layer is the uppermost dielectric layer of the multi-layer dielectric layers, wherein the bottom layer is close to the substrate and the upper layer is far from the substrate.

[0013] According to an embodiment of the present disclosure, the integrated circuit chip further comprises:

[0014] A connector, located in a contact hole in a second dielectric layer, where the second dielectric layer is a dielectric layer located between the first dielectric layer and the substrate.

[0015] According to an embodiment of the present disclosure, the contact hole is a via hole, and the cross-sectional area of the first contact hole is smaller than the cross-sectional area of the second contact hole.

[0016] According to an embodiment of the present disclosure, the resistance of the fuse is greater than the resistance of the connector.

[0017] According to an embodiment of the present disclosure, a first conductive layer is connected to a power source for receiving a power signal, and the first conductive layer is a conductive layer located on the side of the first dielectric layer away from the substrate.

[0018] According to an embodiment of the present disclosure, a second conductive layer is connected to an open-circuit detection device for detecting whether the fuse is blown, and the second conductive layer is a conductive layer located on the side of the first dielectric layer close to the substrate.

[0019] According to an embodiment of the present disclosure, the fuse is a metal fuse.

[0020] According to an embodiment of the present disclosure, multiple layers of the conductive layer and the substrate are arranged parallel to each other.

[0021] According to an embodiment of the present disclosure, the integrated circuit chip further includes:

[0022] A passivation layer, located on the surface of the first conductive layer away from the substrate, where the first conductive layer is the uppermost conductive layer among multiple layers of the conductive layer.

[0023] According to another aspect of the present disclosure, there is provided a method for detecting a fuse of an integrated circuit chip, including:

[0024] Trigger the latching effect of the latch circuit to output a fusing current;

[0025] The fusing current flows through the connector, the conductive layer, and the fuse to blow the fuse.

[0026] According to an embodiment of the present disclosure, the test method further includes:

[0027] Detect whether the fuse is blown;

[0028] If the fuse is blown, output a first signal;

[0029] If the fuse is not blown, output a second signal.

[0030] The present disclosure provides an integrated circuit chip. A fuse is disposed in a first contact hole on a first dielectric layer, and the fuse is connected to a latch circuit. During the test of the integrated circuit chip, the latch effect is triggered, so that the current in the latch circuit continuously increases until the fuse is blown, achieving the blowing of the fuse during the test. And when testing multiple fuses, only the latch circuits of each fuse need to be sequentially triggered, improving the test efficiency and saving the test time.

[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0033] Figure 1 Schematic structural diagram of an integrated circuit chip provided for an exemplary embodiment of the present disclosure.

[0034] Figure 2 Schematic connection diagram of a fuse provided for an exemplary embodiment of the present disclosure.

[0035] Figure 3 Top view of a fuse and a conductive layer provided for an exemplary embodiment of the present disclosure.

[0036] Figure 4 Cross-sectional schematic diagram of a fuse provided for an exemplary embodiment of the present disclosure.

[0037] Figure 5 Cross-sectional schematic diagram of a connector provided for an exemplary embodiment of the present disclosure.

[0038] Figure 6 Schematic structural diagram of a CMOS device provided for an exemplary embodiment of the present disclosure.

[0039] Figure 7 For Figure 6 Equivalent circuit diagram of the parasitic latch circuit of the CMOS device shown.

[0040] Figure 8 Schematic structural diagram of another CMOS device provided for an exemplary embodiment of the present disclosure.

[0041] Figure 9 For Figure 8 Equivalent circuit diagram of the parasitic latch circuit of the CMOS device shown.

[0042] Figure 10 A trigger signal diagram of a latch circuit provided for an exemplary embodiment of the present disclosure.

[0043] Figure 11 A flowchart of a test method for a fuse of an integrated circuit chip provided for an exemplary embodiment of the present disclosure.

[0044] Figure 12 A flowchart of another test method for a fuse of an integrated circuit chip provided for an exemplary embodiment of the present disclosure.

[0045] In the figure:

[0046] 100, substrate; 200, conductive layer; 210, first conductive layer; 220, second conductive layer; 300, dielectric layer; 310, first dielectric layer; 320, second dielectric layer; 400, fuse; 500, latch circuit; 600, connector; 700, passivation layer. Detailed implementation manners

[0047] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted.

[0048] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0049] The terms "a", "one", "the", "said" and "at least one" are used to indicate the existence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", etc. are only used as labels and are not a limitation on the quantity of their objects.

[0050] In the related art, a gate oxide fuse is usually adopted in an integrated circuit. The gate oxide fuse is in an open state before fusing. When fusing, a large voltage difference needs to be applied between the conductive gate and the heavily doped layer to fuse the fuse. When performing fuse tests, for multiple fuses, it is often necessary to first perform a fusing test on one of the fuses, and then fuse another one after one fuse is fused, resulting in a long test time and low test efficiency.

[0051] In this exemplary embodiment, an integrated circuit chip is first provided, as Figure 1 shown. The integrated circuit chip includes a substrate 100, a multi-layer conductive layer 200, a fuse 400, a dielectric layer 300, and a latch circuit 500.

[0052] Wherein, a dielectric layer 300 is provided between adjacent conductive layers 200, a dielectric layer 300 is provided between the substrate 100 and the adjacent conductive layer 200, and contact holes are provided on the dielectric layer 300;

[0053] The fuse 400 is located in a first contact hole on the first dielectric layer 310, and the first dielectric layer 310 is any one of the multi-layer dielectric layers 300;

[0054] The latch circuit 500 is provided on the substrate 100 and connected to the fuse 400. After the latch-up effect is triggered, the current in the latch circuit 500 continuously increases and burns out the fuse 400.

[0055] An integrated circuit chip provided by an embodiment of the present disclosure arranges the fuse 400 in a first contact hole on the first dielectric layer 310 and connects the fuse 400 to the latch circuit 500. When testing the integrated circuit chip, the latch-up effect is triggered, so that the current in the latch circuit 500 continuously increases until the fuse 400 is burned out, realizing the fusing during the test of the fuse 400. And when testing multiple fuses 400, it is only necessary to sequentially trigger the latch circuit 500 of each fuse 400, which improves the test efficiency and saves the test time.

[0056] Further, since the dielectric layer 300 is an insulating layer, in order to achieve electrical connection between the multi-layer conductive layers 200, the integrated circuit chip provided by the embodiments of the present disclosure may further include a connector 600. The connector 600 is located in the second contact hole in the second dielectric layer 320. The second dielectric layer 320 is the dielectric layer 300 excluding the first dielectric layer 310 in the multi-layer dielectric layer 300. The connector 600 is used to connect the conductive layers 200 on two layers of the second dielectric layer 320 where it is located. The second dielectric layer 320 at the bottommost layer has its lower side surface in contact with the substrate 100 and its upper side surface in contact with the conductive layer 200. The latch circuit 500 is disposed on the substrate 100, and the contact holes on the second dielectric layer 320 in contact with the substrate 100 are correspondingly arranged with the latch circuit 500, and the conductive layer 200 and the latch circuit 500 are connected through the connector 600 in the contact holes.

[0057] Among them, the connector 600 may be a connecting wire, a conductive connection block, etc., and the embodiments of the present disclosure do not make specific limitations thereto.

[0058] The integrated circuit chip provided by the embodiments of the present disclosure further includes a passivation layer 700. The passivation layer 700 is located on the surface of the first conductive layer 210 away from the substrate 100. The first conductive layer 210 is located at the uppermost layer of the multi-layer conductive layer 200. The passivation layer 700 is used to prevent surface contamination of the integrated circuit chip and protect the conductive layer 200.

[0059] Preferably, the first dielectric layer 310 is located at the uppermost layer of the multi-layer dielectric layer 300. Among them, the side close to the substrate 100 is the bottom layer, and the side away from the substrate 100 is the upper layer. That is to say, the fuse 400 is located in the uppermost first dielectric layer 310 and connects the conductive layers 200 on the upper and lower sides of the uppermost first dielectric layer 310.

[0060] The first conductive layer 210 is connected to a power supply and is used to receive a power signal. The first conductive layer 210 is located above the first dielectric layer 310 away from the substrate 100. The power signal may be a high level or a low level. The power supply, the fuse 400, and the latch circuit 500 form a fuse detection circuit. When testing the fuse 400, the latch effect is triggered through a trigger signal, the current in the latch circuit 500 continuously increases, and the current flowing through the fuse 400 continuously increases until the fuse 400 is burned out.

[0061] The second conductive layer 220 is connected to a break detection device. The break detection device is used to detect whether the fuse 400 is blown. The second conductive layer 220 is the conductive layer 200 on the side of the first dielectric layer 310 close to the substrate 100. Of course, in actual applications, the break detection device may also be connected to the conductive layer 200 between the first conductive layer 210 and the substrate 100. Among them, the break detection device may be a latch circuit or other break detection circuits.

[0062] For example, as Figure 1 shown, the integrated circuit chip may include three conductive layers 200. The fuse 400 is disposed in the first dielectric layer 310 of the uppermost layer and connects the conductive layers 200 on both sides of the first dielectric layer 310. Connectors 600 are disposed in the contact holes of the remaining two second dielectric layers 320. The latch circuit 500 is disposed on the substrate 100, and the latch circuit 500 is connected to the connector 600 in the second dielectric layer 320 in contact with the substrate 100. Through the conductive layer 200 and the connector 600 thereon, the connection to the fuse 400 is finally achieved.

[0063] Furthermore, in order to ensure that when the latch-up effect is triggered, the current in the circuit continuously increases to fuse the fuse 400 without damaging other devices, especially the connector 600. In the embodiments of the present disclosure, the fuse 400 and the connector 600 may be made of the same conductive material. At this time, the resistance of the fuse 400 needs to be greater than the resistance of the connector 600 to ensure that the fuse 400 is first fused during fusing without damaging other devices.

[0064] Exemplarily, as Figures 3 to 5 shown, the cross-sectional area of the fuse 400 may be designed to be smaller than the cross-sectional area of the connector 600. At this time, the cross-sectional area of the first contact hole for accommodating the fuse 400 may be smaller than the cross-sectional area of the second contact hole for accommodating the connector 600. For example, as Figure 4 shown, the cross-section of the fuse 400 may be a square, and the side length d1 of the square may be 50 nm to 200 nm. The cross-section of the connector 600 may also be a square, and the side length d2 of the square may satisfy 3d1 > d2 > 2d1. The width D of the conductive layer 200 may satisfy 3d1 > D > 2d1.

[0065] The multiple conductive layers 200 are arranged in parallel with each other, and the conductive layer 200 is arranged in parallel with the substrate 100. Among them, the conductive layer 200 is a metal conductive layer, and its material may be copper or aluminum. The connector 600 is a metal connector. The fuse 400 may be a fuse or other fuses, and the material of the fuses may be the same as or different from the material of the connector 600.

[0066] The latch circuit described in the embodiments of the present disclosure may be a parasitic circuit generated by the latch-up effect of a CMOS device. For example, in a feasible implementation manner of the present disclosure, it may be achieved through Figure 6The parasitic circuit generated by the CMOS device shown. The CMOS includes a substrate Su, on which an NMOS and a PMOS are provided. The NMOS includes a P-type silicon substrate Su with a relatively low doping concentration, that is, the P-well PW shown in the figure. Two heavily doped N+ regions and one heavily doped P+ region are fabricated on the P-well PW. The PMOS includes an N-type silicon substrate Su with a relatively low doping concentration, that is, the N-well NW shown in the figure. Two heavily doped P+ regions and one heavily doped N+ region are fabricated on the N-well NW.

[0067] In the CMOS, due to the latching effect, a first parasitic transistor Q1 and a second parasitic transistor Q2 are formed. The first emitter and the second emitter of the first parasitic transistor Q1 are connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal; the collector of the second parasitic transistor Q2 is connected to the base of the first transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives a second trigger signal, and the first emitter and the second emitter are connected to a low level, forming a latching circuit.

[0068] The equivalent circuit of the latching circuit is as Figure 7 shown. The fuse can be connected to the first emitter of the first parasitic transistor Q1. One end of the fuse Fu is connected to the first emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in the CMOS, the fuse Fu is connected to the source of the PMOS. When the latching effect of the CMOS is triggered, the current in the latching circuit continuously increases, and the current flowing through the fuse Fu also continuously increases, eventually fusing the fuse Fu. Of course, the fuse can also be set at the second emitter of the first parasitic transistor Q1, the first emitter of the second parasitic transistor Q2, or the second emitter of the second parasitic transistor Q2.

[0069] In practical applications, a CMOS as shown in Figure 6 can be provided on the substrate. During detection, by the trigger signal, the latching effect of the CMOS is triggered, so that the current flowing through the fuse continuously increases and burns out the fuse. Among them, the trigger signal can be an overshoot signal or an undershoot signal at the trigger terminal of the latching circuit. For example, Figure 7 in the circuit shown, the first receiving terminal G1 is set at the base of the second parasitic transistor Q2, the second receiving terminal G2 is set at the base of the first parasitic transistor Q1, the third receiving terminal G3 is set at the high level terminal, and the fourth receiving terminal G4 is set at the low level terminal. The latching circuit can be triggered by a trigger signal as shown in Figure 10 .

[0070] In another feasible embodiment of the present disclosure, a latching circuit can be generated by a structure as shown in Figure 8 , such as Figure 8As shown, the structure includes a substrate Su, on which an N-type region and a P-type region are provided, namely an N-well NW and a P-well PW. Heavily doped P+ and N+ are fabricated on the N-well NW, and heavily doped P+ and N+ are fabricated on the P-well PW. A third parasitic transistor Q3 and a fourth parasitic transistor Q4 are formed on this structure. Among them, the emitter of the third parasitic transistor Q3 is connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal; for the fourth parasitic transistor Q4, its collector is connected to the base of the third transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives a second trigger signal, and the emitter is connected to a low level, forming a latch circuit. In the latch circuit, when a trigger signal is received, the current in the latch circuit gradually increases.

[0071] Figure 9 is Figure 8 the equivalent circuit diagram of the connection between the parasitic circuit and the fuse Fu, as Figure 8 shown, the fuse Fu can be connected to the emitter of the third parasitic transistor Q3. One end of the fuse Fu is connected to the emitter of the third parasitic transistor Q3, and the other end is connected to the power supply. Correspondingly, the P+ terminal on the N-type region. When the latch-up effect is triggered, the current in the latch circuit continuously increases, and the current flowing through the fuse Fu also continuously increases, eventually melting the fuse Fu. Of course, the fuse can also be arranged at the emitter of the fourth parasitic transistor Q4.

[0072] In practical applications, a structure as Figure 8 shown can be set on the substrate. During detection, by means of a trigger signal, the latch-up effect of the CMOS is triggered, so that the current flowing through the fuse continuously increases and burns out the fuse. Among them, the trigger signal can be an overshoot signal or an undershoot signal at the trigger terminal of the latch circuit.

[0073] In this exemplary embodiment, a method for detecting a fuse of an integrated circuit chip is also provided, as Figure 11 shown, and the method includes the following steps:

[0074] Step S1, trigger the latch-up effect of the latch circuit to output a fusing current;

[0075] Step S2, the fusing current flows through the connector, the conductive layer and the fuse to fuse the fuse.

[0076] By triggering the latch-up effect of the latch circuit, the fusing current output by the latch circuit continuously increases, thereby quickly fusing the fuse, saving detection time. And when detecting multiple fuses, only need to sequentially trigger the latch circuit to ensure the fusing of the fuse, avoiding the situation in the related art that it is necessary to detect the fusing of the current fuse before fusing another fuse, saving detection time and improving detection efficiency.

[0077] Optionally, as Figure 12 shown, after step S2 of a method for detecting a fuse of an integrated circuit chip provided by an embodiment of the present disclosure, the method may further include:

[0078] Step S3, detecting whether the fuse is blown;

[0079] Step S4, if the fuse is blown, outputting a first signal;

[0080] Step S5, if the fuse is not blown, outputting a second signal.

[0081] In step S3, whether the fuse is blown can be detected by an open-circuit detection device, such as a latch circuit, etc.; in step S4, if the fuse is blown, the entire circuit is open, and the open-circuit detection device outputs a first signal, which is used to indicate that the fuse has been blown; in step S5, if the fuse is not blown, a second signal is output, and the second signal is used to indicate that the fuse is unqualified or the circuit is faulty.

[0082] By detecting whether the fuse is blown, outputting a first signal when the fuse is blown, and outputting a second signal when the fuse is not blown, the test result of the fuse can be easily obtained, avoiding the problem that the test result of the fuse cannot be directly obtained due to the fuse being located inside the integrated circuit chip.

[0083] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. An integrated circuit chip, characterized in that, it includes: a substrate; a multi-layer conductive layer, wherein a dielectric layer is provided between adjacent conductive layers, a dielectric layer is provided between the substrate and the adjacent conductive layer, and contact holes are provided on the dielectric layer; the conductive layer includes a first conductive layer and a second conductive layer; a fuse, located in the contact hole on the first dielectric layer, and the first dielectric layer is any one of the multi-layer dielectric layers; a latch circuit, provided in the substrate and connected to the fuse; wherein, the integrated circuit chip further includes: a connector, located in the contact hole in the second dielectric layer, and the second dielectric layer is the dielectric layer between the first dielectric layer and the substrate; the connector is used to connect the conductive layers on the upper and lower layers of the second dielectric layer; the cross-sectional area of the fuse is smaller than the cross-sectional area of the connector; the contact hole on the second dielectric layer in contact with the substrate is correspondingly arranged with the latch circuit, and the conductive layer and the latch circuit are connected through the connector in the contact hole.

2. The integrated circuit chip according to claim 1, characterized in that, the first dielectric layer is the uppermost dielectric layer of the multi-layer dielectric layers, wherein, close to the substrate is the bottom layer, and far from the substrate is the upper layer.

3. The integrated circuit chip according to claim 1, characterized in that, the resistance of the fuse is greater than the resistance of the connector.

4. The integrated circuit chip according to claim 1, characterized in that, the first conductive layer is connected to a power supply for receiving a power supply signal, and the first conductive layer is the conductive layer on the side of the first dielectric layer far from the substrate.

5. The integrated circuit chip according to claim 1, characterized in that, the second conductive layer is connected to an open-circuit detection device, and the open-circuit detection device is used to detect whether the fuse is blown, and the second conductive layer is the conductive layer on the side of the first dielectric layer close to the substrate.

6. The integrated circuit chip according to claim 1, characterized in that, the fuse is a metal fuse.

7. The integrated circuit chip according to claim 1, characterized in that, the multi-layer conductive layers and the substrate are arranged parallel to each other.

8. The integrated circuit chip according to any one of claims 1 to 7, characterized in that, the integrated circuit chip further includes: a passivation layer, located on the side of the first conductive layer far from the substrate, and the first conductive layer is the uppermost conductive layer of the multi-layer conductive layers.

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