Semiconductor device including stress pattern

Abstract

A semiconductor device is provided. A semiconductor device includes: a fin structure, including a stress structure and a semiconductor region sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. In addition, the stress structure includes an oxide.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0108380 filed in the Korean Intellectual Property Office on September 11, 2018, and incorporates the entire disclosure of this application by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] In order to increase the integration density of integrated circuit devices, a multi-gate transistor has been proposed, which includes a fin-shaped or nanowire-shaped silicon body on a substrate and a gate on the silicon body. Since the multi-gate transistor can utilize a three-dimensional channel, it can be scaled.

[0005] In addition, the current control capability of the multi-gate transistor can be improved without increasing the gate length of the multi-gate transistor. Short channel effect (SCE) can be effectively reduced and / or suppressed in the multi-gate transistor, in which the potential of the channel region is affected by the drain voltage. A layer containing a stress material can be formed in a fin-type silicon body to increase carrier mobility in the channel region of a semiconductor device. Summary of the invention

[0006] According to an example embodiment of the inventive concept, a semiconductor device may include a substrate. The semiconductor device may include a fin structure including a stress pattern and a semiconductor pattern sequentially stacked on the substrate. The semiconductor device may include a field insulation layer on a portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure. The gate electrode may intersect the fin structure and extend in a first direction. In addition, the stress pattern may include a first oxide pattern and a second oxide pattern, the first oxide pattern and the second oxide pattern being spaced apart from each other in a second direction different from the first direction.

[0007] According to an example embodiment of the present invention, a semiconductor device may include a substrate. The semiconductor device may include a fin structure including a stress structure and a first semiconductor region sequentially stacked on the substrate. The semiconductor device may include a field insulation layer on a portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure and the field insulation layer. The gate electrode may intersect the fin structure. The stress structure may include a first oxide region including germanium. The stress structure may include a second oxide region spaced apart from the first oxide region. The second oxide region may include germanium. In addition, the stress structure may include a second semiconductor region between the first oxide region and the second oxide region. The second semiconductor region may not contain germanium.

[0008] According to an example embodiment of the present invention, a semiconductor device may include a substrate. The semiconductor device may include a fin structure on the substrate. The semiconductor device may include a field insulation layer on a sidewall portion of the fin structure. The semiconductor device may include a gate electrode on the fin structure, and the gate electrode may intersect the fin structure. In addition, the fin structure may include a first semiconductor layer, a stress region, and a second semiconductor layer sequentially stacked on the substrate. The stress region may include an oxide containing germanium. A first angle between an upper surface of the first semiconductor layer and a first line parallel to the upper surface of the substrate may be different from a second angle between a lower surface of the second semiconductor layer and a second line parallel to the upper surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a layout diagram illustrating a semiconductor device according to example embodiments.

[0010] Figure 2 FIG. 1 is a diagram showing a semiconductor device according to an example embodiment. Figure 1 Cross-sectional view along line AA.

[0011] Figure 3 FIG. 1 is a diagram showing a semiconductor device according to an example embodiment. Figure 1 A cross-sectional view along line BB.

[0012] Figure 4 yes Figure 3 An enlarged view of part S.

[0013] Figure 5 is shown along Figure 4 FIG. 5 is a graph showing a change in the germanium concentration of the first scan line P1 - P2 .

[0014] Figures 6 to 9 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0015] Fig.10 and Fig.11 is a view illustrating a semiconductor device according to example embodiments.

[0016] Fig.12 , Fig.13 and Fig.15 is a view illustrating a semiconductor device according to example embodiments.

[0017] Fig.14 is shown along Fig.13 A graph showing the change in germanium concentration along the scan line P3-P4.

[0018] Fig.16 is shown along Fig.15 A graph showing the change in germanium concentration along the scan line P5-P6.

[0019] Figures 17 to 19 is a view illustrating a semiconductor device according to example embodiments.

[0020] Figure 20 to Figure 22 is a view illustrating a semiconductor device according to example embodiments.

[0021] Figure 23 to Figure 27 is a view illustrating a semiconductor device according to example embodiments.

[0022] Figures 28 to 30 is a view illustrating a semiconductor device according to example embodiments.

[0023] Figure 31 to Figure 37 are views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments.

[0024] Fig.38 and Fig.39 are views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments.

[0025] Fig.40 is a view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0026] Fig.41 and Fig.42 is shown along Fig.40 A graph showing the change in germanium concentration along the scan line P7-P8. DETAILED DESCRIPTION

[0027] Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. The inventive concept may, however, be embodied in many alternate forms and should not be construed as limited to only the example embodiments set forth herein.

[0028] In the drawings of the semiconductor device according to the example embodiments of the present invention, a fin transistor (FinFET) including a fin-type channel region is shown, but the present invention is not limited thereto. The semiconductor device according to the example embodiments of the present invention may include a tunneling transistor, a three-dimensional transistor, a transistor including a nanowire-shaped channel, or a transistor including a nanosheet-shaped channel region. The semiconductor device according to the embodiment of the present invention may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), etc.

[0029] Figure 1 is a layout diagram illustrating a semiconductor device according to example embodiments. Figure 2 FIG. 1 is a diagram showing a semiconductor device according to an example embodiment. Figure 1 Cross-sectional view along line AA. Figure 3FIG. 1 is a diagram showing a semiconductor device according to an example embodiment. Figure 1 A cross-sectional view along line BB. Figure 4 yes Figure 3 An enlarged view of part S. Figure 5 is shown along Figure 4 FIG. 5 is a graph showing a change in the germanium concentration of the first scan line P1 - P2 .

[0030] Reference Figures 1 to 5 , a semiconductor device according to example embodiments may include a substrate 100 , a first fin structure FS, a field insulating layer 105 , a first gate structure GS1 , a second gate structure GS2 , source / drain regions 150 , and an interlayer insulating layer 160 .

[0031] The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 100 may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0032] The substrate 100 may include a first fin structure FS. The first fin structure FS may protrude from the substrate 100. The first fin structure FS may extend in a first direction X parallel to an upper surface of the substrate 100.

[0033] The first fin structure FS may include a first semiconductor pattern 110 , a stress pattern 120 , and a third semiconductor pattern 130 sequentially stacked on a substrate 100 .

[0034] The first semiconductor pattern 110 may protrude from the substrate 100 and may extend in the first direction X. The first semiconductor pattern 110 may be a portion of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 .

[0035] The first semiconductor pattern 110 may include a first semiconductor material. For example, the first semiconductor material may include silicon (Si) or germanium (Ge). The fin structure FS may include a compound semiconductor, such as a TV-TV group compound semiconductor or a III-V group compound semiconductor. Hereinafter, it will be described that the first semiconductor pattern 110 includes silicon.

[0036] The stress pattern 120 may be formed on the first semiconductor pattern 110. The stress pattern 120 may extend in the first direction X.

[0037] The stress pattern 120 may include an oxide of a second semiconductor material. The second semiconductor material may be a material having an oxidation rate faster than that of the first semiconductor material. For example, when the first semiconductor material is silicon, the second semiconductor material may be germanium (Ge). The stress pattern 120 may include at least one of silicon germanium oxide, silicon germanium oxycarbide, and germanium oxide.

[0038] In some embodiments, the stress pattern 120 may include a plurality of oxide patterns. Figures 2 to 4 As shown, the stress pattern 120 may include a first oxide pattern 122 and a second oxide pattern 124. The first oxide pattern 122 and the second oxide pattern 124 may be spaced apart from each other with a second semiconductor pattern 126 therebetween. The stress pattern 120 may include a second semiconductor pattern 126. In some embodiments, the stress pattern 120 may include three or more oxide patterns spaced apart from each other.

[0039] In addition, although the term "pattern" is used in the examples of this article to describe elements 110, 122, 124, 126, and 130, these elements may include corresponding layers / regions and are not limited to patterns. Therefore, elements 110, 122, 124, 126, and 130 may be referred to as a first semiconductor layer / region, a first oxide layer / region, a second oxide layer / region, a second semiconductor layer / region, and a third semiconductor layer / region, respectively, in this article. Similarly, element 120 may be a structure / region that is not limited to a pattern, and therefore may be referred to as a "stress structure" or "stress region" in this article. Additionally or alternatively, the term "first" or the term "second" may be used herein to refer to element 130, and the term "second" or the term "third" may be used herein to refer to element 110, as these terms do not necessarily imply a specific order in the fin structure FS.

[0040] In some embodiments, the first oxide pattern 122 and the second oxide pattern 124 may be spaced apart from each other in a third direction Z that is perpendicular (e.g., orthogonal) to the upper surface of the substrate 100. The first oxide pattern 122, the second semiconductor pattern 126, and the second oxide pattern 124 may be vertically stacked on the substrate 100. The first oxide pattern 122, the second semiconductor pattern 126, and the second oxide pattern 124 may extend in the first direction X.

[0041] The first oxide pattern 122 and the second oxide pattern 124 may include an oxide of the second semiconductor material. The first oxide pattern 122 and the second oxide pattern 124 may include at least one of silicon germanium oxide, silicon germanium oxycarbide, and germanium oxide.

[0042] In some embodiments, the second semiconductor pattern 126 may not contain (ie, may not include) germanium (Ge).For example, the second semiconductor pattern 126 may include a first semiconductor material, for example, silicon (Si).

[0043] A third semiconductor pattern 130 may be formed on the stress pattern 120. The third semiconductor pattern 130 may extend in the first direction X. In some embodiments, the third semiconductor pattern 130 may be a channel region of an NMOS transistor.

[0044] The third semiconductor pattern 130 may directly contact one of the first oxide pattern 122 and the second oxide pattern 124. For example, the third semiconductor pattern 130 may directly contact an upper surface of the second oxide pattern 124.

[0045] The third semiconductor pattern 130 may include a third semiconductor material. The third semiconductor material may be a material having an oxidation rate slower than that of the second semiconductor material. In some embodiments, the third semiconductor material may be the same as the first semiconductor material. For example, the third semiconductor pattern 130 may include silicon (Si).

[0046] In some embodiments, a semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may be oxidized by an oxidation process to form a stress pattern 120 including a first oxide pattern 122 and a second oxide pattern 124. However, a semiconductor layer including silicon (Si) having an oxidation rate slower than that of silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may not be oxidized by the oxidation process to form the first semiconductor pattern 110 and the third semiconductor pattern 130.

[0047] In some embodiments, the stress pattern 120 may apply tensile stress to the third semiconductor pattern 130. This may be caused by, for example, a feature of an oxidation process used to form the stress pattern 120. For example, a semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may expand during the oxidation process so that the stress pattern 120 may be formed. Therefore, tensile stress may be applied to the third semiconductor pattern 130 so that carrier mobility in the third semiconductor pattern 130 may be increased.

[0048] In some embodiments, reference Figure 4, a width W4 of the first oxide pattern 122 and a width W5 of the second oxide pattern 124 may be greater than a width W1 of the first semiconductor pattern 110, a width W2 of the second semiconductor pattern 126, or a width W3 of the third semiconductor pattern 130. Here, the term "width" refers to a width in a second direction Y that is parallel to the upper surface of the substrate 100 and intersects the first direction X. In some embodiments, a semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may expand during an oxidation process to form a first oxide pattern 122 having a width W4 and a second oxide pattern 124 having a width W5.

[0049] In some embodiments, the width W4 of the first oxide pattern 122 may be the same as the width W5 of the second oxide pattern 124 , but is not limited thereto. In some embodiments, the width W4 of the first oxide pattern 122 may be greater than the width W5 of the second oxide pattern 124 .

[0050] The width W1 of the first semiconductor pattern 110, the width W2 of the second semiconductor pattern 126, and the width W3 of the third semiconductor pattern 130 may be the same, but are not limited thereto. In some embodiments, the width W1 of the first semiconductor pattern 110 may be greater than the width W2 of the second semiconductor pattern 126, and the width W2 of the second semiconductor pattern 126 may be greater than the width W3 of the third semiconductor pattern 130.

[0051] A field insulation layer 105 may be formed on the substrate 100 . The field insulation layer 105 may be on (eg, may cover) a portion of a sidewall of the first fin structure FS. For example, the first fin structure FS may be defined by the field insulation layer 105 .

[0052] In some embodiments, the height H1 of the upper surface of the field insulation layer 105 relative to the upper surface of the substrate 100 may be higher than the height of the uppermost surface of the stress pattern 120. For example, the field insulation layer 105 may completely cover the sidewalls of the stress pattern 120. A lower portion of the third semiconductor pattern 130 may be buried in the field insulation layer 105.

[0053] The field insulating layer 105 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0054] In some embodiments, the germanium concentration in the first oxide pattern 122 and the second oxide pattern 124 may be greater than the germanium concentration in the field insulation layer 105. Figure 5 , a scan line P1 - P2 intersecting the first oxide pattern 122 along the second direction Y may be defined. The germanium concentration may rapidly increase from a boundary surface of the first oxide pattern 122 toward an interior of the first oxide pattern 122 along the scan line P1 - P2 .

[0055] exist Figure 3 and Figure 4 105 and the boundary between the first oxide pattern 122 and the field insulation layer 105 and the boundary between the second oxide pattern 124 and the field insulation layer 105 are shown to be visible, but the inventive concept is not limited thereto. In some embodiments, since the field insulation layer 105, the first oxide pattern 122, and the second oxide pattern 124 include oxides, the boundary between the first oxide pattern 122 and the field insulation layer 105 and the boundary between the second oxide pattern 124 and the field insulation layer 105 may not appear clearly.

[0056] The first gate structure GS1 and the second gate structure GS2 may be formed on the first fin structure FS and the field insulating layer 105. The first gate structure GS1 and the second gate structure GS2 may intersect the first fin structure FS. For example, the first gate structure GS1 and the second gate structure GS2 may be spaced apart from each other in the first direction X and may extend in the second direction Y.

[0057] The first gate structure GS1 may include a first gate insulating layer 142 , a first gate electrode 144 , a first gate spacer 146 , a first gate trench GT1 defined by the first gate spacer 146 , and a first capping pattern 148 .

[0058] The second gate structure GS2 may include a second gate insulating layer 242 , a second gate electrode 244 , a second gate spacer 246 , a second gate trench GT2 defined by the second gate spacer 246 , and a second capping pattern 248 .

[0059] The first gate insulating layer 142 may be interposed between the first fin structure FS and the first gate electrode 144. The second gate insulating layer 242 may be interposed between the first fin structure FS and the second gate electrode 244. In some embodiments, the first gate insulating layer 142 may extend along the sidewall and bottom surface of the first gate trench GT1, and the second gate insulating layer 242 may extend along the sidewall and bottom surface of the second trench 6T2.

[0060] The first gate insulating layer 142 and the second gate insulating layer 242 may include a high-k dielectric layer including a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The first gate insulating layer 142 and the second gate insulating layer 242 may include hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof.

[0061] The first gate electrode 144 may be formed on the first gate insulating layer 142. The second gate electrode 244 may be formed on the second gate insulating layer 242. The first gate electrode 144 may fill at least a portion of the first gate trench GT1. The second gate electrode 244 may fill at least a portion of the second gate trench GT2.

[0062] The first gate electrode 144 and the second gate electrode 244 may include, for example, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), or a combination thereof. In some embodiments, the first gate electrode 144 and the second gate electrode 244 may include, for example, silicon or silicon germanium.

[0063] The first gate electrode 144 and the second gate electrode 244 may be formed of a single layer. In some embodiments, the first gate electrode 144 and the second gate electrode 244 may include a work function adjustment layer and a filling layer on the work function adjustment layer. The work function adjustment layer may include, for example, Ti, titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), Ta, tantalum nitride (TaN) or a combination thereof, but is not limited thereto. The filling layer may include, for example, W, Al, Co, Cu, ruthenium (Ru), nickel (Ni), platinum (Pt), Ni-Pt, TiN or a combination thereof.

[0064] The first gate spacer 146 may be formed on a sidewall of the first gate electrode 144. The second gate spacer 246 may be formed on a sidewall of the second gate electrode 244.

[0065] The first gate spacer 146 and the second gate spacer 246 may each include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbon oxynitride, or a combination thereof.

[0066] The first capping pattern 148 may be formed on the first gate electrode 144. The second capping pattern 248 may be formed on the second gate electrode 244.

[0067] The first and second capping patterns 148 and 248 may each include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof.

[0068] In some embodiments, the first gate spacer 146 may be formed on the sidewalls of the first gate electrode 144 and the sidewalls of the first capping pattern 148, and the second gate spacer 246 may be formed on the sidewalls of the second gate electrode 244 and the sidewalls of the second capping pattern 248. Figure 2The first gate electrode 144 may fill a portion of the first gate trench GT1, and the first capping pattern 148 may fill the remaining portion of the first gate trench GT1. The second gate electrode 244 may fill a portion of the second gate trench GT2, and the second capping pattern 248 may fill the remaining portion of the second gate trench GT2.

[0069] In some embodiments, the first capping pattern 148 may be formed on the upper surface of the first gate electrode 144 and the upper surface of the first gate spacer 146 . The second capping pattern 248 may be formed on the upper surface of the second gate electrode 244 and the upper surface of the second gate spacer 246 .

[0070] In some embodiments, the first capping pattern 148 and the second capping pattern 248 may be omitted.

[0071] In some embodiments, the first gate structure GS1 and the second gate structure GS2 may be formed by the same process.

[0072] The source / drain region 150 may be formed in the first fin structure FS. The source / drain region 150 may be formed in the third semiconductor pattern 130 at opposite sides of the first gate electrode 144 and at opposite sides of the second gate electrode 244 .

[0073] The source / drain regions 150 may each include an epitaxial layer formed on the first fin structure FS. For example, the source / drain regions 150 may each be an epitaxial pattern filling a source / drain trench formed in the third semiconductor pattern 130. In some embodiments, the source / drain regions 150 may each be an impurity region formed in the third semiconductor pattern 130.

[0074] In some embodiments, the source / drain regions 150 may each be an elevated source / drain region having an upper surface that is more protruding / higher than an upper surface of the first fin structure FS.

[0075] In some embodiments, the source / drain regions 150 may each include an undercut portion formed under the first gate structure GS1 and the second gate structure GS2. This may be caused by the characteristics of the etching process for forming the source / drain trenches. However, the inventive concept is not limited thereto. For example, the source / drain regions 150 may not include an undercut portion.

[0076] An interlayer insulating layer 160 may be formed on the field insulating layer 105 and the source / drain regions 150. The interlayer insulating layer 160 may be on (eg, may cover) sidewalls of the first gate structure GS1 and the second gate structure GS2.

[0077] In some embodiments, the interlayer insulating layer 160 may further include an etch stop layer extending along an upper surface of the source / drain region 150 .

[0078] For example, the interlayer insulating layer 160 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, flowable oxide (FOX), Tossilazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material or a combination thereof.

[0079] Figures 6 to 9 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figures 6 to 9 is along Figure 1 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0080] Reference Figure 6 In the semiconductor device according to example embodiments, the first semiconductor pattern 110 , the second semiconductor pattern 126 , and the third semiconductor pattern 130 may have inclined surfaces 110US, 126LS, 126US, and 130US, respectively.

[0081] For example, the upper surface of the first semiconductor pattern 110 may have a first surface 110US having an acute angle with respect to the upper surface of the substrate 100. The lower surface of the second semiconductor pattern 126 may have a second surface 126LS having an acute angle with respect to the upper surface of the substrate 100. The upper surface of the second semiconductor pattern 126 may have a third surface 126US having an acute angle with respect to the upper surface of the substrate 100. The lower surface of the third semiconductor pattern 130 may have a fourth surface 130LS having an acute angle with respect to the upper surface of the substrate 100. The first to fourth surfaces 110US, 126LS, 126US, and 130LS may each extend in the first direction X. This may be caused by, for example, the characteristics of the oxidation process that forms the stress pattern 120.

[0082] As the distance from each sidewall of the first semiconductor pattern 110 increases, the height of the first surface 110US of the first semiconductor pattern 110 may increase. As the distance from each sidewall of the second semiconductor pattern 126 increases, the height of the second surface 126LS of the second semiconductor pattern 126 may decrease. Therefore, as an example, a dumbbell-shaped first oxide pattern 122 may be formed.

[0083] As the distance from each sidewall of the second semiconductor pattern 126 increases, the height of the third surface 126US of the second semiconductor pattern 126 may increase. As the distance from each sidewall of the third semiconductor pattern 130 increases, the height of the fourth surface 130LS of the third semiconductor pattern 130 may decrease. Therefore, as an example, a dumbbell-shaped second oxide pattern 124 may be formed.

[0084] Reference Figure 7 In the semiconductor device according to example embodiments, the first fin structure FS may further include a first connection pattern 112 and a second connection pattern 132 .

[0085] The first connection pattern 112 may traverse / extend through the first oxide pattern 122 to connect the first semiconductor pattern 110 and the second semiconductor pattern 126. The second connection pattern 132 may traverse / extend through the second oxide pattern 124 to connect the second semiconductor pattern 126 and the third semiconductor pattern 130. The first connection pattern 112 and the second connection pattern 132 may extend in the first direction X.

[0086] The first and second connection patterns 112 and 132 may include a second semiconductor material. For example, the first and second connection patterns 112 and 132 may include at least one of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and germanium (Ge).

[0087] During the oxidation process for forming the stress pattern 120 , a portion (eg, a central portion) of the semiconductor layer including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may not be oxidized, thereby forming the first and second connection patterns 112 and 132 .

[0088] Reference Figure 8 In the semiconductor device according to example embodiments, a portion of the stress pattern 120 may directly contact the upper surface of the substrate 100 . For example, a lower surface of the first oxide pattern 122 of the stress pattern 120 may directly contact the upper surface of the substrate 100 .

[0089] In some embodiments, the first semiconductor pattern may be omitted (see, for example, Figure 3 110 in the stress pattern 120). Therefore, the lower surface of the stress pattern 120 may directly contact the upper surface of the substrate 100. For example, the lower surface of the first oxide pattern 122 of the stress pattern 120 may directly contact the upper surface of the substrate 100.

[0090] In some embodiments, when the thickness of the stress pattern 120 is adjusted, the tensile stress applied to the third semiconductor pattern 130 by the stress pattern 120 may be adjusted. Here, the term "thickness" refers to the thickness in the third direction Z.

[0091] Reference Fig. 9 , in the semiconductor device according to example embodiments, a height H3 of an upper surface of the field insulation layer 105 may be lower than a height H4 of an uppermost surface of the stress pattern 120 with respect to an upper surface of the substrate 100 .

[0092] The field insulation layer 105 may not vertically overlap at least a portion of the stress pattern 120 (eg, may expose at least a portion of the stress pattern 120 ). In addition, the third semiconductor pattern 130 may not contact the field insulation layer 105 .

[0093] like Fig. 9 As shown, a height H3 of an upper surface of the field insulation layer 105 may be higher than a height of an upper surface of the second semiconductor pattern 126 with respect to an upper surface of the substrate 100 , but the inventive concept is not limited thereto.

[0094] In some embodiments, a height H3 of an upper surface of the field insulation layer 105 relative to an upper surface of the substrate 100 may be lower than a height of an upper surface of the second semiconductor pattern 126. In some embodiments, a height H3 of an upper surface of the field insulation layer 105 relative to an upper surface of the substrate 100 may be lower than a height of an upper surface of the first semiconductor pattern 110.

[0095] Fig.10 and Fig.11 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.10 is along Figure 1 A cross-sectional view taken along line AA. Fig.11 is along Figure 1 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0096] Reference Fig.10 and Fig.11 , the first oxide pattern 122 and the second oxide pattern 124 may be spaced apart from each other in the first direction X.

[0097] The first direction X may be, for example, a longitudinal extension direction of the first fin structure FS. The first oxide pattern 122 , the second semiconductor pattern 126 , and the second oxide pattern 124 may be sequentially positioned (eg, placed / arranged) along the first direction X. The first oxide pattern 122 and the second oxide pattern 124 may each extend in the first direction X.

[0098] In some embodiments, the first oxide pattern 122 may overlap the first gate electrode 144, and the second oxide pattern 124 may overlap the second gate electrode 244. For example, the first oxide pattern 122 may intersect the first gate electrode 144, and the second oxide pattern 124 may intersect the second gate electrode 244. Therefore, the first oxide pattern 122 may apply tensile stress to the third semiconductor pattern 130 between the first oxide pattern 122 and the first gate electrode 144. In addition, the second oxide pattern 124 may apply tensile stress to the third semiconductor pattern 130 between the second oxide pattern 124 and the second gate electrode 244.

[0099] In some embodiments, the second semiconductor pattern 126 may not overlap the first gate electrode 144 and the second gate electrode 244 .

[0100] Figures 12 to 16 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.13 and Fig.15 is along Fig.12 Cross-sectional view taken along line CC. Fig.14 is shown along Fig.13 FIG. 5 is a graph showing a change in the germanium concentration of the second scan line P3 - P4 . Fig.16 is shown along Fig.15 For convenience of explanation, elements repeated with the above-mentioned example will be briefly described or omitted.

[0101] Reference Figures 12 to 16 In the semiconductor device according to example embodiments, a first angle θ1 formed between an extension line of an upper surface of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100 may be different from a second angle θ2 formed between an extension line of a lower surface of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100.

[0102] In some embodiments, Fig.13 As shown, a first angle θ1 formed between an extension line of the first surface 110US of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100 may be greater than a second angle θ2 formed between an extension line of the fourth surface 130LS of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100. The second angle θ2 may be an acute angle, but is not limited thereto. For example, the fourth surface 130LS of the third semiconductor pattern 130 may be parallel to the upper surface of the substrate 100.

[0103] In this case, the germanium concentration in the stress pattern 120 may increase as the distance from the upper surface of the substrate 100 increases. Fig.14As shown, a second scan line P3 - P4 intersecting the stress pattern 120 in the third direction Z may be defined. The germanium concentration in the stress pattern 120 may increase along the second scan line P3 - P4 .

[0104] like Fig.14 As shown, the germanium concentration in the stress pattern 120 may increase exponentially along the second scan line P3 - P4 , but the inventive concept is not limited thereto. For example, the germanium concentration in the stress pattern 120 may increase linearly along the second scan line P3 - P4 .

[0105] In some embodiments, Fig.15 As shown, a first angle θ1 formed between an extension line of the first surface 110US of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100 may be smaller than a second angle θ2 formed between an extension line of the fourth surface 130LS of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100. The first angle θ1 may be an acute angle, but is not limited thereto. For example, the first surface 110US of the third semiconductor pattern 130 may be parallel to the upper surface of the substrate 100.

[0106] In this case, the germanium concentration in the stress pattern 120 may decrease as the distance from the upper surface of the substrate 100 increases. Fig.16 As shown, third scan lines P5 - P6 intersecting the stress pattern 120 in the third direction Z may be defined. The germanium concentration in the stress pattern 120 may decrease along the third scan lines P5 - P6 .

[0107] like Fig.16 As shown, the germanium concentration in the stress pattern 120 may decrease exponentially along the third scan line P5-P6, but the inventive concept is not limited thereto. For example, the germanium concentration in the stress pattern 120 may decrease linearly along the third scan line P5-P6.

[0108] Figures 17 to 19 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.18 and Fig.19 is along Fig.17 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0109] Reference Figures 17 to 19 In a semiconductor device according to an example embodiment, an angle formed between an extension line of an upper surface of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100 may be different from an angle formed between an extension line of a lower surface of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100.

[0110] In some embodiments, Fig.18As shown, an angle formed between an extension line of the second surface 126LS of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100 may be greater than an angle formed between an extension line of the third surface 126US of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100. In this case, the germanium concentration in the first oxide pattern 122 may be lower than the germanium concentration in the second oxide pattern 124. The third surface 126US of the second semiconductor pattern 126 may be parallel to the upper surface of the substrate 100. In some embodiments, the third surface 126US of the second semiconductor pattern 126 may be inclined at an acute angle relative to the upper surface of the substrate 100.

[0111] In this case, in some embodiments, the shortest (eg, minimum) distance D1 between the first semiconductor pattern 110 and the second semiconductor pattern 126 may be smaller than the shortest (eg, minimum) distance D2 between the second semiconductor pattern 126 and the third semiconductor pattern 130 .

[0112] In some embodiments, Fig.19 As shown, an angle formed between an extension line of the second surface 126LS of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100 may be smaller than an angle formed between an extension line of the third surface 126US of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100. In this case, the germanium concentration in the first oxide pattern 122 may be greater than the germanium concentration in the second oxide pattern 124. The third surface 126US of the second semiconductor pattern 126 may be parallel to the upper surface of the substrate 100. In some embodiments, the third surface 126US of the second semiconductor pattern 126 may be inclined at an acute angle relative to the upper surface of the substrate 100.

[0113] In this case, in some embodiments, the shortest (eg, minimum) distance D1 between the first semiconductor pattern 110 and the second semiconductor pattern 126 may be greater than the shortest (eg, minimum) distance D2 between the second semiconductor pattern 126 and the third semiconductor pattern 130 .

[0114] In some embodiments, an angle formed between an extension line of the first surface 110US of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100 may be substantially the same as an angle formed between an extension line of the second surface 126LS of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100. Therefore, a profile of the first surface 110US of the first semiconductor pattern 110 and a profile of the second surface 126LS of the second semiconductor pattern 126 may be symmetrical to each other with respect to the first oxide pattern 122.

[0115] In some embodiments, an angle formed between an extension line of the fourth surface 130LS of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100 may be substantially the same as an angle formed between an extension line of the third surface 126US of the second semiconductor pattern 126 and a line parallel to the upper surface of the substrate 100. Therefore, a profile of the third surface 126US of the second semiconductor pattern 126 and a profile of the fourth surface 130LS of the third semiconductor pattern 130 may be symmetrical to each other with respect to the second oxide pattern 124.

[0116] Figure 20 to Figure 22 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.21 is along Fig. 20 A cross-sectional view taken along line EE. Fig. 22 is along Fig. 20 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0117] Reference Figure 20 to Figure 22 In the semiconductor device according to example embodiments, the first oxide pattern 122 and the second oxide pattern 124 may be sequentially arranged in the first direction X. An angle formed between an extension line of each of the upper and lower surfaces of the first oxide pattern 122 and a line parallel to the upper surface of the substrate 100 may be different from an angle formed between an extension line of each of the upper and lower surfaces of the second oxide pattern 124 and a line parallel to the upper surface of the substrate 100.

[0118] For example, the upper surface of the first semiconductor pattern 110 in contact with the first oxide pattern 122 may include a fifth surface 110US1. The lower surface of the third semiconductor pattern 130 in contact with the first oxide pattern 122 may include a sixth surface 130LS1. The upper surface of the first semiconductor pattern 110 in contact with the second oxide pattern 124 may have a seventh surface 110US2. The lower surface of the third semiconductor pattern 130 in contact with the second oxide pattern 124 may include an eighth surface 130LS2.

[0119] A third angle θ3 formed between an extension line of the fifth surface 110US1 of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100 may be smaller than a fifth angle θ5 formed between an extension line of the seventh surface 110US2 of the first semiconductor pattern 110 and a line parallel to the upper surface of the substrate 100. A fourth angle θ4 formed between an extension line of the sixth surface 130LS1 of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100 may be smaller than a sixth angle θ6 formed between an extension line of the eighth surface 130LS2 of the third semiconductor pattern 130 and a line parallel to the upper surface of the substrate 100.

[0120] In this case, the first germanium concentration in the first oxide pattern 122 may be greater than the second germanium concentration in the second oxide pattern 124. In some embodiments, as shown, the fifth surface 110US1 of the first semiconductor pattern 110 and the sixth surface 130LS1 of the third semiconductor pattern 130 may be inclined at an acute angle relative to the upper surface of the substrate 100. In some embodiments, the fifth surface 110US1 of the first semiconductor pattern 110 and the sixth surface 130LS1 of the third semiconductor pattern 130 may be parallel to the upper surface of the substrate 100.

[0121] In some embodiments, the third angle θ3 may be substantially the same as the fourth angle θ4. The profile of the fifth surface 110US1 of the first semiconductor pattern 110 and the profile of the sixth surface 130LS1 of the third semiconductor pattern 130 may be symmetrical to each other with respect to the first oxide pattern 122. In some embodiments, the fifth angle θ5 may be substantially the same as the sixth angle θ6. The profile of the seventh surface 110US2 of the first semiconductor pattern 110 and the profile of the eighth surface 130LS2 of the third semiconductor pattern 130 may be symmetrical to each other with respect to the second oxide pattern 124.

[0122] In some embodiments, when the first germanium concentration in the first oxide pattern 122 and the second germanium concentration in the second oxide pattern 124 are adjusted, the tensile stress applied to the third semiconductor pattern 130 may be adjusted. For example, the tensile stress applied to a portion of the third semiconductor pattern 130 between the first gate electrode 144 and the stress pattern 120 and the tensile stress applied to a portion of the third semiconductor pattern 130 between the second gate electrode 244 and the stress pattern 120 may be adjusted separately.

[0123] Figure 23 to Figure 27 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.24 and Fig.26 is along Fig.23 A cross-sectional view taken along line GG. Fig.25 and Fig. 27 is along Fig.23 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0124] Reference Figure 23 to Figure 27 In the semiconductor device, the substrate 100 may include a base substrate 102 and a buried insulating layer (BOX) 104. The fin structure FS may directly contact an upper surface of the buried insulating layer 104.

[0125] The base substrate 102 may include a semiconductor material. The base substrate 102 may be, for example, a silicon substrate, but is not limited thereto.

[0126] The buried insulating layer 104 may be formed on the base substrate 102. The buried insulating layer 104 may include, for example, silicon oxide, but is not limited thereto.

[0127] In some embodiments, Fig.24 and Fig.25 As shown, the first semiconductor pattern in the first fin structure FS may be omitted (see, for example, Figure 2 Therefore, the lower surface of the stress pattern 120 may directly contact the upper surface of the buried insulating layer 104.

[0128] In some embodiments, Fig.26 and Fig. 27 As shown, the first semiconductor pattern 110 of the first fin structure FS may directly contact the upper surface of the buried insulating layer 104 .

[0129] In some embodiments, the stress pattern 120 may include a first oxide pattern 122 , a second semiconductor pattern 126 , and a second oxide pattern 124 , as described in the above examples.

[0130] Figures 28 to 30 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Fig.29 is along Fig.28 A cross-sectional view taken along line II. Fig.30 is along Fig.28 For convenience of explanation, elements repeated with the above-mentioned examples will be briefly described or omitted.

[0131] Reference Figures 28 to 30 , in a semiconductor device according to example embodiments, a substrate 100 may include a first region I and a second region II. The first region I and the second region II may be spaced apart from each other, or may be connected to each other.

[0132] The first region I and the second region II may be one of a logic region, an SRAM region, and an input / output region. The first region I and the second region II may be regions in which the same function may be performed, or may be regions in which different functions may be performed.

[0133] As an example, the semiconductor device formed in the first region I may be a reference Figures 1 to 5 In some embodiments, the semiconductor device formed in the first region I may be a semiconductor device as described above. Figure 6 to Figure 27 Any of the semiconductor devices described.

[0134] The semiconductor device formed in the second region II of the substrate 100 may include a second fin structure FSA, a third gate structure GS3, and a fourth gate structure GS4.

[0135] The second fin structure FSA may protrude from the substrate 100 . The second fin structure FSA may extend in a fourth direction P parallel to the upper surface of the substrate 100 . The second fin pattern FSA may be a portion of the substrate 100 , or may include an epitaxial layer grown from the substrate 100 .

[0136] The second fin structure FSA may include a semiconductor material, such as silicon or germanium. In some embodiments, the second fin structure FSA may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-III compound semiconductor. In some embodiments, the second fin structure FSA may include substantially the same material as the first semiconductor pattern 110.

[0137] The third gate structure GS3 and the fourth gate structure GS4 may be formed on the second fin structure FSA and the field insulating layer 105. The third gate structure GS3 and the fourth gate structure GS4 may intersect with the second fin structure FSA. For example, the third gate structure GS3 and the fourth gate structure GS4 may be spaced apart from each other in the fourth direction P, and may extend in a fifth direction Q parallel to the upper surface of the substrate 100 and intersecting with the fourth direction P.

[0138] The third gate structure GS3 may include a third gate insulating layer 342 , a third gate electrode 344 , a third gate spacer 346 , a third gate trench GT3 defined by the third gate spacer 346 , and a third capping pattern 348 .

[0139] The fourth gate structure GS4 may include a fourth gate insulating layer 442 , a fourth gate electrode 444 , a fourth gate spacer 446 , a fourth gate trench GT4 defined by the fourth gate spacer 446 , and a fourth capping pattern 448 .

[0140] In some embodiments, different types of transistors may be formed in the first region I and the second region II, respectively. For example, the semiconductor device formed in the first region I may be an NMOS transistor, and the semiconductor device formed in the second region II may be a PMOS transistor. Alternatively, the semiconductor device formed in the first region I may be a PMOS transistor, and the semiconductor device formed in the second region II may be an NMOS transistor. In some embodiments, the same type of transistor may be formed in each of the first region I and the second region II.

[0141] Figure 31 to Figure 37 are views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Fig.31 , Fig.34 and Fig.36 is along Figure 1 A cross-sectional view taken along line AA. Fig.32 , Fig.33 , Fig.35 and Fig.37 is along Figure 1 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0142] Reference Fig.31 and Fig.32 , a preliminary semiconductor pattern FSp including a first semiconductor pattern 110 , a preliminary stress pattern 120 p , and a third semiconductor pattern 130 may be formed on the substrate 100 .

[0143] The first semiconductor pattern 110, the preliminary stress pattern 120p, and the third semiconductor pattern 130 may be sequentially stacked on the substrate 100. In addition, the first semiconductor pattern 110, the preliminary stress pattern 120p, and the third semiconductor pattern 130 may extend in the first direction X.

[0144] The first semiconductor pattern 110 may include a first semiconductor material, for example, silicon (Si).

[0145] The preliminary stress pattern 120p may include a second semiconductor material, for example, a semiconductor material having an oxidation rate faster than that of the first semiconductor material. For example, the preliminary stress pattern 120p may include one of silicon germanium oxide, silicon germanium oxycarbide, and germanium oxide.

[0146] The preliminary stress pattern 120p may include a second semiconductor pattern 126, a fourth semiconductor pattern 122p, and a fifth semiconductor pattern 124p. The second semiconductor pattern 126 may be interposed between the fourth semiconductor pattern 122p and the fifth semiconductor pattern 124p.

[0147] In some embodiments, the fourth semiconductor pattern 122p, the second semiconductor pattern 126, and the fifth semiconductor pattern 124p may be sequentially stacked on the substrate 100. The second semiconductor pattern 126, the fourth semiconductor pattern 122p, and the fifth semiconductor pattern 124p may extend in the first direction X.

[0148] The fourth and fifth semiconductor patterns 122p and 124p may include the second semiconductor material. For example, the fourth and fifth semiconductor patterns 122p and 124p may include at least one of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and germanium (Ge).

[0149] In some embodiments, the second semiconductor pattern 126 may not include germanium (Ge). For example, the second semiconductor pattern 126 may include the first semiconductor material. For example, the second semiconductor pattern 126 may include silicon (Si).

[0150] The third semiconductor pattern 130 may include a third semiconductor material. The third semiconductor material may be a semiconductor material having an oxidation rate slower than that of the second semiconductor material. For example, the third semiconductor pattern 130 may include silicon (Si).

[0151] The first semiconductor pattern 110 , the preliminary stress pattern 120 p , and the third semiconductor pattern 130 may be formed by patterning a plurality of semiconductor patterns sequentially stacked on the substrate 100 using the mask pattern 310 as an etching mask.

[0152] Reference Fig.33 , a field insulating layer 105 may be formed on a sidewall of the preliminary fin structure FSp.

[0153] The field insulating layer 105 may completely cover the sidewalls of the preliminary fin structure FSp.

[0154] The field insulating layer 105 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0155] refer to Fig.34 and Fig.35 , a first fin structure FS including a stress pattern 120 may be formed.

[0156] For example, the fourth and fifth semiconductor patterns 122p and 124p may be oxidized by performing an oxidation process OP. The oxidation process OP may include, for example, a wet oxidation process, but is not limited thereto.

[0157] The fourth semiconductor pattern 122p and the fifth semiconductor pattern 124p including silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge) may be oxidized by performing an oxidation process OP to form a first oxide pattern 122 and a second oxide pattern 124, respectively. However, the first semiconductor pattern 110, the second semiconductor pattern 126, and the third semiconductor pattern 130, each including silicon (Si) having an oxidation rate slower than that of silicon germanium (SiGe), silicon germanium carbide (SiGeC), or germanium (Ge), may not be oxidized by the oxidation process OP. Therefore, the stress pattern 120 including the first oxide pattern 122, the second semiconductor pattern 126, and the second oxide pattern 124 may be formed in the first fin structure FS.

[0158] refer to Fig.36 and Fig.37 , a recess process may be performed on the field insulation layer 105 .

[0159] Thus, the field insulation layer 105 may expose at least a portion of the third semiconductor pattern 130 .

[0160] The height H1 of the upper surface of the field insulation layer 105 relative to the upper surface of the substrate 100 may be higher than the height H2 of the uppermost surface of the stress pattern 120, but the inventive concept is not limited thereto. For example, the height H1 of the upper surface of the field insulation layer 105 relative to the upper surface of the substrate 100 may be lower than the height H2 of the uppermost surface of the stress pattern 120.

[0161] In some embodiments, the mask pattern 310 may be removed during or after the recess process.

[0162] The first gate structure GS1, the second gate structure GS2, the source / drain region 150 and the interlayer insulating layer 160 may be formed on the first fin structure FS. Figure 2 and Figure 3 The semiconductor device.

[0163] Figure 38 to Figure 39 are views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Fig.38 is along Figure 1 A cross-sectional view taken along line AA. Fig.39 is along Figure 1 For convenience of explanation, elements repeated with the above-described examples will be briefly described or omitted.

[0164] Reference Fig.38 and Fig.39 , a preliminary fin structure FSp including a first semiconductor pattern 110 , a preliminary stress pattern 120 p , and a second semiconductor pattern 126 may be formed on the substrate 100 .

[0165] The preliminary stress pattern 120p may include a second semiconductor pattern 126, a fourth semiconductor pattern 122p, and a fifth semiconductor pattern 124p. The second semiconductor pattern 126 may be interposed between the fourth semiconductor pattern 122p and the fifth semiconductor pattern 124p.

[0166] In some embodiments, the fourth semiconductor pattern 122 p , the second semiconductor pattern 126 , and the fifth semiconductor pattern 124 p may be sequentially arranged along the first direction X. The fourth semiconductor pattern 122 p and the fifth semiconductor pattern 124 p may each extend in the first direction X.

[0167] Can be executed and referenced Figure 33 to Figure 37 The first gate structure GS1, the second gate structure 6S2, the source / drain region 150 and the interlayer insulating layer 160 may be formed on the first fin structure FS. Thus, the reference fin structure FS may be manufactured. Fig.10 and Fig.11 A semiconductor device is described.

[0168] Figure 40 to Figure 42 are views illustrating stages in a method of manufacturing a semiconductor device according to example embodiments. Fig.40 is along Fig.12 Cross-sectional view taken along line CC. Fig.41 and Fig.42 is shown along Fig.40 For convenience of explanation, elements repeated with the above-mentioned example will be briefly described or omitted.

[0169] Reference Fig.40 , a preliminary fin structure FSp including the first semiconductor pattern 110 , the preliminary stress pattern 120 p , and the third semiconductor pattern 130 may be formed.

[0170] In some embodiments, the germanium concentration in the preliminary stress pattern 120p may vary with increasing distance from the upper surface of the substrate 100. For example, a fourth scan line P7-P8 intersecting the preliminary stress pattern 120p in the third direction Z may be defined. The germanium concentration in the preliminary stress pattern 120p may vary along the fourth scan line P7-P8.

[0171] For example, Fig.41 As shown, the germanium concentration in the preliminary stress pattern 120p may increase along the fourth scan line P7-P8.

[0172] Next, you can execute the reference Figure 33 to Figure 37 The first gate structure GS1, the second gate structure GS2, the source / drain region 150 and the interlayer insulating layer 160 may be formed on the first fin structure FS. Thus, the reference fin structure FS may be manufactured. Fig.13 and Fig.14 (or Fig.15 and Fig.16 ) described in detail.

[0173] For example, Fig.42 As shown, the germanium concentration in the preliminary stress pattern 120p may decrease along the fourth scan line P7-P8.

[0174] Next, you can execute the reference Figure 33 to Figure 37 The first gate structure GS1, the second gate structure GS2, the source / drain region 150 and the interlayer insulating layer 160 may be formed on the first fin structure FS. Thus, the reference fin structure FS may be manufactured. Fig.15 A semiconductor device is described.

[0175] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as defined in the following claims.

Claims

1. A semiconductor device, comprising: substrate; A fin structure comprising a stress pattern and a semiconductor pattern sequentially stacked on the substrate; a field insulating layer on a portion of the fin structure; as well as a gate electrode on the fin structure, the gate electrode intersecting the fin structure and extending in a first direction, wherein the stress pattern includes a first oxide pattern and a second oxide pattern, the first oxide pattern and the second oxide pattern are spaced apart from each other in a second direction different from the first direction, Wherein, the semiconductor pattern comprises a first semiconductor material, and Each of the first oxide pattern and the second oxide pattern includes an oxide of a second semiconductor material different from the first semiconductor material.

2. The semiconductor device according to claim 1, wherein The first semiconductor material comprises silicon, and The second semiconductor material includes germanium.

3. The semiconductor device according to claim 2, wherein: A first germanium concentration in the first oxide pattern is different from a second germanium concentration in the second oxide pattern.

4. The semiconductor device according to claim 1, in, The semiconductor pattern includes a first semiconductor pattern, and The stress pattern further includes a second semiconductor pattern between the first oxide pattern and the second oxide pattern.

5. The semiconductor device according to claim 4, wherein: The second semiconductor pattern does not contain germanium.

6. The semiconductor device according to claim 1, in, The semiconductor pattern includes a first semiconductor pattern, The fin structure further includes a second semiconductor pattern between the substrate and the stress pattern, and The first oxide pattern and the second oxide pattern are between the second semiconductor pattern and the first semiconductor pattern.

7. The semiconductor device according to claim 1, in, The first direction is parallel to the upper surface of the substrate, and Wherein, the second direction is perpendicular to the upper surface of the substrate.

8. The semiconductor device according to claim 1, wherein The second direction is a longitudinal extension direction of the fin structure.

9. The semiconductor device according to claim 1, in, The substrate comprises: a base substrate comprising a semiconductor material, and a buried insulating layer on the base substrate, and Wherein, the stress pattern directly contacts the buried insulating layer.

10. The semiconductor device according to claim 1, wherein The stress pattern is configured to apply a tensile stress to the semiconductor pattern.

11. The semiconductor device according to claim 1, wherein The semiconductor pattern includes a channel region of an NMOS transistor.

12. The semiconductor device according to claim 1, further comprising: The first source / drain region and the second source / drain region in the semiconductor pattern are respectively at opposite first and second sides of the gate electrode.

13. A semiconductor device comprising: substrate; A fin structure, comprising a stress structure and a first semiconductor region sequentially stacked on the substrate; a field insulating layer on a portion of the fin structure; as well as a gate electrode on the fin structure and the field insulating layer, the gate electrode intersecting the fin structure, Wherein, the stress structure comprises: a first oxide region comprising an oxide of germanium; a second oxide region spaced apart from the first oxide region, the second oxide region comprising an oxide of germanium; and A second semiconductor region is between the first oxide region and the second oxide region, wherein the second semiconductor region does not contain germanium.

14. The semiconductor device according to claim 13, wherein: The first oxide region, the second semiconductor region, and the second oxide region are sequentially stacked on the substrate.

15. The semiconductor device according to claim 13, in, The fin structure extends in a longitudinal direction, and The first oxide region, the second semiconductor region, and the second oxide region are positioned sequentially in the longitudinal direction.

16. The semiconductor device according to claim 13, wherein: The stress structure directly contacts the substrate.

17. A semiconductor device comprising: substrate; A fin structure comprising a stress structure, a first semiconductor region and a second semiconductor region on the substrate, wherein the second semiconductor region is between the substrate and the stress structure; a field insulating layer on the fin structure; as well as a gate electrode on the fin structure, The stress structure includes a first oxide region and a second oxide region separated from each other. wherein the first oxide region and the second oxide region are between the second semiconductor region and the first semiconductor region, wherein the first semiconductor region and the second semiconductor region include corresponding first semiconductor materials, and Each of the first oxide region and the second oxide region includes an oxide of a second semiconductor material different from the first semiconductor material.

18. The semiconductor device according to claim 17, wherein: The first semiconductor material comprises silicon, and The second semiconductor material includes germanium.

19. The semiconductor device according to claim 18, wherein A first germanium concentration in the first oxide region is different from a second germanium concentration in the second oxide region.

20. The semiconductor device according to claim 17, wherein The fin structure further includes a third semiconductor region between the first oxide region and the second oxide region, and Wherein, the third semiconductor region does not contain germanium.

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