Memory device for reducing leakage current

Abstract

A memory device can be provided, comprising: a normal memory cell array including a first magnetoresistance memory cell, the first magnetoresistance memory cell being connected to a first bit line, a first source line, and a first word line, and being configured to receive a selection voltage through the first word line; a monitor memory cell array including a second magnetoresistance memory cell, the second magnetoresistance memory cell being connected to a first signal line and a second signal line, a gate of a cell transistor of the second magnetoresistance memory cell being configured to receive a non-selection voltage; and a body bias generator, which is configured to sense a leakage current flowing through the first signal line, and control a body voltage provided to each of the body of the cell transistor of the first magnetoresistance memory cell and the body of the cell transistor of the second magnetoresistance memory cell based on the leakage current.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0110997 filed on September 17, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts disclosed herein relate to semiconductor devices, and more particularly, to memory devices for reducing leakage current. Background Art

[0004] A memory device may include a memory cell and may store data in the memory cell. A memory device that requires power to store data stored in a memory cell is called a "volatile memory device." A memory device that does not require power to store data stored in a memory cell is called a "non-volatile memory device."

[0005] The memory device may include a magnetic random access memory (MRAM) as one of the nonvolatile memory devices. MRAM supports relatively high-speed write operations and high-speed read operations and operates with relatively low power, and is therefore very useful for data storage applications. MRAM stores data in a variable resistance element of a memory cell implemented with a magnetoresistive element.

[0006] An MRAM memory cell connected to a specific bit line can be selected to read the data stored therein, and the data stored in the selected memory cell can be output. Leakage current can flow out of an unselected memory cell in the memory cell connected to the specific bit line. When the leakage current increases, errors about the data output from the selected memory cell may occur. For example, the leakage current increases with increasing temperature, and therefore, the probability of errors about the output data may increase. Summary of the invention

[0007] Some example embodiments of the inventive concepts provide a memory device that may reduce a probability of an error occurring with respect to output data by adjusting a leakage current flowing in a memory cell.

[0008] According to example embodiments, a memory device may include: a normal memory cell array including a first magnetoresistance memory cell, the first magnetoresistance memory cell being connected to a first bit line, a first source line, and a first word line, the first magnetoresistance memory cell being configured to receive a selection voltage through the first word line; a monitor memory cell array including a second magnetoresistance memory cell, the second magnetoresistance memory cell being connected to a first signal line and a second signal line, a gate of a cell transistor of the second magnetoresistance memory cell being configured to receive a non-selection voltage; and a body bias generator configured to sense a leakage current flowing through the first signal line and to control a body voltage provided to each of a body of a cell transistor of the first magnetoresistance memory cell and a body of a cell transistor of the second magnetoresistance memory cell based on the leakage current.

[0009] According to an example embodiment, a memory device may include: a normal memory cell array including a first magnetoresistance memory cell, the first magnetoresistance memory cell is connected to a first bit line, a first source line and a first word line, the first magnetoresistance memory cell is configured to receive a selection voltage through the first word line; a monitor memory cell array including a second magnetoresistance memory cell, the second magnetoresistance memory cell is connected to a first signal line and a second signal line, the gate of a cell transistor of the second magnetoresistance memory cell is configured to receive a non-selection voltage; a leakage current generator, which is configured to sense a leakage current flowing through the first signal line; and a negative charge pump, which is configured to reduce a body voltage provided to each of a body of a cell transistor of the first magnetoresistance memory cell and a body of a cell transistor of the second magnetoresistance memory cell when the leakage current is greater than a threshold value.

[0010] According to example embodiments, a memory device may include: a normal memory cell array including normal magnetoresistance memory cells connected to a first bit line, a first source line, and a corresponding word line among a plurality of word lines; a monitor memory cell array including monitor magnetoresistance memory cells connected to a first signal line, a second signal line, and a third signal line, a gate of a cell transistor of the monitor magnetoresistance memory cell being connected to the third signal line and being configured to receive a non-selection voltage through the third signal line; and a body bias generator configured to sense a leakage current flowing through the first signal line and to control a body voltage based on the leakage current, the body voltage being provided to a body of each of the cell transistors included in the normal magnetoresistance memory cell and the monitor magnetoresistance memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above or other objects and features of the present inventive concept will become apparent by describing in detail some example embodiments of the present inventive concept with reference to the attached drawings.

[0012] Figure 1is a block diagram illustrating a memory device according to an example embodiment of the inventive concept.

[0013] Figure 2 It is shown Figure 1 A circuit diagram of transistors included in a functional block.

[0014] Figure 3A and Figure 3B It is shown Figure 2 A cross-sectional view of the transistor form is shown in FIG.

[0015] Figure 4 It is shown Figure 1 A block diagram of a memory device.

[0016] Figure 5 It is shown Figure 4 A diagram of an example of a memory cell of a memory cell array.

[0017] Figure 6 It is shown Figure 4 A circuit diagram of a memory device.

[0018] Figure 7 It is shown Figure 6 FIG. 1 is a diagram of an example of a read operation of a memory device.

[0019] Figure 8 It shows that according to Figure 6 A diagram of the operation of the body bias generator varying the signal.

[0020] Fig. 9 It is shown Figure 6 FIG. 1 is a diagram of an example of a data input / output circuit and a leakage current generator included in a memory device of FIG.

[0021] Fig.10 It is shown Figure 6 FIG. 1 is a diagram of another example of a data input / output circuit and a leakage current generator included in a memory device of FIG.

[0022] Fig.11 It is shown Figure 6 A circuit diagram of an example of a clamping circuit.

[0023] Fig.12 is a flowchart illustrating an operation of a memory device according to an example embodiment of the inventive concept.

[0024] Fig.13 is a block diagram illustrating an electronic system according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Hereinafter, some exemplary embodiments of the inventive concept may be described in detail and clearly so that those having ordinary skill in the art can easily implement the inventive concept.

[0026] Although the terms "same" or "equal" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when an element or value is referred to as being the same as another element or value, it should be understood that the element or value is the same as the other element or value within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0027] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) above and below the stated numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape is not required to be exact, but the latitude of the shape is within the scope of the present disclosure.

[0028] Figure 1 1 is a block diagram illustrating a memory device 1000 according to an example embodiment of the inventive concept. The memory device 1000 may include a volatile memory device (e.g., a dynamic random access memory (DRAM) or a static RAM (SRAM)). The memory device 1000 may include a nonvolatile memory device (e.g., a flash memory device, a magnetic RAM (MRAM) device, a phase change RAM (PRAM) device, a ferroelectric RAM (FRAM) device, or a resistive RAM (RRAM) device).

[0029] Reference Figure 1 , the memory device 1000 may include a functional block 100 and a body bias generator 200. The functional block 100 may perform various functions according to data and / or control signals provided to the memory device 1000. The functional block 100 may include circuits that perform various functions. For example, the functional block 100 may include a memory cell array 110 that stores data.

[0030] The memory cell array 110 may include a normal memory cell array 111 and a monitor memory cell array 112. The normal memory cell array 111 may include memory cells storing data. The functional block 100 may output the data stored in the memory cells of the normal memory cell array 111. The monitor memory cell array 112 may include memory cells constructed to be the same as the memory cells of the normal memory cell array 111. The memory cells of the monitor memory cell array 112 may not store data. The states of the memory cells of the normal memory cell array 111 may be sensed by the monitor memory cell array 112. For example, the leakage current flowing in the normal memory cell array 111 may be sensed by the monitor memory cell array 112.

[0031] Functional block 100 may include a plurality of transistors. A transistor may be one of the smallest logic units constituting functional block 100. For example, the transistor may include a p-channel metal oxide semiconductor (PMOS) transistor or an n-channel metal oxide semiconductor (NMOS) transistor.

[0032] The body bias generator 200 may provide a leakage current ILK to the functional block 100. The leakage current ILK may be a current flowing through some transistors that are in an off state according to the operation of the functional block 100. That is, the body bias generator 200 may allow the leakage current ILK to flow through some transistors of the functional block 100. For example, the body bias generator 200 may apply a specific voltage to some transistors of the functional block 100. In the case where the specific voltage is applied, the leakage current ILK may flow through some transistors.

[0033] In example embodiments, the leakage current may flow to the transistors of the normal memory cell array 111 according to the operation of the functional block 100. The body bias generator 200 may provide the monitor memory cell array 112 with a leakage current ILK that is the same as or substantially the same as the leakage current flowing in the normal memory cell array 111. In this case, the body bias generator 200 may sense the leakage current flowing in the normal memory cell array 111 by providing the leakage current ILK to the monitor memory cell array 112.

[0034] The body bias generator 200 may provide the functional block 100 with a body voltage VBB for the functional block 100. The body voltage VBB may be a voltage provided to the body of a transistor in the functional block 100. The body bias generator 200 may adjust the body voltage VBB based on the leakage current ILK provided to the functional block 100. In an example embodiment, the body bias generator 200 may reduce the body voltage VBB in the event that the leakage current ILK increases.

[0035] When the body voltage VBB is adjusted, the leakage current flowing in the normal memory cell array 111 can be adjusted. For example, when the body voltage VBB is reduced, the leakage current flowing in the normal memory cell array 111 can be reduced. Since the leakage current ILK is the same or substantially the same as the leakage current flowing in the normal memory cell array 111, the leakage current ILK can also be adjusted as the body voltage VBB is adjusted.

[0036] When leakage current flowing in the normal memory cell array 111 increases according to the operation of the functional block 100, the operation of the functional block 100 may not be normally performed. For example, when data stored in the normal memory cell array 111 is read, a read error may increase.

[0037] When the bulk voltage VBB is adjusted based on the leakage current ILK, the leakage current of the normal memory cell array 111 is not increased. Therefore, the operation of the functional block 100 can be performed normally. For example, when performing an operation of reading data stored in the normal memory cell array 111, read errors can be reduced.

[0038] As described above, the body bias generator 200 may adjust the body voltage VBB based on the leakage current ILK provided to the functional block 100. This may mean that the memory device 1000 may be normally operated, and the reliability of the memory device 1000 may be improved.

[0039] Figure 2 It is shown Figure 1 A circuit diagram of transistors included in the functional block 100. Figure 2 , the functional block 100 may include a plurality of PMOS transistors 10 and a plurality of NMOS transistors 20. Figure 2 Although not shown in the figure, various elements may be additionally included in the functional block 100 .

[0040] A first terminal (e.g., source or drain) of each PMOS transistor 10 may be connected to a signal line or a first terminal (e.g., source or drain) of any other transistor, and various voltages may be provided to the first terminal of each PMOS transistor 10. A gate of each PMOS transistor 10 may be connected to a signal line or a terminal of any other transistor, and various voltages may be provided to the gate of each PMOS transistor 10. Since a body of each PMOS transistor 10 is connected to a signal line to which a PMOS body voltage VBBP is provided, the PMOS body voltage VBBP provided from the body bias generator 200 may be provided to the body of each PMOS transistor 10.

[0041] Likewise, a first terminal (e.g., source or drain) of each NMOS transistor 20 may be connected to a signal line or a first terminal (e.g., source or drain) of any other transistor, and various voltages may be provided to the first terminal of each NMOS transistor 20. A gate of each NMOS transistor 20 may be connected to a signal line or a terminal of any other transistor, and various voltages may be provided to the gate of each NMOS transistor 20. Since a body of each NMOS transistor 20 may be connected to a signal line to which an NMOS body voltage VBBN is provided, an NMOS body voltage VBBN provided from a body bias generator 200 may be provided to a body of each NMOS transistor 20.

[0042] As described above, the PMOS body voltage VBBP and the NMOS body voltage VBBN provided from the body bias generator 200 may be provided to the body of each PMOS transistor 10 and the body of each NMOS transistor 20, respectively. Figure 1 The body voltage VBB provided by the body bias generator 200 may include a PMOS body voltage VBBP and an NMOS body voltage VBBN.

[0043] Figure 3A and Figure 3B It is shown Figure 2 A cross-sectional view of a transistor in the form of a transistor is shown in FIG. Figure 3A shows a cross-sectional view of a PMOS transistor 10, Figure 3B A cross-sectional view of an NMOS transistor 20 is shown.

[0044] Reference Figure 3A , for the purpose of forming the PMOS transistor 10, an N well 11 may be formed in a P-type substrate P-Sub. The N well 11 may be formed by implanting an N-type dopant into the P-type substrate P-Sub. P+ doped regions 12 and 13 for the drain and source of the PMOS transistor 10 are formed in the N well 11. An N+ doped region 14 for providing a PMOS body voltage VBBP is formed in the N well 11. Next, a gate insulating layer 15 and a gate electrode 16 are stacked sequentially. The gate insulating layer 15 may be formed of an oxide layer, a nitride layer, or a stacked layer in which an oxide layer and a nitride layer are stacked. The gate electrode 16 may be formed of a polysilicon layer or a metal layer doped with impurity ions (e.g., phosphorus (P), arsenic (As), or boron (B)).

[0045] In the structure of the PMOS transistor 10, a gate voltage may be applied to a gate electrode 16 of the PMOS transistor 10, and a drain voltage and a source voltage may be applied to P+ doped regions 12 and 13 serving as drain and source terminals, respectively. In addition, a PMOS body voltage VBBP may be applied to an N+ doped region 14 serving as a body electrode of the PMOS transistor 10.

[0046] Reference Figure 3B For the purpose of forming the NMOS transistor 20, N+ doped regions 21 and 22 for drain and source may be formed in the P-type substrate P-Sub. A P+ doped region 23 for providing the NMOS body voltage VBBN is formed in the P-type substrate P-Sub. Next, a gate insulating layer 24 and a gate electrode 25 are sequentially stacked.

[0047] In the structure of the NMOS transistor 20, a gate voltage may be applied to a gate electrode 25 of the NMOS transistor 20, and a drain voltage and a source voltage may be applied to N+ doped regions 21 and 22 serving as drain and source terminals, respectively. In addition, an NMOS body voltage VBBN may be applied to a P+ doped region 23 serving as a body electrode of the NMOS transistor 20.

[0048] As described above, the body voltage VBB provided from the body bias generator 200 may be provided to the body of the PMOS transistor 10 through the N+ doped region 14, and to the body of the NMOS transistor 20 through the P+ doped region 23. The body bias generator 200 may adjust the body voltage VBB, thereby adjusting the threshold voltage Vth of the PMOS transistor 10 and the NMOS transistor 20. The leakage current flowing through the PMOS transistor 10 and the NMOS transistor 20 may vary with the threshold voltage Vth of the PMOS transistor 10 and the NMOS transistor 20. Therefore, in the case of adjusting the body voltage VBB, the leakage current flowing through the PMOS transistor 10 and the NMOS transistor 20 may be adjusted. For example, in the case of reducing the body voltage VBB, the threshold voltage Vth of the PMOS transistor 10 and the NMOS transistor 20 may be increased. In this case, the leakage current flowing through the PMOS transistor 10 and the NMOS transistor 20 may be reduced.

[0049] Figure 4 It is shown Figure 1 A block diagram of a memory device 1000 is shown. Figure 4 , the memory device 1000 may include a memory cell array 110, an address decoder 120, a data input / output circuit 130, a control logic 140, and a body bias generator 200. The memory cell array 110, the address decoder 120, the data input / output (I / O) circuit 130, and the control logic 140 may be included in the functional block 100.

[0050] The memory cell array 110 may include a normal memory cell array 111 and a monitor memory cell array 112. The normal memory cell array 111 may include memory cells MC. The memory cells MC may be connected to source lines SL1 to SLn (n is a positive integer), bit lines BL1 to BLn, and word lines WL1 to WLm (m is a positive integer). The memory cells MC may be arranged in a matrix of multiple rows and columns. Each row of memory cells MC may correspond to word lines WL1 to WLm, respectively. Each column of memory cells MC may correspond to source lines SL1 to SLn, respectively, and may correspond to bit lines BL1 to BLn, respectively.

[0051] The monitor memory cell array 112 includes monitor memory cells MMC. The monitor memory cells MMC may be implemented as the same as the memory cells MC of the normal memory cell array 111. For example, each of the memory cells MC and the monitor memory cells MMC may include a variable resistance element whose resistance value is variable. That is, the memory cells MC and the monitor memory cells MMC may be implemented with resistive memory cells.

[0052] The monitor memory cell MMC may be arranged in a column. The monitor memory cell MMC is connected to a first signal line ML1, a second signal line ML2, and a third signal line ML3. The first signal line ML1 may be connected to a body bias generator 200. A ground voltage VSS may be applied to the second signal line ML2 and the third signal line ML3. However, the inventive concept is not limited thereto. For example, a voltage different from the ground voltage VSS may be applied to the second signal line ML2 and the third signal line ML3.

[0053] The address decoder 120 may control voltages of the word lines WL1 to WLm under the control of the control logic 140. For example, the address decoder 120 may apply a selection voltage for reading or writing to a selected word line, and may apply a non-selection voltage for inhibiting reading or writing to an unselected word line.

[0054] The data input / output circuit 130 is connected to the source lines SL1 to SLn and the bit lines BL1 to BLn. Under the control of the control logic 140, the data input / output circuit 130 can write data to the memory cell MC by using the source lines SL1 to SLn and the bit lines BL1 to BLn. The data input / output circuit 130 can write data to the selected memory cell MC. For example, the data input / output circuit 130 can provide a write voltage to one of the source line and the bit line connected to the selected memory cell MC, and can provide a low voltage (e.g., a ground voltage VSS) to the other of the source line and the bit line connected to the selected memory cell MC.

[0055] Under the control of the control logic 140, the data input / output circuit 130 may output the data stored in the memory cell MC by using the source lines SL1 to SLn and the bit lines BL1 to BLn. The data input / output circuit 130 may output the data stored in the selected memory cell MC. For example, the data input / output circuit 130 may provide a read voltage to one of the source line and the bit line connected to the selected memory cell MC, and may provide a low voltage (e.g., a ground voltage VSS) to the other of the source line and the bit line.

[0056] The control logic 140 may receive a control signal and an address from an external device (eg, a memory controller) and may control the address decoder 120 and the data input / output circuit 130 in response to the control signal and the address, thereby performing a write operation or a read operation.

[0057] The body bias generator 200 may provide a leakage current ILK to the monitor memory cell array 112. The leakage current ILK may be the same or substantially the same as a leakage current flowing through the memory cell MC of the normal memory cell array 111 in a write operation or a read operation. The leakage current ILK may be distributed to the corresponding monitor memory cell MMC through the first signal line ML1. The body bias generator 200 may adjust the body voltage VBB based on the leakage current ILK. The adjusted body voltage VBB may be provided to the transistor of the functional block 100.

[0058] For example, in a read operation associated with a selected memory cell MC connected to the first bit line BL1, the first source line SL1, and the first word line WL1, a selection voltage may be applied to the first word line WL1. A read voltage may be applied to one of the first bit line BL1 and the first source line SL1, and a ground voltage VSS may be applied to the other of the first bit line BL1 and the first source line SL1. As the read voltage is applied to the first bit line BL1 or the first source line SL1, a read current may flow in the selected memory cell MC. A leakage current may flow in the remaining unselected memory cells MC connected between the first bit line BL1 and the first source line SL1. The body bias generator 200 may provide the monitor memory cell array 112 with a leakage current ILK that is the same or substantially the same as the leakage current flowing in the remaining unselected memory cells MC. The body bias generator 200 may apply a specific voltage to the first signal line ML1 for providing the leakage current ILK. The specific voltage may be the same as the read voltage applied to one of the first bit line BL1 and the first source line SL1. When the specific voltage is applied to the first signal line ML1, a leakage current ILK may flow. The body bias generator 200 may adjust the body voltage VBB based on the leakage current ILK.

[0059] When the bulk voltage VBB is appropriately adjusted, leakage current flowing in the memory cell array 110 can be reduced. Therefore, in a read operation or a write operation, data errors that may occur when a read current or a write current is reduced due to leakage current can be reduced.

[0060] Figure 5 It is shown Figure 4 FIG. 1 is a diagram showing an example of a memory cell of a memory cell array 110. A memory cell MC of a normal memory cell array 111 is shown in FIG. Figure 5 The memory cell MC may include a variable resistance element VR implemented in a magnetic tunnel junction (MTJ) structure and a cell transistor TR. A first end of the variable resistance element VR may be connected to a bit line BL, and a second end of the variable resistance element VR may be connected to a first end of the cell transistor TR. A second end of the cell transistor TR may be connected to a source line SL. A gate of the cell transistor TR may be connected to a word line WL. For example, the cell transistor TR may be implemented with a PMOS transistor or an NMOS transistor.

[0061] The variable resistance element VR includes a pinned layer PL, a tunnel layer TL, and a free layer FL. The pinned layer PL has a fixed magnetization direction. The magnetization direction of the free layer FL can be changed according to the voltage (or current) applied to the variable resistance element VR.

[0062] The resistance value of the variable resistance element VR can be changed according to whether the magnetization direction of the free layer FL is parallel to the magnetization direction of the pinned layer PL or whether it is anti-parallel to the magnetization direction of the pinned layer PL. The variable resistance element VR can store data according to the magnitude of the resistance value of the variable resistance element VR. For example, when the variable resistance element VR is in a low resistance state, the data of the memory cell MC can be defined as a low value. When the variable resistance element VR is in a high resistance state, the data of the memory cell MC can be defined as a high value.

[0063] Only the memory cells MC of the normal memory cell array 111 are shown in Figure 5 In the embodiment, the monitor memory cell MMC of the monitor memory cell array 112 may also include a variable resistance element VR and a cell transistor TR like the memory cell MC.

[0064] As described above, the memory device 1000 may include memory cells MC and MMC each including a variable resistance element VR and a cell transistor TR. That is, the memory device 1000 may be implemented with an MRAM. However, the inventive concept is not limited thereto. For example, the memory device 1000 may be implemented with various types of memories. Hereinafter, for ease of description, it is assumed that the memory device 1000 is an MRAM.

[0065] Figure 6 It is shown Figure 4 1 is a circuit diagram of a memory device 1000. For example, Figure 6 The memory device 1000 is formed of an MRAM, and only a circuit used in a read operation is shown. However, the inventive concept is not limited thereto. For example, the inventive concept may also be applied to a write operation.

[0066] Reference Figure 6 , the memory device 1000 may include a normal memory cell array 111 , a monitor memory cell array 112 , a reference memory cell array 113 , a data input / output circuit 130 , and a body bias generator 200 . Figure 6 The normal memory cell array 111, the reference memory cell array 113, and the data input / output circuit 130 shown in FIG. 1 may be included in a single input / output block. The memory device 1000 may write or output data through the input / output block. In this way, the data input / output circuit 130 may include a sense amplifier (SA) 131 for outputting a piece of data. Although Figure 6 Although not shown in FIG. 1 , the memory device 1000 may include a plurality of input / output blocks.

[0067] The normal memory cell array 111 may include a plurality of memory cells MC. Each memory cell MC may include a cell transistor TR and a variable resistance element VR implemented in an MTJ structure. The first end of the cell transistor TR may be connected to a specific source line, and the second end of the cell transistor TR may be connected to the first end of the variable resistance element VR. The gate of the cell transistor TR may be connected to a specific word line. The second end of the variable resistance element VR may be connected to a specific bit line. In the operation of the memory device 1000, a ground voltage VSS may be applied to a specific bit line, and a selection voltage or a non-selection voltage may be applied to a specific word line. The selection voltage may be a high voltage that can turn on the cell transistor TR. The non-selection voltage may be a low voltage that can turn off the cell transistor TR. For example, the selection voltage may be a power supply voltage VDD, and the non-selection voltage may be a ground voltage VSS. For example, the selection voltage may be applied to the word line to which the selected memory cell MC is connected, and the ground voltage VSS may be applied to the word line to which the unselected memory cell MC is connected.

[0068] The monitor memory cell array 112 includes a plurality of monitor memory cells MMC. Each monitor memory cell MMC may include a cell transistor TR and a variable resistance element VR implemented in an MTJ structure. The first end of the cell transistor TR may be connected to the first signal line ML1, and the second end of the cell transistor TR may be connected to the first end of the variable resistance element VR. The gate of the cell transistor TR may be connected to the third signal line ML3. The second end of the variable resistance element VR may be connected to the second signal line ML2. In this case, a ground voltage VSS may be applied to the second signal line ML2 and the third signal line ML3. That is, the voltage applied to the second signal line ML2 may be the same as the voltage applied to the specific word line, and the voltage applied to the third signal line ML3 may be the same as the non-select voltage applied to the specific word line. Figure 6 , the voltage applied to the second signal line ML2 and the third signal line ML3 is the ground voltage VSS, but the inventive concept is not limited thereto. The voltage applied to the second signal line ML2 and the third signal line ML3 may vary with the voltage applied to the specific bit line and the non-select voltage applied to the specific word line.

[0069] In this way, the monitor memory cell array 112 may be constructed to be the same as one column of the normal memory cell array 111. In addition, the voltage applied to the monitor memory cell MMC may be the same as the voltage applied to the unselected memory cells MC of the normal memory cell array 111, and thus the monitor memory cell MMC may operate the same or substantially the same as the unselected memory cells MC. For example, the leakage current flowing in the unselected memory cells MC may be the same or substantially the same as the leakage current ILK flowing in the monitor memory cell MMC.

[0070] The reference memory cell array 113 may include a plurality of reference memory cells RMC. Each reference memory cell RMC may include a cell transistor TR, but may not include a variable resistance element VR. In some example embodiments, even if the reference memory cell RMC includes a variable resistance element VR, the variable resistance element VR may be in a short circuit state. A first end of the cell transistor TR is connected to a reference bit line RBL, and a second end of the cell transistor TR is connected to a reference source line RSL. A gate of the cell transistor TR is connected to a specific word line.

[0071] The data input / output circuit 130 may include first to seventh switches s1 to s7, a reference resistor Rref, and a sense amplifier 131. The data input / output circuit 130 may further include switches connected to the bit lines BL2 to BLn-1 and the source lines SL2 to SLn-1. The first to seventh switches s1 to s7 may be closed or opened according to a read operation of the data input / output circuit 130. For example, in a read operation associated with a selected memory cell MC connected to the first bit line BL1 and the first source line SL1, the first switch s1, the second switch s2, the third switch s3, the fourth switch s4, and the seventh switch s7 may be closed, and the remaining switches s5 and s6 may be opened.

[0072] In a read operation, as the first switch s1 and the second switch s2 are closed, a reference signal SIREF may be provided to the sense amplifier 131. The reference signal SIREF may be a voltage or a current output according to an operation of the reference memory cell array 113. As the seventh switch s7 is closed, a ground voltage VSS may be applied to one of the bit lines BL1 to BLn.

[0073] The reference signal SIREF outputted by the reference memory cell array 113 may be determined by the reference resistor Rref. That is, the voltage or current provided to the sense amplifier 131 may vary with the value of the reference resistor Rref. For example, the reference resistor Rref may have a resistance value of the variable resistance element VR corresponding to a low value or a resistance value of the variable resistance element VR corresponding to a high value.

[0074] The sense amplifier 131 may receive a reference signal SIREF provided through a reference source line RSL and an input signal SIIN provided through one of the source lines SL1 to SLn. The sense amplifier 131 may amplify the difference between the received signals SIREF and SIIN, and may output the amplified signal. The reference signal SIREF may have a fixed value determined according to the reference resistor Rref. The input signal SIIN may have a value that changes with the resistance value of the variable resistance element VR (e.g., with the data stored in the memory cell MC). In this way, the signal output from the sense amplifier 131 may change with the input signal SIIN. The data stored in the memory cell MC may be determined by the signal output from the sense amplifier 131.

[0075] As described above, in a read operation, the reference memory cell array 113 may output a reference signal SIREF for determining data stored in the normal memory cell array 111 .

[0076] The body bias generator 200 may include a leakage current generator 210, a pump enable circuit 220, a negative charge pump 230, and a clamp circuit 240. The leakage current generator 210 may provide a leakage current ILK to the monitor memory cell array 112 and the pump enable circuit 220. The leakage current generator 210 may provide the leakage current ILK to the monitor memory cell array 112 through the first signal line ML1. The provided leakage current ILK may flow to the monitor memory cell MMC.

[0077] In an example embodiment, the leakage current generator 210 may apply a voltage that is the same as or substantially the same as a voltage of the first node no1 to the first signal line ML1. The first node no1 may be an output node (or an input node) of the normal memory cell array 111. For example, the voltage of the first node no1 may be a read voltage applied to the normal memory cell array 111. In the case where a voltage that is the same as or substantially the same as the voltage of the first node no1 is applied to the first signal line ML1, a leakage current ILK that is the same as or substantially the same as a leakage current flowing to the normal memory cell array 111 may flow to the monitor memory cell array 112. Fig.10 and Fig.11 The operation of the leakage current generator 210 is described in detail.

[0078] The pump enable circuit 220 may determine whether the leakage current ILK is greater than a threshold value. The pump enable circuit 220 may provide an enable signal EN to the negative charge pump 230 according to the result of the determination. For example, in the case where the leakage current ILK is greater than the threshold value, the enable signal EN may be provided to the negative charge pump 230. In the case where the leakage current ILK is not greater than the threshold value, the enable signal EN may not be output.

[0079] The pump enable circuit 220 may include a comparator 221 and a variable resistor 222. The comparator 221 may compare a threshold voltage VTR with a leakage voltage VDET determined based on the leakage current ILK. When the leakage voltage VDET is greater than the threshold voltage VTR, the comparator 221 may output an enable signal EN. The leakage voltage VDET may be determined based on the leakage current ILK and the variable resistor 222. The leakage voltage VDET output to the comparator 221 may be adjusted as the variable resistor 222 is adjusted. In this way, the output of the enable signal EN may be controlled as the variable resistor 222 is adjusted.

[0080] The negative charge pump 230 may receive an enable signal EN. The negative charge pump 230 may reduce the bulk voltage VBB in response to the enable signal EN. For example, when the negative charge pump 230 operates, the bulk voltage VBB may become smaller than the ground voltage VSS.

[0081] The clamp circuit 240 can sense the bulk voltage VBB. The clamp circuit 240 can clamp the bulk voltage VBB to a desired (or alternatively, a preset) voltage so that the bulk voltage VBB is not higher than the desired (or alternatively, a preset) voltage. For example, the clamp circuit 240 can sense that the bulk voltage VBB is higher than the ground voltage VSS and can clamp the bulk voltage VBB to the ground voltage VSS. Fig.12 The operation of the clamp circuit 240 is described in detail.

[0082] As described above, the memory device 1000 may include the monitor memory cell array 112 configured the same as the normal memory cell array 111. The memory device 1000 may apply the same or substantially the same voltage as the voltage (e.g., read voltage) applied to the normal memory cell array 111 to the monitor memory cell array 112 through the body bias generator 200. As such, the same or substantially the same leakage current ILK as the leakage current flowing in the normal memory cell array 111 may be provided to the monitor memory cell array 112. In this case, the leakage current ILK may be sensed by the memory device 1000. The memory device 1000 may adjust the body voltage VBB based on the leakage current ILK.

[0083] Figure 6 1 and 2 , the sense amplifier 131 is shown as being connected to the reference source line RSL and the source lines SL1 to SLn, but the inventive concept is not limited thereto. For example, the sense amplifier 131 may be connected to the reference bit line RBL and the bit lines BL1 to BLn. In this case, the ground voltage VSS may be applied to the reference source line RSL and the source lines SL1 to SLn.

[0084] Figure 7 It is shown Figure 6 FIG. 1 is a diagram of an example of a read operation of the memory device 1000. Figure 7 , the memory device 1000 may perform a read operation on the memory cell MC1. In order to output the data stored in the memory cell MC1, the selection voltage VSL may be applied to the second word line WL2 connected to the memory cell MC1. In this way, the cell transistor connected to the second word line WL2 may be turned on. For example, the selection voltage VSL may be 1.8V. The ground voltage VSS may be applied to the remaining word lines WL1 and WL3 to WLm except the second word line WL2. In this case, the cell transistors connected to the word lines WL1 and WL3 to WLm may be turned off. For example, the ground voltage VSS may be 0V.

[0085] In order to output the data stored in the memory cell MC1, the first switch s1 to the fourth switch s4 and the seventh switch s7 may be closed. In this case, the reference source line RSL and the first source line SL1 may be connected to the sense amplifier 131. Voltages (e.g., read voltages) may be applied to the reference source line RSL and the first source line SL1, respectively. In this case, a read current IRD may be provided to the reference source line RSL and the first source line SL1. The reference bit line RBL may be connected to the reference resistor Rref. The read current IRD provided to the reference source line RSL may flow to the reference bit line RBL through the cell transistor TR2 of the reference memory cell RMC1. In addition, the ground voltage VSS may be applied to the first bit line BL1. The read current IRD provided to the first source line SL1 may flow to the bit line BL1 through the cell transistor TR1 of the memory cell MC1.

[0086] The sense amplifier 131 can sense the data stored in the memory cell MC1 based on the reference signal SIREF and the input signal SIIN received according to the flow of the read current IRD. For example, the reference signal SIREF can be determined by multiplying the resistance value of the reference resistor Rref by the read current IRD. The input signal SIIN can be determined by multiplying the resistance value of the variable resistance element VR1 in the memory cell MC1 by the read current IRD. Therefore, the sense amplifier 131 can sense the data stored in the memory cell MC1 according to the difference between the resistance value of the reference resistor Rref and the resistance value of the variable resistance element VR1.

[0087] However, when the temperature rises, the threshold voltage of the cell transistor TR decreases. In this case, a leakage current is generated or increased. Because the memory cell MC of the normal memory cell array 111 includes a variable resistance element VR, the voltage difference between the opposite ends of the memory cell MC (for example, the first node no1 and the second node no2) is greater than the voltage difference between the opposite ends of the reference memory cell RMC (for example, the third node no3 and the fourth node no4). In such a case, the leakage current ILKN of the normal memory cell array 111 is significantly greater than the leakage current of the reference memory cell array 113, and therefore, it can be assumed that the leakage current of the reference memory cell array 113 does not exist, or the leakage current of the reference memory cell array 113 is negligible relative to the leakage current ILKN. For example, as Figure 7As shown in , the remaining current (IRD-ILKN) corresponding to the read current IRD flowing to the first source line SL1 excluding the leakage current ILKN can be provided to the memory cell MC1. However, when the leakage current of the reference memory cell array 113 is negligible, it can be assumed that the entire read current IRD flowing to the reference source line RSL can be provided to the reference memory cell RMC1.

[0088] In this way, when the leakage current ILKN of the normal memory cell array 111 and the leakage current of the reference memory cell array 113 do not match, the difference between the reference signal SIREF input to the sense amplifier 131 and the input signal SIIN changes. Therefore, the signal output from the sense amplifier 131 changes. In this case, an error with respect to the output data may occur.

[0089] The body bias generator 200 may adjust the body voltage VBB based on the leakage current ILK that is the same as or substantially the same as the leakage current ILKN. In the case of adjusting the body voltage VBB, the threshold voltage Vth of the cell transistor TR may be increased, thereby alleviating or preventing the leakage current ILKN from being generated or alleviating or preventing the increase of the leakage current ILKN. For example, even if the temperature rises, the leakage current ILK may be controlled not to increase by adjusting the body voltage VBB. That is, the memory device 1000 may adjust the leakage current ILKN so that a data error does not occur in a read operation.

[0090] Figure 8 It shows that according to Figure 6 FIG. 2 is a diagram of a signal that changes with the operation of the body bias generator 200. Figure 8 Each horizontal axis represents temperature. The enable signal EN, the leakage current ILK, the leakage voltage VDET, and the body voltage VBB that vary with temperature are shown in FIG. Figure 8 middle.

[0091] The leakage current ILK will increase as the temperature rises. The leakage voltage VDET based on the leakage current ILK will also increase as the temperature rises. Even if the leakage current ILK or the leakage voltage VDET increases, the enable signal EN may not be output (for example, the enable signal EN is set to a low value) when the leakage current ILK is not greater than the threshold current ITR or the leakage voltage VDET is not greater than the threshold voltage VTR. In this case, the body voltage VBB can be clamped so that the body voltage VBB is not higher than the ground voltage VSS. Therefore, the body voltage VBB can be fixed to the ground voltage VSS.

[0092] When the temperature rises to the first temperature tp1, the leakage current ILK will be greater than the threshold current ITR, and the leakage voltage VDET will be greater than the threshold voltage VTR. In this case, the enable signal EN can be output. The body bias generator 200 can reduce the body voltage VBB in response to the enable signal EN. The body bias generator 200 can continuously reduce the body voltage VBB while outputting the enable signal EN. Therefore, even if the temperature rises continuously, the leakage current ILK will not be greater than the threshold current ITR, and the leakage voltage VDET will not be greater than the threshold voltage VTR.

[0093] Fig. 9 It is shown Figure 6 FIG. 1 is a diagram showing an example of a data input / output circuit 130 and a leakage current generator 210 included in a memory device 1000 of FIG. Fig. 9 , the data input / output circuit 130 may include a first PMOS transistor P1, a second PMOS transistor P2, an eighth switch s8, a ninth switch s9, and a sense amplifier 131. The first PMOS transistor P1 has a first end to which a power supply voltage VDD is applied and a second end connected to a first end of the eighth switch s8. The second PMOS transistor P2 has a first end to which a power supply voltage VDD is applied and a second end connected to a first end of the ninth switch s9. The second end of the eighth switch s8 is connected to a first node no1, and the second end of the ninth switch s9 is connected to a third node no3. The first node no1 may be an output node (or input node) of the normal memory cell array 111. The third node no3 may be an output node (or input node) of the reference memory cell array 113.

[0094] In a read operation, when the eighth switch s8 and the ninth switch s9 are closed, a read current IRD may be output through the first and second PMOS transistors P1 and P2 based on the power supply voltage VDD. The read current IRD may be provided to the normal memory cell array 111 and the reference memory cell array 113.

[0095] The sense amplifier 131 may sense the input voltage VIN of the first node no1 and the reference voltage VREF of the third node no3. For example, the input voltage VIN may be determined by multiplying the read current IRD by the resistance value of the variable resistance element VR. The reference voltage VREF may be determined by multiplying the read current IRD by the resistance value of the reference resistor Rref. The sense amplifier 131 may amplify the difference between the reference voltage VREF and the input voltage VIN, and may output read data.

[0096] As mentioned above, Fig. 9 The memory device 1000 shown in FIG. 1 may include a sense amplifier 131 using a voltage as an input.

[0097] The leakage current generator 210 may include a voltage replica circuit 211. The voltage replica circuit 211 may generate a first voltage V1 that is the same or substantially the same as a voltage of the first node no1 (eg, input voltage VIN). As the first voltage V1 is applied to the first signal line ML1, the leakage current ILK may be provided to the monitor memory cell array 112.

[0098] The leakage current generator 210 may include third to fifth PMOS transistors P3 to P5, first to third NMOS transistors N1 to N3, and a replica resistor Rmtj. The third PMOS transistor P3 has a first end to which a power supply voltage VDD is applied and a second end connected to the first end of the first NMOS transistor N1. The first end of the first NMOS transistor N1 is connected to a common node of the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2. The second end of the first NMOS transistor N1 is connected to the first end of the third NMOS transistor N3. The second end of the third NMOS transistor N3 is connected to the first end of the replica resistor Rmtj, and the selection voltage VSL is applied to the gate of the third NMOS transistor N3. The ground voltage VSS is applied to the second end of the replica resistor Rmtj. The power supply voltage VDD is applied to the first end of the fourth PMOS transistor P4, and the second end of the fourth PMOS transistor P4 is connected to the first end of the second NMOS transistor N2 and the common node of the gate of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5. The second end of the second NMOS transistor N2 is connected to the first signal line ML1. The power supply voltage VDD is applied to a first terminal of the fifth PMOS transistor P5.

[0099] The third PMOS transistor P3, the first to third NMOS transistors N1 to N3, and the replica resistor Rmtj may constitute a voltage replica circuit 211. In the case where the read current IRD is provided by the third PMOS transistor P3 and the first NMOS transistor N1, the voltage of the first end of the third NMOS transistor N3 (for example, the second end of the first NMOS transistor N1) may be the first voltage V1. The replica resistor Rmtj may have the same resistance value as the resistance value of the variable resistance element VR. For example, the replica resistor Rmtj may have the same resistance value as the resistance value of the variable resistance element VR of the selected memory cell MC. The operation of the replica resistor Rmtj and the third NMOS transistor N3 may be the same or substantially the same as the operation of the selected memory cell MC of the normal memory cell array 111. Therefore, the first voltage V1 may be the same or substantially the same as the voltage of the first node no1.

[0100] The first NMOS transistor N1 and the second NMOS transistor N2 may operate as source followers. In this case, the voltage of the second terminal of the second NMOS transistor N2 may also be the first voltage V1. Therefore, the first voltage V1 may be applied to the first signal line ML1.

[0101] The fourth PMOS transistor P4 and the fifth PMOS transistor P5 can operate as a current mirror. In this case, the same current can be output from each of the fourth PMOS transistor P4 and the fifth PMOS transistor P5. The current flowing through the fourth PMOS transistor P4 can be the same as the current flowing through the second NMOS transistor N2. Therefore, the current output from the fourth PMOS transistor P4 can be the leakage current ILK, and the current output from the fifth PMOS transistor P5 can be the leakage current ILK. Therefore, the leakage current generator 210 can provide the leakage current ILK to the pump enable circuit 220.

[0102] As described above, in the case where the sense amplifier 131 using a voltage as an input is employed, the leakage current generator 210 corresponding to the sense amplifier 131 may be implemented.

[0103] Fig.10 It is shown Figure 6 FIG. 1 is a diagram of another example of a data input / output circuit 130 and a leakage current generator 210 included in a memory device 1000 of FIG. Fig.10 , the memory device 1000 may further include a bias circuit 300. The bias circuit 300 may include a current source 301, a buffer 302, a fourth NMOS transistor N4, and a replica resistor Rmtj. The current source 301 may provide a read current IRD to a common node of a first end and a gate of the fourth NMOS transistor N4. A second end of the fourth NMOS transistor N4 is connected to a first end of the replica resistor Rmtj, and a gate of the fourth NMOS transistor N4 is connected to an input of the buffer 302. A ground voltage VSS is applied to a second end of the replica resistor Rmtj. The replica resistor Rmtj may have a resistance value that is the same as a resistance value of the variable resistance element VR. For example, the replica resistor Rmtj may have a resistance value that is the same as a resistance value of the variable resistance element VR of the selected memory cell MC. In the case where the read current IRD is provided to the first end of the fourth NMOS transistor N4, the second end of the fourth NMOS transistor N4 may be a second voltage V2. In this case, the second voltage V2 may be determined by multiplying the read current IRD by the resistance value of the replica resistor Rmtj. Therefore, the second voltage V2 may be the same as the read voltage provided to the normal memory cell array 111. The buffer 302 may output the bias voltage VBIAS based on the received read current IRD.

[0104] The data input / output circuit 130 may include a first NMOS transistor N1, a second NMOS transistor N2, and a sense amplifier 131. A first end of the first NMOS transistor N1 is connected to a first input node of the sense amplifier 131, and a second end of the first NMOS transistor N1 is connected to a first node no1. A first end of the second NMOS transistor N2 is connected to a second input node of the sense amplifier 131, and a second end of the second NMOS transistor N2 is connected to a third node no3. The first node no1 may be an output node (or input node) of the normal memory cell array 111. The third node no3 may be an output node (or input node) of the reference memory cell array 113.

[0105] In a read operation, a bias voltage VBIAS may be applied to the gates of the NMOS transistors N1 and N2 by the bias circuit 300. In this case, the first NMOS transistor N1, the second NMOS transistor N2, and the fourth NMOS transistor N4 may operate as source followers. Thus, the second end of the first NMOS transistor N1 and the second end of the second NMOS transistor N2 may be fixed to the voltage of the second end of the fourth NMOS transistor N4 (e.g., the second voltage V2). In this case, the read current provided to the normal memory cell array 111 may be different from the read current provided to the reference memory cell array 113.

[0106] The sense amplifier 131 may sense an input current IIN provided to a first input node and a reference current IREF provided to a second input node. The input current IIN may correspond to a value obtained by dividing the second voltage V2 by the resistance value of the variable resistance element VR. That is, the magnitude of the input current IIN may be the same as the magnitude of the read current provided to the normal memory cell array 111. The reference current IREF may correspond to a value obtained by dividing the second voltage V2 by the resistance value of the reference resistor Rref. That is, the magnitude of the reference current IREF may be the same as the magnitude of the read current provided to the reference memory cell array 113. The sense amplifier 131 may amplify the difference between the input current IIN and the reference current IREF, and may output data.

[0107] As mentioned above, Fig.10 The memory device 1000 shown in FIG. 1 may include a sense amplifier 131 using current as an input.

[0108] The leakage current generator 210 may include a first PMOS transistor P1, a second PMOS transistor P2, and a third NMOS transistor N3. A power supply voltage VDD is applied to a first end of the first PMOS transistor P1, and a second end of the first PMOS transistor P1 is connected to a first end of the third NMOS transistor N3 and a common node of a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P2. A second end of the third NMOS transistor N3 is connected to a first signal line ML1. A power supply voltage VDD is applied to a first end of the second PMOS transistor P2. A bias voltage VBIAS provided from a bias circuit 300 is applied to a gate of the third NMOS transistor N3. In this case, the third NMOS transistor N3 and the fourth NMOS transistor N4 may operate as source followers, and therefore, a voltage at a second end of the third NMOS transistor N3 may be fixed to a voltage (e.g., a second voltage V2) at a second end of the fourth NMOS transistor N4.

[0109] The voltage V2 of the second end of the third NMOS transistor N3 may be the same as the voltage V2 of the second end of the first NMOS transistor N1. Therefore, the second voltage V2, which is the same as the voltage supplied to the normal memory cell array 111, may be applied to the first signal line ML1. The leakage current ILK may be supplied to the first signal line ML1 by the second voltage V2.

[0110] The first PMOS transistor P1 and the second PMOS transistor P2 may operate as a current mirror. In this case, the same current may be output from the first PMOS transistor P1 and the second PMOS transistor P2. The current flowing through the first PMOS transistor P1 may be the same as the current flowing through the third NMOS transistor N3. The leakage current ILK may be output from the third NMOS transistor N3, and thus the leakage current ILK may be output from the first PMOS transistor P1 and the second PMOS transistor P2. Therefore, the leakage current generator 210 may provide the leakage current ILK to the pump enable circuit 220.

[0111] Fig.11 It is shown Figure 6 240 is a circuit diagram of an example of a clamping circuit. Fig.11, the clamping circuit 240 may include a first resistor R1, a first PMOS transistor P1, a second PMOS transistor P2, and first to third NMOS transistors N1 to N3. A power supply voltage VDD is applied to a first end of the first resistor R1, and a second end of the first resistor R1 is connected to a common node of a first end of the first PMOS transistor P1 and a first end of the second PMOS transistor P2. A second end of the first PMOS transistor P1 is connected to a first end of the first NMOS transistor N1. A first end of the first NMOS transistor N1 is connected to a common node of a gate of the first NMOS transistor N1 and a gate of the second NMOS transistor N2, and a common node of a gate of the first PMOS transistor P1 and a gate of the second PMOS transistor P2. A ground voltage VSS is applied to a second end of the first NMOS transistor N1. A second end of the second PMOS transistor P2 is connected to a common node of a first end of the second NMOS transistor N2 and a gate of the third NMOS transistor N3. A second end of the second NMOS transistor N2 is connected to a node to which a body voltage VBB is provided. The ground voltage VSS is applied to a first terminal of the third NMOS transistor N3, and a second terminal of the third NMOS transistor N3 is connected to a node to which the bulk voltage VBB is supplied.

[0112] In the case where the body voltage VBB is the same as the ground voltage VSS, the gate voltage of the first NMOS transistor N1 may be the same as the gate voltage of the second NMOS transistor N2. In this case, the current flowing through the first NMOS transistor N1 may be the same as the current flowing through the second NMOS transistor N2. In the case where the body voltage VBB is greater than the ground voltage VSS, the current flowing through the first NMOS transistor N1 may be greater than the current flowing through the second NMOS transistor N2. In this way, the voltage of the node "no" can be increased. The first resistor R1, the first PMOS transistor P1 and the second PMOS transistor P2 can be operated as a differential amplifier. In this case, the voltage of the node "no" can be amplified by the first resistor R1, the first PMOS transistor P1 and the second PMOS transistor P2. In the case where the voltage of the node "no" increases, the third NMOS transistor N3 can be turned on, and therefore, the body voltage VBB can be fixed to the ground voltage VSS.

[0113] In the case where the body voltage VBB is greater than the ground voltage VSS, the threshold voltage Vth of the cell transistor may be reduced. This may mean that the leakage current flowing through the cell transistor further increases. The clamp circuit 240 may sense the body voltage VBB and may reduce the body voltage VBB to the ground voltage VSS when the body voltage VBB is higher than the ground voltage VSS. Therefore, the clamp circuit 240 may mitigate or prevent the leakage current flowing through the cell transistor from further increasing.

[0114] Fig.12 is a flowchart illustrating the operation of a memory device according to an example embodiment of the inventive concept. Figure 4 and Fig.12 , in operation S101, the memory device 1000 may apply a selection voltage to one memory cell included in the normal memory cell array 111. For example, the memory device 1000 may apply the selection voltage to a word line connected to the memory cell.

[0115] In operation S102, the memory device 1000 may provide the leakage current ILK to the monitor memory cell array 112. In operation S103, the memory device 1000 may determine whether the leakage current ILK is greater than the threshold current ITR. In the case where the leakage current ILK is greater than the threshold current ITR, in operation S104, the memory device 1000 may reduce the body voltage VBB. In the case where the leakage current ILK is not greater than the threshold current ITR, in operation S105, the memory device 1000 may fix the body voltage VBB to the ground voltage VSS.

[0116] Reference Figures 1 to 12 The components of the described memory device 1000 may be implemented in the form of software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0117] Fig.13 2 is a block diagram illustrating an electronic system 2000 according to an example embodiment of the inventive concept. Fig.13 , the electronic system 2000 may include a host device 2100 and a memory system 2200. For example, the electronic system 2000 may be implemented in electronic devices such as desktop computers, laptop computers, tablet computers, smart phones, wearable devices, video game consoles, servers, electric vehicles, home appliances, and medical devices.

[0118] The host device 2100 may be an electronic device that may perform operations required by the electronic system 2000. To this end, the host device 2100 may store data in the memory system 2200 or may read data stored in the memory system 2200.

[0119] For example, the host device 2100 may be a main processor (e.g., a central processing unit (CPU) or an application processor (AP)), a dedicated processor (e.g., a graphics processing unit (GPU) or a modulator / demodulator (MODEM)), or an image sensor. The host device 2100 may be any device configured to use the memory system 2200.

[0120] The memory system 2200 may store data used for the operation of the electronic system 2000. For example, the memory system 2200 may store write data required by the host device 2100, or may provide read data required by the host device 2100 to the host device 2100.

[0121] To this end, the memory system 2200 may include a controller 2210 and one or more nonvolatile memory devices 2220. The controller 2210 may control the overall operation of the memory system 2200. In an example embodiment, the controller 2210 may control the memory device 2220 in response to a request of the host device 2100 so that data is stored in the memory device 2220 or data is read from the memory device 2220. For example, the controller 2210 may provide various operations, such as a data error correction operation, a performance management operation, and / or an attack defense operation.

[0122] The memory device 2220 may include a memory element configured to store data and output the stored data. For example, the memory element may include a volatile memory element and / or a non-volatile memory element. The memory device 2220 may include a reference Figures 1 to 12 A memory device 1000 is described.

[0123] According to the inventive concept, a memory device and an operating method thereof that can adjust a leakage current flowing to a memory cell can be provided.

[0124] In addition, the memory device according to some example embodiments can reduce or prevent leakage current flowing to the memory cell from increasing even if the temperature increases. Therefore, the probability of an error in output data occurring can be reduced, and the reliability of the memory device can be improved.

[0125] Although the inventive concept has been described with reference to certain example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A memory device, comprising: a normal memory cell array including a first magnetoresistive memory cell connected to a first bit line, a first source line, and a first word line, the first magnetoresistive memory cell being configured to receive a selection voltage through the first word line; a monitor memory cell array including a second magnetoresistive memory cell connected to a first signal line and a second signal line, a gate of a cell transistor of the second magnetoresistive memory cell being configured to receive a non-select voltage; as well as A body bias generator is configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magnetoresistive memory cell and a body of the cell transistor of the second magnetoresistive memory cell based on the leakage current.

2. The memory device according to claim 1, wherein: When the leakage current is greater than a threshold, the body bias generator is configured to reduce the body voltage based on the leakage current, and When the leakage current is not greater than the threshold value, the body bias generator is configured to fix the body voltage to a ground voltage.

3. The memory device according to claim 1, wherein: The memory device is configured to apply a ground voltage to one of the first bit line and the first source line, apply a read voltage to the other of the first bit line and the first source line, and apply the ground voltage to the second signal line.

4. The memory device according to claim 3, wherein: The body bias generator is configured to apply a specific voltage substantially equal to the read voltage to the first signal line, and the leakage current flows through the first signal line based on the specific voltage.

5. The memory device according to claim 3, further comprising: A data input / output circuit is configured to output data stored in the first magnetoresistive memory cell based on a signal output through the first bit line or the first source line in response to an applied ground voltage and an applied read voltage.

6. The memory device of claim 1 , further comprising: a reference memory cell array including a reference memory cell including a cell transistor and not including a variable resistance element, the reference memory cell being connected to a second bit line, a second source line, and the first word line, the reference memory cell being configured to receive the selection voltage through the first word line; as well as A reference resistor is connected to the second bit line.

7. The memory device of claim 6, further comprising: A sense amplifier is configured to amplify a difference between a reference signal provided from the reference memory cell array and an input signal provided from the normal memory cell array.

8. The memory device according to claim 1, wherein: The normal memory cell array further includes a plurality of third magnetoresistive memory cells connected to the first bit line and the first source line, all of the plurality of third magnetoresistive memory cells being configured to receive the non-select voltage, and The leakage current flowing through the first signal line is substantially equal to the leakage current flowing in all of the third magnetoresistive memory cells.

9. A memory device comprising: a normal memory cell array including a first magnetoresistive memory cell connected to a first bit line, a first source line, and a first word line, the first magnetoresistive memory cell being configured to receive a selection voltage through the first word line; a monitor memory cell array including a second magnetoresistive memory cell connected to a first signal line and a second signal line, a gate of a cell transistor of the second magnetoresistive memory cell being configured to receive a non-select voltage; a leakage current generator configured to sense a leakage current flowing through the first signal line; as well as A negative charge pump is configured to reduce a body voltage provided to each of a body of a cell transistor of the first magnetoresistive memory cell and a body of the cell transistor of the second magnetoresistive memory cell when the leakage current is greater than a threshold value.

10. The memory device of claim 9, further comprising: A clamp circuit is configured to sense the bulk voltage and clamp the bulk voltage to the ground voltage when the sensed bulk voltage is greater than a ground voltage.

11. The memory device according to claim 9, wherein: The memory device is configured to apply a ground voltage to one of the first bit line and the first source line, apply a read voltage to the other of the first bit line and the first source line, apply a specific voltage substantially equal to the read voltage to the first signal line, and apply the ground voltage to the second signal line.

12. The memory device according to claim 11, wherein: The leakage current generator includes a voltage replica circuit configured to generate the specific voltage, and the voltage replica circuit includes: a replica resistor configured to have a resistance value substantially equal to a resistance value of a variable resistance element included in the first magnetoresistive memory cell, and A metal oxide semiconductor transistor is connected to the first end of the replica resistor and is configured to receive the selection voltage through a gate of the metal oxide semiconductor transistor.

13. The memory device of claim 9, further comprising: a reference memory cell array including a reference memory cell including a cell transistor and not including a variable resistance element, the reference memory cell being connected to a second bit line, a second source line, and the first word line, the reference memory cell being configured to receive the selection voltage through the first word line; as well as A reference resistor is connected to the second bit line.

14. The memory device of claim 13, further comprising: A sense amplifier is configured to amplify a difference between a reference signal provided from the reference memory cell array and an input signal provided from the normal memory cell array.

15. A memory device comprising: a normal memory cell array including a normal magnetoresistive memory cell connected to a first bit line, a first source line, and a corresponding word line of a plurality of word lines; a monitor memory cell array including a monitor magnetoresistive memory cell connected to a first signal line, a second signal line, and a third signal line, a gate of a cell transistor of the monitor magnetoresistive memory cell being connected to the third signal line and being configured to receive a non-select voltage through the third signal line; as well as A body bias generator is constructed to sense a leakage current flowing through the first signal line and control a body voltage based on the leakage current, the body voltage being provided to the body of each cell transistor included in the normal magnetoresistive memory cell and the body of each cell transistor included in the monitor magnetoresistive memory cell.

16. The memory device of claim 15, wherein: The memory device is configured to apply a selection voltage to a first word line among the plurality of word lines, and to apply the non-selection voltage to the remaining word lines among the plurality of word lines.

17. The memory device of claim 16, wherein: The memory device is constructed to apply a ground voltage to one of the first bit line and the first source line and apply a read voltage to the other of the first bit line and the first source line, apply a specific voltage substantially equal to the read voltage to the first signal line, and apply the ground voltage to the second signal line.

18. The memory device of claim 17, further comprising: A data input / output circuit is constructed to output data stored in a selected normal magnetoresistance memory cell connected to the first word line among the normal magnetoresistance memory cells based on a signal output through the first bit line or the first source line in response to an applied ground voltage and an applied read voltage.

19. The memory device of claim 15, further comprising: a reference memory cell array including reference memory cells, each of which includes a cell transistor and does not include a variable resistance element, the reference memory cells being connected to a second bit line, a second source line, and a corresponding word line of the plurality of word lines; as well as A reference resistor is connected to the second bit line.

20. The memory device of claim 19, further comprising: A sense amplifier is configured to amplify a difference between a reference signal provided from the reference memory cell array and an input signal provided from the normal memory cell array.

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