Process Variations with Die-Level Traceability

Abstract

The present invention is entitled "Process Variations with Die-Level Traceability". The present invention provides devices, systems and methods for uniquely identifying integrated circuits. For at least one embodiment, a method for marking a given integrated circuit from a plurality of integrated circuits includes the following operations: manufacturing a plurality of identifier devices to each integrated circuit of the plurality of integrated circuits; testing each identifier device of the plurality of identifier devices to obtain a test result for each identifier device; associating each test result obtained for each identifier device manufactured to each given integrated circuit to form an analog identifier for the given integrated circuit; and storing each analog identifier for each integrated circuit of the plurality of integrated circuits in a database. For at least one embodiment, a method for identifying an integrated circuit previously marked according to the present disclosure is provided. Commercial articles marked using embodiments of the present disclosure are also described.

Description

Technical Field

[0001] The technology described herein as a whole relates to methods for uniquely identifying an integrated circuit (IC). More specifically, the technology described herein uses random IC-IC variations, which occur during the manufacture of otherwise identically designed integrated circuits, to distinguish one integrated circuit from another. Specifically, the technology described herein relates to using a Zener diode to provide an analog identifier for identifying an integrated circuit. The technology described herein also relates to devices and systems for identifying using an analog identifier determined during the manufacture of an integrated circuit. Background Art

[0002] As is well known and understood, integrated circuits are typically manufactured using one or more process steps. Such process steps are typically performed in batches. These batches typically include multiple wafers, each of which includes multiple integrated circuits. Typically, for a given batch, each integrated circuit can be identified during manufacturing based on the location of each integrated circuit on the wafer. Typically, an XY coordinate system is used to identify a portion of a wafer, which is typically referred to as an integrated circuit. This coordinate system can be used during manufacturing and before the wafer is cut into each integrated circuit. For example, a given integrated circuit can be manufactured in batch "Q" at X coordinate "A" and Y coordinate "B" on wafer "N". Each of Q, N, A, and B is a real number. Therefore, during the manufacturing process, a batch / wafer / integrated circuit identification scheme can typically be used to complete the identification of each integrated circuit. This identification scheme allows tracking of each integrated circuit during manufacturing, in a database, or otherwise. However, during manufacturing, each wafer is ultimately cut into individual integrated circuits, packaged, and then used as needed. The packaging for the integrated circuit typically identifies the batch in which it is manufactured, but does not identify the wafer or the location on it. When dicing and packaging wafers, traceability of a given IC is no longer possible based solely on lot / wafer / IC identification schemes. Instead, additional identifiers are usually required.

[0003] In addition, integrated circuits are typically manufactured in large quantities and used in quality-critical applications. Examples of such applications include, but are not limited to, automotive electronics. Although significant process controls are used during the manufacture of integrated circuits to prevent and minimize the occurrence of defects, due to the large number of circuits typically manufactured, even rare problems, such as those measured in parts per million (ppm) and / or parts per billion (ppb), may be troublesome. The large-scale use of such circuits in automobiles and other implementations further enhances this concern. Such use typically results in hundreds of circuits for each given vehicle or other implementation. Given the quantities involved, such errors may result in substantial business, economic, and other pressures on manufacturers of such circuits. These issues typically result in manufacturers increasing their efforts to determine the root cause of the failure when a defect occurs in order to meet zero-defect standards.

[0004] However, determining the root cause of a defect in an integrated circuit is inherently difficult. This difficulty is often caused, at least in part, by the large number of possible failure modes that result from the combination of complex manufacturing processes and complex circuit designs. In addition, determining whether a solution actually overcomes a defect often results in a significant cost to the manufacturer in long-term improvements and the use of numerous engineers to clearly identify and implement corrective actions as best as possible to prevent defects in the integrated circuit. Therefore, it is very important to obtain as much information as possible about the defective integrated circuit. If the integrated circuit is uniquely identifiable, any previously stored information about the integrated circuit can be accessed. This information can be used to apply statistical post-processing techniques such as part average testing, which is a commonly known method for detecting and removing statistical outliers during production testing.

[0005] It is worth noting that many methods for uniquely identifying integrated circuits have been proposed. These methods include using marks or indicators on integrated circuits, packaging, or other aspects. Examples of such methods are disclosed in patents and / or patent application publications US2017 / 0243831, US2003 / 0062609, EP2625708, US2016 / 0351508, US2005 / 0042780, US2014 / 0061952, etc. Other methods include using additional circuit components such as memory components, certain discrete components such as resistors and capacitors, or non-discrete components such as transistors. Examples of such methods are disclosed in patents and / or patent application publications US6161213, US6941536, US2004 / 0124437, US2004 / 0006404, etc. However, each of these known methods is inadequate for various reasons, including requiring additional process steps, requiring the use of additional and significant die space to provide components for die-level tracking, providing only partial traceability, utilizing identifiers that are subject to tampering, alteration or duplication, requiring the use of specialized test equipment to track a given integrated circuit, requiring the use of digital identifiers, etc.

[0006] Therefore, there is a need to provide die-level traceability using natural process variations that occur during integrated circuit fabrication, where such traceability does not require the use of additional process steps, does not require a large amount of die space, is tamper-resistant, and can be detected using commonly available test equipment and processes. Such needs are addressed by one or more embodiments of the present disclosure. Summary of the invention

[0007] Various embodiments of the present disclosure relate generally to devices, systems, and methods for uniquely identifying integrated circuits. According to at least one embodiment, a method for marking a given integrated circuit from a plurality of integrated circuits may include the following operations: a plurality of identifier devices are manufactured to each of the plurality of integrated circuits. The method may also include testing each of the plurality of identifier devices to obtain a test result for each identifier device. The method may also include associating each test result obtained for each identifier device manufactured to each given integrated circuit to form an analog identifier for the given integrated circuit. The method may also include storing each analog identifier for each of the plurality of integrated circuits in a database.

[0008] For at least one embodiment, a method for marking a given integrated circuit from a plurality of integrated circuits may include using a plurality of identifier devices, the plurality of identifier devices including Zener diodes. The method may also include testing each identifier device in the plurality of identifier devices by determining a reverse breakdown voltage of each of the Zener diodes. For at least one embodiment, at least ten Zener diodes may be used.

[0009] For at least one embodiment, a method for marking a given integrated circuit from a plurality of integrated circuits may include determining a plurality of identifier devices required to uniquely identify each integrated circuit of the plurality of integrated circuits from each integrated circuit of the rest of the plurality of integrated circuits. For at least one embodiment, each analog identifier formed for each integrated circuit of the plurality of integrated circuits may uniquely correspond to a single given integrated circuit of the plurality of integrated circuits.

[0010] For at least one embodiment, a method for marking a given integrated circuit from a plurality of integrated circuits may include associating at least one of the plurality of integrated circuits with an article of commerce. For at least one embodiment, each of the plurality of identifier devices may be monotonically variable with at least one of time and temperature.

[0011] According to at least one embodiment of the present disclosure, a method for identifying an integrated circuit under test from a plurality of integrated circuits is provided. For at least one embodiment, the method may include receiving an integrated circuit under test, which is one of a plurality of integrated circuits manufactured in a given batch of integrated circuits. The integrated circuit under test includes a plurality of identifier devices. The method may include testing each identifier device in the plurality of identifier devices to obtain a plurality of test results. The method may include correlating the plurality of test results to form an analog identifier for the integrated circuit under test.

[0012] A method for identifying an integrated circuit under test from a plurality of integrated circuits may include accessing a database including a plurality of analog identifiers, wherein each of the plurality of analog identifiers corresponds to a single given integrated circuit that is one of a plurality of integrated circuits in a given batch of integrated circuits manufactured. The method may include comparing the integrated circuit under test analog identifier to the plurality of analog identifiers.

[0013] For at least one embodiment, a method for identifying an integrated circuit under test from a plurality of integrated circuits may include identifying the integrated circuit under test as a single integrated circuit among a plurality of integrated circuits in a given batch of integrated circuits based on a correlation of an analog identifier of the integrated circuit under test with an analog identifier of the plurality of analog identifiers.

[0014] For at least one embodiment, the integrated circuit under test has been previously marked according to a corresponding embodiment of the marking method described herein.

[0015] For at least one embodiment, an analog identifier for each integrated circuit in a plurality of integrated circuits may be used to perform dynamic part average testing (DPAT) on the plurality of integrated circuits to perform electrical test insertion on the packaged integrated circuits.

[0016] For at least one embodiment, each of the plurality of identifier devices is a Zener diode. A method for identifying a tested integrated circuit from a plurality of integrated circuits may include the following operations: testing each of the plurality of identifier devices to determine a reverse breakdown voltage of each of the Zener diodes. The method may include the following operations: comparing the tested integrated circuit analog identifier with the plurality of analog identifiers; and determining a correlation coefficient between the tested integrated circuit analog identifier and each of the plurality of analog identifiers. For at least one embodiment, the correlation coefficient may be based on a Pearson correlation.

[0017] For at least one embodiment, a method for identifying an integrated circuit under test from a plurality of integrated circuits may include identifying the integrated circuit under test when a correlation coefficient of the integrated circuit under test analog identifier compared to a given one of the plurality of analog identifiers is substantially 1.0. For at least one embodiment, the identification occurs when a correlation coefficient of the integrated circuit under test analog identifier compared to the given one of the plurality of analog identifiers is between 0.9 and 1.0. For at least one embodiment, each of the plurality of identifier devices varies monotonically with at least one of time and temperature.

[0018] According to at least one embodiment of the present disclosure, an identifiable integrated circuit includes multiple identifier devices on each integrated circuit in an integrated circuit batch. For at least one embodiment, each of the multiple identifier devices returns a first series of test results when tested. For at least one embodiment, the first series of test results collectively form a first analog identifier of the integrated circuit. Each of the multiple identifier devices may include a Zener diode. The first series of test results may be caused by the use of automatic test equipment testing. Such testing may include testing of the reverse breakdown voltage of each of the multiple identifier devices. Such testing may be performed before packaging the integrated circuit. The first analog identifier may be saved for later use in identifying the integrated circuit. A second, later test using automatic test equipment may include testing of the reverse breakdown voltage of each of the multiple identifier devices. Such testing may return a second series of test results, forming a second analog identifier. The second series of test results may vary monotonically with time and temperature relative to the first series of test results. The correlation between the first series of test results and the second series of test results may be used to associate the first analog identifier with the second analog identifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Features, aspects, advantages, functions, modules, and components of devices, systems, and methods provided by various embodiments of the present disclosure are further disclosed herein with respect to at least one of the following description and drawings.

[0020] Figure 1A is a histogram representing results implemented for a set of integrated circuits based on a first test and used in conjunction with one or more embodiments of the present disclosure.

[0021] Figure 1B is a histogram representing results based on a second test implemented for a set of integrated circuits and used in conjunction with one or more embodiments of the present disclosure.

[0022] Figure 2 is a line graph representing test results for various integrated circuits and a plurality of Zener diode implementations and used to generate and / or identify a simulated identifier for a given integrated circuit in accordance with at least one embodiment of the present disclosure.

[0023] Figure 3 is a flow chart illustrating a method for determining an analog identifier of an integrated circuit and identifying the integrated circuit based on a previously determined analog identifier and used in accordance with at least one embodiment of the present disclosure.

[0024] Figure 4 is a flow chart illustrating a method for identifying an integrated circuit that has been previously marked with one or more analog identifiers in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Various embodiments described herein relate to a method for uniquely identifying an integrated circuit by associating the integrated circuit with an analog identifier. According to at least one embodiment, the analog identifier is stable and can be determined during manufacturing, post-manufacturing testing, and after field use of the integrated circuit. According to at least one embodiment, the analog identifier can be determined based on the characteristics of one or more discrete components (each of which is herein an "identifier device"). According to at least one embodiment, the measured device characteristics can correspond to a specific batch, lot, wafer, integrated circuit, or otherwise used to manufacture a given integrated circuit. According to at least one embodiment, the measured characteristics of one or more identifier devices (such as Zener diodes) can be used to provide an analog identifier for a given integrated circuit. According to at least one embodiment of the present disclosure, multiple Zener diodes can be used to uniquely identify an integrated circuit. According to at least one embodiment of the present disclosure, the analog identifier can be based on a given characteristic of the identifier device, such as the reverse breakdown voltage of the Zener diode. According to at least one embodiment, a set of Zener diodes can be manufactured to each integrated circuit used to form each integrated circuit, so that the response characteristics of each such set of Zener diodes can be used to form a unique identifier for a given integrated circuit. Such an identifier effectively serves as a fingerprint of the integrated circuit ("IC fingerprint"). According to at least one embodiment, a Zener diode used to provide the functionality of a given integrated circuit may be used in whole or in part to identify an integrated circuit. According to at least one embodiment, a Zener diode may be added to an integrated circuit to provide a unique analog identifier that provides an IC fingerprint.

[0026] In accordance with developments of the inventive concepts of the present disclosure, the use of a Zener diode to provide such IC fingerprinting results from the novel and non-obvious discovery that one or more identifier devices (such as a Zener diode) can be fabricated on the same integrated circuit and tested using the same process during each of fabrication, testing, post-wafer dicing, and use to identify a given integrated circuit. More specifically, this can be accomplished by basing the analog identifier on one or more characteristics of the identifier device (such as the reverse breakdown voltage of a Zener diode). It should be understood that other types of identifier devices and / or characteristics can be used to generate an IC fingerprint.

[0027] For at least one embodiment in which Zener diodes are utilized, a characteristic of a set of Zener diodes is that their reverse breakdown voltage varies monotonically over both time and temperature. This device characteristic provides a stable analog identifier for each Zener diode, and when combined, in accordance with at least one embodiment of the present disclosure, collectively provides an IC fingerprint that is stable over time. This stability arises at least in part because each reverse breakdown voltage generated in a given set of Zener diodes drifts monotonically. Therefore, the relative difference between the reverse bias voltages of the Zener diodes remains the same over time and temperature, and this relative difference generated on the set of Zener diodes can be used to provide an IC fingerprint. More specifically, the measured characteristics of the set of Zener diodes can be associated with previously measured characteristics of a given integrated circuit, thereby facilitating the identification of the integrated circuit later. Such previously and / or later measured characteristics of an integrated circuit marked using one or more monotonically behaving devices can be determined at any time, such as during the manufacture, testing, use, or other processes of a given integrated circuit.

[0028] Secondly and for at least one embodiment, device characteristics that can be accurately and precisely measured by automatic test equipment can be used. Such device characteristics provide a basis for analog identifiers, where even small variations between devices and by extension analog identifiers are identifiable. For at least one embodiment, the reverse breakdown voltage of a Zener diode provides one such device characteristic. Other devices and / or characteristics thereof can be used according to one or more embodiments of the present disclosure.

[0029] Third, and for at least one embodiment, an analog identifier may be utilized. It should be appreciated that an analog identifier helps retain a large amount of information about a device (such as a Zener diode) used to provide an IC fingerprint. In contrast, when a low-bit count digital representation of such information is utilized, information about such an identifier device may be lost or otherwise not retained.

[0030] Fourth, it should be appreciated that various embodiments of the present disclosure provide various improvements over known solutions. For example, by using a Zener diode as one or more identifier devices, the additional area used to identify a given integrated circuit can be limited, if necessary. This savings can be achieved because the size of the Zener diode is typically relatively small and / or it is commonly used in integrated circuits. When commonly used, it may only be necessary to add a small amount or even no additional Zener diodes (i.e., identifier devices) to provide an IC fingerprint.

[0031] Furthermore, it should be appreciated that only a small number (typically 20 or less) of Zener diodes may be required to provide an IC fingerprint. Given the accuracy and precision of the device characteristics of Zener diodes, and the degree to which one such device characteristic varies from Zener diode to Zener diode, the number of identifier devices utilized may be conserved. These variations may be determined using automated test equipment, and may be based on simulation information, including but not limited to the exponential current-voltage behavior common to Zener diodes.

[0032] Furthermore, it should be understood that the prior art, in accordance with one or more embodiments of the present disclosure, did not contemplate the use of Zener diodes to provide die-level traceability, where devices such as resistors, capacitors, transistors, or others are contemplated. In contrast, it should be understood that, in accordance with the present disclosure, although Zener diode device characteristics may vary over time and temperature and may be inherently less sensitive to process variations, these disadvantages may be overcome. First, changes in a collection of Zener diodes typically occur in a monotonic manner without affecting the relative characteristics of the collection. Second, changes in the measured value of the reverse breakdown voltage of the Zener diodes may be negligible compared to the actual reverse breakdown voltage of the Zener diodes. Therefore, as described herein, the recorded prior art did not contemplate their use as identifiers for integrated circuits. Therefore, it should be understood that, in accordance with at least one embodiment of the present disclosure, the use of Zener diodes is fundamentally different from known methods of identifying integrated circuits.

[0033] More specifically, in at least one embodiment of the present disclosure, Zener diodes provide integrated circuit device components whose device characteristics are measurable and unique from the perspective of one set of Zener diodes to another set of Zener diodes. These device characteristics facilitate creating an analog identifier for the integrated circuit, where the analog identifier is based on at least one measured device characteristic of each of a plurality of Zener diodes provided in the integrated circuit. For at least one embodiment, an analog identifier for the integrated circuit may include a set of individual measured device characteristics for each of a plurality of identifier devices, such as Zener diodes.

[0034] In addition, it should be understood that the Zener diode used to identify a given integrated circuit can appear in the circuit itself or elsewhere on the integrated circuit, such as appearing on the silicon substrate embodying such integrated circuit. Given the relatively small footprint of the Zener diode, any additional Zener diode added to an integrated circuit to provide die-level traceability for a given integrated circuit in accordance with at least one embodiment of the present disclosure will generally result in a method that utilizes insubstantial area of ​​the integrated circuit. As used herein, insubstantial use of integrated circuit area, such as an integrated circuit occupying 1 to 10 square millimeters of a substrate, uses less than 1% of the total available area provided by such substrate. However, one of ordinary skill in the art will understand that the relative use of portions of a given substrate will vary with the size of the integrated circuit on such substrate, the number of identifier devices actually used to provide an IC fingerprint, and other factors.

[0035] It should be understood that the number of Zener diodes used to identify an integrated circuit can vary based on a number of variables, such as the number of integrated circuits on a wafer, the number of wafers in a batch, and the probability that one integrated circuit is incorrectly identified as another. Monte Carlo simulation and other known statistical methods can be used to identify the number of Zener diodes and / or other identifier devices that are expected to be used to uniquely identify integrated circuits in a given batch. In addition, it should be understood that the number of devices used in the first set of identifier devices can vary from the number used in the second set of identifier devices. These differences can vary based on the characteristics of the devices used in any given set of identifier devices to provide an IC fingerprint. It should be understood that the batch of integrated circuit manufacturing is usually identified on the package of the integrated circuit.

[0036] For example, Figure 1A As shown, a given set of integrated circuits can be identified by testing the Zener diodes fabricated thereon under a first test condition X(i). As shown, each of integrated circuits 1, 2, 3, and 4 returns characteristics that fall into the third result (from the highest result). Therefore, based on the first test condition, integrated circuits 1-4 cannot be identified separately from each other. Figure 1BAs shown, the second test condition X(i+1) can also be applied to a set of integrated circuits. As shown, integrated circuit 1 returns a unique result (falling into the highest result alone), while integrated circuits 2, 3 and 4 share the test results with other unidentified integrated circuits. Therefore, based solely on the second test condition, integrated circuits 2, 3 and 4 are not individually identifiable. However, when the results of the first test condition are observed in conjunction with the results of the second test condition, each of integrated circuits 1 and 4 can be individually identified, while integrated circuits 2 and 3 require other test conditions to be uniquely identifiable. Therefore, it should be understood that by using multiple Zener diodes and / or test conditions, an integrated circuit can be uniquely identified relative to other integrated circuits in a batch based on test results measured during manufacturing and later during use, where the same test is used in both stages.

[0037] More specifically, if Figure 2 As shown, multiple integrated circuits 100 may each include multiple Zener diodes (identified as ZD-1, ZD-2, ..., ZD-n). Each Zener diode is ideally identical on each integrated circuit, but such devices will vary slightly during manufacturing. Therefore, each integrated circuit will exhibit a reverse breakdown voltage of the Zener diode, which will be different and distinguishable from another on a certain scale. As shown, for the ZD-1 result, the integrated circuit (35, 12) (where 35 is the X coordinate on a given wafer and 12 is the Y coordinate on a given wafer) may not be easily distinguished from one or more other integrated circuits on a given wafer (such as (22, 10), (8, 5), (38, 13)). However, when based on a combination of multiple Zener diode results, each integrated circuit can be uniquely identified. That is, according to at least one embodiment of the present disclosure, a combination of test results measured across a combination of Zener diodes formed on a given integrated circuit can be used to provide a unique analog identifier for the integrated circuit. The unique analog identifier essentially serves as an IC fingerprint, where multiple data values ​​for a unique device (e.g., a Zener diode) at a unique integrated circuit location are used for identification purposes. Thus, for various embodiments of the present disclosure, multiple reverse breakdown voltages (each associated with a unique Zener diode) form the IC fingerprint of the integrated circuit. Thus, in accordance with at least one embodiment of the present disclosure, an analog identifier for a given integrated circuit is provided.

[0038] It should be understood that the analog identifier can be obtained at any time during the manufacturing and / or testing process when the specific coordinate location of the integrated circuit on a given wafer is known. For at least one embodiment, the analog identifier is determined during wafer sorting. The analog identifier of each integrated circuit can be stored in a suitable database for later use in determining the identity of the integrated circuit.

[0039] like Figure 2 As further shown in , when an integrated circuit ("tested integrated circuit") is returned for any purpose (such as in response to an identification failure, customer return, test rejection, or other reason), the tested integrated circuit can be subjected to the same electrical test conditions that were previously used to measure the characteristics upon which the analog identifier was based during wafer sorting or at another test time. That is, each of the Zener diodes on the tested integrated circuit can be tested and compared to the previously determined analog identifier to identify the original wafer location of the tested integrated circuit. That is, IC fingerprint matching can occur. As shown in FIG. Figure 2 As shown, the "qualification failed" integrated circuit test results are very similar to the test results recorded earlier for the (35,12) integrated circuit. Engineers can then use such location information (granting access to any previously stored information about the integrated circuit) to more specifically identify one or more conditions, such as the root cause of a defect for a given integrated circuit.

[0040] Furthermore, it should be understood that the range of reverse breakdown voltages may vary depending on the type of Zener device utilized. Typically, Zener diodes with reverse breakdown voltages ranging between 1 volt and 10 volts may be utilized. However, other embodiments may use other ranges.

[0041] In addition, it should be understood that although various embodiments are described herein in the context of the reverse breakdown voltage characteristics of a Zener diode, the present disclosure is not intended to be so limited. Other monotonic and stable relationships of device components can be used to collectively form an analog identifier for a given integrated circuit. For example, other diodes, resistors (e.g., high ohm polysilicon resistors, medium ohm polysilicon resistors, low ohm polysilicon resistors, metal resistors, etc.), transistors (e.g., CMOS transistors, DMOS transistors, bipolar transistors, etc.), or capacitors (e.g., metal insulator metal capacitors, metal oxide metal capacitors, polyoxide polysilicon capacitors, active area capacitors, etc.) can be used as one or more identifier devices. It should be understood that a collection of identifier devices can include the use of devices of the same given type or various types.

[0042] In addition, it should be understood that a given batch may include hundreds of thousands of integrated circuits. Each integrated circuit in such an integrated circuit may include multiple Zener diodes to create an analog identifier. As described above, each Zener diode will have a reverse breakdown voltage that may be slightly different from another instance of the same Zener diode on a different integrated circuit. Therefore, when the tested integrated circuit is to be identified, a generally known technique can be used to determine a set of results obtained across a set of Zener diodes on the tested integrated circuit relative to the results previously obtained during the manufacture and sorting of the integrated circuits in the batch. For at least one embodiment, a correlation coefficient can be utilized. For other embodiments, other statistical techniques can be used to determine the correlation between the tested integrated circuit and the previously identified integrated circuit. Ideally, the tested integrated circuit will have a correlation coefficient substantially the same as a single previously identified integrated circuit across the set of Zener diodes. As used herein, when the correlation coefficient is equal to 0.9 or higher, substantially the same correlation coefficient is generated between the integrated circuit and the previously identified integrated circuit.

[0043] like Figure 3 FIG. 1 shows a process for generating an analog identifier for each integrated circuit in a batch according to at least one embodiment of the present disclosure. It should be understood that the present disclosure is not limited to Figure 3 The operations shown, or their ordering, may use additional, fewer, other, and / or other arrangements of process steps according to other embodiments of the present disclosure.

[0044] As shown, the process begins by determining a plurality of unique identifier data points for distinguishing each integrated circuit from other integrated circuits in the batch (operation 300). It should be understood that the number of unique identifier data points to be used for such identification may be determined based on simulations such as Monte Carlo simulations, trial and error, known practices, or other simulations, and that such unique identifier data points may vary based on other factors, such as the type of identifier device used to provide the unique identifier, the accuracy achieved for manufacturing such an identifier device, etc. For at least one embodiment, one to ten unique identifiers are used. For at least one embodiment, ten to thirteen unique identifiers are used. For at least one embodiment, at least twenty unique identifiers are used. For at least one embodiment, equal to or more than 30 unique identifiers are used.

[0045] Once the number of unique identifiers is determined, the process continues with manufacturing the identifier devices selected to provide the unique identifiers (operation 302). The manufacture of the identifier devices can occur at any suitable time during the manufacture of each given integrated circuit and using known processes. The timing and manufacturing techniques utilized are well known and beyond the scope of this disclosure. As described above, for at least one embodiment, one or more of the identifier devices in the identifier device is a Zener diode. For at least one embodiment, each of the identifier devices in the identifier device is a Zener diode. For at least one embodiment, a combination of Zener diodes and other devices is utilized to provide the desired number of unique identifiers. For other embodiments, any type of identifier device or combination of identifier devices may be utilized to provide the desired number of unique identifiers.

[0046] The process continues to test each identifier device (operation 304) to obtain one or more device characteristics. As described above, the testing of each identifier device can occur at any given time. For at least one embodiment, the testing is performed during the sorting process. The testing of each identifier device can be based on any one or more desired characteristics that can be measured for the selected identifier device. For at least one embodiment and as shown in sub-operation 304A, the process may include determining one or more test characteristics to be tested for each identifier device. For at least one embodiment, the tested device characteristics include characteristics that are monotonic over time. For at least one embodiment, the tested device characteristics include characteristics that are monotonic over temperature for a set of devices. For at least one embodiment, the tested device characteristics include characteristics that are monotonic over both time and temperature for a set of devices. For at least one embodiment, when the identifier device is a Zener diode, the tested device characteristics include the reverse breakdown voltage of the Zener diode. For at least one embodiment, each identifier device in the identifier device can be tested using an integrated circuit configured in a test mode and a multiplexer directly or indirectly connected to commonly available automatic test equipment.

[0047] The test results for each of the tested identifier devices are collected and associated with the specific integrated circuit on which the identified device was manufactured, per operation 306. For at least one embodiment, such association includes mapping the identified device to the integrated circuit at the determined coordinate location on the wafers of a given production lot.

[0048] The associated test results are stored in a database, per operation 308. The test results may be stored in their native format, encrypted, compressed, or otherwise processed for storage.

[0049] like Figure 4As shown, a method for identifying a previously Figure 3 Embodiments of the process of performing IC fingerprinting of an integrated circuit (the aforementioned "test integrated circuit") using an analog identifier.

[0050] According to operation 400, the process begins when an integrated circuit under test is received for identification. It should be understood that the integrated circuit under test may be identified after the integrated circuit under test has been identified. Figure 3 The integrated circuit is received at any time after the process of performing IC fingerprint identification on the integrated circuit or any other process that provides an IC fingerprint based on one or more device characteristics of a set of identifier devices. For at least one embodiment, the integrated circuit under test may include a defective integrated circuit. For at least one embodiment, the integrated circuit under test may be received before, at the same time, or after being used for one or more products. Upon receiving the integrated circuit under test, the process continues to start testing the integrated circuit under test. For at least one embodiment, the integrated circuit under test is tested using each identifier device and all of the test processes and identification devices used in operation 304. However, it should be understood that the testing of the integrated circuit under test may include the use of one or more tests and / or subsets of the tests of the identifier devices used in operation 304. That is, the testing of the integrated circuit under test may involve the use of an iterative process in which additional tests and / or identifier devices are tested until those test operations required to identify the IC fingerprint of a given integrated circuit have been performed.

[0051] Results achieved from the testing of the integrated circuit under test are collected, per operation 402. These results (e.g., measured voltages) may be collected in an analog format, or processed and digitized according to any process used per operation 308. For at least one embodiment, the results achieved from the testing of the integrated circuit under test are collected for comparison with results achieved from the testing of the integrated circuit, per operation 306.

[0052] Per operation 404, results from the testing of the integrated circuit under test are compared to the results stored per operation 308. It should be appreciated that the results stored per operation 308 may include a very large set of groups. Therefore, various data comparison and / or statistical analysis tools may be used per operation 404. For at least one embodiment, operation 404 includes the calculation and use of a correlation coefficient, such as a Pearson coefficient. For at least one embodiment, a correlation coefficient ranging between 0.9 and 1.0 indicates that a match has occurred between the integrated circuit under test and a previously tested integrated circuit, where such testing was previously performed per operations 304 and 306.

[0053] According to operation 406, identification of the integrated circuit under test by coordinate, wafer, and lot is recorded.

[0054] It should be understood that the identification of integrated circuits during processing and later during / after use can be used for any desired purpose. As described above, such use can include identifying the root cause of an integrated circuit defect. In other use cases, use can include attaching the integrated circuit to a commercial article and using the above process to later positively identify the source of the commercial article. That is, by attaching the integrated circuit to the goods at or before the commercial article is sold and / or used, these commercial articles can be identified at any time and information can be generated to help prevent counterfeiting or theft, track products, or other functions. Therefore, it should be understood that the above-mentioned processes and techniques for identifying integrated circuits can be applied to other uses and used in conjunction with any substrate, surface or other, where one or more identifier devices (such as Zener diodes) can be manufactured, attached or otherwise provided and reliably tested over time, temperature and / or other usage changes and / or conditions.

[0055] Although various embodiments of the claimed invention have been described above with a certain degree of particularity or with reference to one or more separate embodiments, those skilled in the art may make many changes to the disclosed embodiments without departing from the spirit or scope of the claimed invention. The use of the terms "about", "approximately" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there may be minor changes that prevent the value from being exactly equal to the stated value. Therefore, expected differences such as a 10% difference are reasonable differences that will be expected and known to those of ordinary skill in the art, and are acceptable relative to the statements or ideal goals of one or more embodiments of the present disclosure. It should also be understood that the terms "top" and "bottom", "left" and "right", "up" and "down", "first", "second", "before", "after" and other similar terms are only used for the purpose of description and ease of reference, and are not intended to be limited to any orientation or configuration of any element of the various embodiments of the present disclosure or any sequence of operations. In addition, the terms "and" and "or" are not intended to be used in a limiting or expansive manner, and cover any possible range of combinations of elements and operations of the embodiments of the present disclosure. Other embodiments can therefore be conceived. It is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative of the embodiments only and not limiting. Changes in detail or structure may be made without departing from the basic elements of the invention as defined in the appended claims.

Claims

1. A method for marking a given integrated circuit from a plurality of integrated circuits, comprising: fabricating a plurality of identifier devices onto a given integrated circuit of the plurality of integrated circuits; testing each identifier device of the plurality of identifier devices to obtain a unique test result for each identifier device of the plurality of identifier devices; associating each unique test result together to form an analog identifier for the given integrated circuit; as well as The simulation identifier is stored in a database.

2. The method according to claim 1, wherein at least one identifier device of the plurality of identifier devices comprises a zener diode; and The method further comprises: Determine the reverse breakdown voltage of each Zener diode.

3. The method according to claim 1, further comprising: determining a number of identifier devices required to uniquely identify the given integrated circuit; wherein the analog identifier uniquely identifies the given integrated circuit from among the plurality of integrated circuits; and Wherein at least one identifier device varies monotonically with at least one of time and temperature.

4. The method according to claim 3, further comprising: The given integrated circuit is associated with an article of commerce.

5. A method for identifying an integrated circuit under test from a plurality of integrated circuits, comprising: receiving the integrated circuit under test; wherein the integrated circuit under test is a given integrated circuit from a plurality of integrated circuits manufactured in a batch of integrated circuits; wherein the integrated circuit under test includes a plurality of identifier devices; testing each identifier device of the plurality of identifier devices to obtain a set of test results; associating the set of test results to form a first simulation identifier; accessing a database comprising a plurality of simulation identifiers; wherein each analog identifier of the plurality of analog identifiers corresponds to a single integrated circuit; comparing the first analog identifier to each of the plurality of analog identifiers; as well as The integrated circuit under test is identified as the given integrated circuit based on a correlation of the first analog identifier with two or more analog identifiers of the plurality of analog identifiers.

6. The method according to claim 5, wherein the integrated circuit under test has been previously marked as the given integrated circuit from among the plurality of integrated circuits; and Wherein at least one identifier device of the plurality of identifier devices varies monotonically with at least one of time and temperature.

7. The method according to claim 6, wherein at least one identifier device of the plurality of identifier devices is a Zener diode; and The method further comprises: Determine the reverse breakdown voltage of each Zener diode.

8. The method according to claim 5, wherein the correlation is a Pearson correlation; and Wherein the identification occurs when the resulting correlation coefficient of the Pearson correlation is between 0.9 and 1.

0.

9. A device comprising a markable integrated circuit manufactured according to any of the methods of claims 1 to 4.

10. An identifiable integrated circuit, comprising: a plurality of identifier devices formed in an integrated circuit; wherein each identifier device of the plurality of identifier devices is characterized by a first test result when first tested prior to packaging of the integrated circuit, the first test result comprising a first reverse breakdown voltage; wherein a first set of first test results forms a first analog identifier for the integrated circuit; and whereby a second set of second test results resulting from a second test of each of the plurality of identifier devices forms a second simulated identifier; Whereby, said second set of test results comprises at least one second test result that varies monotonically with time and temperature relative to the first series of test results; and Thus, based on the correlation of the first set of first test results and the second set of second test results, the first analog identifier can be matched with the second analog identifier and the integrated circuit identified thereby.

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