Method for manufacturing crystalline silicon solar cell wafers and crystalline silicon solar cell wafers

Abstract

The present invention relates to a method for manufacturing a crystalline silicon solar cell and a crystalline silicon solar cell. The method includes providing a substrate sheet and applying grid lines on the top surface and the bottom surface of the substrate sheet. The solar cell includes an N-type silicon wafer, an N-type polysilicon passivation layer located on the bottom surface of the N-type silicon wafer, and a P-type doping layer formed by a boron doping step on the top surface of the N-type silicon wafer. When setting up the crystalline silicon solar cell, the N-type polysilicon passivation layer is prepared prior to boron doping the top surface of the N-type silicon wafer. According to the present invention, the N-type polysilicon passivation layer is formed first during the manufacturing process and then boron doping is performed on the surface of the silicon wafer. Therefore, when the N-type polysilicon passivation layer is formed, the PN junction has not been formed on the top surface of the silicon wafer yet. At this time, even if phosphorus is plated around to the top surface, it will not affect the performance of the solar cell.

Description

Technical Field

[0001] The present invention relates to the field of energy, and in particular to a crystalline silicon solar cell and a method for manufacturing the same. Background Art

[0002] With the accelerated consumption of conventional fossil energy such as coal, oil and natural gas, the ecological environment is deteriorating, especially the increasingly severe global climate change caused by greenhouse gas emissions, and the sustainable development of human society has been seriously threatened. Countries around the world have formulated their own energy development strategies to cope with the limited resources of conventional fossil energy and the environmental problems caused by its development and utilization. Solar energy has become one of the most important renewable energy sources due to its reliability, safety, extensiveness, longevity, environmental protection and sufficient resources, and is expected to become the main pillar of global electricity supply in the future.

[0003] In the new round of energy transformation, my country's photovoltaic industry has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges. Conversion efficiency and reliability are the biggest technical obstacles to the development of the photovoltaic industry, while cost control and scale have formed economic constraints.

[0004] In recent years, various new crystalline silicon technologies have emerged one after another. Currently, PERC solar cells are the main ones in the market, and the mainstream production efficiency can exceed 22%. However, the conversion efficiency of PERC solar cells will be subject to more restrictions. At present, a new type of passivation contact structure can increase the conversion efficiency of the cell to more than 23% by superimposing 2-3 processes on the existing PERC technology. Passivation contact technology is increasingly favored by the market and various research institutions due to its strong compatibility with the existing PERC technology.

[0005] The existing passivation contact technology for crystalline silicon solar cells is to prepare an N-type doped polysilicon film on the back of N-type crystalline silicon. However, during the doping process, phosphorus will be plated onto the front of the silicon wafer. Since the diffusion coefficient of phosphorus is larger than that of boron, it will destroy the P-type thin layer and PN junction on the front, resulting in low efficiency or even failure of the solar cell.

[0006] In order to solve these problems, some solutions are to first coat a protective film such as silicon nitride, silicon carbide, etc. on the front emitter, and then wash off the front protective film after the N-type doped polysilicon is plated on the back. Although this process can effectively avoid the damage of phosphorus plating to the front PN junction, it requires additional coating and cleaning steps, which increases the cost of battery manufacturing, which is not conducive to the development of passivated contact battery technology.

[0007] Therefore, it is necessary to provide a method for manufacturing a crystalline silicon solar cell and a crystalline silicon solar cell to at least partially solve the above problems. Summary of the invention

[0008] An object of the present invention is to provide a method for manufacturing a crystalline silicon solar cell and a crystalline silicon solar cell, in which an N-type polysilicon or doped silicon carbide passivation layer is formed first during the manufacturing process and then boron doping is performed on the surface of the silicon wafer. Therefore, when the N-type passivation layer is formed, a PN junction has not been formed on the top surface of the silicon wafer. At this time, even if phosphorus is plated onto the top surface, it will not affect the performance of the solar cell.

[0009] Moreover, the present invention also omits the step of additionally providing a protective layer, thereby omitting redundant processes and reducing costs. The crystalline silicon solar cell provided by the present invention has a relatively simple structure and is easy to manufacture. The manufacturing method provided by the present invention has a simple process route and is easy to implement.

[0010] According to one aspect of the present invention, there is provided a method for manufacturing a crystalline silicon solar cell, the method comprising providing a substrate wafer and applying grid lines on the top surface and the bottom surface of the substrate wafer. The solar cell comprises an N-type silicon wafer, an N-type passivation layer located on the bottom surface of the N-type silicon wafer, and a P-type doping layer formed by a boron doping step located on the top surface of the N-type silicon wafer. The N-type passivation layer is an N-type polysilicon passivation layer or a doped silicon carbide passivation layer. When providing the crystalline silicon solar cell, the N-type passivation layer is prepared before boron doping is performed on the top surface of the N-type silicon wafer.

[0011] In one embodiment, the method sequentially comprises the following steps:

[0012] Provide an N-type silicon wafer;

[0013] Provide a silicon dioxide tunneling layer on the bottom surface of the N-type silicon wafer;

[0014] Provide an N-type passivation layer on the bottom surface of the silicon dioxide tunneling layer, the N-type passivation layer being a polysilicon passivation layer or a doped silicon carbide passivation layer;

[0015] Etch the edges and the top surface of the N-type silicon wafer to remove phosphorus thereon;

[0016] Perform boron doping or ion implantation on the top surface of the N-type silicon wafer to form a P-type doping layer on the top surface of the N-type silicon wafer.

[0017] In one embodiment, the method further comprises the following steps after the step of performing boron doping on the top surface of the N-type silicon wafer: etching the edges of the N-type silicon wafer and the bottom surface of the N-type passivation layer to remove boron thereon.

[0018] In one embodiment, the steps of etching the edges and top surface of the N-type silicon wafer and etching the edges of the N-type silicon wafer and the bottom surface of the N-type passivation layer are implemented by chemical wet and / or dry etching methods.

[0019] In one embodiment, the method further includes: after etching the bottom surface of the N-type polysilicon passivation layer to remove boron, an alumina passivation film is provided on the top surface of the P-type doping layer.

[0020] In one embodiment, the method further includes the following steps after the step of providing the alumina passivation film: a silicon nitride antireflection film, a silicon oxynitride antireflection film, or a silicon carbide antireflection film is provided on the top surface of the alumina passivation film and the bottom surface of the N-type passivation layer.

[0021] In one embodiment, the silicon nitride antireflection film, the silicon oxynitride antireflection film, or the silicon carbide antireflection film is provided by a PECVD method, and the thickness of the silicon nitride antireflection film, the silicon oxynitride antireflection film, or the silicon carbide antireflection film is formed to be 70 nm - 200 nm.

[0022] In one embodiment, the tunneling layer is a silicon dioxide tunneling layer, and the step of providing the silicon dioxide tunneling layer includes: preparing the silicon dioxide tunneling layer by at least one of thermal oxidation, ozone, wet oxidation, and ALD methods, and making the thickness of the silicon dioxide tunneling layer be 0.5 nm - 3 nm.

[0023] In one embodiment, the step of providing the N-type passivation layer includes: preparing the N-type polysilicon passivation layer by at least one of an LPCVD method, a PECVD method, an ion implantation method, and an ALD method, and making the thickness of the N-type polysilicon passivation layer be 20 nm - 300 nm.

[0024] In one embodiment, the step of boron doping is implemented by a thermal diffusion or ion implantation method, such that the sheet resistance of the surface of the P-type doping layer is 40 Ω / □ - 300 Ω / □.

[0025] In one embodiment, there is no step of providing a protective layer on the top surface of the N-type silicon wafer before providing the N-type passivation layer.

[0026] According to another aspect of the present invention, there is provided a crystalline silicon solar cell manufactured by the method according to any one of the above solutions, the crystalline silicon solar cell including:

[0027] An N-type silicon wafer;

[0028] A tunneling layer pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer, the tunneling layer being provided on the bottom surface of the N-type silicon wafer;

[0029] An N-type passivation layer pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer. The N-type passivation layer is a polysilicon passivation layer or a doped silicon carbide passivation layer, and the N-type passivation layer is disposed on the bottom surface of the tunneling layer;

[0030] A P-type doping layer configured after preparing the N-type passivation layer. The P-type doping layer is disposed on the top surface of the N-type silicon wafer;

[0031] An aluminum oxide passivation layer disposed on the top surface of the P-type doping layer.

[0032] In one embodiment, it further includes a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the aluminum oxide passivation layer and on the bottom surface of the N-type passivation layer.

[0033] In one embodiment, the tunneling layer is a silicon dioxide tunneling layer, and the thickness of the silicon dioxide tunneling layer is 0.5 nm - 3 nm.

[0034] In one embodiment, the thickness of the N-type passivation layer is 20 nm - 300 nm.

[0035] In one embodiment, the thickness of the silicon nitride antireflection film is 70 nm - 200 nm.

[0036] According to the present invention, during the process of manufacturing a solar cell wafer, the N-type passivation layer is first formed and then boron doping is performed on the surface of the silicon wafer. Therefore, when the N-type passivation layer is formed, the PN junction has not been formed on the top surface of the silicon wafer. At this time, even if phosphorus is plated onto the top surface, it will not affect the performance of the solar cell wafer. Moreover, the present invention also omits the step of additionally setting a protective layer, thereby omitting redundant processes and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to better understand the above and other objects, features, advantages and functions of the present invention, reference may be made to the preferred embodiments shown in the accompanying drawings. The same reference numerals in the drawings refer to the same components. Those skilled in the art should understand that the drawings are intended to schematically illustrate the preferred embodiments of the present invention and have no restrictive effect on the scope of the present invention. The components in the drawings are not drawn to scale.

[0038] Figure 1 Is a flowchart of a manufacturing method according to a preferred embodiment of the present invention;

[0039] Figure 2 Is a top view of a crystalline silicon solar cell wafer according to a preferred embodiment of the present invention;

[0040] Figure 3 Is Figure 1Schematic diagram after the cross-sectional view taken along line A-A of the present invention is rotated clockwise by 90°. Detailed implementation manners

[0041] Now referring to the accompanying drawings, the detailed implementation manners of the present invention will be described in detail. What is described here is only the preferred implementation manner of the present invention, and those skilled in the art can think of other ways to implement the present invention based on the preferred implementation manner, and those other ways also fall within the scope of the present invention.

[0042] The present invention provides a method for manufacturing a crystalline silicon solar cell and a crystalline silicon solar cell. Figure 1 The flowchart showing the method for manufacturing a crystalline silicon solar cell is Figure 2 and Figure 3 is the schematic diagram of the crystalline silicon solar cell.

[0043] Figure 1 The schematic diagram showing the method for manufacturing a crystalline silicon solar cell according to a preferred implementation manner of the present invention is shown, and this method sequentially includes steps S1 to S6.

[0044] S1 is a pre-treatment step. It includes sub-steps such as S11 and S12 (not shown).

[0045] S11 is, for example, the step of setting an N-type silicon wafer, which includes the processes of cleaning and texturing the N-type silicon wafer to remove metal ions and the cutting damage layer on the surface of the N-type silicon wafer.

[0046] S12 is, for example, the step of setting a silicon dioxide tunneling layer on the bottom surface of the N-type silicon wafer. This step can be achieved, for example, by at least one of thermal oxidation, ozone, wet oxidation, and ALD methods, and the silicon dioxide tunneling layer can be formed to have a thickness of 0.5 nm - 3 nm.

[0047] S2 is the step of setting an N-type polysilicon passivation layer (or doped silicon carbide passivation layer) on the bottom surface of the silicon dioxide tunneling layer. This step can be achieved, for example, by at least one of the LPCVD method, PECVD method, ion implantation method, and ALD method, and the thickness of the N-type passivation layer can be formed to be 20 nm - 300 nm. In this step, part of the phosphorus will be deposited by plating around to the edges and top surface of the N-type silicon wafer.

[0048] S3 is the step of etching the edges and top surface of the N-type silicon wafer, and this step can remove the phosphorus deposited by plating around to the edges and top surface of the N-type silicon wafer in step S2. This etching can be achieved, for example, by chemical wet and / or dry etching methods.

[0049] S4 is the step of boron doping on the top surface of the N-type silicon wafer. Boron doping on the top surface of the N-type silicon wafer can form a P-type doped layer on the top surface of the N-type silicon wafer, and a structure similar to a PN junction can be formed between the P-type doped layer and the N-type silicon wafer. The step of boron doping is achieved by thermal diffusion or ion implantation methods, so that the sheet resistance of the surface of the P-type doped layer is 40 Ω / sq - 300 Ω / sq. In this step, part of the boron will be deposited by plating around to the edge of the N-type silicon wafer and the bottom surface of the N-type polysilicon passivation layer.

[0050] S5 is the step of etching the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer. This step can remove the boron deposited by plating around to the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer. This step can be achieved, for example, by chemical wet and / or dry etching methods.

[0051] Since the diffusion coefficient of phosphorus is larger than that of boron, the phosphorus deposited by plating around to the top surface of the N-type silicon wafer usually destroys the P-type doped layer and the PN junction during the preparation of the N-type passivation layer. However, in the present invention, since the step of setting the N-type passivation layer is before the step of boron doping on the top surface of the N-type silicon wafer, the P-type doped surface and the PN junction have not been formed on the top surface of the N-type silicon wafer when the N-type passivation layer is generated. Therefore, even if phosphorus is deposited by plating around to the top surface of the N-type silicon wafer at this time, it will not affect the performance of the solar cell. Moreover, the present invention also omits the step of additionally setting a protective layer, thus omitting redundant processes and reducing costs.

[0052] S6 is the subsequent processing step. This step may include sub-steps such as S61 to S62 (not shown).

[0053] S61 can be, for example, the step of setting a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the alumina passivation film and the bottom surface of the N-type passivation layer. Preferably, the thickness of the silicon nitride antireflection film, the silicon oxynitride antireflection film or the silicon carbide antireflection film can be 70 nm - 200 nm.

[0054] S62 can be, for example, the step of printing grid lines, or the step of printing electrodes. In this step, one or more of silver, gold, copper, aluminum, and nickel can be used to print main grid lines and sub-grid lines on the top surface and the bottom surface of the substrate wafer. Figure 3 The grid lines shown in are sub-grid lines.

[0055] Figure 2 and Figure 3 shows a schematic diagram of the crystalline silicon solar cell 1 manufactured according to the above method. The crystalline silicon solar cell 1 includes a substrate wafer and grid lines provided on the top surface and the bottom surface of the substrate wafer. Refer to Figure 3, the substrate sheet includes an N-type silicon wafer 2, an alumina passivation layer 4, a silicon dioxide tunneling layer 6 pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer 2, and an N-type passivation layer 7 pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer 2. The grid lines include sub-grid lines and main grid lines, which can be made of one or more of metals such as silver, gold, copper, aluminum, nickel, etc. Figure 3 The top-side sub-grid line 8 located on the top side of the N-type silicon wafer 2 and the bottom-side sub-grid line 9 located on the bottom side of the N-type silicon wafer 2 are shown in Figure 3 .

[0056] Among them, the thickness of the N-type silicon wafer 2 is 100 μm - 220 μm, the top surface of the N-type silicon wafer 2 is a P-type doped layer 3, the P-type doped layer is a structural layer configured after the N-type passivation layer 7 is prepared, and a structure similar to a PN junction is formed between the N-type silicon wafer 2 and the P-type doped layer 3. The alumina passivation layer 4 is disposed on the P-type doped layer 3 and the thickness of the alumina passivation layer 4 is approximately 1 nm - 20 nm. The silicon dioxide tunneling layer 6 is disposed on the bottom surface of the N-type silicon wafer 2 and its thickness is approximately 0.5 nm - 3 nm.

[0057] The N-type passivation layer 7 is disposed on the bottom surface of the silicon dioxide tunneling layer 6, and the N-type passivation layer 7 is a passivation layer doped with phosphorus, which can protect the silicon dioxide tunneling layer 6 and can provide a passivation effect on the crystalline silicon solar cell wafer 1. The thickness of the N-type polysilicon passivation layer 7 can be, for example, 20 nm - 300 nm.

[0058] Preferably, a silicon nitride antireflection film 5 (or silicon oxynitride antireflection film, silicon carbide antireflection film) can also be disposed on the top surface of the alumina passivation layer 4 and the bottom surface of the N-type passivation layer 7. The thickness of the silicon nitride antireflection film 5 can be, for example, 70 nm - 200 nm.

[0059] The present invention provides a method for manufacturing a crystalline silicon solar cell wafer and a crystalline silicon solar cell wafer, in which an N-type passivation layer is formed first during the manufacturing process and then boron doping is performed on the surface of the silicon wafer. Therefore, when the N-type passivation layer is formed, a PN junction has not yet been formed on the top surface of the silicon wafer. At this time, even if phosphorus is plated around to the top surface, it will not affect the performance of the solar cell wafer.

[0060] Moreover, the present invention also omits the step of additionally setting a protective layer, thereby omitting redundant processes and reducing costs. The structure of the crystalline silicon solar cell wafer provided by the present invention is relatively simple and easy to manufacture, and the manufacturing method provided by the present invention has a simple process route and is easy to implement.

[0061] The above description of various embodiments of the present invention is provided to a person of ordinary skill in the relevant art for the purpose of description. It is not intended to exclude or limit the present invention to a single disclosed embodiment. As described above, a person of ordinary skill in the art taught above will understand various alternatives and modifications of the present invention. Therefore, although some alternative embodiments are specifically described, a person of ordinary skill in the art will understand or relatively easily develop other embodiments. The present invention is intended to include all alternatives, modifications, and variations of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention described above.

[0062] Reference numerals:

[0063] Crystalline silicon solar cell 1

[0064] N-type silicon wafer 2

[0065] P-type doping layer 3

[0066] Aluminum oxide passivation layer 4

[0067] Silicon nitride antireflection film 5

[0068] Silicon dioxide tunneling layer 6

[0069] N-type passivation layer 7

[0070] Top-side auxiliary grid line 8

[0071] Bottom-side auxiliary grid line 9.

Claims

1. A method for manufacturing a crystalline silicon solar cell, the method comprising providing a substrate sheet and applying grid lines on the top surface and the bottom surface of the substrate sheet, the solar cell comprising an N-type silicon wafer, an N-type passivation layer on the bottom surface of the N-type silicon wafer, and a P-type doping layer formed by a boron doping step on the top surface of the N-type silicon wafer, the N-type passivation layer being an N-type polysilicon passivation layer or a doped silicon carbide passivation layer, characterized in that, When setting the crystalline silicon solar cell, the N-type passivation layer is prepared before boron doping the top surface of the N-type silicon wafer.

2. The method according to claim 1, characterized in that, The method sequentially includes the following steps: setting an N-type silicon wafer; setting a tunneling layer on the bottom surface of the N-type silicon wafer; setting an N-type passivation layer on the bottom surface of the tunneling layer, where the N-type passivation layer is a polysilicon passivation layer or a doped silicon carbide passivation layer; etching the edges and the top surface of the N-type silicon wafer to remove phosphorus thereon; Performing boron doping or ion implantation on the top surface of the N-type silicon wafer to form a P-type doping layer on the top surface of the N-type silicon wafer.

3. The method according to claim 2, characterized in that, The method further includes the following steps after the step of performing boron doping on the top surface of the N-type silicon wafer: etching the edges of the N-type silicon wafer and the bottom surface of the N-type polysilicon passivation layer to remove boron thereon.

4. The method according to claim 3, characterized in that, The steps of etching the edges and the top surface of the N-type silicon wafer and etching the edges of the N-type silicon wafer and the bottom surface of the N-type polysilicon passivation layer are realized by chemical wet etching and / or dry etching methods.

5. The method according to claim 3, characterized in that, The method further includes: after etching the bottom surface of the N-type polysilicon passivation layer to remove boron, setting an aluminum oxide passivation film on the top surface of the P-type doping layer.

6. The method according to claim 5, characterized in that, The method further includes the following steps after the step of setting the aluminum oxide passivation film: setting a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the aluminum oxide passivation film and the bottom surface of the N-type passivation layer.

7. The method according to claim 6, characterized in that, The silicon nitride antireflection film, the silicon oxynitride antireflection film or the silicon carbide antireflection film is set by PECVD method, and the thickness of the silicon nitride antireflection film, the silicon oxynitride antireflection film or the silicon carbide antireflection film is formed to be 70nm - 200nm.

8. The method according to claim 2, characterized in that, The tunneling layer is a silicon dioxide tunneling layer, and the step of setting the silicon dioxide tunneling layer includes: preparing the silicon dioxide tunneling layer by using at least one of thermal oxidation, ozone, wet oxidation and ALD methods, and making the thickness of the silicon dioxide tunneling layer be 0.5nm - 3nm.

9. The method according to claim 2, characterized in that, The step of setting the N-type passivation layer includes: preparing the N-type passivation layer by using at least one of LPCVD method, PECVD method, ion implantation method, ALD method, and making the thickness of the N-type passivation layer be 20nm - 300nm.

10. The method according to claim 2, characterized in that, The step of boron doping is realized by thermal diffusion or ion implantation method, so that the surface sheet resistance of the P-type doping layer is 40Ω / □ - 300Ω / □.

11. The method according to claim 2, characterized in that, There is no step of setting a protective layer on the top surface of the N-type silicon wafer before setting the N-type passivation layer.

12. A crystalline silicon solar cell manufactured by the method according to any one of claims 1-11, characterized in that, The crystalline silicon solar cell includes: an N-type silicon wafer; a tunneling layer pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer, the tunneling layer being disposed on the bottom surface of the N-type silicon wafer; an N-type passivation layer pre-configured before configuring the structural layer on the top surface of the N-type silicon wafer, the N-type passivation layer being a polysilicon passivation layer or a doped silicon carbide passivation layer, the N-type passivation layer being disposed on the bottom surface of the tunneling layer; a P-type doping layer configured after preparing the N-type passivation layer, the P-type doping layer being disposed on the top surface of the N-type silicon wafer; an aluminum oxide passivation layer, the aluminum oxide passivation layer being disposed on the top surface of the P-type doping layer.

13. The crystalline silicon solar cell according to claim 12, characterized in that, It further includes a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the aluminum oxide passivation layer and on the bottom surface of the N-type passivation layer.

14. The crystalline silicon solar cell according to claim 12, characterized in that, The tunneling layer is a silicon dioxide tunneling layer, and the thickness of the silicon dioxide tunneling layer is 0.5 nm - 3 nm.

15. The crystalline silicon solar cell according to claim 12, characterized in that, The thickness of the N-type passivation layer is 20 nm - 300 nm.

16. The crystalline silicon solar cell according to claim 13, characterized in that, The thickness of the silicon nitride antireflection film is 70 nm - 200 nm.

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