Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention relates to a semiconductor device manufacturing method and a semiconductor device, the semiconductor device manufacturing method comprising: forming an organic insulating layer on a semiconductor on which a metal wiring is provided, the organic insulating layer having an opening to expose a portion of the metal wiring; forming a seed metal layer, the seed metal layer covering the portion of the metal wiring exposed from the opening, the inner side surface of the opening of the organic insulating layer, and the peripheral edge of the opening of the organic insulating layer; forming a mask, the mask covering the edge of the seed metal layer and exposing a portion of the seed metal layer formed in the opening; and forming a barrier metal layer on the seed metal layer exposed from the mask by electroless plating. The mask comprises an organic material or an inorganic dielectric material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Japanese application No. JP2018-175212 filed on September 19, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0004] Japanese Unexamined Patent Publication 2005-150578 discloses a technology related to a semiconductor device and a method for manufacturing a semiconductor device. According to the manufacturing method disclosed in Japanese Unexamined Patent Publication 2005-150578, a conductive film (including a Ti film and a Pd film in order from bottom to top) is used as a base film of a gold bump (Au bump) for redistribution (UBM: Bump Under Metal). The Ti film and the Pd film are deposited by sputtering. When the redistributed resistance causes a problem, an Au film is formed on the Pd film to form a redistribution structure having Ti, Pd, and Au stacked in order from bottom to top.

[0005] Japanese Unexamined Patent Publication 2007-251158 discloses a technique related to a bump forming method. According to the bump forming method disclosed in Japanese Unexamined Patent Publication 2007-251158, a diffusion barrier film pattern is formed on a substrate on which a conductive pad is formed, and then a seed film is formed. Next, a conductive bump is formed on the seed film, and the seed film is patterned using the conductive bump as an etching mask. A diffusion barrier film pattern is formed on the diffusion barrier film by dry etching, and a seed film pattern is formed on the seed film by wet etching.

[0006] Japanese Unexamined Patent Publication 2017-130527 discloses a technology related to a semiconductor device. In the semiconductor device disclosed in Japanese Unexamined Patent Publication 2017-130527, a source electrode formed on the upper end surface side of a semiconductor substrate is covered with two types of passivation films (a hard passivation film and a passivation film). The passivation films covering the source electrodes each have an opening, and the UBM used as a barrier film is formed to be wider than the opening.

[0007] In order to mount the semiconductor device on a substrate or the like in a flip chip manner, a ball grid array (BGA) package can be used. A solder bump is formed on the wiring layer of such a semiconductor device (see, for example, Japanese Unexamined Patent Publication 2005-150578, Japanese Unexamined Patent Publication 2007-251158, and Japanese Unexamined Patent Publication 2017-130527). In order to suppress the mutual diffusion of the metal material between the solder and the wiring layer, a barrier metal layer (UBM) is provided between the wiring layer and the solder bump. In addition, an insulating film such as polyimide is provided on the semiconductor region. Summary of the invention

[0008] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes: forming an organic insulating layer on a semiconductor on which a metal wiring is provided, the organic insulating layer having an opening to expose a portion of the metal wiring; forming a seed metal layer, the seed metal layer covering the portion of the metal wiring exposed from the opening, the inner side of the opening of the organic insulating layer, and the peripheral portion of the opening of the organic insulating layer; forming a mask covering an edge of the seed metal layer and exposing a portion of the seed metal layer formed in the opening; and forming a barrier metal layer on the seed metal layer exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing and other objects, aspects and advantages will be better understood through the following detailed description of preferred embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a plan view showing a semiconductor device 1A according to a first embodiment;

[0011] Figure 2 is along Figure 1 An enlarged view of a cross section taken along line II-II shown in FIG. 1 (for a basic structure of solder ball 17);

[0012] Figure 3A and 3B is a cross-sectional view showing a step according to a method for manufacturing the semiconductor device 1A;

[0013] Figure 4 is a cross-sectional view showing a step according to a method for manufacturing the semiconductor device 1A;

[0014] Figure 5 is an enlarged cross-sectional view showing a basic structure of a solder ball 17 used in the semiconductor device according to the second embodiment.

[0015] Figures 6A to 6C are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to a second embodiment;

[0016] Figures 7A to 7C is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification;

[0017] Figures 8A to 8C is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification;

[0018] Fig. 9A and 9B is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification;

[0019] Fig. 10A and 10B is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification;

[0020] Fig.11A and 11B is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification; and

[0021] Fig.12 is an enlarged cross-sectional view of a basic structure for a solder ball 17 manufactured according to a conventional method. DETAILED DESCRIPTION

[0022] Problems to be solved by the present disclosure

[0023] When the adhesion between the barrier metal layer and the insulating film used as UBM is low, the following problem occurs, that is, due to the thermal stress generated when, for example, solder balls are installed, the barrier metal layer is easily separated from the insulating film. In particular, when the insulating film contains an organic insulator such as polyimide, the above-mentioned problem tends to occur significantly due to the large difference in thermal expansion coefficient between the barrier metal layer and the organic insulator. When a gap is generated between the barrier metal layer and the insulating film, solder may invade the gap. When the solder invades the gap, fracture is likely to occur at the interface between the barrier metal layer and the wiring layer, which deteriorates the reliability of the semiconductor device. This phenomenon occurs at the interface between the barrier metal layer and the wiring layer, and therefore, even when the barrier metal layer becomes thicker, the phenomenon cannot be eliminated.

[0024] One aspect of the present disclosure is a method for manufacturing a semiconductor device, the method comprising: a first step of forming an organic insulating layer on a surface of a semiconductor region provided with a metal wiring, the organic insulating layer having an opening to expose a portion of the metal wiring; a second step of forming a seed metal layer, the seed metal layer covering the portion of the metal wiring exposed from the opening, the inner side of the opening of the organic insulating layer, and the periphery of the opening of the organic insulating layer; a third step of forming a mask covering an edge of the seed metal layer and exposing a portion of the seed metal layer formed in the opening; and a fourth step of forming a barrier metal layer on the seed metal layer exposed from the mask by electroless plating. The mask mainly contains an organic material or an inorganic dielectric material.

[0025] Effects of the present disclosure

[0026] According to one aspect of the present disclosure, a semiconductor device manufacturing method and a semiconductor device enable reduction of cracking at an interface between a barrier metal layer and a wiring layer caused by solder intrusion and improvement of reliability.

[0027] Description of the embodiments of the present disclosure

[0028] Specific examples of semiconductor devices and methods for manufacturing the same according to embodiments of the present disclosure will be described below with reference to the accompanying drawings. In addition, it should be understood that the present disclosure is not limited to these examples, but is limited by the scope of the claims, and includes all modifications within the meaning and scope equivalent to the claims. In the following description, in the description of the drawings, the same elements are represented by the same reference numerals, and redundant explanations are omitted.

[0029] (First embodiment)

[0030] Figure 1 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 1 As shown in FIG. 1 , the semiconductor device 1A of the present embodiment is a BGA type semiconductor device having a plurality of solder balls 17 provided on the surface of a semiconductor region 10. The plurality of solder balls 17 are arranged on one face of the semiconductor region 10 in a grid pattern.

[0031] Figure 2 is along Figure 1 An enlarged view of the cross section taken along the line II-II shown in FIG. Figure 2 As shown in FIG. 1 , the semiconductor device 1A includes a semiconductor region 10, a metal wiring 12 provided on the surface of the semiconductor region 10, an inorganic insulating layer 11 and an organic insulating layer 14 provided on the surface of the semiconductor region 10. In addition, the semiconductor device 1A includes an inorganic insulating layer 13, a seed metal layer 15, a barrier metal layer 16 and a solder ball 17.

[0032] For example, the semiconductor region 10 of the nitride semiconductor device includes a channel layer made of gallium nitride (GaN) and a barrier layer made of aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN). The semiconductor device 1A having such a configuration constitutes a high electron mobility transistor (HEMT). Note that the semiconductor region 10 may include a semiconductor layer for a field effect transistor (FET) other than the HEMT or for any other semiconductor functional device.

[0033] The metal wiring 12 is provided on the inorganic insulating layer 11. The metal wiring 12 is connected to an electrode (e.g., a source electrode and a drain electrode) in ohmic contact with the semiconductor region 10 or an electrode (e.g., a gate electrode) in Schottky contact with the semiconductor region 10. The metal wiring 12 is made of a metal such as gold (Au). The inorganic insulating layer 11 is placed between the metal wiring 12 and the semiconductor region 10. The inorganic insulating layer 11 is made of a silicon compound such as silicon nitride (SiN). The thickness of the metal wiring 12 is, for example, in the range of 0.5 μm to 3.0 μm.

[0034] The inorganic insulating layer 13 is, for example, an insulating silicon compound layer, and is, as an example, a SiN layer or a SiO2 layer. The inorganic insulating layer 13 is provided on the entire semiconductor region 10 and covers the first inorganic insulating layer 11 and the metal wiring 12. The inorganic insulating layer 13 is in contact with the inorganic insulating layer 11. In addition, the inorganic insulating layer 13 has an opening 13a on the metal wiring 12 to expose a portion of the metal wiring 12. When viewed in the thickness direction of the semiconductor region 10, the opening 13a overlaps with the solder ball 17. The thickness of the inorganic insulating layer 13 is, for example, in the range of 0.03 μm to 3 μm.

[0035] The organic insulating layer 14 is, for example, a polyimide layer. The organic insulating layer 14 is provided on the entire surface of the semiconductor region 10 and covers the inorganic insulating layer 11 and the metal wiring 12. According to the present embodiment, the organic insulating layer 14 is provided on the inorganic insulating layer 13 and is in contact with the inorganic insulating layer 13. Similar to the inorganic insulating layer 13, the organic insulating layer 14 has an opening 14a on the metal wiring 12 to expose a portion of the metal wiring 12. When viewed in the thickness direction of the semiconductor region 10, the opening 14a is aligned with the opening 13a of the inorganic insulating layer 13 and overlaps with the solder ball 17. The thickness of the organic insulating layer 14 is, for example, in the range of 1 μm to 6 μm.

[0036] The seed metal layer 15 is, for example, a layer made of a metal such as titanium (Ti) or palladium (Pa). In one example, the seed metal layer 15 includes a Ti layer and a Pd layer disposed on the Ti layer. With this configuration, the thickness of the Ti layer is, for example, in the range of 0.005 μm to 0.1 μm, and has a thickness of 50 nm as an example. In addition, the thickness of the Pd layer is, for example, in the range of 0.01 μm to 0.5 μm, and has a thickness of 100 nm as an example. When the barrier metal layer 16 is formed by electroless plating, the seed metal layer 15 is used as a seed metal. In addition, when the barrier metal layer 16 contains Ni (or NiCr) and the metal wiring 12 contains Au, the seed metal layer 15 prevents Ni (or NiCr) and Au from forming an alloy.

[0037] The seed metal layer 15 covers the portion of the metal wiring 12 exposed from the openings 13a, 14a, the inner side surface of the opening 13a of the inorganic insulating layer 13, the inner side surface of the opening 14a of the organic insulating layer 14, and the surface 14b of the organic insulating layer 14 on the periphery of the opening 14a. According to the present embodiment, the seed metal layer 15 is in contact with the portion of the metal wiring 12 exposed from the openings 13a, 14a, the inner side surface of the opening 13a of the inorganic insulating layer 13, the inner side surface of the opening 14a of the organic insulating layer 14, and the surface 14b of the organic insulating layer 14 on the periphery of the opening 14a.

[0038] The barrier metal layer 16 is a layer made of a metal such as nickel (Ni) or a nickel-chromium alloy (NiCr). The barrier metal layer 16 is provided to prevent mutual diffusion of solder constituting the solder ball 17 and gold (Au) constituting the metal wiring 12. The barrier metal layer 16 is provided on the seed metal layer 15 and in contact with the seed metal layer 15. When the barrier metal layer 16 is a Ni layer, the thickness of the barrier metal layer 16 is, for example, in the range of 3 μm to 6 μm.

[0039] When viewed in the thickness direction of the barrier metal layer 16, the edge (outer edge) 16a of the barrier metal layer 16 is located inside the edge (outer edge) 15a of the seed metal layer 15 (positioned closer to the opening 14a than the edge 15a of the metal layer 15). In other words, when viewed in the thickness direction of the barrier metal layer 16, the barrier metal layer 16 is disposed inside the seed metal layer 15. The edge 16a of the barrier metal layer 16 does not extend beyond the edge 15a of the seed metal layer 15, so that the barrier metal layer 16 and the organic insulating layer 14 do not contact each other (are separated from each other). The distance W1 from the edge 15a of the seed metal layer 15 to the edge 16a of the barrier metal layer 16 is, for example, in the range of 4 μm to 8 μm. Note that, for example, the seed metal layer 15 and the barrier metal layer 16 have a circular shape in a plan view.

[0040] The solder ball 17 has a substantially spherical structure made of metal such as an alloy of tin and silver (Sn—Ag). The solder ball 17 is disposed on the barrier metal layer 16 and covers the entire barrier metal layer 16. The solder ball 17 may partially contact the seed metal layer 15.

[0041] A method for manufacturing the above-described semiconductor device 1A will be described below. Figure 3A , Figure 3B and Figure 4 2 are cross-sectional views showing steps according to a method for manufacturing the semiconductor device 1A.

[0042] First, epitaxial growth of the semiconductor region 10 is performed on the substrate. This growth is performed by, for example, metal organic chemical vapor deposition (MOCVD). Next, electrodes (not shown) (for example, gate electrode, source electrode, and drain electrode) are formed on the semiconductor region 10. A resist mask having an opening is formed on the semiconductor region 10, a metal used as an electrode material is vapor-deposited in the opening of the resist mask and on the resist mask, and the metal on the resist mask is removed (stripped) together with the resist mask, thereby forming an electrode.

[0043] Then, if Figure 3A As shown in FIG. 1 , an inorganic insulating layer 11 is formed on a semiconductor region 10. The inorganic insulating layer 11 can be formed by, for example, plasma CVD. Subsequently, a metal wiring 12 having a predetermined planar pattern is formed on the inorganic insulating layer 11 by, for example, electroplating. At this time, the metal wiring 12 and the electrode are connected to each other through an opening formed in the inorganic insulating layer 11.

[0044] Subsequently, an inorganic insulating layer 13 and an organic insulating layer 14 are formed on the surface of the semiconductor region 10 provided with the metal wiring 12 (first step). The inorganic insulating layer 13 is formed by, for example, plasma CVD. The organic insulating layer 14 is formed by, for example, spin-coating the material of the organic insulating layer 14 (for example, polyimide) on the semiconductor region 10. Then, a mask (not shown) having openings corresponding to the openings 13a, 14a is formed on the organic insulating layer 14, and the organic insulating layer 14 is etched through the mask to form the opening 14a. The material of the mask is, for example, SiN or SiO2. The opening of the mask is formed by photolithography or electron beam lithography. Thereafter, the inorganic insulating layer 13 is etched through the opening 14a to form the opening 13a. Note that the openings 13a, 14a can be formed by dry etching using plasma.

[0045] Subsequently, the exposed portion of the metal wiring 12 from the openings 13a, 14a, the inner side of the opening 14a of the organic insulating layer 14, the inner side of the opening 13a of the inorganic insulating layer 13, and the periphery of the opening 14a of the organic insulating layer 14 are covered with the seed metal layer 15 (second step). Like each electrode, the seed metal layer 15 is formed by vapor deposition and stripping. That is, a resist mask is formed on the organic insulating layer 14, the resist mask having an opening corresponding to the plane position and plane shape of the seed metal layer 15. Then, the metal used as the material of the seed metal layer 15 is vapor deposited in the opening of the resist mask and on the resist mask, and the metal on the resist mask is removed (stripped) together with the resist mask.

[0046] Subsequently, a mask R is formed on the organic insulating layer 14 (third step). The mask R has an opening Ra on the seed metal layer 15, and the diameter of the opening Ra is larger than the opening 14a and smaller than the seed metal layer 15. Therefore, when viewed in the thickness direction of the semiconductor region 10, the opening Ra is located in the seed metal layer 15, and the mask R covers the edge 15a of the seed metal layer 15 around a portion of the opening Ra. The distance W2 between the inner side surface of the opening Ra of the mask R and the edge 15a of the seed metal layer 15 is, for example, in the range of 4 μm to 8 μm. In addition, the opening Ra of the mask R exposes a portion of the seed metal layer 15 formed in the openings 13a, 14a.

[0047] The mask R mainly contains an organic material. For example, the mask R contains a negative resist. As an example, the mask R is made of a negative resist. With such a configuration, the negative resist is applied to the organic insulating layer 14 and the seed metal layer 15, and the area other than the area corresponding to the opening Ra is exposed and developed, thereby allowing only the unexposed area Ra corresponding to the opening to be removed.

[0048] Then, if Figure 3B As shown in FIG. 1 , the barrier metal layer 16 is formed on the seed metal layer 15 exposed from the opening Ra of the mask R (the fourth step). At this time, the barrier metal layer 16 is formed by electroless plating using the seed metal layer 15 as a seed metal. Specifically, the barrier metal layer 16 is formed by electroless plating (e.g., autocatalytic electroless plating) using hypophosphite as a catalyst for autocatalytic plating. The reason for using electroless plating is that electroless plating is more reliable than electroplating.

[0049] Electroless plating is a method of applying plating without using an external power source, and examples of electroless plating include displacement plating using an ionization tendency, autocatalytic electroless plating (reduction plating) using a reducing agent, and displacement reduction plating as a combination of displacement plating and reduction plating. Although autocatalytic electroless plating is used here, another electroless plating can be used. On the other hand, electroplating is a method for applying plating by using an external power source to cause current to flow between electrodes to supply electrons from the cathode.

[0050] In this step, the exposed surface of the seed metal (seed metal layer 15) for electroless plating is defined by the mask R. Therefore, the barrier metal layer 16 grows in the region defined by the mask R (in the opening Ra). The mask R restricts the lateral growth of the barrier metal layer 16. As a result, the opening Ra is filled with the barrier metal layer 16.

[0051] Subsequently, an Au layer 51 is formed on the barrier metal layer 16 (see Figure 2 ). The Au layer 51 is formed by, for example, electroless plating, electroplating, vapor deposition and lift-off or sputtering. Figure 4 As shown in FIG. 1 , the mask R is removed. After the mask R is removed, the surface of the organic insulating layer 14 may be irradiated with oxygen plasma for a short time. This allows the organic components of the organic insulating layer 14 to react with oxygen to make the surface condition of the organic insulating layer 14 better.

[0052] Thereafter, solder balls 17 are formed on the barrier metal layer 16 (on the Au layer 51) (see FIG. Figure 2 ) (Fifth step). In this step, after applying the flux, a solder ball 17 having a diameter of, for example, 160 μm is formed by performing reflow soldering (heat treatment) at, for example, 250° C. In this step, Au formed continuously with the seed metal layer 15 is almost entirely diffused into the solder ball 17. Thereafter, the flux is washed off. Through the above steps, a solder ball 17 having a diameter of, for example, 160 μm is manufactured. Figure 1 and Figure 2 A semiconductor device 1A of this embodiment is shown in FIG.

[0053] A description will be given of the effects obtained by the method of manufacturing the semiconductor device 1A according to the present embodiment described above and the problems of the conventional manufacturing method. Fig.12 is an enlarged cross-sectional view of the basic structure of the solder ball 17 manufactured according to the conventional method. Figure 3A The barrier metal layer 16 is formed under the mask R shown in FIG. With this configuration, as shown in FIG. Fig.12 As shown in FIG. 1 , the barrier metal layer 16 grows laterally beyond the seed metal layer 15 and reaches the organic insulating layer 14 not covered by the seed metal layer 15 .

[0054] Generally, a BGA type semiconductor device is mounted on a printed wiring board having a wiring pattern according to BGA. In many cases, a printed wiring board is formed using a resin substrate as a base. On the other hand, the substrate of the semiconductor device is made of a semiconductor or an inorganic insulator. Therefore, the difference in thermal expansion coefficient between the printed wiring board and the substrate of the semiconductor device is large, and thus changes in temperature during the formation of the solder ball 17, changes in ambient temperature under the use environment, and the like apply stress to the printed wiring board and the substrate of the semiconductor device. Generally, since the semiconductor device is smaller than the printed wiring board, it is assumed that the solder ball absorbs this stress to some extent, but some stress is also applied to the substrate of the semiconductor device. This stress causes the basic structure of the solder ball to separate from the semiconductor device. In particular, as Fig.12 As shown in FIG. 1 , when there is a portion where the seed metal layer 15 is not interposed between the organic insulating layer 14 and the barrier metal layer 16, the barrier metal layer 16 is easily separated from the organic insulating layer 14 because the difference in thermal expansion coefficient between the organic insulating layer 14 and the barrier metal layer 16 is large and the adhesion between the organic insulating layer 14 and the barrier metal layer 16 is low. Note that the thermal expansion coefficient of the polyimide constituting the organic insulating layer 14 is approximately 25×10 -6 / °C, and the thermal expansion coefficient of Ni constituting the barrier metal layer 16 is 13×10 -6 / ℃ to 16×10 -6 / ℃ range.

[0055] In order to solve such a problem, according to the present embodiment, during the manufacture of the semiconductor device 1A, a mask R covering the edge 15a of the seed metal layer 15 is formed, and the barrier metal layer 16 is allowed to grow only within the opening Ra of the mask R. This allows only the longitudinal growth of the barrier metal layer 16 and restricts the lateral growth of the barrier metal layer 16. Therefore, it is possible to prevent the barrier metal layer 16 from growing onto the organic insulating layer 14 beyond the edge 15a of the seed metal layer 15. Therefore, according to the present embodiment, it is possible to reduce the fracture at the interface between the barrier metal layer 16 and the metal wiring 12 due to the invasion of solder, and then improve the reliability of the semiconductor device 1A. In addition, according to the present embodiment, it is only necessary to add the steps of forming and removing the mask R to the conventional manufacturing method, and thus it is possible to suppress the increase in the number of manufacturing steps.

[0056] The mask R of the present embodiment mainly contains an organic material. It is also conceivable that the mask R is made of a metal such as Cu, but using an organic material to form the mask R brings the following advantages. That is, when the barrier metal layer 16 is made thicker to further improve the reliability of the semiconductor device, the mask R needs to be made thicker accordingly. Compared with metals, organic materials have low rigidity and high flexibility, so that even when the mask R is made thicker, the mask R is not easily affected by environmental stress.

[0057] After the step of forming the barrier metal layer 16, a step of forming the solder ball 17 on the barrier metal layer 16 may be provided. When the solder ball 17 is formed, there is a large temperature change due to the reflow soldering. According to the manufacturing method of the present embodiment, even in this case, it is possible to prevent the barrier metal layer 16 from being separated and improve the reliability of the semiconductor device 1A.

[0058] After the step of forming the barrier metal layer 16, the step of forming the Au layer 51 on the barrier metal layer 16 may be provided without interruption. This makes it possible to increase the wettability of the surface of the barrier metal layer 16 facing the solder ball 17 and thus facilitate the formation of the solder ball 17. The subsequent heat treatment step diffuses almost all of the Au layer 51 into the solder ball 17 and eventually causes the Au layer 51 to disappear.

[0059] The mask R may include a negative resist, and a step of removing the mask R may be provided after the step of forming the barrier metal layer 16. When a positive resist is used, the resist on the portion irradiated with light during exposure is removed by development, while the portion not irradiated with light during exposure is left. Uneven light irradiation may produce residues in the opening of the resist (i.e., on the seed metal layer 15). The residues may reduce the adhesion between the seed metal layer 15 and the barrier metal layer 16. On the other hand, when a negative resist is used, at the time of development, the resist on the portion irradiated with light during exposure is left, while the portion not irradiated with light during exposure is removed by development. This makes it less likely that residues will be produced in the opening of the resist (i.e., on the seed metal layer 15). Therefore, the reduction in adhesion between the seed metal layer 15 and the barrier metal layer 16 can be suppressed.

[0060] Compared with positive resist, negative resist tends to have low viscosity, short exposure time and low required exposure. Therefore, since negative resist is easy to develop compared with positive resist, residue is less likely to occur. In addition, compared with positive resist, negative resist can be easily dissolved with a remover in a short time, and thus changes in the characteristics of semiconductor device 1A can be suppressed.

[0061] The negative resist is formed thicker to allow the inner side of the opening to be easily formed into a flared shape. When the inner side of the opening of the resist has a flared shape, the barrier metal layer 16 has a trapezoidal shape. On the contrary, when the inner side of the opening of the resist has a tapered shape, the barrier metal layer 16 has an inverted trapezoidal shape. The solder ball 17 formed on the barrier metal layer 16 is combined by wettability, and therefore the barrier metal layer 16 with an inverted trapezoidal shape makes it difficult for the solder ball 17 to reach the side surface of the barrier metal layer 16, making the bonding surface smaller, causing process changes, and causing air to enter to produce a gap. When the barrier metal layer 16 has a trapezoidal shape, the solder ball 17 is bonded to almost the entire surface of the barrier metal layer 16, which eliminates the above-mentioned inconvenience and increases adhesion. As described above, forming the inner side of the opening of the resist into a flared shape allows the shape of the barrier metal layer 16 to be easily changed, and therefore allows the adhesion strength with the solder ball 17 to be improved.

[0062] The barrier metal layer 16 may be a Ni layer and have a thickness in the range of 3 μm to 6 μm. Ni and solder are less likely to diffuse into each other, so Ni is suitable as a base for the solder ball 17. In addition, providing a Ni layer having such a thickness enables further improvement in the reliability of the semiconductor device 1A.

[0063] The seed metal layer 15 may include a Ti layer and a Pd layer disposed on the Ti layer, the Ti layer may have a thickness of 50 nm, and the Pd layer may have a thickness of 100 nm. With this configuration, the presence of the Ti layer increases the adhesion between the seed metal layer 15 and the metal wiring 12, while the presence of the Pd layer allows easy electroless plating on the barrier metal layer 16.

[0064] In the step of forming the mask R, the distance W2 between the edge 15a of the seed metal layer 15 and the inner edge of the mask R may be in the range of 4 μm to 8 μm. This makes it possible to ensure that the distance W1 between the edge 16a of the barrier metal layer 16 and the edge 15a of the seed metal layer 15 is in the range of 4 μm to 8 μm after removing the mask R, thereby satisfactorily obtaining the above-mentioned effect of the present embodiment.

[0065] (Second embodiment)

[0066] Figure 51 is an enlarged cross-sectional view showing the basic structure of the solder ball 17 used for the semiconductor device according to the second embodiment. Note that the solder ball 17 is not shown. The difference between this embodiment and the first embodiment described above is the material of the mask. According to this embodiment, a mask 18 mainly containing an inorganic dielectric material is provided instead of the mask R mainly containing an organic material of the first embodiment. In one example, the mask 18 mainly contains an insulating silicon compound. The insulating silicon compound is, for example, SiN or SiO2. Even after the semiconductor device is manufactured, the mask 18 is left in the semiconductor device. In other words, in addition to the components of the first embodiment, the semiconductor device of this embodiment also includes a mask 18.

[0067] The mask 18 has an opening 18a on the seed metal layer 15, and the diameter of the opening 18a is larger than the opening 14a and smaller than the seed metal layer 15. Therefore, when viewed in the thickness direction of the semiconductor region 10, the opening 18a is in the seed metal layer 15, and the portion of the mask 18 close to the opening 18a covers the edge 15a of the seed metal layer 15. The distance W3 between the inner side surface of the opening 18a of the mask 18 and the edge 15a of the seed metal layer 15 is, for example, in the range of 4 μm to 8 μm. In addition, the opening 18a of the mask 18 exposes the portion of the seed metal layer 15 formed in the openings 13a, 14a. The thickness of the mask 18 is determined according to the thickness of the barrier metal layer 16, and is, for example, in the range of 1.0 μm to 3.5 μm.

[0068] The barrier metal layer 16 is provided on the seed metal layer 15 exposed from the mask 18. The outer side surface (outer edge 16a) of the barrier metal layer 16 is in contact with the inner side surface of the opening 18a of the mask 18 and is located inside the edge 15a of the seed metal layer 15 (closer to the opening 14a than the edge 15a of the seed metal layer 15). In other words, when viewed in the thickness direction of the barrier metal layer 16, the barrier metal layer 16 is provided in the region defined by the mask 18. Note that the mask 18 has, for example, a ring shape in a plan view.

[0069] FIG. 6A to FIG. 6C 1 is a cross-sectional view showing the steps of the semiconductor device manufacturing method according to the present embodiment. First, as in the first embodiment, the semiconductor region 10, the inorganic insulating layer 11, the metal wiring 12, the inorganic insulating layer 13, the organic insulating layer 14 and the seed metal layer 15 are formed in sequence. Next, a mask 18 is formed on the organic insulating layer 14. Specifically, as Fig. 6A As shown in FIG. 1 , first, a film 18A made of the constituent material of the mask 18 is formed on the entire semiconductor region 10. Next, a resist mask is formed on the edge 15a by photolithography. Then, the film 18A exposed from the resist mask is removed by etching. Figure 6B This allows a mask 18 to be formed covering the edge 15a, as shown in . Thereafter, the resist mask is removed.

[0070] Then, if Figure 6C As shown in the figure, a barrier metal layer 16 is formed on the seed metal layer 15 exposed from the mask 18. At this time, the barrier metal layer 16 is formed by electroless plating using the seed metal layer 15 as the seed metal. In this step, the exposed surface of the seed metal (seed metal layer 15) for electroless plating is defined by the mask 18. Therefore, the barrier metal layer 16 grows in the area defined by the mask 18 (in the opening 18a). The mask 18 restricts the lateral growth of the barrier metal layer 16. As a result, the opening 18a is filled with the barrier metal layer 16. The subsequent steps are the same as those in the first embodiment.

[0071] According to the present embodiment, during the manufacture of the semiconductor device, a mask 18 covering the edge 15a of the seed metal layer 15 is formed, and the barrier metal layer 16 is allowed to grow only within the opening 18a of the mask 18. This allows only the longitudinal growth of the barrier metal layer 16 and restricts the lateral growth of the barrier metal layer 16. Therefore, it is possible to prevent the barrier metal layer 16 from growing onto the organic insulating layer 14 beyond the edge 15a of the seed metal layer 15. Therefore, according to the present embodiment, it is also possible to reduce the fracture at the interface between the barrier metal layer 16 and the metal wiring 12 due to the intrusion of the solder, thereby improving the reliability of the semiconductor device 1A.

[0072] According to the present embodiment, unlike the first embodiment, the mask 18 mainly contains an inorganic dielectric material. This configuration allows the mask 18 to be retained without being removed, and thus makes it possible to prevent the edge 15a of the seed metal layer 15 and the vicinity of the edge 15a from being exposed. This in turn makes it possible to suppress the degradation of the periphery of the seed metal layer 15.

[0073] Inorganic dielectric materials (e.g., SiN) and organic materials (e.g., polyimide) have thermal expansion coefficients that are equal to each other. This can reduce stress caused by temperature changes, thereby suppressing the separation of the mask 18 from the organic insulating layer 14, which in turn enables the reliability of the semiconductor device 1A to be further improved. Note that the mask 18 is in contact with the barrier metal layer 16, and the difference in thermal expansion coefficients between the barrier metal layer 16 and the mask 18 is large. Therefore, when the barrier metal layer 16 repeatedly expands and contracts in response to temperature changes, stress is applied to the mask 18. However, even if a crack is formed in the mask 18, the crack will not grow further, so that the adhesion between the mask 18 and the organic insulating layer 14 is maintained, and the intrusion of solder is suppressed.

[0074] An example of a method for further increasing the adhesion between the mask 18 and the organic insulating layer 14 includes changing the film quality in the thickness direction of the mask 18. That is, it is preferred that the density of the inorganic dielectric material of the portion of the mask 18 in contact with the organic insulating layer 14 is low, and the density of the inorganic dielectric material gradually increases with increasing distance from the organic insulating layer 14. Such a mask 18 can be formed by stacking a plurality of layers having different film qualities or by continuously changing the film quality in the thickness direction.

[0075] (Remodel)

[0076] 7A to 11B 1 is a diagram showing steps included in a method for manufacturing a semiconductor device according to a modification of the first embodiment. Fig. 7A As shown in , epitaxial growth of a semiconductor layer 22 is performed on a semiconductor substrate 21 to form a semiconductor region 10. Next, an electrode 23 is formed on the semiconductor layer 22 to form contact with the semiconductor layer 22, and the respective surfaces of the electrode 23 and the semiconductor layer 22 are covered by a passivation film 24. The electrode 23 is, for example, an ohmic electrode. The passivation film 24 is, for example, a SiN film. Then, an opening is formed in the passivation film 24 to expose the electrode 23.

[0077] Next, if Figure 7B As shown in , a polyimide layer 25 (bottom layer) is applied, and a SiN layer 26 is formed on the polyimide layer 25. The thickness of the polyimide layer 25 is, for example, 1.4 μm, and the thickness of the SiN layer 26 is, for example, 100 nm. Then, a resist pattern is formed on the SiN layer 26, and the SiN layer 26 is etched through the resist pattern to form an opening exposing the polyimide layer 25. After the resist pattern is removed, the polyimide layer 25 is etched through the opening of the SiN layer 26 to form an opening exposing the electrode 23.

[0078] Then, if Figure 7C As shown in , a seed metal 27 and a metal wiring 28 (bottom layer) are formed on the electrode 23. The seed metal 27 has a thickness of, for example, 515 nm. The metal wiring 28 is made of, for example, Au and has a thickness of, for example, 1 μm. Specifically, first, the seed metal 27 is vapor-deposited on the entire semiconductor region 10, and when viewed in the thickness direction, a resist pattern having an opening is formed on the seed metal 27, the opening including the opening of the SiN layer 26. Thereafter, the metal wiring 28 is formed in the opening of the resist pattern by electroplating. After the resist pattern is stripped off, a portion of the metal 27 exposed from the metal wiring 28 is removed by etching. Thereafter, heat treatment is performed. The heat treatment temperature is, for example, 350°C. Since the metal immediately after plating is in a so-called sparse state, the heat treatment allows the metal to return to a normal state.

[0079] Then, if Fig. 8A As shown in , SiN layer 29, polyimide layer 30 (intermediate layer) and SiN layer 31 are sequentially formed. Polyimide layer 30 has a thickness of, for example, 2.0 μm, and SiN layer 31 has a thickness of, for example, 130 nm. A resist pattern is formed on SiN layer 31, and SiN layer 31 is etched through the resist pattern to form an opening exposing polyimide layer 30. After the resist pattern is removed, polyimide layer 30 and SiN layer 29 are etched through the opening of SiN layer 31 to form an opening exposing metal wiring 28.

[0080] Then, if Figure 8B As shown in FIG. 1 , a seed metal 32 and a metal wiring 33 (intermediate layer) are formed on the metal wiring 28. The seed metal 32 has a thickness of, for example, 205 nm. The metal wiring 33 is made of, for example, Au and has a thickness of, for example, 1 μm. Note that the method for forming the seed metal 32 and the metal wiring 33 is the same as the method for forming the seed metal 27 and the metal wiring 28 described above.

[0081] Then, if Figure 8C As shown in , the SiN layer 34, the polyimide layer 35, and the SiN layer 36 are sequentially formed. The thickness of the SiN layer 34 is, for example, 300 nm, the thickness of the polyimide layer 35 is, for example, 2.0 μm, and the thickness of the SiN layer 36 is, for example, 300 nm. A resist pattern is formed on the SiN layer 36, and the SiN layer 36 is etched through the resist pattern to form an opening exposing the polyimide layer 35. After the resist pattern is removed, the polyimide layer 35 and the SiN layer 34 are etched through the opening of the SiN layer 36 to form an opening exposing the metal wiring 33.

[0082] Then, if Fig. 9A As shown in FIG. 1 , a seed metal 37 and a metal wiring 38 (intermediate layer) are formed on the metal wiring 33. The seed metal 37 has a thickness of, for example, 205 nm. The metal wiring 38 is made of, for example, Au and has a thickness of, for example, 1 μm. Note that the method for forming the seed metal 37 and the metal wiring 38 is the same as the method for forming the seed metal 27 and the metal wiring 28 described above.

[0083] Then, if Fig. 9B As shown in , a SiN layer 39, a polyimide layer 40 (intermediate layer), and a SiN layer 41 are sequentially formed. The thickness of the SiN layer 39 is, for example, 200 nm, the thickness of the polyimide layer 40 is, for example, 2.0 μm, and the thickness of the SiN layer 41 is, for example, 200 nm. A resist pattern is formed on the SiN layer 41, and the SiN layer 41 is etched through the resist pattern to form an opening exposing the polyimide layer 40. After the resist pattern is removed, the polyimide layer 40 and the SiN layer 39 are etched through the opening of the SiN layer 41 to form an opening exposing the metal wiring 38.

[0084] Then, if Fig. 10A As shown in FIG. 1 , a seed metal 42 and a metal wiring 43 (top layer) are formed on the metal wiring 38. The seed metal 42 has a thickness of, for example, 205 nm. The metal wiring 43 is made of, for example, Au and has a thickness of, for example, 2 μm. Note that the method for forming the seed metal 42 and the metal wiring 43 is the same as the method for forming the seed metal 27 and the metal wiring 28 described above.

[0085] Then, if Fig. 10B As shown in , a SiN layer 44, a polyimide layer 45 (top layer), and a SiN layer 46 are formed in sequence. The thickness of the SiN layer 44 is, for example, 200 nm, the thickness of the polyimide layer 45 is, for example, 6.0 μm, and the thickness of the SiN layer 46 is, for example, 200 nm. A resist pattern is formed on the SiN layer 46, and the SiN layer 46 is etched through the resist pattern to form an opening exposing the polyimide layer 45. After the resist pattern is removed, the polyimide layer 45 and the SiN layer 44 are etched through the opening of the SiN layer 46 to form an opening exposing the metal wiring 43. Note that according to the present modification, the metal wiring 43 corresponds to the metal wiring 12 of the first embodiment, the SiN layer 44 corresponds to the inorganic insulating layer 13 of the first embodiment, and the polyimide layer 45 corresponds to the organic insulating layer 14 of the first embodiment.

[0086] Then, if Fig.11A As shown in , a seed metal layer 15 is formed on the metal wiring 43. Specifically, first, a resist pattern is formed, the resist pattern having an opening including an exposed portion of the metal wiring 43. The metal material of the seed metal layer 15 is vapor-deposited in the opening of the resist pattern and on the resist pattern, and the metal material on the resist pattern is removed (stripped) together with the resist pattern. Note that the composition of the seed metal layer 15 is the same as that in the first embodiment described above.

[0087] Then, if Fig. 11B As shown in FIG. 1 , a mask R having an opening Ra is formed, and a barrier metal layer 16 is formed in the opening Ra by electroless plating. The specific shapes and constituent materials of the mask R and the barrier metal layer 16 are the same as those in the first embodiment described above. The thickness of the barrier metal layer 16 is, for example, in the range of 3 μm to 6 μm. Thereafter, an Au layer 51 is formed on the barrier metal layer 16 by electroless plating (see FIG. 1 ). Figure 1 The thickness of the Au layer 51 is, for example, 10 nm. The mask R is removed, and the solder ball 17 is formed (see FIG. Figure 1 ), and then the semiconductor device is completed.

[0088] The semiconductor device manufacturing method and the semiconductor device according to the present disclosure are not limited to the above-mentioned embodiments, and various other modifications are possible. For example, according to the first embodiment, a photoresist has been given as an example of an organic dielectric material constituting a mask for limiting the lateral growth of a barrier metal layer. Various other materials can be used as organic dielectric materials. In addition, according to the second embodiment, an insulating silicon compound (SiN or SiO2) has been used as an example of an inorganic dielectric material constituting a mask for limiting the lateral growth of a barrier metal layer. Various other materials can be used as inorganic dielectric materials. According to each of the above-mentioned embodiments, HEMT has been given as an example of a semiconductor region, but the manufacturing method according to the present disclosure is not limited to HEMT, and is applicable to various semiconductor devices provided with metal wiring and solder balls.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an organic insulating layer on the semiconductor on which the metal wiring is provided, the organic insulating layer having an opening to expose a portion of the metal wiring; forming a seed metal layer, the seed metal layer covering the portion of the metal wiring exposed from the opening, the inner side surface of the opening of the organic insulating layer, and the peripheral edge of the opening of the organic insulating layer; forming a mask, the mask covering an edge of the seed metal layer and exposing a portion of the seed metal formed in the opening; forming a barrier metal layer on the seed metal exposed from the mask by electroless plating; without removing the mask, forming solder balls on the barrier metal layer and the mask by reflow soldering, Wherein, the mask comprises an inorganic dielectric material.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The solder balls are formed by reflow soldering at 250°C, and The diameter of the solder ball is 160 μm.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising: After forming the barrier metal layer, continuously forming a gold (Au) layer on the barrier metal layer, Wherein, the thickness of the Au layer is 10 nm.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, in, The mask includes an insulating silicon compound.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, in, The barrier metal layer is a nickel (Ni) layer, and a thickness of the Ni layer is 3 μm to 6 μm.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The seed metal layer includes a titanium (Ti) layer and a palladium (Pd) layer on the titanium layer, and The thickness of the titanium layer was 50 nm, and the thickness of the palladium layer was 100 nm.

7. The method for manufacturing a semiconductor device according to claim 1 or 2, in, A distance between the edge of the seed metal layer and an inner edge of the mask is 4 μm to 8 μm.

8. A method for manufacturing a semiconductor device, comprising: forming an organic insulating layer on the semiconductor on which the metal wiring is provided, the organic insulating layer having a first opening to expose a portion of the metal wiring; forming a seed metal layer, the seed metal layer covering the portion of the metal wiring exposed from the first opening and the inner side surface and the peripheral edge portion of the first opening of the organic insulating layer; forming a mask, the mask covering the edge of the seed metal layer and the organic insulating layer, the mask having a second opening to expose a portion of the seed metal layer; and forming a barrier metal layer on the seed metal layer exposed from the second opening of the mask; without removing the mask, forming solder balls on the barrier metal layer and the mask by reflow soldering, Wherein, the barrier metal layer is separated from the organic insulating layer.

9. The method for manufacturing a semiconductor device according to claim 8, in, The solder ball having a diameter of 160 μm was formed by reflow soldering at 250° C.

10. The method for manufacturing a semiconductor device according to claim 8 or 9, further comprising: After forming the barrier metal layer, continuously forming an Au layer on the barrier metal layer, Wherein, the thickness of the Au layer is 10 nm.

11. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein: The mask includes an insulating silicon compound, and The mask remains on the edge of the seed metal layer.

12. The method for manufacturing a semiconductor device according to claim 8 or 9, in, The barrier metal layer is a Ni layer, and the Ni layer has a thickness of 3 μm to 6 μm.

13. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein: The seed metal layer includes a Ti layer and a Pd layer on the Ti layer, and The thickness of the Ti layer was 50 nm, and the thickness of the Pd layer was 100 nm.

14. The method for manufacturing a semiconductor device according to claim 8 or 9, in, A distance between the edge of the seed metal layer and an inner edge of the mask is 4 μm to 8 μm.

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