A chip packaging structure and packaging method thereof

Abstract

The present invention relates to a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. From top to bottom, it comprises a chip (10), a through silicon via (11), a rewiring layer (14), a metal connecting column (21) and a solder ball (24), which transmits the signal received by the chip (10) downward; the through silicon via (11) below the electrode (19) penetrates the silicon substrate (12) from top to bottom and is fixedly connected to the rewiring layer (14); a metal connecting column (21) is arranged below the rewiring layer (14), and the longitudinal section of the metal connecting column (21) is trapezoidal; the encapsulation material layer (20) encapsulates the rewiring layer (14) and the metal connecting column (21), and the solder ball (24) is fixedly connected to the lower surface of the metal connecting column (21). The present invention provides a packaging structure and a packaging method that can improve the mechanical strength of the chip after packaging without increasing the thickness of the silicon wafer.

Description

Technical Field

[0001] The invention relates to a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. Background Art

[0002] Through Silicon Via (TSV) interconnection technology is currently considered to be one of the most advanced technologies in the semiconductor industry. It uses short vertical electrical connections or "Through Silicon Via" through silicon to establish electrical connections from the effective surface of the chip to the back, thereby providing the shortest interconnection path. Through Silicon Via filling is a difficult process for TSV production, and the aspect ratio of TSV is one of the factors affecting the difficult process. In semiconductor products, the thickness of the silicon wafer determines the depth of the through silicon via, and the width of the TSV must meet the design requirements and cannot be increased at will. The thicker the silicon wafer, the deeper the TSV, the more difficult it is to etch the through silicon via, and the more difficult it is to form a continuous insulating layer / seed layer / barrier layer on the sidewall of the through silicon via. At the same time, the easier it is to form holes during the filling process of the through silicon via, the greater the difficulty of filling. In general, this packaging technology has the following difficulties: First, if the thickness of the silicon wafer is thicker, the deeper the through silicon via, the more difficult it is to achieve the etching, insulation, seed layer formation and electroplating filling of the through silicon via during the process, and the cost is higher; Second, if the thickness of the silicon wafer is thinner, the chip has the problem of insufficient mechanical strength and easy to break during use. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a packaging structure and packaging method that does not increase the thickness of the silicon wafer and the difficulty of TSV implementation and processing cost, while improving the mechanical strength of the packaged chip.

[0004] The present invention is achieved in that:

[0005] The present invention provides a chip packaging structure, which includes a chip, a through silicon via, a rewiring layer, a metal connection column and a solder ball from top to bottom, and transmits the signal received by the chip downward;

[0006] The chip comprises a silicon substrate, an electrode and a functional area, wherein the electrode and the functional area are arranged on the front side of the silicon substrate, the rewiring layer is arranged on the lower surface of the chip, a plurality of through silicon vias for transmitting signals are arranged below the electrode, the through silicon vias penetrate the silicon substrate up and down and are fixedly connected to the rewiring layer, a metal connecting column is arranged below the rewiring layer, and the longitudinal section of the metal connecting column is in a trapezoidal shape;

[0007] It also includes an encapsulation material layer, which encapsulates the rewiring layer and the metal connecting column. The lower surface of the metal connecting column is flush with the back of the encapsulation material layer and the lower surface of the metal connecting column is exposed. The solder ball is fixedly connected to the lower surface of the metal connecting column.

[0008] Optionally, the cross-section of the through silicon via includes but is not limited to a square hole and a circular hole.

[0009] Optionally, the number of the electrodes is an even number.

[0010] The present invention provides a packaging method for a chip packaging structure, and the implementation steps are as follows:

[0011] Step 1: Provide a carrier wafer and a wafer with a functional area on the front side, the wafer is a collection of a plurality of chips 10, and use a temporary bonding method to bond the wafer to the carrier wafer through a temporary bonding adhesive;

[0012] Step 2: Thinning the wafer by grinding to form a chip with a functional area on the front side, and thinning the chip to a desired thickness;

[0013] Step 3: Paste or coat a mask material on the back of the chip, form an opening in the mask material by photolithography, form a through-silicon via array at the corresponding electrode according to a pre-designed method by deep silicon etching or laser drilling in the silicon substrate, and remove the mask material;

[0014] An insulating layer is formed on the sidewall of the through silicon via and the back of the chip by sputtering or other processes to insulate the through silicon via from the wafer;

[0015] Step 4: Re-attach or coat the mask material on the back of the chip, fill the metal in the mask pattern opening by electroplating to form a through silicon via, and at the same time form a rewiring layer on the back of the chip according to a pre-set plan;

[0016] A plating seed layer is formed by a sputtering process, and the seed layer covers the sidewalls of the through silicon via and the back of the chip, so as to facilitate electroplating thickening; after the electroplating thickening is completed, the seed layer on the back of the chip is removed by an etching process, and then the above wafer plane is subjected to plasma treatment;

[0017] Step 5: Coating the encapsulation material on the back of the chip by encapsulation to form an encapsulation layer, and thinning the encapsulation layer to a desired thickness by chemical mechanical polishing or grinding;

[0018] Step 6: Using laser drilling, a through hole is formed in the encapsulation material layer according to a pre-designed scheme to expose the lower surface of the rewiring layer;

[0019] Step 7: forming a metal seed layer on the sidewall and bottom of the through hole by a sputtering process;

[0020] Step 8: Fill the through hole by ball planting, the solder in the through hole and the metal seed layer form a metal connection column fixedly connected to the redistribution layer, and a solder ball under the metal connection column, complete the chip packaging, and form a wafer-level package;

[0021] Step nine: separating the carrier wafer from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive;

[0022] Step 10: Use laser or blade to cut the wafer-level package into individual packages.

[0023] Optionally, the metal connecting column is made of one or more of tin, silver and copper.

[0024] Optionally, the thickness of the metal connecting column is 50-200 microns.

[0025] Optionally, the solder ball is made of one or more of tin, silver, and copper.

[0026] Optionally, the through silicon via filling method is half filling or solid filling.

[0027] Beneficial Effects

[0028] The chip packaging structure proposed in the present invention has the following advantages by adding a 50-150 micron encapsulation material layer on the back of the silicon wafer in an encapsulation manner:

[0029] 1. Maintain the thickness of silicon wafers at 50-150 microns. Under the same TSV opening size requirements, reduce the TSV aspect ratio, reduce the difficulty of TSV etching, and facilitate the formation of a continuous insulating layer / seed layer / barrier layer on the sidewall of the TSV, reduce process difficulty, and reduce costs. A smaller TSV aspect ratio is conducive to TSV filling, reduces the formation of holes during the filling process, improves the yield rate, reduces the difficulty of production, and reduces costs. By increasing the overall thickness of the wafer through the encapsulation layer, the problem of insufficient mechanical strength and easy breakage of the wafer process and the chip during subsequent use is improved;

[0030] 2. The packaging method proposed for the packaging structure of the present invention has low manufacturing difficulty and low cost. Metal pillars for transmitting signals are formed before the encapsulation material layer to form metal connecting pillars. The process steps are simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic cross-sectional view of a chip packaging structure of the present invention;

[0032] Figure 2A-2H for Figure 1 A schematic diagram of the process flow of the packaging structure;

[0033] In the figure:

[0034] Chip 10

[0035] Through Silicon Via 11

[0036] Rewiring layer 14

[0037] Electrode 19

[0038] Encapsulation material layer 20

[0039] Metal connecting column 21

[0040] Solder ball 24

[0041] Through hole 27

[0042] Carrier disc 30

[0043] Temporary bonding adhesive31. DETAILED DESCRIPTION Example

[0044] The present invention provides a chip packaging structure, such as Figure 1 As shown, Figure 1 The schematic cross-sectional view of an embodiment of the present invention shows a chip packaging structure comprising a chip 10, a through silicon via 11, a redistribution layer (RDL) 14, an encapsulation material layer 20, a metal connection column 21 and a solder ball 24 from top to bottom, which transmits the signal received by the chip 10 downward to a circuit board such as a PCB.

[0045] The front side of the silicon substrate 12 of the chip 10 is provided with an electrode 19 and a functional area (not shown in the figure of the functional area), and the thickness after thinning is in the range of 50-150 microns. The number of electrodes 19 is an even number, and generally, the electrodes 19 are arranged in an array. Under the electrodes 19 in the silicon substrate 12 of the chip 10, a number of silicon through vias 11 for transmitting signals are provided according to a pre-designed scheme, and the cross-section in the figure illustrates two silicon through vias 11. The filling material of the silicon through via 11 is one or more of copper, gold, and silver. The cross section of the silicon through via 11 includes but is not limited to a square hole and a circular hole. The filling method of the silicon through via 11 is half-filled or solid filled.

[0046] The through silicon via 11 penetrates the silicon substrate 12 from top to bottom and is fixedly connected to the redistribution layer (RDL) 14 on the lower surface of the chip.

[0047] The redistribution layer (RDL) 14 is made of one or more materials such as copper, gold, and silver, and is connected to the through silicon via 11 for transmitting electrical signals.

[0048] The encapsulation material layer 20 encapsulates the rewiring layer 14 and the metal connection column 21. At least one metal connection column 21 is provided in the encapsulation material layer 20 according to a pre-designed scheme, and the longitudinal section of the metal connection column 21 is trapezoidal. The material of the metal connection column 21 is one or more of tin, silver, and copper. The height of the metal connection column 21 is 50-150 microns; the metal connection column 21 is flush with the back side 26 of the encapsulation material layer, and the metal connection column 21 is connected to the solder ball 24, and the material of the solder ball 24 is one or more of tin, silver, and copper.

[0049] The functional area on the front side of the chip 10 receives the signal and transmits it to the redistribution layer (RDL) 14 through its electrode 19 and silicon through via 11. The redistribution layer (RDL) 14 is fixedly connected to the metal connection column 21 located in the encapsulation material layer 20. The metal connection column 21 transmits the chip signal downward through the solder ball 24.

[0050] In view of the above chip packaging structure, the present invention provides a packaging method for a chip packaging structure, and the implementation steps are as follows:

[0051] Step 1: If Figure 2A As shown, a carrier wafer 30 and a wafer with a functional area on the front are provided. The wafer is a collection of a plurality of chips 10. The wafer is bonded to the carrier wafer 30 by a temporary bonding method through a temporary bonding adhesive 31.

[0052] Step 2: If Figure 2B As shown, the chip 10 with the functional area on the front side is formed by thinning the wafer by grinding, and the chip 10 is thinned to a desired thickness, generally 50-150 microns;

[0053] Step 3: If Figure 2C As shown, a mask material is attached or coated on the back of the chip, an opening is formed in the mask material by photolithography, and a through silicon via 11 array is formed in the silicon substrate 12 at the corresponding electrode 19 according to a pre-designed manner by deep silicon etching or laser drilling, and the mask material is removed; the cross section of the through silicon via 11 includes but is not limited to a square hole and a circular hole;

[0054] An insulating layer is formed on the side wall of the through silicon via 11 and the back side of the chip by a process such as sputtering to insulate the through silicon via 11 from the wafer (the insulating layer is not shown in the figure);

[0055] Step 4: If Figure 2D As shown, a mask material is re-attached or coated on the back of the chip, and metal is filled in the mask pattern opening by electroplating to form a through silicon via 11. At the same time, a rewiring layer 14 is formed on the back of the chip according to a pre-set scheme. The material of the rewiring layer 14 is one or more of copper, gold, and silver;

[0056] Specifically, a plating seed layer is formed by processes such as sputtering, and the seed layer covers the side walls of the through silicon via 11 and the back of the chip to facilitate electroplating thickening. After the electroplating thickening is completed, the seed layer on the back of the chip is removed by processes such as corrosion, and then the above-mentioned wafer plane is plasma treated, and the gas used for the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride.

[0057] Step 5: If Figure 2EAs shown, the encapsulation material is coated on the back of the chip by encapsulation to form an encapsulation material layer 20, and the encapsulation material layer is thinned to a desired thickness, generally 50-200 microns, by a chemical mechanical polishing (CMP) step or grinding;

[0058] Step 6: If Figure 2F As shown, by laser drilling or the like, a through hole 27 is formed on the upper surface of the encapsulation material layer according to a pre-designed scheme, exposing the lower surface of the rewiring layer 14;

[0059] Step 8: If Figure 2G As shown, the through hole 27 is filled by ball planting, and the solder in the through hole 27 and the metal seed layer form a metal connecting column 21 fixedly connected to the redistribution layer 14, and a solder ball 24 under the metal connecting column 21, so as to complete the chip packaging and form a wafer-level package; the metal connecting column 21 and the solder ball 24 are made of one or more of tin, silver, and copper;

[0060] Step 9: If Figure 2H As shown, the carrier wafer is separated from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive 31;

[0061] Step 10: Use laser or blade to cut the wafer-level package into individual packages.

[0062] The specific implementation methods described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: It comprises, from top to bottom, a chip (10), a through silicon via (11), a rewiring layer (14), a metal connection column (21) and a solder ball (24), and transmits the signal received by the chip (10) downward; The chip (10) comprises a silicon substrate (12), an electrode (19) and a functional area. The chip has a thickness of 50-150 microns. The electrode (19) and the functional area are arranged on the front side of the silicon substrate (12). The rewiring layer (14) is arranged on the back side of the chip (10). A plurality of through-silicon vias (11) for transmitting signals are arranged below the electrode (19). The through-silicon vias (11) penetrate the silicon substrate (12) vertically and are fixedly connected to the rewiring layer (14). A metal connecting column (21) is arranged below the rewiring layer (14). The longitudinal section of the metal connecting column (21) is in the shape of a trapezoid. It also includes an encapsulation material layer (20) directly covering the back side of the chip, the encapsulation material layer (20) encapsulating the redistribution layer (14) and the metal connection column (21), the lower surface of the metal connection column (21) is flush with the back side of the encapsulation material layer (20), and the lower surface of the metal connection column (21) is exposed, and the solder ball (24) is fixedly connected to the lower surface of the metal connection column (21).

2. The chip packaging structure according to claim 1, characterized in that: The cross section of the through silicon via (11) is a square hole or a circular hole.

3. The chip packaging structure according to claim 1, characterized in that: The number of the electrodes (19) is an even number.

4. A packaging method for a chip packaging structure, the implementation steps of which are as follows: Step 1: providing a carrier wafer (30) and a wafer with a functional area on the front side, the wafer being a collection of a plurality of chips (10), and bonding the wafer to the carrier wafer (30) by temporary bonding using a temporary bonding adhesive (31); Step 2: Thinning the wafer by grinding to form a chip (10) with a functional area on the front side, and thinning the chip (10) to a desired thickness, wherein the thickness of the chip after thinning is 50-150 microns; Step 3: attaching or coating a mask material on the back of the chip, forming an opening in the mask material by photolithography, forming a through-silicon via (11) array at the corresponding electrode (19) in the silicon substrate (12) by deep silicon etching or laser drilling according to a pre-designed method, and removing the mask material; An insulating layer is formed on the side wall of the through silicon via (11) and the back side of the chip by a sputtering process, so that the through silicon via (11) is insulated from the wafer; Step 4: re-attach or coat the mask material on the back of the chip, fill the mask pattern opening with metal by electroplating to form a through silicon via (11), and simultaneously form a rewiring layer (14) on the back of the chip according to a pre-set scheme; Forming an electroplating seed layer through a sputtering process, the seed layer covers the side wall of the through silicon hole (11) and the back of the chip, facilitating electroplating thickening; After the electroplating thickening is completed, the seed layer on the back of the chip is removed by an etching process, and then the above wafer plane is subjected to plasma treatment; Step 5: coating the encapsulation material on the back of the chip by encapsulation to form an encapsulation material layer (20) directly covering the back of the chip, and thinning the encapsulation material layer (20) to a desired thickness by chemical mechanical polishing or grinding; Step 6: using laser drilling to form a through hole (27) in the encapsulation material layer (20) according to a pre-designed scheme, exposing the lower surface of the redistribution layer (14); Step 7: forming a metal seed layer on the sidewall and bottom of the through hole (27) by a sputtering process; Step 8: Fill the through hole (27) by ball planting, the solder in the through hole (27) and the metal seed layer form a metal connection column (21) fixedly connected to the redistribution layer (14), and a solder ball (24) below the metal connection column (21), complete the chip packaging, and form a wafer-level package; Step nine: separating the carrier wafer from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive (31); Step 10: Use laser or blade to cut the wafer-level package into individual packages.

5. The packaging method of the chip packaging structure according to claim 4, characterized in that: The material of the metal connection column (21) is one or more of tin, silver and copper.

6. The packaging method of the chip packaging structure according to claim 4 or 5, characterized in that: The thickness of the metal connecting column (21) is 50-200 microns.

7. The packaging method of the chip packaging structure according to claim 4, characterized in that: The material of the solder ball (24) is one or more of tin, silver and copper.

8. The packaging method of the chip packaging structure according to claim 4, characterized in that: The through silicon via (11) is filled in a half-filling or solid-filling manner.

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