A packaging structure and packaging method of a chip

Abstract

The present invention relates to a packaging structure and a packaging method for a chip, belonging to the technical field of semiconductor chip packaging. It includes, from top to bottom, a chip (10), a through-silicon via (11), a metal pad (13), a metal connecting pillar (21), a redistribution layer (23), and solder balls (24), which transmit the signals received by the chip (10) downward; the through-silicon via (11) below the electrode (19) penetrates the silicon substrate (12) up and down and is fixedly connected to the metal pad (13), and a metal connecting pillar (21) is arranged below the redistribution layer (14); the encapsulant layer (20) encapsulates the metal connecting pillar (21) and the metal pad (13), and an array of solder balls (24) is arranged on the lowermost layer of the redistribution layer (23). The present invention provides a packaging structure and a packaging method that can neither increase the thickness of the silicon wafer nor improve the mechanical strength of the packaged chip.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a packaging method of a chip, belonging to the technical field of semiconductor chip packaging. Background Art

[0002] The Through-Silicon Via (TSV) interconnection technology is currently considered one of the most advanced technologies in the semiconductor industry. By using short vertical electrical connections or "through-silicon vias" through silicon, electrical connections are established from the active surface of the chip to the back surface, thus providing the shortest interconnection path. TSV filling is a difficult process in TSV fabrication, and the aspect ratio of TSV is one of the influencing factors of this difficult process. In semiconductor products, the thickness of the silicon wafer determines the depth of the TSV, and the width of the TSV must meet the design requirements and cannot be increased arbitrarily. The thicker the silicon wafer, the deeper the TSV, the greater the difficulty in etching the TSV, and it is more difficult to form a continuous insulating layer / seed layer / barrier layer on the sidewall of the TSV. At the same time, it is easier to form holes during the TSV filling process, and the filling difficulty is greater. Generally speaking, this packaging technology has the following difficulties: First, if the silicon wafer is thick, the deeper the TSV, the more difficult it is to implement processes such as TSV etching, insulation, seed layer formation, and electroplating filling during the process, and the cost is higher; Second, if the silicon wafer is thin, the chip has problems of insufficient mechanical strength and is prone to breakage during use. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a packaging structure and a packaging method that neither increase the thickness of the silicon wafer, the implementation difficulty of TSV, and the processing cost, nor can improve the mechanical strength of the packaged chip.

[0004] The present invention is implemented as follows:

[0005] A packaging structure of a chip according to the present invention includes, from top to bottom, a chip, a through-silicon via, a metal pad, a metal connection column, a redistribution layer, and a solder ball, which transmits the signals received by the chip downward;

[0006] The chip includes a silicon substrate, electrodes, and a functional area. The electrodes and the functional area are disposed on the front surface of the silicon substrate. The metal pads are discontinuously disposed on the lower surface of the chip. A plurality of through-silicon vias for transmitting signals are provided below the electrodes. The through-silicon vias penetrate the silicon substrate up and down and are fixedly connected to the metal pads;

[0007] The encapsulation layer encapsulates the metal connection posts and the metal pads. The metal connection posts penetrate through the encapsulation layer vertically. The lower surface of the metal connection posts is flush with the back surface of the encapsulation layer. The metal connection posts are connected to the redistribution layer, which includes at least one dielectric layer and at least one layer of redistribution metal pattern layers arranged alternately. The dielectric layer wraps the redistribution metal pattern layers and / or fills the space between adjacent redistribution metal pattern layers. There is a selective electrical connection between the redistribution metal pattern layers, which are connected to the metal connection posts for transmitting electrical signals. The lowest layer of the redistribution layer is provided with solder balls arranged in an array.

[0008] Optionally, the cross-section of the through-silicon via includes, but is not limited to, a square hole or a circular hole.

[0009] Optionally, the number of the electrodes is an even number.

[0010] Optionally, the cross-section of the metal pad is circular or square.

[0011] The encapsulation method of an encapsulation structure of a chip according to the present invention is implemented as follows:

[0012] Step 1: Provide a carrier wafer and a wafer with a functional area on the front surface. The wafer is an aggregate of a plurality of chips. The wafer is bonded to the carrier wafer by a temporary bonding method using a temporary bonding adhesive.

[0013] Step 2: Thinning the wafer by lapping to form a chip with a functional area on the front surface, and thinning the chip to the required thickness.

[0014] Step 3: Stick or coat a masking material on the back surface of the chip. Openings are formed in the masking material by photolithography. A through-silicon via array is formed at corresponding electrodes in the silicon substrate by deep silicon etching or laser drilling according to a pre-designed pattern, and the masking material is removed.

[0015] An insulating layer is formed on the sidewall of the through-silicon via and the back surface of the chip by processes such as sputtering to insulate the through-silicon via from the wafer.

[0016] Step 4: Re-stick or coat a masking material on the back surface of the chip. Metal is filled in the openings of the masking pattern by electroplating to complete the through-silicon via process. Meanwhile, discontinuous metal pads are formed on the back surface of the chip by electroplating. The metal pads are fixedly connected to the lower surface of the through-silicon via.

[0017] Step 5: A plurality of metal connection posts are formed on the metal pads in sequence by photolithography, electroplating, and etching processes.

[0018] Step 6: Coat the back surface of the chip with an encapsulation material in an encapsulation manner. The encapsulation material encapsulates the metal connection posts and the metal pads to form an encapsulation layer.

[0019] Step Seven: Through a planarization process of performing a chemical mechanical polishing step or a grinding step, grind the encapsulant layer to expose the metal connection posts and make the back surface of the encapsulant layer flush with the metal column surface of the metal connection posts; then perform plasma treatment on the above wafer plane, and the gas used for the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride;

[0020] Step Eight: On the back surface of the encapsulant layer, form a multi-layer redistribution layer and a multi-layer redistribution layer opening in sequence by means of sputtering, photolithography, electroplating, etc. The redistribution layer includes at least one dielectric layer and at least one layer of redistribution metal pattern layers arranged alternately with each other. The dielectric layer wraps the redistribution metal pattern layer and / or fills between adjacent redistribution metal pattern layers. There is a selective electrical connection between the redistribution metal pattern layers, and the multi-layer redistribution layer is fixedly connected to the metal connection posts downward through the multi-layer redistribution layer opening;

[0021] Step Nine: Form solder balls on the redistribution layer by means of ball planting to complete chip packaging and form a wafer-level package;

[0022] Step Ten: Separate the carrier wafer from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive;

[0023] Step Eleven: Cut the wafer-level package into individual packages by means of laser or blade.

[0024] Optionally, the metal gasket material is one or more of copper, gold, and silver.

[0025] Optionally, the material of the metal connection posts is one or more of tin, silver, and copper.

[0026] Optionally, in Step Four, the process of the redistribution layer further includes the following process: form an electroplated metal seed layer through a sputtering process, and the metal seed layer covers the side wall of the through-silicon via and the back surface of the functional area chip on the front side to facilitate electroplating thickening; form the through-silicon via through electroplating filling; after the electroplating thickening is completed, remove the metal seed layer on the back surface of the chip through processes such as etching, and then perform plasma treatment on the above wafer plane.

[0027] Optionally, the filling method of the through-silicon via is semi-filling or solid filling.

[0028] Optionally, the material of the redistribution metal pattern layer is one or more of copper, gold, and silver.

[0029] Beneficial Effects

[0030] The chip packaging structure proposed by the present invention adds an encapsulant layer with a thickness of 50 - 150 microns to the back surface of the silicon wafer in a packaging manner, and its advantages are as follows:

[0031] 1. Maintain the thickness of the silicon wafer at 50 - 150 microns. Under the TSV requirements of the same opening size, reduce the aspect ratio of the TSV, reduce the difficulty of TSV etching, which is conducive to forming a continuous insulating layer / seed layer / barrier layer on the sidewall of the through - silicon via, reduce the process difficulty and cost; a smaller aspect ratio of the TSV is beneficial to the filling of the through - silicon via, reduce the formation of holes during the filling process, improve the yield, reduce the manufacturing difficulty and cost. Increase the overall thickness of the wafer through the encapsulant layer to improve the problem of insufficient mechanical strength and easy breakage of the wafer during the subsequent use process;

[0032] 2. The packaging method proposed for the packaging structure of the present invention has low manufacturing difficulty and low cost. Metal pillars for transmitting signals are formed before the encapsulant layer to form metal connection pillars, and the process steps are simple and easy to implement. Brief Description of the Drawings

[0033] Figure 1 It is a schematic cross - sectional view of a packaging structure of a chip according to the present invention;

[0034] Figures 2A - 2J is Figure 1 a schematic diagram of the process flow of the packaging structure of

[0035] In the figure:

[0036] Chip 10

[0037] Through - silicon via 11

[0038] Metal gasket 13

[0039] Redistribution layer 14

[0040] Electrode 19

[0041] Dielectric layer 29

[0042] Encapsulant layer 20

[0043] Metal connection pillar 21

[0044] Back side of the encapsulant layer 22

[0045] Redistribution layer 23

[0046] Solder ball 24

[0047] Carrier wafer 30

[0048] Temporary bonding adhesive 31. Detailed Description of the Invention Embodiment

[0049] A packaging structure of a chip according to the present invention, as Figure 1 shown, Figure 1 is a schematic cross - sectional view of an embodiment of the present invention.

[0050] The encapsulation structure of a chip according to the present invention includes, from top to bottom, a chip 10, through-silicon vias 11, metal pads 13, an encapsulant layer 20, metal pillars 21, a redistribution layer 23, and solder balls 24, which transmit the signals received by the chip 10 downward to a circuit board such as a PCB.

[0051] On the front surface of the silicon substrate 12 of the chip 10, there are electrodes 19 and a functional area (not shown in the figure). The thickness after thinning is in the range of 50 - 150 microns. The number of electrodes 19 is an even number. Generally, the electrodes 19 are arranged in an array. Below the electrodes 19 in the silicon substrate 12 of the chip 10, several through-silicon vias 11 for transmitting signals are provided according to a pre-designed scheme. Two through-silicon vias 11 are schematically shown in the cross-section in the figure. The filling material of the through-silicon vias 11 is one or several of copper, gold, and silver. The cross-section of the through-silicon vias 11 includes, but is not limited to, a square hole or a circular hole. The filling method of the through-silicon vias 11 is semi-filled or solid-filled.

[0052] The through-silicon vias 11 penetrate through the silicon substrate 12 up and down and are fixedly connected to the metal pads 13 on the back surface of the chip. The material of the metal pads 13 is one or several of copper, gold, and silver. The metal pads 13 are discontinuous, and their cross-section is circular or square.

[0053] The encapsulant layer 20 encapsulates the metal pillars 21 and the metal pads 13. At least one metal pillar 21 is provided in the encapsulant layer 20 according to a pre-designed scheme. The material of the metal pillars 21 is one or several of copper, gold, and silver. The height range of the metal pillars 21 is 50 - 150 microns, and their cross-section includes, but is not limited to, a square hole or a circular hole. The metal pillars 21 penetrate through the encapsulant layer 20 up and down. The lower surface of the metal pillars 21 is flush with the back surface 22 of the encapsulant layer. The metal pillars 21 are connected to the redistribution layer 23. The redistribution layer 23 includes at least one dielectric layer 29 and at least one layer of redistribution metal pattern layers arranged alternately. The material of the redistribution metal pattern layers is one or several of copper, gold, and silver. The dielectric layer 29 wraps the redistribution metal pattern layers and / or fills between adjacent redistribution metal pattern layers. There is a selective electrical connection between the redistribution metal pattern layers, which is connected to the metal pillars 21 and is used to transmit electrical signals. The solder balls 24 arranged in an array are provided on the lowermost layer of the redistribution layer 23.

[0054] The functional area on the front surface of the chip 10 receives signals, which are transmitted downward through its electrodes 19 and through-silicon vias 11 to the metal pads 13. The metal pads 13 are fixedly connected to the metal pillars 21 located in the encapsulant layer 20. The metal pillars 21 are fixedly connected to the redistribution layer 23 on the back surface 22 of the encapsulant layer. The redistribution layer 23 transmits the signals of the chip 10 downward through the solder balls 24.

[0055] For the above chip packaging structure, the present invention provides a packaging method for the chip packaging structure, and the implementation steps are as follows:

[0056] Step 1: As Figure 2A shown, provide a carrier wafer 30 and a wafer with a functional area on the front. This wafer is an aggregate of a plurality of chips 10. Adhere the wafer to the carrier wafer 30 by means of temporary bonding through a temporary bonding adhesive 31;

[0057] Step 2: As Figure 2B shown, thin the wafer by grinding to form the chip 10 with a functional area on the front, and thin the chip 10 to the required thickness, generally 50 - 150 microns;

[0058] Step 3: As Figure 2C shown, attach or coat a masking material on the back of the chip, form an opening in the masking material through photolithography, and form an array of through - silicon vias 11 at the corresponding electrodes 19 in the silicon substrate 12 by deep silicon etching or laser drilling according to the pre - design, and remove the masking material; the through - silicon vias 11 include but are not limited to square holes and circular holes;

[0059] Form an insulating layer on the side walls of the through - silicon vias 11 and the back of the chip through processes such as sputtering to insulate the through - silicon vias 11 from the wafer (the insulating layer is not shown in the figure);

[0060] Step 4: As Figure 2D shown, re - attach or coat a masking material on the back of the chip, fill the opening in the masking pattern with metal by electroplating to complete the through - silicon via 11 process; discontinuous metal pads 13 are formed on the back of the chip, and the metal pads 13 are fixedly connected to the lower surface of the through - silicon vias 11;

[0061] Specifically, cover a metal seed layer on the side walls of the through - silicon vias 11 and the back of the chip by sputtering process to facilitate electroplating thickening; form the through - silicon vias 11 by electroplating filling. The filling material can be one or several of gold, silver, and copper, and the filling method can be semi - filling or full - filling. At the same time, electroplate to form the metal pads 13; after electroplating thickening, remove the ineffective metal seed layer by processes such as etching, and then perform plasma treatment on the plane of the above - mentioned wafer. The gas used for the plasma treatment is one or several of argon, oxygen, and carbon tetrafluoride.

[0062] Step 5: As Figure 2E shown, form a number of metal connection posts 21 on the metal pads 13 in sequence by means of photolithography, electroplating, etching, etc. The material can be one or several of gold, silver, and copper, the height is 50 - 200 microns, and its cross - section includes but is not limited to square holes and circular holes;

[0063] Step 6: As Figure 2FAs shown, the encapsulation material is coated on the back of the chip in an encapsulation manner. The encapsulation material wraps the metal connection posts 21 and the metal pads 13 to form an encapsulation layer 20. The thickness of the encapsulation material is 50 - 200 microns.

[0064] Step Seven: As Figure 2G shown, through a planarization process of performing a chemical mechanical polishing (CMP) step or a grinding step, the encapsulation layer 20 is ground to expose the metal connection posts 21 and make the back surface 22 of the encapsulation layer flush with the metal column surface of the metal connection posts 21. Then, the above wafer plane is subjected to plasma treatment, and the gas used in the plasma treatment is one or several of argon, oxygen, and carbon tetrafluoride.

[0065] Step Eight: As Figure 2H shown, on the back surface 22 of the encapsulation layer, a multi-layer redistribution layer 23 and multi-layer redistribution layer openings are formed in sequence by means of sputtering, photolithography, electroplating, etc. The redistribution layer 23 includes at least one dielectric layer 29 and at least one layer of redistribution metal pattern layers arranged in an interlaced manner. The dielectric layer wraps the redistribution metal pattern layers and / or fills between adjacent redistribution metal pattern layers. There is a selective electrical connection between the redistribution metal pattern layers. The multi-layer redistribution layer 23 is fixedly connected to the metal connection posts 21 downward through the multi-layer redistribution layer openings.

[0066] Step Nine: As Figure 2I shown, solder balls 24 are formed on the redistribution layer 23 by means of ball planting to complete the chip encapsulation and form a wafer-level package. The solder balls 24 are made of one or several of tin, silver, and copper.

[0067] Step Ten: As Figure 2J shown, by irradiating UV light or laser on the temporary bonding adhesive 31, the carrier wafer 30 is separated from the wafer-level package.

[0068] Step Eleven: The wafer-level package is cut into individual packages by means of laser or blade.

[0069] The above specific embodiments have further detailed the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A packaging structure of a chip, characterized in that, It includes, from top to bottom, a chip (10), a through-silicon via (11), a metal pad (13), a metal connecting post (21), a redistribution layer (23), and a solder ball (24), and transmits the signals received by the chip (10) downward; The chip (10) includes a silicon substrate (12), electrodes (19), and a functional area. The electrodes (19) and the functional area are disposed on the front surface of the silicon substrate (12). The metal pads (13) are discontinuously disposed on the back surface of the chip (10). A plurality of through-silicon vias (11) for transmitting signals are provided below the electrodes (19). The through-silicon vias (11) penetrate the silicon substrate (12) up and down and are fixedly connected to the metal pads (13); The encapsulant layer (20) is located on the back surface of the chip (10), and the thickness of the encapsulant layer (20) is 50 - 150 microns. The encapsulant layer (20) encapsulates the metal connecting posts (21) and the metal pads (13). The metal connecting posts (21) are fixedly connected to the surface of the metal pads (13) facing away from the chip. The metal connecting posts (21) penetrate the encapsulant layer (20) up and down, and the lower surface of the metal connecting posts (21) is flush with the back surface of the encapsulant layer (22). The metal connecting posts (21) are connected to the redistribution layer (23). The redistribution layer (23) includes at least one dielectric layer (29) and at least one layer of redistribution metal pattern layers arranged alternately with each other. The dielectric layer (29) wraps the redistribution metal pattern layers and / or fills between adjacent redistribution metal pattern layers. Selective electrical connections exist between the redistribution metal pattern layers and are connected to the metal connecting posts (21) for transmitting electrical signals. An array of solder balls (24) is provided on the lowermost layer of the redistribution layer (23).

2. The encapsulation structure according to claim 1, characterized in that, The cross-section of the through-silicon via (11) is a square hole or a circular hole.

3. The encapsulation structure according to claim 1, wherein The number of the electrodes (19) is an even number.

4. The encapsulation structure according to claim 1, wherein, The cross-section of the metal pad (13) is circular or square.

5. A packaging method for a packaging structure of a chip, and the implementation steps are as follows: Step 1: Provide a carrier wafer (30) and a wafer with a functional area on the front surface. The wafer is an aggregate of a plurality of chips (10). The wafer is bonded to the carrier wafer (30) by a temporary bonding method through a temporary bonding adhesive (31); Step 2: Thinning the wafer by a grinding method to form a chip (10) with a functional area on the front surface, and thinning the chip (10) to a required thickness; Step 3: Paste or coat a masking material on the back surface of the chip. Openings are formed in the masking material by photolithography. An array of through-silicon vias (11) is formed in the silicon substrate (12) at corresponding electrodes (19) according to a pre-designed pattern by deep silicon etching or laser drilling, and the masking material is removed; An insulating layer is formed on the sidewalls of the through-silicon vias (11) and the back surface of the chip by a sputtering process to insulate the through-silicon vias (11) from the wafer; Step Four: Reattach or coat a mask material on the back of the chip, and use electroplating to fill metal within the openings of the mask pattern to complete the Through-Silicon Via (TSV) (11) process. Meanwhile, use electroplating to form discontinuous metal pads (13) on the back of the chip, and the metal pads (13) are fixedly connected to the lower surface of the Through-Silicon Via (TSV) (11). Step Five: Form a number of metal connection posts (21) on the metal pads (13) through photolithography, electroplating, and etching processes in sequence, and the metal connection posts (21) are fixedly connected to the surface of the metal pads (13) facing away from the chip. Step Six: Coat the back of the chip with an encapsulation material in a packaging manner, and the encapsulation material wraps the metal connection posts (21) and the metal pads (13) to form an encapsulation layer (20), and the thickness of the encapsulation layer (20) is 50 - 150 microns. Step Seven: Through a planarization process of performing a chemical mechanical polishing step or a grinding step, grind the encapsulation layer (20) to expose the metal connection posts (21) and make the back surface (22) of the encapsulation layer flush with the metal column surface of the metal connection posts (21); then perform plasma treatment on the above wafer surface, and the gas used for the plasma treatment is one or several of argon, oxygen, and carbon tetrafluoride. Step Eight: On the back surface (22) of the encapsulation layer, form a multi-layer redistribution layer (23) and multi-layer redistribution layer openings through sputtering, photolithography, and electroplating in sequence. The redistribution layer (23) includes at least one dielectric layer (29) and at least one layer of redistribution metal pattern layers arranged alternately. The dielectric layer wraps the redistribution metal pattern layers and / or fills between adjacent redistribution metal pattern layers. There is selective electrical connection between the redistribution metal pattern layers, and the multi-layer redistribution layer (23) is fixedly connected to the metal connection posts (21) downward through the multi-layer redistribution layer openings. Step Nine: Form solder balls (24) on the redistribution layer (23) by ball mounting to complete chip packaging and form a wafer-level package. Step Ten: Separate the carrier wafer (30) from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive (31). Step Eleven: Cut the wafer-level package into individual packages by using laser or blade methods.

6. The encapsulation method according to claim 5, wherein The material of the metal pads (13) is one or several of copper, gold, and silver.

7. The encapsulation method according to claim 5, wherein The material of the metal connection posts (21) is one or several of tin, silver, and copper.

8. The encapsulation method according to claim 5, characterized in that, In Step Four, the process of the redistribution layer (14) further includes the following processes: form an electroplated metal seed layer through sputtering, and the metal seed layer covers the sidewall of the Through-Silicon Via (TSV) (11) and the back of the chip with a functional area on the front side to facilitate electroplating thickening; form the Through-Silicon Via (TSV) (11) through electroplating filling; after electroplating thickening is completed, remove the metal seed layer on the back of the chip through etching, and then perform plasma treatment on the above wafer surface.

9. The chip packaging method according to claim 5, wherein The filling method of the Through-Silicon Via (TSV) (11) is semi-filling or solid filling.

10. The chip packaging method according to claim 5, wherein The material of the redistribution metal pattern layer is one or several of copper, gold, and silver.

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