L-type transistor, semiconductor memory, and method for manufacturing the same

Abstract

The application provides an L-shaped transistor, a semiconductor memory and a preparation method thereof. The L-shaped transistor has an L-shaped fin extending along a second direction, a first source / drain region is formed in a vertical fin part of the L-shaped fin, a second source / drain region is formed in a horizontal straight fin part of the L-shaped fin, a gate is arranged on the horizontal straight fin part and extends along the first direction, so that a vertical L-shaped channel is formed between the first source / drain region and the second source / drain region, the effective channel length is increased, the short channel effect is overcome, and smaller feature sizes are facilitated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to an L-type transistor, a semiconductor memory, and a method for manufacturing the same. Background Technology

[0002] In the field of semiconductor devices, especially memory, methods to increase device integration density include reducing device feature size and improving cell structure. However, as feature size decreases, small-sized transistors generate severe short-channel effects. Therefore, by improving the device cell structure, such as designing a three-dimensional transistor structure, the area occupied by a single device cell can be greatly reduced under the same feature size, thereby increasing device integration density.

[0003] Therefore, it is necessary to design a new vertical transistor structure, semiconductor memory and its manufacturing method, so as to greatly reduce the area occupied by a single device unit under the same feature size, thereby increasing the device integration density. Summary of the Invention

[0004] The purpose of this invention is to provide an L-type transistor, a semiconductor memory, and a method for manufacturing the same, which greatly reduces the area occupied by a single device unit under the same feature size conditions, thereby increasing the device integration density.

[0005] To achieve the above objectives, the present invention provides an L-type transistor, comprising:

[0006] A semiconductor substrate having L-shaped fins, the L-shaped fins including a horizontal fin portion extending along a second direction and a vertical fin portion vertically disposed at one end of the horizontal fin portion, wherein the bottom end of the vertical fin portion is connected to one end of the horizontal fin portion, and a second source / drain region is formed in the horizontal fin, and a first source / drain region is formed in the top end of the vertical fin portion; and...

[0007] A gate is disposed on the horizontal fin portion and extends along a first direction.

[0008] Optionally, the semiconductor substrate further has a first trench extending along the first direction, the first trench being located outside the two sidewalls of the L-shaped fin extending along the first direction, and the bottom of the first trench extending to the sidewall of the horizontal fin portion, exposing the two sidewalls of the L-shaped fin extending along the first direction in the first trench.

[0009] Optionally, the semiconductor substrate further has a second trench extending along the second direction and exposing the sidewalls of the L-shaped fin extending along the second direction, and the first trench extending to the end of the first direction to the second trench, such that the first trench and the second trench are connected on the sidewalls of the second trench.

[0010] Optionally, the L-type transistor further includes a buried conductor electrically connected to the second source / drain region, the buried conductor being embedded in the second trench and extending along a second direction, and the gate extending along a first direction into the second trench and spanning over the buried conductor.

[0011] Optionally, the L-type transistor further includes a conductive contact structure formed in the second trench and disposed between the buried conductor and the second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the buried conductor. The bottom surface of the conductive contact structure is isolated from the semiconductor substrate surface at the bottom of the second trench.

[0012] Optionally, the L-type transistor further includes a first dielectric layer, which fills the second trench, and the embedded wire is located on the first dielectric layer in the second trench, and the embedded wire is insulated from the semiconductor substrate through the first dielectric layer.

[0013] Optionally, the L-shaped transistor further includes a second dielectric layer that fills the second trench and buries the embedded wire therein.

[0014] Optionally, the L-shaped transistor further includes a gate dielectric layer and a gate isolation layer. The gate dielectric layer is formed between the gate and the L-shaped fin, and the gate isolation layer covers the gate and fills the space above the first trench, the second trench, and the horizontal fin portion to bury the gate therein.

[0015] The present invention also provides a method for fabricating an L-type transistor, comprising the following steps:

[0016] A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction to form an L-shaped fin, a first trench and a second trench. The L-shaped fin includes a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at one end of the horizontal fin portion, and the bottom end of the vertical fin portion is connected to one end of the horizontal fin portion. The second trench extends along the second direction and exposes the sidewall of the L-shaped fin extending along the second direction. The first trench extends along the first direction and exposes the sidewall of the L-shaped fin extending along the first direction.

[0017] An embedded conductor is formed in the second trench, the embedded conductor extending along a second direction; and,

[0018] A gate is formed on the horizontal fin portion, and the gate extends along the first direction.

[0019] Optionally, the step of forming the L-shaped fin, the first groove, and the second groove includes:

[0020] The semiconductor substrate is etched along the first direction and the second direction, respectively, to form a first trench and a second trench of the same depth; and,

[0021] The semiconductor substrate on one side of the first trench is etched along the first direction, with the etching depth being less than the depth of the first trench, to form a gate trench connecting the first trench and the L-shaped fin. The horizontal fin portion of the L-shaped fin is located at the bottom of the gate trench, and the vertical fin portion of the L-shaped fin is located on one side of the gate trench.

[0022] Optionally, before forming the embedded conductor, a second source / drain region is first formed in the horizontal fin portion, and the embedded conductor formed thereafter is electrically connected to the second source / drain region; after forming the gate, a first source / drain region is formed in the top portion of the vertical fin portion; or, before forming the embedded conductor, a first source / drain region is formed in the top portion of the vertical fin portion and a second source / drain region is formed in the horizontal fin portion, and the embedded conductor formed thereafter is electrically connected to the second source / drain region; or, after forming the gate, a first source / drain region is formed in the top portion of the vertical fin portion and a second source / drain region is formed in the horizontal fin portion, and the embedded conductor is electrically connected to the second source / drain region.

[0023] Optionally, before forming the embedded wire, a first dielectric layer is filled in the second trench, the embedded wire is located on the first dielectric layer in the second trench, and the embedded wire is insulated from the semiconductor substrate through the first dielectric layer.

[0024] Optionally, the step of forming the gate includes:

[0025] A second dielectric layer is filled into the second trench, and the top surface of the second dielectric layer is flush with the top surface of the horizontal fin portion;

[0026] A gate dielectric layer is formed on the surface of the L-shaped fin, the first trench, and the second trench;

[0027] Gate material is filled in the first trench, the second trench, and the gate trench, and the gate material is etched to the surface of the gate dielectric layer on the horizontal fin portion, leaving only a portion of the gate material in the gate trench to form a gate extending along the first direction in the gate trench; and,

[0028] A gate isolation layer is filled in the second trench, the first trench, and the gate trench to bury the gate in the gate trench.

[0029] The present invention also provides a semiconductor memory, characterized in that it comprises: a plurality of L-type transistors as described in the present invention, all of the L-type transistors being formed on the same semiconductor substrate and arranged in an array along a first direction and a second direction in cell rows and cell columns; the gates of all the L-type transistors in each cell row being connected as a single unit to serve as a word line of the semiconductor memory; and the embedded wires of all the L-type transistors in each cell column being connected as a single unit to serve as a bit line of the semiconductor memory.

[0030] The present invention also provides a method for fabricating a semiconductor memory, characterized in that it includes: fabricating a plurality of L-type transistors using the L-type transistor fabrication method of the present invention, wherein all the L-type transistors are formed on the same semiconductor substrate and arranged in an array along a first direction and a second direction in cell rows and cell columns, wherein the gates of all the L-type transistors in each cell row are connected as a single unit to serve as a word line of the semiconductor memory; and the embedded wires of all the L-type transistors in each cell column are connected as a single unit to serve as a bit line of the semiconductor memory.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] 1. The L-shaped transistor of the present invention has an L-shaped fin extending along a second direction. A first source / drain region is formed in the vertical fin portion of the L-shaped fin, and a second source / drain region is formed in the horizontal straight fin portion of the L-shaped fin. A gate is disposed on the horizontal straight fin portion and extends along the first direction, thereby forming a vertical L-shaped channel between the first source / drain region and the second source / drain region. Compared with a planar transistor, the vertical L-shaped channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillar between the first source / drain region and the second source / drain region, overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. At the same time, the second source / drain region of the L-shaped transistor of the present invention is located at the bottom and can be led out by embedded wires buried outside the sidewall of the L-shaped fin, avoiding direct lead-out from the transistor surface. This makes it easier to form isolation around the transistor, avoiding the use of enlarged shallow trench isolation rules, significantly reducing the difficulty of shallow trench isolation manufacturing, reducing the device area in the same size case, and thus providing higher device integration in a given space.

[0033] 2. The method for fabricating the L-type transistor of the present invention involves etching a semiconductor substrate along a first direction and a second direction to form an L-type fin, a first trench, and a second trench. An embedded conductive line extending along the second direction is formed in the second trench. A gate is formed on the horizontal fin portion, a first source / drain region is formed at the top of the vertical fin portion, and a second source / drain region is formed in the horizontal fin portion. This forms an L-type transistor. The process is simple, and the first and second trenches can achieve isolation between the L-type transistor and adjacent devices. This avoids the need for enlarged shallow trench isolation rules, significantly reducing the difficulty of shallow trench isolation manufacturing and the process defects of the isolation structure. This is beneficial for further miniaturization of product size and improvement of device performance.

[0034] 3. The semiconductor memory of the present invention includes a plurality of L-type transistors of the present invention arranged in an array. Since the second source / drain regions of each L-type transistor are located at the bottom of the transistor, they do not need to be directly led out from the surface of the transistor, making it easier to form isolation between transistors in the array. This reduces the memory cell area within the same size, enabling a cell area of ​​less than 8F. 2 (e.g., 4F) 2 A densely packed memory array (where F is the minimum structural width used in the photolithography process) is used to improve device integration.

[0035] 4. The semiconductor memory fabrication method of the present invention simplifies the process by using the L-type transistor fabrication method of the present invention to fabricate multiple L-type transistors arranged in an array. Isolation between adjacent memory cells and between the memory array and the peripheral circuit can be achieved through the first trench and the second trench, making device isolation easier to form and resulting in a semiconductor memory with higher performance and lifespan. Attached Figure Description

[0036] Figure 1 This is a three-dimensional structural diagram of an L-type transistor according to a specific embodiment of the present invention.

[0037] Figure 2A It is along Figure 1 A schematic diagram of the cross-sectional structure of the XX' line in the diagram.

[0038] Figure 2B It is along Figure 1 A schematic diagram of the cross-sectional structure of the MM' line.

[0039] Figure 2C It is along Figure 1 A schematic diagram of the cross-sectional structure of the YY' line in the diagram.

[0040] Figure 2D It is along Figure 1 A schematic diagram of the cross-sectional structure of the NN' line in the diagram.

[0041] Figure 3 This is a flowchart of a method for fabricating an L-type transistor according to a specific embodiment of the present invention.

[0042] Figures 4A to 4D yes Figure 3 The diagram shows a top view of the device structure in the fabrication method of the L-type transistor.

[0043] Figures 5A to 5D Corresponding to Figures 4A to 4D A schematic diagram of the cross-sectional structure at line XX' in the diagram.

[0044] Figures 6A to 6D Corresponding to Figures 4A to 4D A schematic diagram of the cross-sectional structure at the MM' line.

[0045] Figures 7A to 7D Corresponding to Figures 4A to 4D A schematic diagram of the cross-sectional structure at the YY' line.

[0046] Figures 8A to 8D Corresponding to Figures 4A to 4D A schematic diagram of the cross-sectional structure at the NN' line.

[0047] Figure 9 for Figure 3 The diagram shows the schematic of the three-dimensional structure of the device in the fabrication method of the L-type transistor.

[0048] The reference numerals in the attached figures are as follows:

[0049] 100 - Semiconductor substrate;

[0050] 1001 - Initial vertical fins;

[0051] 101-L type fins;

[0052] The horizontal fin portion of the 1011-L type fin;

[0053] The vertical fin portion of the 1012-L type fin;

[0054] 101a - First source / drain region;

[0055] 101b - Second source / leak region;

[0056] 102 - A first groove extending in a first direction;

[0057] 103 - A second groove extending along the second direction;

[0058] 104 - Gate trench extending along the first direction;

[0059] 105 - First dielectric layer;

[0060] 106 - Embedded conductor;

[0061] 107 - Conductive contact structure;

[0062] 108 - Second dielectric layer;

[0063] 109 - Gate dielectric layer;

[0064] 110 - Gate, word line;

[0065] 111 - Gate isolation layer. Detailed Implementation

[0066] To make the objectives and features of the present invention more apparent and understandable, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the embodiments described. It should be readily understood that the meanings of "on" and "on" in this document should be interpreted in the broadest sense, such that "on" and "on" mean not only "directly on" something without intermediate features or intermediate layers, but also "on" something with intermediate features or intermediate layers. When the L-type transistor is a transistor in a memory cell of a semiconductor memory, the first direction is the word line direction / row direction of the semiconductor memory, and the second direction is the bit line direction / column direction of the semiconductor memory.

[0067] Figure 1 This is a three-dimensional structural schematic diagram of an L-type transistor according to an embodiment of the present invention; Figure 2A It is along Figure 1 A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figure 2B It is along Figure 1 A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 2C It is along Figure 1 A schematic diagram of the cross-sectional structure of the YY' line in the diagram; Figure 2D It is along Figure 1 A schematic diagram of the cross-sectional structure of the NN' line in the diagram. Figure 1 To clearly show the buried structures in the L-type transistor, such as the gate, second gate, second source / drain region, buried wires, and conductive contact structures, the gate dielectric layer and second dielectric layer are omitted, leaving the gate, second gate, second source / drain region, buried wires, and conductive contact structures visible on the outside. Figures 2A to 2D The cross-sectional structure in the image shows the omitted gate dielectric layer, second dielectric layer, and other film layer structures.

[0068] Please refer to Figure 1 as well as Figures 2A to 2DAn embodiment of the present invention provides an L-type transistor, including a semiconductor substrate 100 having L-type fins 101, an embedded wire 106, a conductive contact structure 107, and a gate 110.

[0069] The semiconductor substrate 100 can be made of any suitable material well known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The L-shaped fin 101 includes a horizontal fin portion 1011 extending along a second direction and a vertical fin portion 1012 vertically disposed at one end of the horizontal fin portion 1011. The bottom end of the vertical fin portion 1012 is integrally connected to one end of the horizontal fin portion 1011. A second source / drain region 101b is formed in the end of the horizontal fin 1011 away from the vertical fin portion 1012, and a first source / drain region 101a is formed in the top end of the vertical fin portion 1012. The first source / drain region 101a and the second source / drain region 101b can be formed using a source / drain ion implantation process. Furthermore, depending on the transistor structure of different conductivity types, the first source / drain region 101a and the second source / drain region 101b are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doped ions in the first source / drain region 101a and the second source / drain region 101b are N-type doped ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the first source / drain region 101a and the second source / drain region 101b are P-type doped ions, such as boron (B) ions and boron fluoride (BF2). + Gallium (Ga) ions, indium (In) ions. In this embodiment, the first source / drain region 101a can be a source region, and the second source / drain region 101b can be a drain region.

[0070] The semiconductor substrate 100 further has a first trench 102 extending along the first direction and a second trench 103 extending along the second direction. The bottom of the first trench 102 extends to the sidewall of the horizontal fin portion 1011, exposing the sidewalls of the L-shaped fins extending along the first direction (i.e., the sidewalls of the vertical fin portion 1012 and the horizontal fin portion 1011 along the first direction) in the first trench 102. The second trench 103 extends along the second direction and exposes the sidewalls of the L-shaped fins 101 extending along the second direction (i.e., exposing the sidewalls of the vertical fin portion 1012 and the horizontal fin portion 1011 along the second direction). The first trench 102 extends along its end in the first direction to the second trench 103, such that the first trench 102 and the second trench 103 communicate on the sidewall of the second trench 103. The first trench 102 and the second trench 103 have the same depth. When multiple L-type transistors are formed consecutively along the second direction, the first trench 102 between two adjacent L-type transistors along the second direction is the isolation trench between the two L-type transistors. This first trench 102 can expose the sidewall of the vertical fin portion 1012 of the L-type transistor to which it belongs and extend its bottom to the horizontal fin portion 1011 of another L-type transistor away from its vertical fin portion 1012, and expose the sidewall of the horizontal fin portion 1011 of the other L-type transistor away from the vertical fin portion 1012 (the sidewall extending along the first direction) in the first trench 102.

[0071] In this embodiment, the gate 110 of the L-type transistor is located on one end of the horizontal fin portion 1011 near the vertical fin portion 1012 and extends along the first direction (i.e., it may only partially overlap with the second source / drain region 101b). The gate 110 is used to control the current flow between the first source / drain region 101a and the second source / drain region 101b.

[0072] The embedded conductor 106 is embedded in the second trench 103 and extends along the second direction. The gate 110 extends along the first direction into the second trench 103 and spans over the embedded conductor 106. The embedded conductor 106 can be electrically connected to the second source / drain region 101b through the conductive contact structure 107. The top surfaces of the embedded conductor 106 and the conductive contact structure 107 are flush with and lower than the top surface of the horizontal fin portion 1011. The second dielectric layer 108 fills the second trench 103 and covers the top surfaces of the embedded conductor 106 and the conductive contact structure 107. The top surface of the second dielectric layer 108 is flush with the top surface of the horizontal fin portion 1011, which can provide a flat trench bottom surface for the formation of the gate 110, so that the portion of the gate 110 extending on the horizontal fin portion 1011 and the portion spanning over the embedded conductor 106 are set at the same height and bottom. The region above the horizontal fin 1011 forms a gate trench 104 relative to the vertical fin portion 1012. The L-shaped fin 101 is essentially defined by the second trench 103, the first trench 102, and the gate trench 104. Figure 4B and Figure 5B As shown.

[0073] The embedded conductor 106 can be straight, filling the first dielectric layer 105 of the second trench 103, and extending along the second direction to the entire length of the second trench 103. The embedded conductor 106 is isolated from the semiconductor substrate 100 at the bottom of the second trench 103 through the first dielectric layer 105 in the second trench 103, and is electrically connected to the second source / drain region 101b through a conductive contact structure 107. The top surfaces of the embedded conductor 106 and the conductive contact structure 107 are flush with each other and both are lower than the top surface of the second source / drain region 101b. The conductive contact structure 107 is used to realize the electrical connection between the embedded wire 106 and the second source / drain region 101b. The conductive contact structure 107 is located in the second trench 103 and between the second source / drain region 101b and the embedded wire 106. One sidewall of the conductive contact structure 107 is in contact with the sidewall surface of the second source / drain region 101b, and the other sidewall of the conductive contact structure 107 is in contact with the sidewall surface of the embedded wire 106. The bottom surface of the conductive contact structure 107 is isolated from the surface of the semiconductor substrate 100 at the bottom of the second trench 103 by a first dielectric layer 105.

[0074] Furthermore, the embedded conductor 106 can be formed using processes such as vapor deposition, electroplating, chemical vapor deposition, and atomic layer deposition. It can be a single-layer structure or a stacked structure. The stacked structure, for example, includes two layers: a metal bottom layer and a polycrystalline silicon top layer. The metal bottom layer can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold, but is not limited thereto. The polycrystalline silicon top layer can be a heavily doped polycrystalline silicon layer, such as an N-type doped polycrystalline silicon layer, or a metal silicide layer formed by reacting with polycrystalline silicon. The materials of the first dielectric layer 105 and the second dielectric layer 108 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The materials of the conductive contact structure 107 can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold.

[0075] A gate dielectric layer 109 is also formed between the gate 110 and the L-shaped fin 101 (including the vertical fin portion 1012 and the horizontal fin portion 1011). The gate dielectric layer 109 is used to isolate the gate 110 and the L-shaped fin 101. The top surface of the gate 110 is lower than the top surface of the vertical fin portion 1011, and the sidewall of the gate 110 only partially overlaps with the first source / drain region 101a in height. To avoid leakage between the first source / drain region 101a and the gate 110, a gate isolation layer 111 is covered on the gate 110, that is, the gate 110 is covered and buried by the gate isolation layer 111. Preferably, the top surface of the gate isolation layer 111 is flush with the top surface of the vertical fin portion 1012, that is, the gate isolation layer 111 exposes the top surface of the vertical fin portion 1012, providing a flat operating platform for subsequent processes. The gate dielectric layer 109 can be formed using a thermal oxidation (dry or wet) process. The gate film layer corresponding to the gate 110 can be formed using physical vapor deposition or chemical vapor deposition. The gate material can be polycrystalline silicon or a metal gate material. When the gate 110 is made of polycrystalline silicon, the gate dielectric layer 109 can be made of silicon dioxide. When the gate 110 is made of a metal gate material, the gate dielectric layer 109 can be made of a high-k dielectric with a dielectric constant K greater than 7. The gate 110 has a stacked structure, which includes a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 109. The gate isolation layer 111 can be formed using chemical vapor deposition, atomic layer deposition, or other processes. The material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0076] In this embodiment, the L-shaped transistor forms an L-shaped vertical conductive channel in the current flow direction from the first source / drain region 101a to the bottom of the second source / drain region 101b. Compared to a planar transistor, the vertical L-shaped channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillars (i.e., fins) between the first source / drain region 101a and the second source / drain region 101b, thus overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. Therefore, even as the device size shrinks, although the absolute distance between the first source / drain region 101a and the second source / drain region 101b decreases, the short-channel effect of the transistor can still be effectively improved because the formed conductive channel is an L-shaped vertical conductive channel. Furthermore, the second source / drain region 101b of the L-type transistor of the present invention is located at the bottom and can be led out through embedded wires buried outside the sidewalls of the L-type fins extending in the second direction, avoiding direct lead-out from the transistor surface. This makes it easier to form isolation around the transistor, avoiding the use of enlarged shallow trench isolation rules, significantly reducing the difficulty of shallow trench isolation manufacturing, reducing the device area within the same size, and thus providing higher device integration density in a given space. The L-type transistor of the present invention is particularly suitable for semiconductor memories such as DRAMs with higher storage density.

[0077] The following will use the process of forming multiple L-type transistors of this invention in semiconductor memories such as dynamic random access memory as an example, and combine it with... Figure 3 , Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D as well as Figures 8A to 8D as well as Figure 9 This will be explained in detail in the method for fabricating the L-type transistor of the present invention. The first direction is the word line direction / row direction, and the second direction is the bit line direction / column direction. It should be understood that... Figures 4A to 4D The diagram shown is merely a top view of the structure corresponding to the manufacturing process of L-shaped transistors arranged in a two-row, two-column array. Figure 9 The diagram shown is merely a three-dimensional representation of a manufactured L-shaped transistor arranged in one row and two columns. For larger arrays, a single transistor can be used as a repeating unit. Figures 4A to 4D as well as Figure 9 It involves repeated expansion in at least one of the upward, downward, leftward, or rightward directions, corresponding to... Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D as well as Figures 8A to 8D It can be repeatedly expanded to the left and right using a transistor region as the repeating unit.

[0078] Please refer to Figure 3 An embodiment of the present invention provides a method for fabricating an L-type transistor, comprising the following steps:

[0079] S1, a semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form an L-shaped fin, a first trench and a second trench. The L-shaped fin includes a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at one end of the horizontal fin portion, and the bottom end of the vertical fin portion is connected to one end of the horizontal fin portion. The second trench extends along the second direction and exposes the sidewall of the L-shaped fin extending along the second direction. The first trench extends along the first direction and exposes the sidewall of the L-shaped fin extending along the first direction.

[0080] S2, a second source / drain region is formed in the horizontal fin portion, and an embedded wire is formed in the second trench, the embedded wire extending along the second direction and electrically connected to the second source / drain region;

[0081] S3, a gate is formed on the horizontal fin portion, and a first source / drain region is formed in the top end portion of the vertical fin portion, the gate extending along the first direction.

[0082] Figure 4A This is a top view schematic diagram of the L-type transistor fabrication method in one embodiment of the present invention during step S1. Figure 5A It is along Figure 4A A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figure 6A It is along Figure 4A A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 7A It is along Figure 4A A schematic diagram of the cross-sectional structure of the YY' line in the diagram; Figure 8A It is along Figure 4A A schematic diagram of the cross-sectional structure of the NN' line.

[0083] Please refer to Figure 4A , Figure 5A , Figure 6A , Figure 7A as well as Figure 8AIn step S1, firstly, a semiconductor substrate 100 with a flat surface is provided. The semiconductor substrate 100 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth process. The semiconductor substrate 100 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. Then, the semiconductor substrate 100 is etched along mutually perpendicular first and second directions to form a plurality of L-shaped fins 101, a plurality of first trenches 102 extending along the first direction, and a plurality of second trenches 103 extending along the second direction. Each L-shaped fin 101 extends along the second direction, each second trench 103 exposes the sidewalls of the plurality of adjacent L-shaped fins 101 extending along the second direction, and two adjacent first trenches 102 expose the sidewalls of the sandwiched L-shaped fins 101 extending along the first direction. The first trenches 102 and second trenches 103 have the same depth. The specific process is as follows:

[0084] Step 1: Form a first hard mask pattern (not shown) on the semiconductor substrate 100 to define a plurality of parallel second trenches 103 extending along a second direction and a plurality of parallel first trenches 102 extending along a first direction, such that the first hard mask pattern can cover and protect the semiconductor substrate 100 area corresponding to each L-shaped fin 101 and cover the semiconductor substrate 100 area corresponding to each first trench 102 and each second trench 103 exposed. The first hard mask pattern can be a stacked structure having an oxide layer (not shown) and a nitride layer (not shown). More specifically, the oxide layer and the nitride layer can be sequentially formed on the semiconductor substrate 100 using a deposition process or the like. Further, a photoresist (not shown) can be coated onto the surface of the nitride layer, and an exposure and development process can be performed to form a photoresist pattern (not shown). The photoresist pattern can expose the areas on the semiconductor substrate 100 where the first trench 102 and the second trench 103 are to be formed, and the exposed portions can have lines arranged side-by-side along a second direction and lines arranged side-by-side along a first direction. Then, the nitride layer and the oxide layer can be sequentially etched using an etching process that utilizes the photoresist pattern as an etching mask to form a first hard mask pattern. Afterward, the photoresist pattern is removed.

[0085] Step 2: The semiconductor substrate 100 is etched using an etching process that utilizes the first hard mask pattern as an etching mask to form multiple first trenches 102 of the same depth extending along a first direction and multiple second trenches 103 of the same depth extending along a second direction. The first trenches 102 and the second trenches 103 are connected at their intersections. The first trenches 102 are used to achieve isolation between adjacent L-type transistors, and the second trenches 103 are used to create buried conductors (i.e., bit lines of semiconductor memory). The semiconductor substrate 100 between two adjacent first trenches 102 and two adjacent second trenches 103 forms the initial vertical fin 1001 corresponding to the L-type transistor. The first trenches 102 extend from their ends along the first direction to the second trenches 103, so that the first trenches 102 and the second trenches 103 are connected on the sidewalls of the second trenches 103.

[0086] Step 3: A sacrificial layer can be formed on the entire structure to fill the first trench 102 and the second trench 103. The material of the sacrificial layer is different from that of the semiconductor substrate 100 to facilitate subsequent removal, such as silicon oxide, silicon nitride, or silicon oxynitride. Subsequently, a chemical mechanical planarization process can be used to remove the first hard mask pattern and the sacrificial layer above it to provide a flat process surface for subsequent processes.

[0087] Step 4: A second hard mask pattern (not shown) can be formed on the remaining sacrificial layer and semiconductor substrate 100. The second hard mask pattern is used to define multiple linear gate trenches 104 extending side by side along the first direction, so that the second hard mask pattern can expose a portion of the initial vertical fin 1001 on one side of the first trench 102 while covering and protecting the other areas of the initial vertical fin 1001 and the sacrificial layer. The formation process of the second hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be described again here.

[0088] Step 5: The exposed initial vertical fin 1001 is etched using an etching process that utilizes the second hard mask pattern as an etching mask. The etching depth is less than that of the first trench 102 to form a gate trench 104 and an L-shaped fin 101 that connect the first trench 102. The L-shaped fin 101 includes a horizontal fin portion 1011 extending along a second direction and a vertical fin portion 1012 vertically disposed at one end of the horizontal fin portion 1011. The bottom end of the vertical fin portion 1012 is connected to one end of the horizontal fin portion 1011. The horizontal fin portion 1011 is located at the bottom of the gate trench 104. The second trench 103 exposes the sidewall of the L-shaped fin 101 extending along the second direction. The gate trench 104 extends from the end of the first direction to the second trench 103, so that the gate trench 104 and the second trench 103 are connected on the sidewall of the second trench 103. The first trench 102, which communicates with the sidewall of the gate trench 104, exposes the sidewall of the horizontal fin portion 1011 extending in the first direction away from the end of the vertical fin portion 1012. The gate trench 104 communicates with the first trench 102 to expose the upper surface of the L-shaped fin 101. The side of the L-shaped fin 101 facing away from the gate trench 104 also has another first trench 102 to achieve isolation between the L-shaped fin 101 and the adjacent L-shaped fin 101.

[0089] Step Six: The second hard mask pattern and the sacrificial layer can be removed to expose the surface of the L-shaped fin 101. The process for removing the sacrificial layer can be a wet etching process, and the process for removing the second hard mask pattern can be a chemical mechanical planarization process or a wet etching process.

[0090] It should be noted that in the above steps, the first trench 102 and the second trench 103 are formed first, and then the gate trench 104 and the L-shaped fin 101 are formed. However, the technical solution of the present invention is not limited to this. The gate trench 104 can be etched in the semiconductor substrate 100 first, and then the first trench 102 and the second trench 103 can be etched further. The specific method is similar to the above and will not be repeated here. Figure 4A The first and second directions shown are not perpendicular, but rather form an angle of 5 to 85 degrees. This results in initial fins 1001 that are parallelogram-shaped and distributed in an island-like pattern. Furthermore, the second direction is perpendicular to the horizontal line of the semiconductor substrate 100 from left to right, allowing for more efficient utilization of the active area and resulting in smaller transistor cell areas; for example, a minimum of 4F can be achieved. 2 This allows for the matching of the hexagonal close-packed structure of the capacitors when connecting them to the vertical fin portion 1012, which is beneficial for manufacturing memory with higher storage density. In other embodiments of the present invention, Figure 4A and Figure 4BThe first and second directions shown can also be perpendicular, thus forming an initial fin 1001 distributed in a rectangular island shape.

[0091] Figure 4B This is a top view schematic diagram of the L-type transistor fabrication method in one embodiment of the present invention during step S2. Figure 5B It is along Figure 4B A schematic diagram of the cross-sectional structure of line XX' in the diagram; Figure 6B It is along Figure 4B A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 7B It is along Figure 4B A schematic diagram of the cross-sectional structure of the YY' line in the diagram; Figure 8B It is along Figure 4B A schematic diagram of the cross-sectional structure of the NN' line in the diagram.

[0092] Please refer to Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B In step S2, a second source / drain region 101b is formed in the horizontal fin portion 1011, and an embedded wire 106 is formed in the second trench 103. The embedded wire 106 extends along the second direction and is electrically connected to the second source / drain region 101b. The specific process is as follows:

[0093] Step one involves depositing a first dielectric layer 105 on the entire semiconductor substrate 100 structure, including the L-shaped fin 101, the first trench 102, and the second trench 103, using either chemical vapor deposition (CVD) or atomic layer deposition (ALD). A back-etching process is then performed to remove excess first dielectric layer 105 from areas outside the first trench 102 and the second trench 103. The remaining thickness of the first dielectric layer 105 at the bottom of the first trench 102 and the second trench 103 is sufficient to ensure that the bottom surface height of the subsequently formed buried conductor 106 reaches at least the bottom surface height of the second source / drain region 101b. This ensures electrical connection between the buried conductor 106 and the second source / drain region 101b, and also ensures isolation between the buried conductor 106 and the horizontal fin portion 1011 below the second source / drain region 101b and the semiconductor substrate 100. The material of the first dielectric layer 105 only needs to have a high etch selectivity relative to the semiconductor substrate 100; for example, it can be silicon oxide, silicon nitride, or silicon oxynitride.

[0094] Step two, a first sacrificial layer (not shown) can be deposited on the entire semiconductor substrate 100 structure having the first dielectric layer 105 using processes such as chemical vapor deposition (CVD) or spin coating dielectric layer (SOD) to fill the first trench 102, the second trench 103 and the gate trench 104. The material of the first sacrificial layer is different from that of the semiconductor substrate 100 and the first dielectric layer 105 to facilitate subsequent removal, such as silicon oxide, silicon nitride or silicon oxynitride.

[0095] Step 3: The first sacrificial layer in the region corresponding to the second source / drain region of the gate trench 104 is removed using processes such as masking, photolithography, and etching to expose the region of the horizontal fin portion 1011 used to form the second source / drain region. Then, the top exposed of the horizontal fin portion 1011 is doped with drain ions using a source / drain ion implantation process to form the second source / drain region 101b located at the end of the horizontal fin portion 1011 away from the vertical fin portion 1012. That is, the top surface of the second source / drain region 101b is the top surface of the horizontal fin portion 1011. Furthermore, depending on the transistor structure of different conductivity types, the second source / drain region 101b is doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doped ions in the second source / drain region 101b are N-type doped ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the second source / drain region 101b are P-type doped ions, such as boron (B) ions, boron fluoride (BF2+) ions, gallium (Ga) ions, and indium (In) ions.

[0096] Step 4: A second sacrificial layer (not shown) can be deposited on the entire semiconductor substrate 100 structure having the second source / drain region 101b using processes such as chemical vapor deposition (CVD) or spin coating dielectric layer (SOD) to fill the exposed gate trench 104. The top of the second sacrificial layer can be further planarized using a chemical mechanical polishing process so that the top surface of the second sacrificial layer and the vertical fin portion 1011 are flush. The material of the second sacrificial layer is different from that of the semiconductor substrate 100 and the first dielectric layer 105, but can be the same as that of the first sacrificial layer to facilitate subsequent removal, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0097] Step 5: Open the contact hole (not shown) in the second trench 103 for manufacturing the conductive contact structure 107 through a series of processes such as masking, photolithography, and etching. The contact hole exposes part of the sidewall of the second source / drain region 101b facing the second trench 103. When the top surface of the first dielectric layer 105 is higher than the top surface of the horizontal fin portion 1011, the contact hole extends into the first dielectric layer 105 to a certain depth, so that the bottom surface of the contact hole is between the top surface of the horizontal fin portion 1011 and the bottom surface of the second source / drain region 101b. Then, fill the contact hole with conductive metal material through processes such as electroplating, sputtering, or chemical vapor deposition to form the conductive contact structure 107 filled in the contact hole.

[0098] Step Six: Then, through a series of processes such as masking, photolithography, and etching, the conductive trench (not shown) for manufacturing the embedded wire 106 in the second trench 103 is opened. The depth of the conductive trench can be the same as the depth of the bottom surface of the conductive contact structure 107 (i.e., the depth of the contact hole), slightly deeper than the depth of the bottom surface of the conductive contact structure 107 (i.e., the depth of the contact hole), or slightly shallower than the depth of the bottom surface of the conductive contact structure 107 (i.e., the depth of the contact hole). The length of the conductive trench extends to... The entire second trench 103 is formed with one side of the conductive trench exposing the sidewall of the conductive contact structure 107 facing away from the second source / drain region 101b, while the other side of the conductive trench does not expose the sidewall of the vertical fin portion 1012 facing the second trench 103. In this case, the conductive trench and the contact hole containing the conductive contact structure 107 are connected. Conductive metal material is filled into the conductive trench through processes such as electroplating, sputtering, or chemical vapor deposition to form an embedded conductor 106 filled in the conductive trench. The embedded conductor 106 and the conductive contact structure 107 are preferably a laminated structure, which may include various materials such as tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold.

[0099] Step seven involves further etching the embedded wire 106 and conductive contact structure 107 so that the top surface of the embedded wire 106 and conductive contact structure 107 is lower than the top surface of the second source / drain region 101b (i.e., not higher than the top surface of the horizontal fin portion 1011). This also removes excess conductive metal material deposited at other locations during the formation of the embedded wire 106 and conductive contact structure 107. A second dielectric layer 108 is then deposited on the embedded wire 106 and conductive contact structure 107 using processes such as chemical vapor deposition (CVD) or atomic layer deposition. The material of the second dielectric layer 108 only needs to have a high etch selectivity relative to the semiconductor substrate 100, the buried wire 106, and the conductive contact structure 107. For example, it can be silicon oxide, silicon nitride, amorphous carbon, organic dielectric (ODL), and low-k dielectric (dielectric constant K is less than 4). The second dielectric layer 108 is etched back so that the top surface of the second dielectric layer 108 is flush with the top surface of the horizontal fin portion 1011, so as to bury the buried wire 106 and the conductive contact structure 107 and provide a flat process surface for the subsequent formation of the gate 110.

[0100] Step 8: Remove the second sacrificial layer and the first sacrificial layer to re-expose the first trench 102, the gate trench 104, and the second trench 103 having buried wires 106 and conductive contact structures 107 above the first dielectric layer 105.

[0101] It should be understood that the technical solution for forming the embedded wire 106 in this invention is not limited to this, as long as the embedded wire 106 can be electrically connected to the second source / drain region 101b and isolated from other parts of the L-shaped fin 101.

[0102] Figure 4C and Figure 4D This is a top view schematic diagram of the L-type transistor fabrication method in one embodiment of the present invention during step S3. Figure 5C In order to perform step S3 along Figure 4C A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figure 5D In order to perform step S3 along Figure 4D A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figure 6C In order to perform step S3 along Figure 4C A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 6D In order to perform step S3 along Figure 4D A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 7C In order to perform step S3 along Figure 4C A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 7DIn order to perform step S3 along Figure 4D A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 8C In order to perform step S3 along Figure 4C A schematic diagram of the cross-sectional structure of the YY' line in the diagram; Figure 8D In order to perform step S3 along Figure 4D A schematic diagram of the cross-sectional structure of the NN' line in the diagram.

[0103] Please refer to Figure 4C and Figure 4D , Figure 5C and Figure 5D , Figure 6C and Figure 6D , Figure 7C and Figure 7D , Figure 8C and Figure 8D In step S3, a gate dielectric layer 109, a gate 110, a first source / drain region 101a, and a gate isolation layer 111 are formed. The specific process includes:

[0104] Step 1: A third sacrificial layer (not shown) can be deposited on the entire semiconductor substrate 100 structure having the embedded wire 106 and the second dielectric layer 108 using processes such as chemical vapor deposition (CVD) or spin coating dielectric layer (SOD) to fill the exposed first trench 102, second trench 103 and gate trench 104. The top of the second sacrificial layer can be further planarized using a chemical mechanical polishing process so that the top surface of the second sacrificial layer and the vertical fin portion 1011 are flush. The material of the third sacrificial layer is different from that of the semiconductor substrate 100 and the first dielectric layer 105. It can be the same as the material of the first sacrificial layer and the second sacrificial layer to facilitate subsequent removal. For example, it can be silicon oxide, silicon nitride or silicon oxynitride.

[0105] Step 2: The area of ​​the gate trench 104 used to form the gate is reopened through a series of processes such as masking, photolithography, and etching, that is, a gate filling trench (not shown) is formed. The gate filling trench extends along the first direction and passes through the second trench 103. One side of the gate filling trench exposes the sidewall of the vertical fin portion 1012 facing the gate trench 104, and the bottom of the gate filling trench exposes the top surface of the second source / drain region 101b. Thermal oxidation (wet oxidation or dry oxidation) or in-situ vapor generation process (ISSG) can be used to form a gate dielectric layer 109 on the sidewall and bottom surface of the gate filling trench. In addition, when the gate 110 formed later is a metal gate, a high-K dielectric (K greater than 7) can be deposited by chemical vapor deposition or atomic layer deposition lamp process to form the gate dielectric layer 109.

[0106] Step 3: Deposit gate material on the surface of the gate dielectric layer 109 through processes such as evaporation, electroplating, chemical vapor deposition, and atomic layer deposition until the gate filling trench is filled to form the gate 110. The gate 110 can be a single-layer structure or a multilayer structure. Its material can be a material used to make polysilicon gates, such as undoped polysilicon or doped polysilicon, or a material used to make metal gates, such as a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 109.

[0107] Step 4: Remove the third sacrificial layer and deposit a gate isolation layer 111 using processes such as chemical vapor deposition until the first trench 102, the second trench 103, and the gate trench 104 are filled. The material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Then, the top surface of the gate isolation layer 111 can be further planarized to the top surface of the vertical fin portion 1011 using a chemical mechanical planarization process. At this time, the gate isolation layer 111 covers the gate 110 and fills the first trench 102, the second trench 103, and the gate trench 104 above the horizontal fin portion 1011, burying the gate 110 in the gate trench 104, thus forming a buried gate 110 (i.e., a word line of the semiconductor memory) on the horizontal fin portion 1011.

[0108] Step 5: The top portion of the vertical fin portion 1012 is doped with source ions using a source / drain ion implantation process to form a first source / drain region 101a located at the top portion of the vertical fin portion 1012. That is, the top surface of the first source / drain region 101a is the top surface of the vertical fin portion 1012. Furthermore, the first source / drain region 101a is doped with ions of the same conductivity type as the second source / drain region 101b.

[0109] The three-dimensional structure of the L-type transistor obtained by the fabrication method of the present invention can be referred to Figure 9 As shown.

[0110] It should be noted that in the above embodiments, the second source / drain region 101b is formed before the embedded bit line 106 is formed and the first source / drain region 101a is formed after the gate 110 is formed, as examples. However, the technical solution of the present invention is not limited to this. In one embodiment of the present invention, the second source / drain region 101b can be formed in the horizontal fin portion 1011 before the embedded wire 106 is formed, and the first source / drain region 101a can be formed in the top end portion of the vertical fin portion 1012 at the same time. In another embodiment of the present invention, after the gate 110 is formed, the first source / drain region 101a can be formed in the top end portion of the vertical fin portion 1012 using the gate 110 as a mask, and the second source / drain region 101b can be formed in the horizontal fin portion 1011 at the same time, thereby making the embedded wire 106 electrically connected to the second source / drain region 101b. The specific formation processes of the embedded bit line 106, the first source / drain region 101a, and the second source / drain region 101b in these embodiments are similar to those in the above embodiments, and will not be repeated here.

[0111] In summary, the method for fabricating the L-type transistor of the present invention involves first etching a semiconductor substrate along a first direction and a second direction to form an L-type fin, a first trench, and a second trench; then, forming a buried conductive line extending along the second direction in the second trench, forming a gate on the horizontal fin portion, forming a first source / drain region in the vertical fin portion, and forming a second source / drain region in the horizontal fin portion, thereby forming an L-type transistor. This method is simple and can achieve isolation between the L-type transistor and adjacent devices through the first and second trenches, avoiding the use of enlarged shallow trench isolation rules, significantly reducing the difficulty of shallow trench isolation manufacturing and the process defects of the isolation structure, which is beneficial for further miniaturization of product size and improvement of device performance.

[0112] Please continue to refer to this. Figure 9 , Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D as well as Figures 8A to 8DAn embodiment of the present invention also provides a semiconductor memory, including a plurality of L-type transistors as described in the present invention. These L-type transistors are formed on the same semiconductor substrate 100 and arranged in an array along a first direction and a second direction in cell rows and cell columns. Each L-type transistor is connected to a corresponding storage capacitor to form a storage cell and a storage array. The gate trenches 104 of all L-type transistors in each cell row are connected as one unit (i.e., connected as one unit along the row direction), so that the gates 110 of all L-type transistors in the cell row are connected as one unit to serve as a word line (WL) of the semiconductor memory. The buried wires 106 of all L-type transistors in each cell column are connected as one unit to serve as a bit line (BL) of the semiconductor memory.

[0113] The semiconductor substrate 100 also has a second trench 103 extending along the second direction. The second trench 103 exposes the sidewalls of the L-shaped fins 101 of all the L-shaped transistors on the cell column extending along the second direction. The bit line (i.e., the buried conductor 106) is formed in the second trench 103. The second source / drain regions 101b of all the L-shaped transistors on the cell column are exposed in the second trench 103 and electrically connected to the bit line. The first trench 102 extends along the first direction and passes through the second trench 103. The gate trenches 104 of the L-shaped fins 101 of all the L-shaped transistors on the cell column extend along the first direction and pass through the second trench 103. The first trench 102 and the gate trenches 104 are both connected to the second trench 103 on the sidewalls of the second trench 103, so that the word line (i.e., the gate) 110 spans the bit line (i.e., the buried conductor 106). In other words, the multiple first trenches 102 extending along the first direction and the second trenches 103 extending along the second direction intersect each other, which can define the location of each memory cell and define the memory array of the semiconductor memory of the present invention.

[0114] The semiconductor memory of the present invention, by employing the L-type transistors of the present invention to form the memory array, increases the effective channel length while occupying the same substrate area, overcomes the short-channel effect, and the bit lines are buried at the bottom, requiring direct lead-out from the transistor surface, making it easier to form isolation between transistors in the array. This reduces the memory cell area within the same size, thus enabling a memory cell area of ​​less than 8F. 2 (e.g., 4F) 2 The densely packed memory array improves device integration.

[0115] Please continue to refer to this. Figure 3 as well as Figures 4A to 4D , Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D , Figures 8A to 8D as well as Figure 9 The present invention also provides a method for fabricating a semiconductor memory. Multiple L-type transistors are fabricated using the L-type transistor fabrication method described herein, and all the L-type transistors are formed on the same semiconductor substrate 100 and arranged in an array along a first direction and a second direction in cell rows and cell columns. The gates 110 of all the L-type transistors in each cell row are connected as a single unit to form a word line of the semiconductor memory; the embedded wires 106 of all the L-type transistors in each cell column are connected as a single unit to form a bit line of the semiconductor memory. The specific fabrication process can be referred to the L-type transistor fabrication method described above, and will not be repeated here.

[0116] The semiconductor memory fabrication method of the present invention uses the L-type transistor fabrication method of the present invention to fabricate multiple L-type transistors, which simplifies the process and achieves a cell area of ​​less than 8F. 2 (e.g., 4F) 2 This densely packed memory array improves device integration. Furthermore, adjacent rows of memory cells can be isolated via the first trench, and adjacent columns can be isolated via the second trench. This avoids the need for enlarged shallow trench isolation rules, significantly reducing the manufacturing difficulties and process defects of shallow trench isolation structures, which is beneficial for further miniaturization of product size and improvement of device performance. In addition, embedded bit lines can be formed, eliminating the need for direct routing from the memory array surface, making it easier to form isolation between transistors in the array and reducing the memory cell area within the same size.

[0117] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. An L-type transistor, characterized in that, include: A semiconductor substrate having L-shaped fins, the L-shaped fins including a horizontal fin portion extending along a second direction and a vertical fin portion vertically disposed at one end of the horizontal fin portion, wherein the bottom end of the vertical fin portion is connected to one end of the horizontal fin portion, and a second source / drain region is formed in the horizontal fin, and a first source / drain region is formed in the top end of the vertical fin portion; and... A gate is disposed on the horizontal fin portion and extends along a first direction, both the first direction and the second direction are parallel to the surface of the semiconductor substrate, and the first direction and the second direction form an angle of 5°-85° or 90°. The semiconductor substrate further includes a first trench extending along the first direction, the first trench being located outside the two sidewalls of the L-shaped fin extending along the first direction, and the bottom of the first trench extending to the sidewall of the horizontal fin portion, exposing the two sidewalls of the L-shaped fin extending along the first direction in the first trench; the semiconductor substrate further includes a second trench extending along the second direction and exposing the sidewalls of the L-shaped fin extending along the second direction, the first trench extending along the end of the first direction to the second trench, such that the first trench and the second trench are connected on the sidewall of the second trench; An embedded conductor is electrically connected to the second source / drain region. The embedded conductor is embedded in the second trench and extends along a second direction. The gate extends along a first direction into the second trench and spans over the embedded conductor.

2. The L-type transistor as described in claim 1, characterized in that, It also includes a conductive contact structure formed in the second trench and disposed between the embedded wire and the second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the embedded wire. The bottom surface of the conductive contact structure is isolated from the semiconductor substrate surface at the bottom of the second trench.

3. The L-type transistor as described in claim 2, characterized in that, It also includes a first dielectric layer, which fills the second trench, and the embedded wire is located on the first dielectric layer, and the embedded wire is insulated from the semiconductor substrate through the first dielectric layer.

4. The L-type transistor as described in claim 3, characterized in that, The L-shaped transistor further includes a second dielectric layer that fills the second trench and buries the embedded wire therein.

5. The L-type transistor as described in claim 1, characterized in that, It also includes a gate dielectric layer and a gate isolation layer. The gate dielectric layer is formed between the gate and the L-shaped fin, and the gate isolation layer covers the gate and fills the space above the first trench, the second trench and the horizontal fin portion to bury the gate therein.

6. A method for fabricating an L-type transistor, characterized in that, Includes the following steps: A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction to form an L-shaped fin, a first trench and a second trench. The L-shaped fin includes a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at one end of the horizontal fin portion, and the bottom end of the vertical fin portion is connected to one end of the horizontal fin portion. The second trench extends along the second direction and exposes the sidewall of the L-shaped fin extending along the second direction. The first trench extends along the first direction and exposes the sidewall of the L-shaped fin extending along the first direction. An embedded conductor is formed in the second trench, the embedded conductor extending along the second direction; as well as, A gate is formed on the horizontal fin portion, the gate extends along the first direction, both the first direction and the second direction are parallel to the surface of the semiconductor substrate, and the first direction and the second direction form an angle of 5°-85° or 90°.

7. The method for fabricating an L-type transistor as described in claim 6, characterized in that, The steps of forming the L-shaped fin, the first groove, and the second groove include: The semiconductor substrate is etched along the first direction and the second direction, respectively, to form a first trench and a second trench of the same depth; and, The semiconductor substrate on one side of the first trench is etched along the first direction, with the etching depth being less than the depth of the first trench, to form a gate trench connecting the first trench and the L-shaped fin. The horizontal fin portion of the L-shaped fin is located at the bottom of the gate trench, and the vertical fin portion of the L-shaped fin is located on one side of the gate trench.

8. The method for fabricating an L-type transistor as described in claim 6, characterized in that, Before forming the embedded conductor, a second source / drain region is first formed in the horizontal fin portion, and the embedded conductor formed thereafter is electrically connected to the second source / drain region; after forming the gate, a first source / drain region is formed in the top portion of the vertical fin portion; or, before forming the embedded conductor, a first source / drain region is formed in the top portion of the vertical fin portion and a second source / drain region is formed in the horizontal fin portion, and the embedded conductor formed thereafter is electrically connected to the second source / drain region; or, after forming the gate, a first source / drain region is formed in the top portion of the vertical fin portion and a second source / drain region is formed in the horizontal fin portion, and the embedded conductor is electrically connected to the second source / drain region.

9. The method for fabricating an L-type transistor as described in claim 6, characterized in that, Before forming the embedded conductor, a first dielectric layer is filled in the second trench, the embedded conductor is located on the first dielectric layer in the second trench, and the embedded conductor is insulated from the semiconductor substrate through the first dielectric layer.

10. The method for fabricating an L-type transistor as described in claim 7, characterized in that, The step of forming the gate includes: A second dielectric layer is filled into the second trench, and the top surface of the second dielectric layer is flush with the top surface of the horizontal fin portion; A gate dielectric layer is formed on the surface of the L-shaped fin, the first trench, and the second trench; Gate material is filled in the first trench, the second trench, and the gate trench, and the gate material is etched to the surface of the gate dielectric layer on the horizontal fin portion, leaving only a portion of the gate material in the gate trench to form a gate extending along the first direction in the gate trench; and, A gate isolation layer is filled in the second trench, the first trench, and the gate trench to bury the gate in the gate trench.

11. A semiconductor memory, characterized in that, include: A plurality of L-type transistors as described in any one of claims 1 to 5, wherein all the L-type transistors are formed on the same semiconductor substrate and arranged in an array along a first direction and a second direction in cell rows and cell columns; the gates of all the L-type transistors in each cell row are connected together to form a word line of the semiconductor memory; The embedded wires of all the L-type transistors on each of the cell columns are connected together to form a bit line of the semiconductor memory.

12. A method for fabricating a semiconductor memory, characterized in that, include: A plurality of L-type transistors are fabricated using the fabrication method of any one of claims 6 to 10, wherein all the L-type transistors are formed on the same semiconductor substrate and arranged in an array along a first direction and a second direction in cell rows and cell columns, and the gates of all the L-type transistors in each cell row are connected as a single unit to serve as a word line of the semiconductor memory. The embedded wires of all the L-type transistors on each of the cell columns are connected together to form a bit line of the semiconductor memory.

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