Method of manufacturing a semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, which can appropriately bond a plurality of different components to a conductive plate. A conductive plate having a first configuration region set on the front surface and a second configuration region located at a position different in height from the first configuration region is prepared. Next, a first bonding material is applied to the first configuration region, and a second bonding material different from the first bonding material is applied to the second configuration region. Then, the first component can be bonded to the first configuration region via the first bonding material, and the second component can be bonded to the second configuration region via the second bonding material. In this case, the heights of the first configuration region and the second configuration region set on the front surface of the conductive plate are different. Therefore, by, for example, flexibly using a mask by means of screen printing, different first and second bonding materials suitable for the first and second components can be applied to the first and second configuration regions, respectively.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] Semiconductor devices include semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Such semiconductor devices are used, for example, as power conversion devices.

[0003] A semiconductor device includes a semiconductor chip including the above-described semiconductor element. Such a semiconductor chip is disposed on a conductive plate such as a circuit pattern. When manufacturing such a semiconductor device, solder is applied to a region where the semiconductor chip is disposed on the conductive plate by stencil printing such as screen printing or metal mask printing. In stencil printing, a mask having openings formed corresponding to each arrangement region can be disposed on the conductive plate, and paste-like solder can be applied to each opening using a squeegee. Therefore, the productivity of the method for applying solder by stencil printing is high, and cost can be suppressed.

[0004] In addition, in a semiconductor device, not only a semiconductor chip is disposed on a conductive plate, but also components such as external connection terminals and electronic components are disposed together with the semiconductor chip according to its form. Thereby, the semiconductor device can achieve a desired function and can also improve convenience.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: International Publication No. 2014 / 148319

[0008] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2017-038019 Summary of the Invention

[0009] Technical Problem

[0010] In stencil printing, only one type of solder can be applied. Therefore, for a semiconductor device in which a plurality of different components are disposed on a conductive plate, only a common solder can be applied to the arrangement regions of the respective components on the conductive plate. However, in this case, among the different components disposed in the respective arrangement regions on the conductive plate, there are components that are properly joined to the conductive plate and components that are not properly joined and cause joining failures.

[0011] The present invention has been made in view of this aspect, and an object thereof is to provide a method for manufacturing a semiconductor device capable of appropriately joining a plurality of different components to a conductive plate.

[0012] Technical Solution

[0013] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a preparation step of preparing a conductive plate having a first arrangement region set on a front surface and a second arrangement region located at a position different in height from the first arrangement region; a coating step of coating a first bonding material on the first arrangement region and a second bonding material different from the first bonding material on the second arrangement region; and a bonding step of bonding a first component to the first arrangement region via the first bonding material and bonding a second component to the second arrangement region via the second bonding material.

[0014] Technical Effect

[0015] According to the disclosed technology, a plurality of different components can be appropriately joined to a conductive plate, and a reduction in the reliability of the semiconductor device can be suppressed. Description of the Drawings

[0016] FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figure 2 is a diagram for explaining the coating step of the method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 3 is a cross-sectional view of a main part of a semiconductor device according to the second embodiment.

[0019] Figure 4 is a diagram showing a contact component of a semiconductor device according to the second embodiment.

[0020] Figure 5 is a diagram for explaining a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Figure 6 is a cross-sectional view of a main part of a semiconductor device according to the third embodiment.

[0022] Figure 7 is a cross-sectional view of a main part of a semiconductor device according to the fourth embodiment.

[0023] Figure 8 is a diagram for explaining a method for manufacturing a semiconductor device according to the fourth embodiment.

[0024] Figure 9 is a cross-sectional view of a main part of a semiconductor device according to the fifth embodiment.

[0025] Figure 10 It is a diagram (part 1) for explaining the manufacturing method of the semiconductor device of the fifth embodiment.

[0026] Figure 11 It is a diagram (part 2) for explaining the manufacturing method of the semiconductor device of the fifth embodiment.

[0027] Symbol Explanation

[0028] 1 Conductive plate

[0029] 1a First configuration region

[0030] 1b Second configuration region

[0031] 2a First bonding material

[0032] 2b Second bonding material

[0033] 3a First component

[0034] 3b Second component

[0035] 4, 51 First mask

[0036] 4a First opening

[0037] 5, 52 Second mask

[0038] 5a Second opening

[0039] 10, 10a, 10b, 10c Semiconductor device

[0040] 11 Ceramic circuit board

[0041] 12 Insulating plate

[0042] 13 Metal plate

[0043] 14a, 14b, 14c, 14d, 14e Circuit pattern

[0044] 14a1 Chip configuration region

[0045] 14a2 Wiring configuration region

[0046] 14a4 Depression

[0047] 14b1 Component configuration region

[0048] 14c1 Step

[0049] 15a, 15b, 15c, 15d Solder

[0050] 16 Semiconductor chip

[0051] 17 Contact Component

[0052] 17a Main Body

[0053] 17b Hollow Hole

[0054] 17b1, 17b2 Opening End

[0055] 18 Metal Block

[0056] 19 Electronic Component

[0057] 21 Heat Dissipation Plate

[0058] 22 Lead Frame

[0059] 22a, 22b Connection Part

[0060] 23 Housing

[0061] 24 External Connection Terminal

[0062] 24a Internal Connection Part

[0063] 24b External Connection Part

[0064] 51a, 55a Wiring Opening

[0065] 52a, 54a, 57a Chip Opening

[0066] 53 Third Mask

[0067] 53a, 56a Component Opening

[0068] 54 Fourth Mask

[0069] 54b, 57b Foot

[0070] 55 Fifth Mask

[0071] 56 Sixth Mask

[0072] 57 Seventh Mask Detailed Implementation Manner

[0073] Hereinafter, with reference to the accompanying drawings, the implementation manner will be described.

[0074] [First Embodiment]

[0075] Using FIGS. 1 and Figure 2 the manufacturing method of the semiconductor device according to the first embodiment will be described. FIG. 1 is a diagram for explaining the manufacturing method of the semiconductor device according to the first embodiment. It should be noted that Figures 1A to 1C respectively represent the preparation process, coating process, and bonding process included in the manufacturing method of the semiconductor device. Figure 2This is a diagram for the coating process in the manufacturing method of the semiconductor device according to the first embodiment. FIGS. 1 and Figure 2 This is a diagram showing the main part in the manufacturing process of the semiconductor device in a side cross-sectional view.

[0076] First, a conductive plate 1 is prepared. The conductive plate 1 is made of a conductive material and has a plate shape. The conductive plate 1 can be used as, for example, a circuit pattern formed on an insulating plate such as ceramics, a circuit pattern of a metal substrate, and a lead frame. As Figure 1A shown, such a conductive plate 1 is respectively provided with a first arrangement region 1a and a second arrangement region 1b at different positions in height on the front surface. Regions with different heights can be formed by an etching method, stamping, or the like.

[0077] Next, as Figure 1B shown, a first bonding material 2a is coated on the first arrangement region 1a, and a second bonding material 2b different from the first bonding material 2a is coated on the second arrangement region 1b. As the coating method at this time, a stencil printing such as metal mask printing or screen printing can be used. In addition, the first bonding material 2a and the second bonding material 2b can be a paste-like solder or adhesive. Further, the second bonding material 2b can be a solder having at least one of the liquidus temperature, the composition of the flux material, and the amount of the flux material different from that of the first bonding material 2a. The coating process can be performed as follows, for example. As Figure 2 (A) of FIG. shows, first, the second bonding material 2b is coated on the second arrangement region 1b using a first mask 4 having a first opening 4a corresponding to the second arrangement region 1b set at a low position. Then, as Figure 2 (B) of FIG. shows, after removing the first mask 4, the first bonding material 2a is coated on the first arrangement region 1a using a second mask 5 having a second opening 5a corresponding to the first arrangement region 1a set at a high position. In this way, the first bonding material 2a and the second bonding material 2b coated on the first arrangement region 1a and the second arrangement region 1b are selected to be different materials suitable for the first component 3a and the second component 3b described later. In addition, by changing the thicknesses of the first mask 4 and the second mask 5, bonding materials with different thicknesses can also be respectively coated on the first arrangement region 1a and the second arrangement region 1b. By operating in this way, the first bonding material 2a and the second bonding material 2b coated on the first arrangement region 1a and the second arrangement region 1b can be set to different thicknesses suitable for the first component 3a and the second component 3b.

[0078] Then, it is joined to the first component 3a via the first joining material 2a in the first configuration region 1a, and joined to the second component 3b via the second joining material 2b in the second configuration region 1b. As the joining at this time, a heating process can be used. For example, first, using a jig or the like, the first component 3a is arranged via the first joining material 2a in the first configuration region 1a, and the second component 3b is arranged via the second joining material 2b in the second configuration region 1b. Next, while the positions of the first component 3a and the second component 3b are fixed by the jig, heating is performed. By operating in this way, the first joining material 2a and the second joining material 2b are hardened, and the first component 3a and the second component 3b can be joined. At this time, since the first joining material 2a and the second joining material 2b are selected to be materials suitable for joining the first component 3a and the second component 3b, the first component 3a and the second component 3b can be appropriately joined in the first configuration region 1a and the second configuration region 1b.

[0079] In the manufacturing method of the semiconductor device as described above, first, a conductive plate 1 having a first configuration region 1a set on the front surface and a second configuration region 1b located at a position different in height from the first configuration region 1a is prepared. Next, the first joining material 2a is applied to the first configuration region 1a, and a second joining material 2b different from the first joining material 2a is applied to the second configuration region 1b. Then, the first component 3a can be joined to the first configuration region 1a via the first joining material 2a, and the second component 3b can be joined to the second configuration region 1b via the second joining material 2b. In this case, the heights of the first configuration region 1a and the second configuration region 1b set on the front surface of the conductive plate 1 are different. Therefore, for example, by flexibly using a mask by screen printing, different first joining material 2a and second joining material 2b suitable for the first component 3a and the second component 3b can be applied to the first configuration region 1a and the second configuration region 1b, respectively. Therefore, the first component 3a and the second component 3b can be reliably joined to the first configuration region 1a and the second configuration region 1b of the conductive plate 1, and a decrease in the stability of the semiconductor device can be suppressed.

[0080] In the first embodiment, the case where the first configuration region 1a is provided at a high position on the front surface of the conductive plate 1 and the second configuration region 1b is provided at a low position has been described. Therefore, in Figure 1B (and Figure 2In the coating process shown, first, coating is performed in the second arrangement region 1b set at a low position, and then, coating is performed in the first arrangement region 1a set at a position higher than the second arrangement region 1b. However, it is not limited to this case. For example, in the case where the first arrangement region 1a is set at a low position and the second arrangement region 1b is set at a high position, coating can be first performed in the first arrangement region 1a and then in the second arrangement region 1b. That is, it is preferable to first perform coating in the arrangement region set at a low position and then in the arrangement region set at a high position. In addition, it is preferable that the height of the bonding material coated in the arrangement region set at a low position is lower than the height in the arrangement region set at a high position. That is, it is preferable that the thickness of the bonding material coated in the arrangement region set at a low position is smaller than the height difference between the high position and the low position. By such an operation, the next coating can be performed without contacting the previously coated bonding material.

[0081] It should be noted that in the first embodiment, the case where two arrangement regions, the first arrangement region 1a and the second arrangement region 1b, are provided on the front surface of the conductive plate 1 has been described. However, it is not limited to this case. Three or more arrangement regions with different heights are set on the front surface of the conductive plate 1, and by flexibly using masks applicable to each arrangement region, different bonding materials can also be coated.

[0082] [Second Embodiment]

[0083] In the second embodiment, Figure 3 and Figure 4 are used to more specifically describe the semiconductor device of the first embodiment. Figure 3 is a cross-sectional view of the main part of the semiconductor device of the second embodiment. It should be noted that Figure 3 shows an enlarged view of the end of the cross-section of the ceramic circuit board 11 included in the semiconductor device 10. In addition, Figure 4 is a view showing the contact member of the semiconductor device of the second embodiment. It should be noted that Figure 4 of (A) shows a top view of the contact member 17, Figure 4 of (B) shows Figure 4 a cross-sectional view taken along the single dotted line X-X of (A).

[0084] The semiconductor device 10 has at least a ceramic circuit board 11, a semiconductor chip 16 bonded to the front surface of the ceramic circuit board 11 via a solder 15a, and a contact member 17 bonded to the front surface of the ceramic circuit board 11 via a solder 15b. It should be noted that Figure 3 the solders 15a and 15b of the semiconductor device 10 shown are in a hardened state, and are solders obtained by performing a hardening treatment on the pasty solders 15a and 15b before hardening.

[0085] In addition, although a plurality of semiconductor chips 16 and contact members 17 can be provided as needed on the front surface of the ceramic circuit board 11, only one semiconductor chip 16 and one contact member 17 are illustrated in Figure 3 . It should be noted that the front surface refers to the surface on the side where the semiconductor chip 16 and the contact member 17 are arranged in the semiconductor device 10 ( Figure 3 the upper side in Figure 3 ). In addition, the back surface refers to the surface on the opposite side of the side where the semiconductor chip 16 and the contact member 17 are arranged in the semiconductor device 10 ( Figure 3 the lower side in

[0086] The ceramic circuit board 11 includes an insulating board 12, a metal board 13 formed on the back surface of the insulating board 12, and a circuit pattern 14a formed on the front surface of the insulating board 12. It should be noted that the circuit pattern 14a is one of the plurality of circuit patterns formed on the insulating board 12. The insulating board 12 is made of a highly heat-conductive ceramic such as alumina, aluminum nitride, or silicon nitride with excellent heat conductivity. The metal board 13 is made of a metal such as aluminum, iron, silver, copper, or an alloy containing at least one of them with excellent heat conductivity. The circuit pattern 14a is made of a metal such as copper or a copper alloy with excellent conductivity. In addition, in order to improve the corrosion resistance, metals such as nickel and / or gold can be formed on the front surface of the metal board 13 and the circuit pattern 14a by, for example, electroplating treatment. Specifically, in addition to nickel and / or gold, there are also nickel-phosphorus alloys and / or nickel-boron alloys, etc. In addition, gold can be laminated on the nickel-phosphorus alloy. As the ceramic circuit board 11 having such a configuration, for example, a DCB (Direct Copper Bonding) substrate and an AMB (Active Metal Brazed) substrate can be used. The ceramic circuit board 11 can conduct the heat generated in the semiconductor chip 16 to the Figure 3 lower side in

[0087] In addition, a chip arrangement area 14a1 and a wiring arrangement area 14a2 are respectively set on the front surface of the circuit pattern 14a. The wiring arrangement area 14a2 is formed at the bottom of the concave recess 14a4 and is located at a position lower than the chip arrangement area 14a1. It should be noted that the thickness of the circuit pattern 14a is preferably 0.10 mm or more and 5.00 mm or less, more preferably 0.20 mm or more and 2.00 mm or less. The depth of the recess 14a4 is preferably 0.1 times or more and 0.9 times or less of the thickness of the circuit pattern 14a, more preferably 0.1 times or more and 0.5 times or less of the thickness of the circuit pattern 14a. In addition, the width of the recess 14a4 is preferably 1.05 times or more and 1.50 times or less of the outer diameter of the opening end 17b2 of the contact member 17 described later, more preferably 1.1 times or more and 1.25 times or less of the outer diameter of the opening end 17b2 of the contact member 17. If the contact member 17 is arranged at the center of the wiring arrangement area 14a2 (recess 14a4) with such a diameter, the distance from the outer diameter of the opening end 17b2 of the contact member 17 to the inner wall of the recess 14a4 can be appropriately ensured.

[0088] The semiconductor chip 16 includes switching elements such as IGBT and power MOSFET. Such a semiconductor chip 16 has, for example, a drain (or collector) as a main electrode on the back surface and a gate and a source (or emitter) as main electrodes on the front surface. In addition, the semiconductor chip 16 includes diodes such as SBD (Schottky Barrier Diode) and FWD (Free Wheeling Diode) as required. Such a semiconductor chip 16 has a cathode as a main electrode on the back surface and an anode as a main electrode on the front surface. The back side of the semiconductor chip 16 is joined to the chip arrangement area 14a1 of the circuit pattern 14a by solder 15a.

[0089] As Figure 4 shown, the contact member 17 has a cylindrical main body portion 17a in which a hollow hole 17b penetrating between the through-opening ends 17b1 and 17b2 is formed inside. In Figure 3 , the side of the opening end 17b2 is joined to the recess 14a4 of the circuit pattern 14a by solder 15b. In addition, a pin-shaped external connection terminal (not shown) is pressed into the opening end 17b1 side facing the opening end 17b2 joined to the circuit pattern 14a. It should be noted that the external connection terminal is made of aluminum, iron, silver, copper, or an alloy containing at least one of them with excellent conductivity. The external connection terminal is rod-shaped, and its cross-section forms a square, for example. The external connection terminal is pressed into the hollow hole 17b of the contact member 17 and is electrically connected to the circuit pattern 14a via the contact member 17.

[0090] Such a contact member 17 is also made of aluminum, iron, silver, copper, or an alloy containing at least one of them, which has excellent electrical conductivity. In addition, in order to improve corrosion resistance, for example, metals such as nickel and / or gold can be formed on the front surface (the surface of the main body portion 17a and the surface of the hollow hole 17b) of the contact member 17 by electroplating treatment or the like. Specifically, in addition to nickel and / or gold, there are also nickel-phosphorus alloys and / or nickel-boron alloys. In addition, gold can be laminated on the nickel-phosphorus alloy. In addition, in the contact member 17, the inner diameters of the opening ends 17b1 and 17b2 of the hollow hole 17b are preferably 0.20 mm or more and 2.00 mm or less, more preferably 0.50 mm or more and 1.50 mm or less. The outer diameters of the opening ends 17b1 and 17b2 of the contact member 17 are preferably 1.00 mm or more and 2.50 mm or less, more preferably 1.50 mm or more and 2.00 mm or less. In addition, the contact member 17 may have a flange-shaped protrusion at either or both of the opening ends 17b1 and 17b2.

[0091] As described above, the solder 15a is disposed between the semiconductor chip 16 and the chip arrangement region 14a1 of the circuit pattern 14a. The paste-like solder 15a is hardened to bond the semiconductor chip 16 and the chip arrangement region 14a1 of the circuit pattern 14a. At this time, the hardened solder 15a conducts the heat from the semiconductor chip 16 to the circuit pattern 14a. Therefore, if the hardened solder 15a contains a lot of voids, the thermal conductivity is reduced. Therefore, a paste-like solder 15a made of a material in which the hardened solder 15a does not contain a large amount of voids is selected. Therefore, the paste-like solder 15a is preferably a solder containing a large amount of flux material, having high wettability, and a low melting point (liquidus temperature). Such a solder 15a uses a medium-temperature solder having a liquidus temperature of 200 °C or more and less than 225 °C, or a medium-high temperature solder. For example, a medium-high temperature solder such as a tin (Sn)-silver (Ag)-copper (Cu) system or a Sn-Ag-Cu-nickel (Ni)-germanium (Ge) system having a liquidus temperature of 219 °C is preferred. As the flux material, rosin reducing agents such as rosin acid and solvents such as butyl carbitol are used. In addition, acrylic-based and polyether-based polymers, thixotropic agents such as triglycerides and fatty acid esters, and active agents such as adipic acid and fumaric acid can be appropriately included. In this case, the amount of the flux material is preferably 10% or more and 15% or less by weight. In addition, as another solder 15a, a medium-temperature solder such as a Sn-indium (In)-Ag-bismuth (Bi) system having a liquidus temperature of 206 °C is preferably used, and the same flux material as described above is used. In this case, the amount of the flux material is preferably 10% or more and 15% or less by weight.

[0092] As described above, the solder 15b is disposed between the contact member 17 and the wiring arrangement region 14a2 of the circuit pattern 14a. The paste-like solder 15b is hardened to join the contact member 17 and the wiring arrangement region 14a2 of the circuit pattern 14a. At this time, it is possible that the paste-like solder 15b surges up from the hollow hole 17b of the contact member 17. If the solder 15b surges up from the hollow hole 17b of the contact member 17, the amount of the solder 15b in the wiring arrangement region 14a2 decreases, and the contact member 17 cannot be properly joined to the wiring arrangement region 14a2 of the circuit pattern 14a. Moreover, the external connection terminal cannot be pressed into the contact member 17, and when pressed, a load is applied to the contact member 17 and the contact member 17 may be bent. Therefore, the paste-like solder 15b is preferably a solder that does not contain a large amount of flux material, has low wettability, and has a high melting point (liquidus temperature) so that the paste-like solder 15b does not surge up from the hollow hole 17b of the contact member 17.

[0093] Compared with the paste-like solder 15a, the paste-like solder 15b preferably has a smaller amount of flux material. For example, in the case where the solder 15a and the solder 15b are the above-mentioned medium-high temperature solders having substantially the same liquidus temperature, the amount of the flux material of the paste-like solder 15b is smaller than the amount of the flux material of the paste-like solder 15a. In this case, the weight ratio of the flux material is preferably smaller than the weight ratio of the flux material of the paste-like solder 15a. On this basis, it is preferably 8% or more and 12% or less by weight.

[0094] In addition, compared with the solder 15a, the solder 15b preferably has a higher liquidus temperature. For example, in the case where the amounts of the flux materials of the paste-like solder 15a and the paste-like solder 15b are substantially equal, the liquidus temperature of the solder 15b is higher than the liquidus temperature of the solder 15a. In the case where the solder 15a is a medium-temperature solder such as an Sn-In-Ag-Bi system having a liquidus temperature of 206 °C, the solder 15b can be an Sn-Ag-Cu system, an Sn-Ag-Cu-Ni-Ge system, etc. having a liquidus temperature higher than that of the solder 15a and a liquidus temperature of 219 °C.

[0095] Next, Figure 5 A method of applying the paste-like solders 15a and 15b to the ceramic circuit board 11 of such a semiconductor device 10 will be described. Figure 5 It is a diagram for explaining a method of manufacturing a semiconductor device according to the second embodiment. It should be noted that Figure 5 (A) of Figure 5 (B) of

[0096] First, prepare the ceramic circuit board 11. As described above, the circuit pattern 14a of the ceramic circuit board 11 is respectively provided with a chip arrangement region 14a1 and a wiring arrangement region 14a2 at the bottom of the recessed portion 14a4 located at a position lower than the chip arrangement region 14a1.

[0097] Next, as shown in (A) of Figure 5 , a first mask 51 having a wiring opening 51a corresponding to the wiring arrangement region 14a2 is arranged on the circuit pattern 14a of the ceramic circuit board 11. Thereby, the front surface of the circuit pattern 14a except for the wiring arrangement region 14a2 is covered with the first mask 51. In this state, a squeegee (not shown) is slid on the first mask 51, and the paste solder 15b is applied from the wiring opening 51a to the wiring arrangement region 14a2 of the recessed portion 14a4. If the first mask 51 is removed, the solder 15b can be applied only to the wiring arrangement region 14a2 of the circuit pattern 14a.

[0098] Next, as shown in (B) of Figure 5 , a second mask 52 having a chip opening 52a corresponding to the chip arrangement region 14a1 is arranged on the circuit pattern 14a of the ceramic circuit board 11. Thereby, the front surface of the circuit pattern 14a except for the chip arrangement region 14a1 is covered with the second mask 52. In this state, a squeegee (not shown) is slid on the second mask 52, and the paste solder 15a is applied from the chip opening 52a to the chip arrangement region 14a1. If the second mask 52 is removed, the solder 15a can be applied only to the chip arrangement region 14a1 of the circuit pattern 14a. It should be noted that the first mask 51 and the second mask 52 are made of, for example, metal, resin, etc., and the thickness is 0.1 mm or more and 0.5 mm or less.

[0099] Then, using a jig or the like, the semiconductor chip 16 and the contact member 17 are arranged on the chip arrangement region 14a1 and the wiring arrangement region 14a2 of the circuit pattern 14a of the ceramic circuit board 11 via the solders 15a and 15b. If the solder hardening treatment is performed using a reflow furnace or the like in this state, a semiconductor device 10 is obtained in which the semiconductor chip 16 and the contact member 17 are joined via the hardened solders 15a and 15b on the chip arrangement region 14a1 and the wiring arrangement region 14a2 of the circuit pattern 14a of the ceramic circuit board 11 ( Figure 3 ).

[0100] Thus, in the method of manufacturing the semiconductor device 10 described above, a ceramic circuit board 11 having a circuit pattern 14a is prepared. The circuit pattern 14a has a chip arrangement area 14a1 and a wiring arrangement area 14a2 with a recess 14a4 at a position lower than the chip arrangement area 14a1 on the front side. Next, a paste solder 15b is applied to the wiring arrangement area 14a2 by metal mask printing, and a paste solder 15a is applied to the chip arrangement area 14a1. Then, the semiconductor chip 16 can be bonded to the chip arrangement area 14a1 via the paste solder 15a, and the contact member 17 can be bonded to the wiring arrangement area 14a2 via the paste solder 15b. In this case, the chip arrangement area 14a1 and the wiring arrangement area 14a2 are set at positions with different heights on the front side of the circuit pattern 14a. Therefore, by using the first mask 51 and the second mask 52 flexibly according to the area in metal mask printing, different solders 15a and 15b suitable for the semiconductor chip 16 and the contact member 17 can be applied to the chip arrangement area 14a1 and the wiring arrangement area 14a2 respectively. Thereby, voids are suppressed in the solder 15a under the semiconductor chip 16, and the upwelling of the solder 15b with respect to the contact member 17 is suppressed. Therefore, the semiconductor chip 16 and the contact member 17 can be reliably bonded to the chip arrangement area 14a1 and the wiring arrangement area 14a2 of the circuit pattern 14a, and a decrease in the stability of the semiconductor device 10 can be suppressed.

[0101] It should be noted that in the second embodiment, an example is given in which solders with different melting points (liquidus temperatures) or different amounts of flux are used for the paste solders 15a and 15b. However, this is not limited to this example, and solders with different flux components can also be used for the paste solders 15a and 15b.

[0102] In addition, in the second embodiment, an example is given in which the contact member 17 is arranged together with the semiconductor chip 16. However, this is not limited to the contact member 17, and for example, a wiring material made of a conductive material such as a lead frame or a connection pin can also be used.

[0103] [Third Embodiment]

[0104] In the third embodiment, Figure 6 a semiconductor device using a metal block as a wiring material in the second embodiment will be described. Figure 6 is a main part cross-sectional view of the semiconductor device of the third embodiment. It should be noted that Figure 6 the semiconductor device 10a shown magnifies the end of the cross-section near the ceramic circuit board 11 included in the semiconductor device 10a. In addition, components included in the semiconductor device 10a are denoted by the same reference numerals as those of the semiconductor device 10, and detailed descriptions thereof are omitted or simplified.

[0105] The semiconductor device 10a at least includes a ceramic circuit board 11, a semiconductor chip 16 bonded to the front surface of the ceramic circuit board 11 via a solder 15a, and a metal block 18 bonded to the front surface of the ceramic circuit board 11 via a solder 15c. It should be noted that Figure 6 The solders 15a and 15c of the shown semiconductor device 10a are in a hardened state, and are the solders obtained by subjecting the pasty solders 15a and 15c before hardening to a hardening process. Moreover, the semiconductor device 10a includes: a heat sink 21 provided on the back surface of the ceramic circuit board 11; a lead frame 22 electrically connected to the semiconductor chip 16 and the metal block 18; a housing 23 surrounding the ceramic circuit board 11 and the like; and an external connection terminal 24 electrically connected to the metal block 18.

[0106] The metal block 18 is in a rectangular parallelepiped or cube shape and is made of aluminum, iron, silver, copper, which have excellent conductivity, or an alloy containing at least one of them. In addition, in order to improve the corrosion resistance, for example, metals such as nickel and / or gold can be formed on the surface of the metal block 18 by electroplating treatment or the like. Specifically, in addition to nickel and / or gold, there are also nickel-phosphorus alloys and / or nickel-boron alloys, etc. Moreover, gold can be laminated on the nickel-phosphorus alloy.

[0107] The heat sink 21 is made of aluminum, iron, silver, copper, which have excellent conductivity, or an alloy containing at least one of them. In addition, in order to improve the corrosion resistance, for example, a material such as nickel can be formed on the front surface of the heat sink 21 by electroplating treatment or the like. Specifically, in addition to nickel, there are also nickel-phosphorus alloys, nickel-boron alloys, etc.

[0108] It should be noted that a cooler (not shown) can also be installed on the back surface side of the heat sink 21 via a solder or a silver solder or the like to improve the heat dissipation performance. In this case, the cooler is made of, for example, aluminum, iron, silver, copper, which have excellent thermal conductivity, or an alloy containing at least one of them. In addition, as the cooler, a heat sink, or a heat dissipation body composed of a plurality of heat sinks, and a cooling device using water cooling can be applied. In addition, the heat sink 21 can be integrally formed with such a cooler. In this case, the heat sink 21 is made of aluminum, iron, silver, copper, which have excellent thermal conductivity, or an alloy containing at least one of them. Then, in order to improve the corrosion resistance, for example, a material such as nickel can be formed on the front surface of the heat sink 21 integrated with the cooler by electroplating treatment or the like. Specifically, in addition to nickel, there are also nickel-phosphorus alloys, nickel-boron alloys, etc.

[0109] The lead frame 22 is also made of aluminum, iron, silver, copper, or an alloy containing at least one of them, which has excellent electrical conductivity. Additionally, in order to improve corrosion resistance, for example, metals such as nickel and / or gold can be formed on the surface of the lead frame 22 through electroplating treatment or the like. Specifically, in addition to nickel and / or gold, there are also nickel-phosphorus alloys and / or nickel-boron alloys, etc. Furthermore, gold can be laminated on the nickel-phosphorus alloy. The connection portion 22a on one end side of the lead frame 22 is electrically and mechanically connected to the main electrode of the semiconductor chip 16 via solder (not shown) or the like. The connection portion 22b on the other end side of the lead frame 22 is electrically and mechanically connected to the front surface of the metal block 18 by laser bonding or the like. Thus, the semiconductor chip 16 and the metal block 18 are electrically connected via the lead frame 22.

[0110] The housing 23 is, for example, box-shaped and made of a thermoplastic resin. Such resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile-butadiene-styrene copolymer (ABS) resin, etc. Additionally, the housing 23 is integrally formed with external connection terminals 24 made of a conductive material. The housing 23 is joined to the heat sink 21 by an adhesive, and the internal connection portion 24a on one end side of the external connection terminal 24 is electrically and mechanically connected to the front surface of the metal block 18 by laser bonding or the like. Thus, the external connection portion 24b on the other end side of the external connection terminal 24 is electrically connected to the semiconductor chip 16 via the lead frame 22, the metal block 18, and the external connection terminal 24.

[0111] Additionally, in the semiconductor device 10a, the inside of the housing 23 can also be sealed with a sealing material (not shown). The sealing material can be made of a thermosetting resin such as maleimide-modified epoxy resin, maleimide-modified phenol resin, maleimide resin, etc. Additionally, the sealing material can be made of silicone such as silicone resin. Such a sealing material is injected into the housing 23 from a predetermined injection port formed in the housing 23, and seals the ceramic circuit board 11, the semiconductor chip 16, the metal block 18, etc. on the heat sink 21.

[0112] Even in such a semiconductor device 10a, the paste solder 15a disposed between the semiconductor chip 16 and the chip arrangement region 14a1 of the circuit pattern 14a preferably contains no voids when hardened. Therefore, similarly to the second embodiment, the paste solder 15a is preferably a solder containing a large amount of flux material, having high wettability, and a low melting point (liquidus temperature). Such a solder 15a uses a medium-high temperature solder with a liquidus temperature of 200 °C or higher and lower than 225 °C. For example, a medium-high temperature solder such as an Sn-Ag-Cu system or an Sn-Ag-Cu-Ni-Ge system with a liquidus temperature of 219 °C is preferably used. As the flux material, resin reducing agents such as rosin acid, solvents such as butyl carbitol, etc. are used, and thixotropic agents such as acrylic-based and polyether-based polymers, glycerol triesters and fatty acid esters, and active agents such as adipic acid and fumaric acid are also used. In this case, the amount of the flux material is preferably 10% or more and 15% or less by weight.

[0113] As described above, the solder 15c is disposed between the metal block 18 and the wiring arrangement region 14a2 of the circuit pattern 14a. Thereafter, the paste solder 15c is hardened to join the metal block 18 and the wiring arrangement region 14a2 of the circuit pattern 14a. When power is applied between the lead frame 22 and the external connection terminal 24, heat is generated in the metal block 18. It is preferable that the heat generated from the metal block 18 is appropriately conducted to the back side of the ceramic circuit board 11. Therefore, if the hardened solder 15c contains a large amount of voids, the thermal conductivity is reduced. Therefore, a paste solder 15c made of a material that does not contain a large amount of voids after hardening is selected. Therefore, similarly to the solder 15a, the paste solder 15c also preferably contains a large amount of flux material and has high wettability. In addition, the metal block 18 has a larger heat capacity than other joined components such as the semiconductor chip 16. Therefore, in the solder hardening process, it is difficult to heat the joined portion of the metal block 18 compared to other joined portions such as the semiconductor chip. Therefore, the solder 15c is preferably a solder with a lower melting point (liquidus temperature) than the solder 15a. Such a solder 15c uses a low-temperature solder or a medium-low temperature solder with a liquidus temperature lower than 200 °C. For example, a low-temperature solder such as a Bi-Sn system with a liquidus temperature of 139 °C, or a medium-low temperature solder such as an Sn-zinc (Zn)-Bi system with a liquidus temperature of 196 °C is preferably used. As the flux material, resin reducing agents such as rosin acid, solvents such as butyl carbitol, etc. are used. In addition, thixotropic agents such as acrylic-based and polyether-based polymers, glycerol triesters and fatty acid esters, and active agents such as adipic acid and fumaric acid can be appropriately included. Similarly to the case of the solder 15a, in this case, the amount of the flux material is preferably 10% or more and 15% or less by weight.

[0114] Even in the semiconductor device 10a with such a configuration, solder 15a and 15c can be applied to the chip arrangement region 14a1 and the wiring arrangement region 14a2 of the circuit pattern 14a respectively by metal mask printing using the first mask 51 and the second mask 52 in the same manner as in the second embodiment.

[0115] Thereby, voids in the solder 15a at the lower part of the semiconductor chip 16 are suppressed, and voids in the solder 15c at the lower part of the metal block 18 are also suppressed. Therefore, the semiconductor chip 16 and the metal block 18 can be reliably joined to the chip arrangement region 14a1 and the wiring arrangement region 14a2 of the circuit pattern 14a, and a reduction in the stability of the semiconductor device 10a can be suppressed.

[0116] It should be noted that in the third embodiment, an example of arranging the metal block 18 electrically connected to the lead frame 22 and the external connection terminal 24 is illustrated. However, it is not limited to such a metal block 18. For example, a metal block 18 composed of a radiator or the like without electrical connection can also be used.

[0117] [Fourth Embodiment]

[0118] In the fourth embodiment, a semiconductor device using an electronic component instead of the wiring material in the second embodiment will be described. Figure 7 FIG. is a main part cross-sectional view of the semiconductor device of the fourth embodiment. It should be noted that Figure 7 the shown semiconductor device 10b magnifies an end portion of a cross-section near the ceramic circuit board 11 included in the semiconductor device 10b. In addition, components included in the semiconductor device 10b are denoted by the same reference numerals as those of the semiconductor devices 10 and 10a having the same configurations, and detailed descriptions thereof are omitted or simplified. Figure 7

[0119] The semiconductor device 10b has at least a ceramic circuit board 11, a semiconductor chip 16 joined to the front surface of the ceramic circuit board 11 via solder 15a, and an electronic component 19 joined to the front surface of the ceramic circuit board 11 via solder 15d. It should be noted that Figure 7 the shown solder 15a and 15d of the semiconductor device 10b are in a hardened state, and are solders obtained by performing a hardening process on the paste-like solder 15a and 15d before hardening.

[0120] On the insulating board 12 of the ceramic circuit board 11 in the fourth embodiment, circuit patterns 14b, 14c, and 14d are provided. It should be noted that the circuit patterns 14b and 14c are formed on the surface of the insulating board 12 at a predetermined interval. Illustration of the boundary between the circuit patterns 14c and 14d is omitted. The circuit pattern 14c has a step 14c1. For the circuit pattern 14c, the​Figure 7 The front face on the right side in Figure 7 is at the same height as the front face of the circuit pattern 14d, and the

[0121] front face on the left side in

[0122] is at the same height as the front face of the circuit pattern 14b. In addition, a component arrangement area 14b1 that straddles the gap between the circuit patterns 14b and 14c is set on the front faces of the circuit patterns 14b and 14c. A chip arrangement area 14a1 that is located at a position higher than the component arrangement area 14b1 is set on the front face of the circuit pattern 14d.

[0123] The electronic component 19 is, for example, a control IC (Integrated Circuit), a thermistor, a capacitor, a resistor, etc. Such an electronic component 19 is arranged on the circuit patterns 14b and 14c via solder 15d. Even in such a semiconductor device 10b, the solder 15a arranged between the semiconductor chip 16 and the chip arrangement area 14a1 of the circuit pattern 14d is the same as in the second embodiment, and a medium-high temperature solder having a liquidus temperature of 200°C or higher and lower than 225°C is used. For example, a medium-high temperature solder such as an Sn-Ag-Cu system and an Sn-Ag-Cu-Ni-Ge system having a liquidus temperature of 219°C is preferably used. Moreover, as a flux material, a resin reducing agent such as rosin acid, a solvent such as butyl carbitol, etc. are used. In addition, a polymer of an acrylic system and a polyether system, a thixotropic agent such as triglyceride and fatty acid ester, an active agent such as adipic acid and fumaric acid, etc. can be appropriately included. In this case, the amount of the flux material is preferably 10% or more and 15% or less by weight.As described above, the solder 15d is disposed between the electronic component 19 and the component arrangement regions 14b1 of the circuit patterns 14b and 14c. Subsequently, the paste-like solder 15d is hardened to bond the electronic component 19 to the component arrangement regions 14b1 of the circuit patterns 14b and 14c. At this time, if the solder 15d is used to connect across the gap between the circuit patterns 14b and 14c in a bridge shape, a short circuit will occur. In addition, the joints of the component arrangement regions 14b1 are very small compared to the joints of the chip arrangement region 14a1. Therefore, poor bonding is likely to occur, and it is necessary to reliably bond using a small amount of solder 15d. Therefore, the paste-like solder 15d is preferably a solder with less flux material than the paste-like solder 15a, moderate wettability, and a low melting point (liquidus temperature). Such a solder 15d uses a low-temperature solder with a liquidus temperature lower than 200°C, or a medium-low temperature solder. For example, a medium-low temperature solder such as an Sn-Zn-Bi system with a liquidus temperature of 196°C, or a low-temperature solder such as a Bi-Sn system with a liquidus temperature of 139°C is preferably used. As the flux material, resin reducing agents such as rosin acid, solvents such as butyl carbitol, etc. are used, and thixotropic agents such as acrylic-based and polyether-based polymers, glycerol triesters and fatty acid esters, and active agents such as adipic acid and fumaric acid are also used. The amount of the flux material of the paste-like solder 15d is less than the amount of the flux material of the paste-like solder 15a. In this case, the weight ratio of the flux material is preferably less than the weight ratio of the flux material of the solder 15a. On this basis, it is preferably, for example, 8% or more and 12% or less by weight.

[0124] Next, Figure 8 A method of applying the paste-like solders 15a and 15d to the ceramic circuit board 11 of such a semiconductor device 10b will be described. Figure 8 It is a diagram for explaining a method of manufacturing a semiconductor device according to the fourth embodiment. It should be noted that Figure 8 (A) and (B) respectively show a case where the solder 15d and 15a are sequentially applied to the component arrangement regions 14b1 of the circuit patterns 14b, 14c, 14d and the chip arrangement region 14a1 by metal mask printing.

[0125] First, a ceramic circuit board 11 is prepared. As described above, the circuit patterns 14b, 14c, and 14d of the ceramic circuit board 11 are respectively provided with a component arrangement region 14b1 and a chip arrangement region 14a1. The component arrangement region 14b1 is set at a position lower than the chip arrangement region 14a1.

[0126] Next, as Figure 8As shown in (A), a third mask 53 having a component opening 53a corresponding to the component arrangement region 14b1 is disposed on the circuit patterns 14b, 14c, 14d of the ceramic circuit board 11. Thus, the front surfaces of the circuit patterns 14b, 14c, 14d other than the component arrangement region 14b1 are covered by the third mask 53. In this state, a squeegee (not shown) is slid on the third mask 53, and the paste solder 15d is applied from the component opening 53a to the component arrangement region 14b1. At this time, by adjusting the material, tension, and the pressing strength of the squeegee against the mask surface of the third mask 53, the third mask 53 can be flexed toward the component arrangement region 14b1 while applying the solder. If the third mask 53 is removed, the solder 15d can be applied only to the component arrangement region 14b1 of the circuit patterns 14b, 14c.

[0127] Next, as Figure 8 shown in (B), a fourth mask 54 having a chip opening 54a corresponding to the chip arrangement region 14a1 is disposed on the circuit patterns 14b, 14c, 14d of the ceramic circuit board 11. Thus, the surfaces of the circuit patterns 14b, 14c, 14d other than the chip arrangement region 14a1 are covered by the fourth mask 54. In this state, a squeegee (not shown) is slid on the fourth mask 54, and the paste solder 15a is applied from the chip opening 54a to the chip arrangement region 14a1. If the fourth mask 54 is removed, the solder 15a can be applied only to the chip arrangement region 14a1 of the circuit pattern 14d. By adjusting the material, tension, and the pressing strength of the squeegee against the mask surface of the fourth mask 54, the application can be performed while maintaining the interval from the previously applied component arrangement region 14b1. Thus, the back surface of the fourth mask 54 can be prevented from contacting the solder 15d, and the solder 15d can be maintained. It should be noted that the fourth mask 54 may have feet 54b corresponding to the step 14c1 when disposed on the circuit patterns 14b, 14c, 14d.

[0128] Then, a semiconductor chip 16 and an electronic component 19 are disposed via the solders 15a, 15d on the chip arrangement region 14a1 and the component arrangement region 14b1 of the circuit patterns 14b, 14c, 14d of the ceramic circuit board 11 using a jig or the like. In this state, if a solder hardening process is performed using a reflow furnace or the like, a semiconductor device 10b is obtained in which the semiconductor chip 16 and the electronic component 19 are joined via the hardened solders 15a, 15d on the chip arrangement region 14a1 and the component arrangement region 14b1 of the circuit patterns 14b, 14c, 14d of the ceramic circuit board 11 ( Figure 7 ).

[0129] Accordingly, voids are suppressed in solder 15a at the lower part of semiconductor chip 16, and solder 15d at the lower part of electronic component 19 suppresses open circuits at minute joint portions and suppresses the generation of short circuits due to solder bridges. Therefore, semiconductor chip 16 and electronic component 19 can be reliably joined to chip arrangement region 14a1 and component arrangement region 14b1 of circuit patterns 14b, 14c, 14d, and a reduction in the reliability of semiconductor device 10b can be suppressed.

[0130] [Fifth Embodiment]

[0131] In the fifth embodiment, a semiconductor device in which a semiconductor chip, a contact component, and an electronic component are arranged on ceramic circuit board 11 will be described. Figure 9 FIG. is a main part cross-sectional view of the semiconductor device of the fifth embodiment. It should be noted that Figure 9 the semiconductor device 10c shown magnifies an end portion of a cross-section near ceramic circuit board 11 included in semiconductor device 10c. In addition, components included in semiconductor device 10c are denoted by the same reference numerals as those of semiconductor devices 10, 10a, 10b, and detailed descriptions thereof are omitted or simplified. Figure 9 Semiconductor device 10c includes at least ceramic circuit board 11, and semiconductor chip 16, contact component 17, and electronic component 19 joined to the front surface of ceramic circuit board 11 via solders 15a, 15b, 15d. It should be noted that

[0132] solders 15a, 15b, 15d of the semiconductor device 10c shown are in a hardened state and are solders obtained by subjecting pasty solders 15a, 15b, 15d before hardening to a hardening process. Figure 9 On insulating board 12 of ceramic circuit board 11 in the fifth embodiment, circuit patterns 14b, 14c, 14e are provided. It should be noted that circuit patterns 14b, 14c are formed on the front surface of insulating board 12 at a predetermined interval. Illustration of the boundary between circuit patterns 14c, 14e is omitted. Circuit pattern 14c includes step 14c1. For circuit pattern 14c, the

[0133] right-side front surface in is at the same height as the front surface of circuit pattern 14e, and the Figure 9 in of step 14c1 Figure 9The front surface on the left side in [it] is at the same height as the front surface of the circuit pattern 14b. In addition, on the front surfaces of the circuit patterns 14b and 14c, a component arrangement area 14b1 that straddles the gap between the circuit patterns 14b and 14c is set. On the front surface of the circuit pattern 14e, a chip arrangement area 14a1 located at a position higher than the component arrangement area 14b1 is set. In addition, a recessed portion 14a4 is formed on the front surface of the circuit pattern 14e, and a wiring arrangement area 14a2 is set at a position lower than the chip arrangement area 14a1 and the component arrangement area 14b1.

[0134] Even in such a semiconductor device 10c, the solder 15a disposed between the semiconductor chip 16 and the chip arrangement area 14a1 of the circuit pattern 14e uses a medium-high temperature solder having a liquidus temperature of 200 °C or higher and lower than 225 °C. For example, a medium-high temperature solder (medium-high temperature type) such as an Sn-Ag-Cu system or an Sn-Ag-Cu-Ni-Ge system having a liquidus temperature of 219 °C is preferably used. As a flux material, a rosin reducing agent such as rosin acid and a solvent such as butyl carbitol are used. In addition, a polymer of an acrylic acid system and a polyether system, a thixotropic agent such as a triglyceride and a fatty acid ester, and an active agent such as adipic acid and fumaric acid can be appropriately included. In this case, the amount of the flux material is preferably 10% by weight or more and 15% by weight or less.

[0135] As described above, the solder 15b is disposed between the contact member 17 and the wiring arrangement area 14a2 of the circuit pattern 14e. Similar to the second embodiment, in this case, the paste-like solder 15b is preferably a material that does not cause an upwelling from the hollow hole 17b of the contact member 17. In this case, compared with the paste-like solder 15a, the paste-like solder 15b is preferably a solder that does not contain a large amount of flux material, has low wettability, and has a high melting point (liquidus temperature). Such a solder 15b uses a high temperature solder having a liquidus temperature of 225 °C or higher. For example, a high temperature solder such as an Sn-antimony (Sb) system having a liquidus temperature of 241 °C is preferably used. As a flux material, a rosin reducing agent such as rosin acid and a solvent such as butyl carbitol are used. In addition, a polymer of an acrylic acid system and a polyether system, a thixotropic agent such as a triglyceride and a fatty acid ester, and an active agent such as adipic acid and fumaric acid can be appropriately included. In this case, the weight ratio of the flux material is preferably less than the weight ratio of the flux material of the paste-like solder 15a. On this basis, it is preferably, for example, 8% by weight or more and 12% by weight or less.

[0136] In addition, as described above, the solder 15d is disposed between the electronic component 19 and the component arrangement regions 14b1 of the circuit patterns 14b and 14c. Similar to the fourth embodiment, compared with the paste solder 15a, the paste solder 15d is preferably a solder with less flux material, moderate wettability, and a low melting point (liquidus temperature). Such a solder 15d uses a medium-temperature solder or a medium-low-temperature solder with a liquidus temperature lower than that of the solder 15a. For example, a medium-temperature solder such as an Sn-Zn-Bi system with a liquidus temperature of 196°C is preferred. As the flux material, a rosin reducing agent such as rosin acid, a solvent such as butyl carbitol, etc. are used. In addition, a polymer of an acrylic acid system and a polyether system, a thixotropic agent such as triglyceride and fatty acid ester, and an active agent such as adipic acid and fumaric acid can be appropriately contained. In this case, the weight ratio of the flux material is preferably smaller than the weight ratio of the flux material of the paste solder 15a. On this basis, it is preferably, for example, 8% or more and 12% or less by weight.

[0137] Next, use Figure 10 and Figure 11 to illustrate the method of applying the paste solders 15a, 15b, and 15d to the ceramic circuit board 11 of such a semiconductor device 10c. Figure 10 and Figure 11 are diagrams for explaining the manufacturing method of the semiconductor device of the fifth embodiment. It should be noted that Figure 10 in (A), (B) and Figure 11 respectively show the cases where the solder 15d, 15b, and 15a are sequentially applied to the component arrangement regions 14b1, the wiring arrangement region 14a2, and the chip arrangement region 14a1 of the circuit patterns 14b, 14c, and 14e by metal mask printing.

[0138] First, prepare the ceramic circuit board 11. As described above, the component arrangement regions 14b1, the wiring arrangement region 14a2, and the chip arrangement region 14a1 are set in the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11. In addition, a recess 14a4 is formed in the circuit pattern 14e, and the wiring arrangement region 14a2 is set at a position lower than the component arrangement region 14b1 and the chip arrangement region 14a1.

[0139] Next, as Figure 10As shown in (A), a fifth mask 55 having a wiring opening 55a corresponding to the wiring configuration area 14a2 is disposed on the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11. Thus, the front surfaces of the circuit patterns 14b, 14c, and 14e other than the wiring configuration area 14a2 are covered by the fifth mask 55. In this state, a squeegee (not shown) is slid on the fifth mask 55 to apply the paste solder 15b from the wiring opening 55a to the wiring configuration area 14a2 of the recess 14a4. If the fifth mask 55 is removed, the solder 15b can be applied only to the wiring configuration area 14a2 of the circuit pattern 14e. It should be noted that the fifth mask 55 may be held horizontally on the circuit patterns 14b, 14c, and 14e when disposed thereon.

[0140] Next, as Figure 10 shown in (B), a sixth mask 56 having a component opening 56a corresponding to the component configuration area 14b1 is disposed on the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11. Thus, the front surfaces of the circuit patterns 14b, 14c, and 14e other than the component configuration area 14b1 are covered by the sixth mask 56. In this state, a squeegee (not shown) is slid on the sixth mask 56 to apply the paste solder 15d from the component opening 56a to the component configuration area 14b1. If the sixth mask 56 is removed, the solder 15d can be applied only to the component configuration areas 14b1 of the circuit patterns 14b and 14c.

[0141] As Figure 11 shown, the sixth mask 56 is removed, and a seventh mask 57 having a chip opening 57a corresponding to the chip configuration area 14a1 is disposed on the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11. Thus, the front surfaces of the circuit patterns 14b, 14c, and 14e other than the chip configuration area 14a1 are covered by the seventh mask 57. In this state, a squeegee (not shown) is slid on the seventh mask 57 to apply the paste solder 15a from the chip opening 57a to the chip configuration area 14a1. If the seventh mask 57 is removed, the solder 15a can be applied only to the chip configuration area 14a1 of the circuit pattern 14e. By separately adjusting the material, tension, and pressing strength of the squeegee against the mask surface of the sixth mask 56 and the seventh mask 57, it is possible to apply the solder while maintaining a gap from the previously applied wiring configuration area 14a2 and in another component configuration area. Thus, it is possible to maintain the previously applied solder in a state where the sixth mask 56 and the seventh mask 57 do not contact the previously applied solder. It should be noted that the seventh mask 57 may include a leg portion 57b corresponding to the step 14c1 when disposed on the circuit patterns 14b, 14c, and 14e. Thus, the seventh mask 57 can easily maintain a gap from the solder 15d.

[0142] Then, using a jig or the like, a semiconductor chip 16, a contact member 17, and an electronic component 19 are disposed via solders 15a, 15b, and 15d on the chip arrangement region 14a1, the wiring arrangement region 14a2, and the component arrangement region 14b1 of the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11. In this state, a solder hardening process is performed using a reflow furnace or the like. Through such an operation, a semiconductor device 10c is obtained in which the semiconductor chip 16, the contact member 17, and the electronic component 19 are joined via the hardened solders 15a, 15b, and 15d on the chip arrangement region 14a1, the wiring arrangement region 14a2, and the component arrangement region 14b1 of the circuit patterns 14b, 14c, and 14e of the ceramic circuit board 11( Figure 9 ).

[0143] Thereby, voids are suppressed from being generated in the solder 15a under the semiconductor chip 16, the solder 15b is suppressed from rising with respect to the contact member 17, and short circuits are suppressed from being generated due to the solder 15d under the electronic component 19. Therefore, the semiconductor chip 16, the contact member 17, and the electronic component 19 can be reliably joined to the chip arrangement region 14a1, the wiring arrangement region 14a2, and the component arrangement region 14b1 of the circuit patterns 14b, 14c, and 14e, and a reduction in the reliability of the semiconductor device 10c can be suppressed.

[0144] It should be noted that, as an example, the combinations and the numbers of the semiconductor chip 16, the contact member 17, and the electronic component 19 of the fifth embodiment can be arbitrarily determined. In addition, in such a case, the height of each of the arrangement regions only needs to be different, and is set according to the types and the number of combinations of the components used.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising: a preparation step of preparing a single conductive plate having a first arrangement region and a second arrangement region respectively set on the front surface, wherein the second arrangement region is located at a position higher than the first arrangement region; a coating step of covering the conductive plate including the second arrangement region with a first mask having a first opening corresponding to the first arrangement region, and coating an uncured first bonding material on the first arrangement region via the first opening without exceeding the height of the second arrangement region. After the coating of the first bonding material, instead of the first mask, covering the conductive plate of the first arrangement region coated with the uncured first bonding material without exceeding the height of the second arrangement region with a second mask having a second opening corresponding to the second arrangement region and having a flat surface disposed on the conductive plate, and coating an uncured second bonding material different from the first bonding material on the second arrangement region via the second opening; and a bonding step of bonding a first component to the first arrangement region via the first bonding material and bonding a second component to the second arrangement region via the second bonding material.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in the bonding step, the second mask is removed, the first component and the second component are respectively disposed on the first arrangement region and the second arrangement region via the uncured first bonding material and the uncured second bonding material, the uncured first bonding material and the uncured second bonding material are heated together to simultaneously bond the first component and the second component to the first arrangement region and the second arrangement region respectively.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the first bonding material and the second bonding material are solder, at least one of the liquidus temperature of the second bonding material, the composition of the flux material, and the amount of the flux material is different from that of the first bonding material.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the first component is a semiconductor chip and the second component is a wiring component, the amount of the flux material of the second bonding material is less than the amount of the flux material of the first bonding material.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the liquidus temperature of the second bonding material is substantially equal to the liquidus temperature of the first bonding material.

6. The method for manufacturing a semiconductor device according to claim 3, wherein the first component is a semiconductor chip and the second component is a wiring component, the liquidus temperature of the second bonding material is higher than the liquidus temperature of the first bonding material.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the amount of the flux material of the second bonding material is substantially equal to the amount of the flux material of the first bonding material.

8. The method for manufacturing a semiconductor device according to claim 4, wherein The wiring component is a cylindrical contact component, a connection pin, or a lead frame having a hollow hole formed therein.

9. The method of manufacturing a semiconductor device according to claim 3, wherein the first component is a semiconductor chip and the second component is a metal block, the liquidus temperature of the second bonding material is lower than the liquidus temperature of the first bonding material.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the amount of the flux material of the second bonding material is substantially equal to the amount of the flux material of the first bonding material.

11. The method of manufacturing a semiconductor device according to claim 3, wherein the first component is a semiconductor chip and the second component is an electronic component, the amount of the flux material of the second bonding material is less than the amount of the flux material of the first bonding material.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the liquidus temperature of the second bonding material is lower than the liquidus temperature of the first bonding material.

Images