Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package device includes a substrate, an encapsulant, a trench, a spacer, and a conductive material. The substrate includes a first surface, a second surface opposite the first surface, and a side surface extending from the first surface to the second surface. The encapsulant is disposed on the first surface of the substrate and includes a first surface and a second surface opposite the first surface. The trench passes through the encapsulant and includes a first portion adjacent the first surface of the encapsulant and a second portion between the first portion and the substrate. A width of the first portion is greater than a width of the second portion. The spacer is disposed in the trench and in contact with the encapsulant. The conductive material is disposed in the trench and encapsulates the spacer.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor packaging apparatus, and more specifically, to a semiconductor packaging apparatus including a spacer. Background Technology

[0002] In semiconductor packaging devices, shielding walls (e.g., segmented shielding (CPS)) are typically implemented to prevent electromagnetic interference between different electronic components. In implementing a CPS structure, trenches are formed to penetrate the molding compound (or sealant) of the semiconductor packaging device, and conductive material is filled into the trenches and grounded to form the shielding wall.

[0003] However, the coefficient of thermal expansion (CTE) of the conductive materials currently used to fill the trenches is much greater than that of the molding compounds (e.g., twice as large), making bending possible during subsequent operations such as baking, reflow, or cooling. Weight pressing can be used to suppress bending but may require additional tools, operations, and costs. Summary of the Invention

[0004] In one aspect, according to some embodiments, a semiconductor packaging device includes a substrate, a sealant, a trench, a gasket, and a conductive material. The substrate includes a first surface, a second surface opposite to the first surface, and side surfaces extending from the first surface to the second surface. The sealant is disposed on the first surface of the substrate and includes the first surface and the second surface opposite to the first surface. The trench extends through the sealant and includes a first portion adjacent to the first surface of the sealant and a second portion between the first portion and the substrate. The width of the first portion is greater than the width of the second portion. The gasket is disposed in the trench and contacts the sealant. The conductive material is disposed in the trench and encapsulates the gasket.

[0005] In another embodiment, according to some embodiments, a semiconductor packaging device includes a substrate, a sealant, a trench, a gasket, and a conductive material. The substrate includes a first surface, a second surface, and side surfaces extending from the first surface to the second surface. The sealant encapsulates the first surface of the substrate and includes the first surface and the second surface opposite to the first surface. The trench extends through the sealant. The gasket is disposed in the trench and contacts the sealant. The conductive material fills the trench and encapsulates the top surface of the gasket.

[0006] In another aspect, according to some embodiments, a method of manufacturing a semiconductor packaging device includes: providing a substrate; providing a sealant on the substrate; removing a portion of the sealant to form a trench; placing a gasket in the trench and in contact with the sealant; and forming a conductive material in the trench. The conductive material encapsulates the gasket. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that various features may not be drawn to scale, and the dimensions of features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0009] Figure 1B A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0010] Figure 1C A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0011] Figure 2A A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0012] Figure 2B A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0013] Figure 2C This illustration shows a cross-sectional view of a gasket in a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D as well as Figure 3E These are cross-sectional views of semiconductor packaging devices at various manufacturing stages.

[0015] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0016] According to some embodiments of this disclosure, during the implementation of a CPS structure in a semiconductor packaging device, a gasket with a CTE lower than that of the conductive material is placed in a trench of the sealant (or molding compound / encapsulant) of the semiconductor packaging device, and the use of conductive material to fill the trench and encapsulate the gasket can reduce or suppress bending of the semiconductor packaging device.

[0017] Figure 1A The illustration shows a cross-sectional view of a semiconductor packaging apparatus 1 according to some embodiments of the present disclosure. The semiconductor packaging apparatus 1 includes a substrate 10, a sealant (or encapsulant) 20, a trench (or gap / cavity) 30, a gasket 40, a conductive material 50, and electronic components 60 and 70.

[0018] The substrate includes a surface 101, a surface 102 opposite to surface 101, and a surface 103 extending from surface 101 to surface 102. The substrate 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 may include interconnect structures, such as redistribution layers (RDLs) or grounding elements. In some embodiments, the grounding element (e.g., conductive trace 105) is a via exposed from a side surface of the substrate 10. In some embodiments, the grounding element is a metal layer exposed from a side surface of the substrate 10. In some embodiments, the grounding element is a metal trace exposed from a side surface of the substrate 10. In some embodiments, surface 101 of the substrate 10 is referred to as the top surface or first surface, and surface 102 of the substrate 10 is referred to as the bottom surface or second surface.

[0019] Electronic component 60 is disposed on surface 101 of substrate 10. Electronic component 70 is disposed on surface 101 of substrate 10 and spaced apart from electronic component 60 by trench 30. Electronic component 60 may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. Electronic component 70 may have similar features to electronic component 60.

[0020] A sealant 20 is disposed on a surface 101 of a substrate 10. The sealant 20 includes a surface 201 and a surface 202 opposite to the surface 201. The sealant 20 encapsulates the surface 101 of the substrate 10 and the electronic components 60 and 70. In some embodiments, the sealant 20 comprises an epoxy resin with fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material having silicone dispersed therein, or a combination thereof.

[0021] The trench 30 passes through or penetrates the sealant 20. For example, the trench 30 divides the sealant 20 into a first portion covering electronic component 60 and a second portion covering electronic component 70. The trench 30 includes portions 32 and 34. Portion 32 is adjacent to surface 201 of the sealant 20. Portion 34 is between portion 32 and substrate 10. For example, portion 32 is above portion 34. The width W1 of portion 32 is greater than the width W2 of portion 34. The trench 30 may taper from surface 201 to surface 202 of the sealant 20. The substrate 10 includes a terminating layer 107 on or adjacent to surface 101 of the substrate 10. The terminating layer 107 is exposed from the trench 30. The top surface of the terminating layer 107 may have a groove corresponding to portion 34 of the trench 30. The groove may be formed during an operation, such as laser or etching, to form the trench 30.

[0022] like Figure 1A As shown, the groove 30 is defined by surfaces 203, 204, and 205 of the sealant 20. Surfaces 203 and / or 205 may be perpendicular to surface 201 of the sealant 20. Surfaces 203 and / or 205 may be slanted / inclined relative to surface 201 of the sealant 20 (e.g., as shown). Figure 1C As shown, surface 205 is inclined relative to surface 201 of sealant 20. Portions 32 and / or 34 of trench 30 may have a tapered shape. Portions 32 and / or 34 of trench 30 may gradually taper in a direction from surface 202 of sealant 20 toward surface 201. Surface 204 may be parallel to surface 201 of sealant 20. Surface 204 may be inclined relative to surface 201 of sealant 20. In some embodiments, when manufacturing a semiconductor package device 1, the inclined surface 204 may help guide the gasket 40 during placement of the gasket 40 in the trench 30. A trapezoidal portion 207 of sealant 20 is defined by surfaces 204 and 205. The trapezoidal portion 207 is located between portions 32 and 34 of trench 30. The trapezoidal portion 207 separates portions 32 and 34 of trench 30. The trapezoidal portion 207 may be trapezoidal. The trapezoidal portion 207 may have an angle greater than or equal to 90° defined by surfaces 204 and 205.

[0023] A gasket 40 is disposed in a trench 30. The gasket 40 contacts the sealant 20. The gasket 40 contacts or engages with the trapezoidal portion 207 of the sealant 20. A portion of the gasket 40 is in a portion 34 of the trench 30. At least half of the gasket 40 is in a portion 32 of the trench 30. The width WS of the gasket 40 is greater than the width W2 of the portion 34 of the trench 30. In some embodiments, the gasket 40 may contact surfaces 203 and / or 205 of the sealant 20. In some embodiments, the gasket 40 provides support force to the sealant 20 by engaging with the trapezoidal portion 207 of the sealant 20 to reduce bending of the semiconductor package device 1.

[0024] Gasket 40 may be completely within groove 30. Gasket 40 may be completely surrounded by sealant 20. The top or surface of gasket 40 may be smaller than or equal to the surface 201 of sealant 20. The top surface of gasket 40 may be coplanar with the surface 201 of sealant 20. Figure 1A In the illustrated embodiment, the gasket 40 has a spherical or annular shape. However, the shape of the gasket 40 is not limited. The gasket 40 can be square, conical, or any suitable shape. For example, the gasket 40 may taper gradually in the direction toward the substrate 10. The gasket 40 may contain a conductive material, such as a metal. The gasket 40 may contain copper (Cu). In some embodiments, the gasket 40 may contain a non-conductive material.

[0025] Conductive material 50 is disposed in trench 30. For example, conductive material 50 fills trench 30. Conductive material 50 encapsulates gasket 40. Conductive material 50 encapsulates the top surface of gasket 40. Figure 1A In the illustrated embodiment, conductive material 50 is further disposed on surface 201 and surface (or side surface) 209 of sealant 20 and surface 103 of substrate 10. Conductive material 50 covers sealant 20 and substrate 10. Conductive material 50 may provide electromagnetic shielding between electronic component 60 and electronic component 70. Conductive material 50 may comprise a metal, such as silver (Ag). Gasket 40 and conductive material 50 may form a CPS structure. Substrate 10 includes conductive traces 105 electrically connected to conductive material 50. Conductive traces 105 may be grounded.

[0026] In some embodiments, the coefficient of thermal expansion (CTE) of the conductive material 50 is greater than that of the sealant 20. For example, the CTE of the conductive material 50 may be in the range of about 45 ppm / °C to about 65 ppm / °C. The CTE of the conductive material 50 may be about 54 ppm / °C. The CTE of the sealant 20 may be in the range of about 5 ppm / °C to about 15 ppm / °C. The CTE of the sealant 20 may be about 9 ppm / °C. During temperature cycling in the manufacture of the semiconductor package device 1, the conductive material 50 may have greater shrinkage stress than the sealant 20. Bending problems may occur, and the width of the trench 30 may tend to decrease. In some embodiments, the CTE of the conductive material 50 is greater than that of the gasket 40. For example, the CTE of the gasket 40 may be in the range of about 10 ppm / °C to about 30 ppm / °C. The CTE of the gasket 40 may be about 17 ppm / °C. During temperature cycling in the manufacture of the semiconductor package device 1, the gasket 40 may have lower shrinkage stress than the conductive material 50, thereby reducing bending. The gasket 40 can reduce bending by engaging with the trapezoidal portion 207 of the sealant 20.

[0027] Figure 1B illustrate Figure 1A A top view of a portion of a semiconductor packaging device 1. For ease of understanding, only the sealant 20, trench 30, gasket 40, and conductive material 50 are depicted. Note that the gasket 40 is depicted with dashed lines because it is covered by the conductive material 50. See also Figure 1B The surface 201 of the sealant 20 defines openings 2011 and 2012. For example, from a top view, openings 2011 and 2012 correspond to the contour of the groove 30. Openings 2011 and 2012 expose the groove 30. The position of opening 2011 corresponds to the position of the gasket 40. Opening 2012 is positioned adjacent to opening 2011. Openings 2011 and 2012 are connected. The width W3 of opening 2011 is greater than the width W4 of opening 2012. See also Figure 1A The width W3 of opening 2011 can be the same as the width W1 of portion 32 of groove 30. The width W4 of opening 2012 can be the same as the width W2 of portion 34 of groove 30. For example... Figure 1B As shown, the width WS of the pad 40 is greater than the width W4 of the opening 2012, which helps to fix the position of the pad 40 during the placement of the pad 40 in the trench 30 when manufacturing the semiconductor packaging device 1.

[0028] Figure 2A A cross-sectional view illustrating a semiconductor packaging apparatus 2 according to some embodiments of the present disclosure is shown. The semiconductor packaging apparatus 2 has... Figure 1A It has similar characteristics to semiconductor packaging device 1. Some differences between semiconductor packaging device 2 and semiconductor packaging device 1 are described below.

[0029] Semiconductor packaging device 2 has a gasket 210 and a trench 30b. The gasket 210 may be part of a sealant 20. The gasket 210 and the sealant 20 are integrally formed. The gasket 210 and the sealant 20 have the same material. In other embodiments, the gasket 210 and the sealant 20 are formed of different materials. The surface 2101 of the gasket 210 is coplanar with the surface 201 of the sealant 20. The trench 30b gradually decreases in size from the surface 201 to the surface 202 of the sealant 20. The trench 30b is filled with a conductive material 50 to form a CPS structure between electronic components 60 and 70 to avoid electromagnetic interference (EMI) between electronic components 60 and 70.

[0030] Figure 2B illustrate Figure 2A A top view of a portion of the semiconductor packaging device 2. For ease of understanding, only the sealant 20, trench 30, gasket 210, and conductive material 50 are depicted. Several gaskets 210 are intermittently arranged along the trench 30b. Figure 2C Explanation along Figure 2B An example of a cross-sectional view of the gasket 210 of line AA' in the diagram. For example... Figure 2B and Figure 2C As shown, the side surface 210s of the pad 210 may be inclined relative to the surface 2101 of the pad 210. The pad 210 may gradually decrease in size in the direction from the surface 2101 toward the substrate 10.

[0031] Figure 3A , Figure 3B , Figure 3C , Figure 3D as well as Figure 3E These are cross-sectional views of semiconductor packaging devices at various manufacturing stages.

[0032] See Figure 3AA substrate 10 is provided. The substrate 10 has conductive traces 105 and a terminating layer 107. Electronic components 60 and 70 are disposed on the substrate 10. The electronic components 60 and / or 70 can be disposed by any suitable operation, such as bonding with a die attach film (DAF) or by flip-chip bonding. A sealant 20 is provided. The sealant 20 is formed on the substrate 10 to cover the electronic components 60 and 70. The sealant 20 can be formed by any suitable operation (e.g., molding operation).

[0033] See Figure 3B A portion of the sealant 20 is removed to form the trench 30'. The trench 30' can be formed by any suitable operation (e.g., laser operation or etching operation). In some embodiments, at least a portion of the termination layer 107 is exposed after the trench 30' is formed.

[0034] See Figure 3C A portion of the sealant 20 is further removed to form a trench 30 defined by surfaces 203, 204, and 205 of the sealant 20. The trench 30 includes portions 32 and 34. A trapezoidal portion 207 is formed defined by surfaces 204 and 205. The trapezoidal portion 207 is exposed to the trench 30. The trapezoidal portion 207 (or trench 30) can be formed by any suitable operation (e.g., laser operation, etching operation, or cutting operation).

[0035] See Figure 3D The gasket 40 is placed in the groove 30 to contact or engage with the trapezoidal portion 207. The gasket 40 may contact the surfaces 203 and / or 205 of the sealant 20. The gasket 40 may have annular, square, conical, or any suitable shape. The gasket 40 may be placed by any suitable operation (e.g., alignment or patching operation).

[0036] See Figure 3E Conductive material 50 is formed in trench 30 to encapsulate gasket 40. Conductive material 50 is formed to fill trench 30. Conductive material 50 and gasket 40 form a CPS structure between electronic component 60 and electronic component 70 to avoid electromagnetic interference (EMI) between electronic component 60 and electronic component 70. Conductive material 50 is formed on sealant 20. Conductive material 50 is formed to cover sealant 20 and substrate 10. Conductive material 50 can be formed by any suitable operation (e.g., screen printing, brushing, vacuum printing, sputtering, spraying, dispensing, or a combination thereof). Vacuum printing can be used to integrally form portions of conductive material 50 covering sealant 20 and substrate 10 within trench 30.

[0037] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to a situation where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" parallel can refer to a range of angular variation of less than or equal to ±10° relative to 0° (e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°). For example, "generally" vertical can refer to a range of angles relative to 90°, that is, less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0038] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the difference between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered planar or substantially planar.

[0039] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0040] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Differences may exist between embodiments of this disclosure and actual devices due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor packaging apparatus, comprising: A substrate comprising a first surface, a second surface opposite to the first surface, and a side surface extending from the first surface to the second surface; A sealant on the first surface of the substrate, the sealant comprising a first surface and a second surface opposite to the first surface; A trench that passes through the sealant, the trench comprising a first portion adjacent to the first surface of the sealant and a second portion between the first portion and the substrate, the width of the first portion being greater than the width of the second portion; A gasket, which is placed in the groove and in contact with the sealant; and A conductive material is disposed in the trench and encapsulates the gasket. The gasket engages with the ladder-shaped portion of the sealant to provide support to the sealant, thereby reducing bending of the semiconductor package.

2. The semiconductor packaging apparatus of claim 1, wherein the spacer does not fill the trench.

3. The semiconductor packaging apparatus of claim 1, wherein the surface of the first portion of the trench is substantially perpendicular to the first surface of the sealant.

4. The semiconductor packaging apparatus of claim 3, wherein the spacer is spaced apart from the substrate, and a portion of the spacer is in the second portion of the trench.

5. The semiconductor packaging apparatus of claim 3, wherein the pad has a spherical shape, and have At least half of it is in the first portion of the trench.

6. The semiconductor packaging apparatus of claim 1, wherein the coefficient of thermal expansion (CTE) of the gasket is greater than the CTE of the sealant.

7. The semiconductor packaging apparatus of claim 1, wherein the CTE of the conductive material is greater than the CTE of the pad, and wherein the CTE of the pad is greater than 10 ppm / ℃ and less than 30 ppm / ℃.

8. The semiconductor packaging apparatus according to claim 1, further comprising: A first electronic component is disposed on the first surface of the substrate; A second electronic component is disposed on the first surface of the substrate and spaced apart from the first electronic component by the trench. The distance between the pad and the substrate is greater than the height of the first electronic component.

9. The semiconductor packaging apparatus of claim 1, wherein the conductive material is further disposed on the side surfaces of the sealant and the substrate, wherein the width of the gasket is greater than the width of the second portion.

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