Device packaging

Abstract

An electronic device package includes a first substrate, a second substrate, and a conductive layer. The first substrate includes a first bonding pad and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad, which is at least partially inserted into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 62 / 735,000, filed September 21, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to an electronic device package, and more particularly, to an electronic device package including a conductive structure that passes through an interface between two non-uniform substrates. Background Technology

[0004] For example, mobile phones and other wireless communication devices typically include antennas for transmitting and receiving radio frequency (RF) signals. Wireless communication devices generally consist of an antenna substrate and a communication substrate. These two substrates have different requirements. For instance, the dielectric layer of the antenna substrate needs a relatively low dielectric constant (Dk) and a relatively low dissipation factor (Df) to achieve the desired peak gain and a thinner thickness, while the dielectric layer of the communication substrate needs a relatively high dielectric constant (Dk). Traditional wireless communication devices utilize an air layer as the dielectric layer of the antenna substrate. Air has a low dielectric constant (Dk), but the gap (thickness) of the air layer is difficult to control, thus severely impacting antenna performance. Summary of the Invention

[0005] In some embodiments, an electronic device package includes a first substrate, a second substrate, and a conductive layer. The first substrate includes a first bonding pad and a cavity exposing the first bonding pad. The second substrate is laminated onto the first substrate. The second substrate includes a second bonding pad that is at least partially inserted into the cavity of the first substrate. The conductive layer is disposed in the cavity and is at least between the first and second bonding pads to connect the first and second bonding pads.

[0006] In some embodiments, an electronic device package includes a first substrate, a second substrate, and a conductive structure. The second substrate is laminated on the first substrate. The first and second substrates include a non-uniform interface. The conductive structure is embedded in the first and second substrates and extends through the non-uniform interface. The conductive structure includes a first bonding pad adjacent to the first substrate and a second bonding pad adjacent to the second substrate and electrically connected to the first bonding pad. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of some embodiments of this disclosure will be readily understood from the following detailed description. Various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1This is a cross-sectional view of an electronic device package according to some embodiments of the present disclosure.

[0009] Figure 1A Based on some embodiments of this disclosure Figure 1 An enlarged cross-sectional view of region "A" in the image.

[0010] Figure 1B This is a top view of an electronic device package according to some embodiments of the present disclosure.

[0011] Figure 2A , Figure 2B , Figure 2C and Figure 2D This describes the operations used to manufacture an electronic device package according to some embodiments of the present disclosure.

[0012] Figure 3 This is a cross-sectional view of an electronic device package according to some embodiments of the present disclosure.

[0013] Figure 4 This is a side view of an electronic device package according to some embodiments of the present disclosure.

[0014] Figure 4A Based on some embodiments of this disclosure Figure 4 An enlarged cross-sectional view of region "B" in the image.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E This describes the operations used to manufacture an electronic device package according to some embodiments of the present disclosure.

[0016] Figure 6 This is a cross-sectional view of an electronic device package according to some embodiments of the present disclosure.

[0017] Figure 7 This is a cross-sectional view of an electronic device package 5 according to some embodiments of the present disclosure.

[0018] Figure 8A , Figure 8B , Figure 8C and Figure 8D This describes the operations used to manufacture an electronic device package according to some embodiments of the present disclosure.

[0019] Figure 9 This is a cross-sectional view of an electronic device package according to some embodiments of the present disclosure.

[0020] Figure 10 This is a cross-sectional view of an electronic device package according to a comparative embodiment of the present disclosure. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which an additional feature is formed or arranged between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0022] As used herein, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” may be used to describe the relationship between one element or feature and another element(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0023] This disclosure provides an electronic device package. The electronic device package includes two or more non-uniform substrates or layers laminated together. The non-uniform substrates are selected to meet different requirements of the electronic device package. For example, high-k and rigid substrates are used to meet the requirements of communication circuits such as RF circuits, while low-k and soft substrates are used to meet the peak gain requirements of antenna circuits with reduced thickness. The electronic device package includes a conductive structure passing through the non-uniform interface between the non-uniform substrates. The RF circuits and antenna circuits of the non-uniform substrates are directly connected through the non-uniform interface via the conductive structure, rather than being electrically connected to each other through the non-uniform interface, thus reducing signal transmission losses at the non-uniform interface. Therefore, the power consumption of the electronic device package can be reduced.

[0024] Figure 1 This is a cross-sectional view of an electronic device package 1 according to some embodiments of the present disclosure. Figure 1A Based on some embodiments of this disclosure Figure 1 An enlarged cross-sectional view of region "A" in the image, and Figure 1B This is a top view of an electronic device package 1 according to some embodiments of the present disclosure. Figure 1 ( Figure 1A and Figure 1B As shown, the electronic device package 1 includes a first substrate 10, a second substrate 30, and a conductive layer 50. The first substrate 10 includes at least one bonding pad (also referred to as a first bonding pad) 12 disposed on a surface (also referred to as a first surface) 10A, and a cavity C that at least partially exposes the bonding pad 12. In some embodiments, the first substrate 10 may include a package substrate, such as a core substrate, which includes a core layer 21, one or more dielectric layers 22, and one or more circuit layers 24 stacked on top of each other. The circuit layers 24 may be disposed on, adjacent to, or embedded in the dielectric layers and exposed through the dielectric layers. The material of each of the dielectric layers 22 may individually include organic dielectric materials such as epoxy-based materials (e.g., FR4), resin materials (e.g., bismaleimide-triazine (BT), polypropylene (PP)), molding compounds, or other suitable materials. The dielectric layers 22 may include transparent, translucent, or opaque materials. The circuit layer 24 may be configured as a redistribution layer (RDL) and electrically connected to the conductive layer 50. In some embodiments, the circuit layer 24 may be electrically connected via conductive vias 23. The material of each of the circuit layer 24 and the conductive vias 23 may individually comprise a metal such as copper or other suitable conductive material. In some other embodiments, the first substrate 10 may comprise a coreless substrate, and the core layer 21 may be omitted.

[0025] In some embodiments, the first substrate 10 may further include a passivation layer 14, and the passivation layer 14 may define at least a portion of the cavity C. In some embodiments, the passivation layer 14 partially covers the bonding pad 12 and defines an exposed area of ​​the bonding pad 12.

[0026] In some embodiments, the electronic device package 1 may further include at least one semiconductor device 70 disposed on another surface (also referred to as the second surface) 10B of the first substrate 10. The semiconductor device 70 is electrically connected to the circuit layer 24. For example, the semiconductor device 70 may include, but is not limited to, an integrated circuit (IC) such as a radio frequency IC (RFIC), a semiconductor die or chip containing circuitry. In some embodiments, an insulating layer 71, such as a solder mask, may be disposed on the surface 10B of the first substrate 10. The semiconductor device 70 may include a surface mount device (SMD) electrically connected to the circuit layer 22 via a flip chip (FC), the FC being bonded by conductive structures 72 such as conductive adhesives, conductive pads, conductive bumps, and UBM (under-bump metal). In some embodiments, an encapsulation layer 74, such as a molding compound layer, may be disposed on the surface 10B of the first substrate 10 to encapsulate the semiconductor device 70. The encapsulation layer 74 may surround the edge of the semiconductor device 70 and further cover the active and / or non-active surfaces of the semiconductor device 70. In some embodiments, the encapsulation layer 74 may partially expose the circuit layer 24, and a plurality of connection elements 76 may be disposed on the surface 10B of the first substrate 10 and electrically connected to the exposed circuit layer 24. The connection elements 76 may include solder balls, solder bumps, etc., and are electrically connected to the circuit layer 24 through some conductive structure 72.

[0027] A second substrate 30 is laminated onto a first substrate 10. The second substrate 30 includes at least one bonding pad (also referred to as a second bonding pad) 32 that is at least partially inserted into a cavity C of the first substrate 10. The bonding pad 32 is disposed adjacent to a surface (also referred to as a third surface) 30A of the second substrate 30. The bonding pad 32 of the second substrate 30 is electrically connected to a bonding pad 12 of the first substrate 10. The second substrate 30 may include one or more dielectric layers 42. Each dielectric layer 42 may contain a dielectric material. In some embodiments, each dielectric layer 42 may contain a thermosetting plastic, which may contain a liquid-based organic material and may be thermosetting and / or optically curable to provide adhesive properties. For example, the material used to prepare the dielectric layer 42 may be a thermosetting gel containing monomers such as resin monomers, hardeners, catalysts, solvents, diluents, fillers, and other additives. The gel may be thermosetting or optically curable to form a polymeric material. The second dielectric layer 30 may be softer than the first dielectric layer 10. In some other embodiments, the dielectric layer 42 may be pre-stacked and then laminated onto the first substrate 10. In some embodiments, the second substrate 30 and the first substrate 10 are in contact with each other. For example, the uppermost layer of the first substrate 10, such as the passivation layer 14, is in contact with the bottommost layer of the second substrate 30, such as the bottommost dielectric layer 42. The second substrate 30 and the first substrate 10 may be surface-by-surface bonded, for example, by a thermo-pressing lamination technique.

[0028] The second substrate 30 may include an antenna 40. The antenna 40 may include one or more circuit layers 44. In some embodiments, the circuit layers 44 of the antenna 40 are disposed within or between several dielectric layers 42. A first portion of the circuit layer 44 may be electrically connected to a bonding pad 32, for example, through a conductive via 43, and a second portion of the circuit layer 46 may be electrically connected to the first portion of the circuit layer 44 and / or the bonding pad 32. The material of each of the circuit layers 44 and the conductive via 43 may individually comprise a metal such as copper or other suitable conductive material. In some alternative embodiments, one of the circuit layers 44 is exposed from another surface (also referred to as a fourth surface) 30B of the second substrate 30, and an insulating layer 48, such as a solder mask, may be disposed on the dielectric layer 42, covering the circuit layer 44. The antenna 40 may include, for example (but not limited to), a directional antenna, an omnidirectional antenna, an antenna array, a dipole antenna, and / or a patch antenna. The antenna 40 may function as a side-fire coupled antenna or an end-fire radiating antenna. In some embodiments, another antenna may be disposed in dielectric layer 22 and near the edge of dielectric layer 22, and configured as, for example, a dipole antenna.

[0029] In some embodiments, the second substrate 30 may further include at least one reinforcing layer 45 configured to increase the robustness of the second substrate 30. The reinforcing layer 45 does not overlap with the circuit layer 44. In some embodiments, the reinforcing layer 45 and the circuit layer 44 may be formed from the same patterned conductive layer and formed simultaneously.

[0030] A conductive layer 50 is disposed in the cavity C and at least between the bonding pad 12 of the first substrate 10 and the bonding pad 32 of the second substrate 30 to connect the bonding pad 12 and the bonding pad 32. In some embodiments, the material of the conductive layer 50 may include soldering materials such as tin (Sn), lead (Pb), silver (Ag), copper (Cu), or alloys thereof. In some other embodiments, the material of the conductive layer 50 may include metals such as copper and silver, or other suitable conductive materials.

[0031] In some embodiments, the first substrate 10 may be configured as a communication substrate, such as a radio frequency (RF) substrate, and the second substrate 30 may be configured as an antenna substrate. The first substrate 10 and the second substrate 30 are non-uniform substrates containing non-uniform materials. The dielectric layer 22 of the first substrate 10 and the dielectric layer 42 of the second substrate 30 contain non-uniform materials with different properties. The characteristics of the second substrate 30 and the first substrate 10 are individually configured to meet different requirements of the semiconductor device 70, such as an RFIC and an antenna 40. For example, the dielectric constant (Dk) of the first substrate 10 is relatively high to meet the electrical requirements of the RFIC, while the dielectric constant (Dk) of the second substrate 30 is controlled to be relatively low, thereby reducing the thickness of the second substrate 30, increasing the peak gain of the antenna 40, and reducing signal transmission loss in the transmission path of the antenna 40.

[0032] The dielectric constant (Dk) of dielectric layer 42 is relatively low compared to that of dielectric layer 22. For example, the dielectric constant (Dk) of dielectric layer 42 is in the range of about 3.0 to about 3.4 at a frequency of about 10 GHz, and about 2.3 at a frequency of about 60 GHz. The dielectric constant (Dk) of dielectric layer 22 is in the range of about 3.4 to about 3.5 at a frequency of about 10 GHz. The dissipation factor (Df) of dielectric layer 42 is relatively low compared to that of dielectric layer 22. For example, the dissipation factor (Df) of dielectric layer 42 is in the range of about 0.0016 to about 0.0128 at a frequency of about 10 GHz, and about 0.0128 at a frequency of about 10 GHz. The dissipation factor (Df) of dielectric layer 42 is in the range of about 0.004 to about 0.005 at a frequency of about 10 GHz. The coefficient of thermal expansion (CTE) of dielectric layer 42 is relatively higher than that of dielectric layer 22. For example, the CTE of dielectric layer 42 is in the range of about 19 to about 110, while the CTE of dielectric layer 22 is in the range of about 11 to about 13. The Young's modulus of dielectric layer 42 is relatively lower than that of dielectric layer 22. For example, the Young's modulus of dielectric layer 42 is in the range of about 0.4 GPa to about 13 GPa, while the Young's modulus of dielectric layer 22 is in the range of about 25 GPa to about 26 GPa.

[0033] The first substrate 10 and the second substrate 30 are non-uniform materials, therefore the first substrate 10 and the second substrate 30 contain a non-uniform interface S1. The bonding pad 12 of the first substrate 10, the conductive layer 50, and the bonding pad 32 of the second substrate 30 together form a conductive structure 60 embedded in the first substrate 10 and the second substrate 30. The conductive structure 60 passes through the non-uniform interface S1. Figure 1 As shown, the bonding pad 12, conductive layer 50 and bonding pad 32 of conductive structure 60 are electrically connected together rather than electrically coupled, so conductive structure 60 passing through non-uniform interface S1 can reduce signal transmission loss.

[0034] like Figure 1A As shown, the second substrate 30 may be a relatively soft substrate compared to the first substrate 10, so the side surface 30L of the second substrate 30 may extend to partially cover the side surface 14L of the passivation layer 14 of the first substrate 10.

[0035] In some embodiments, a conductive layer 50 is disposed between bonding pad 12 and bonding pad 32. The conductive layer 50 may further cover the edge 32E of bonding pad 32. The cavity C defined by the passivation layer 14 may include, but is not limited to, sidewalls 14E inclined relative to surface 10A. For example, the cavity C may include a bowl-shaped profile with a larger aperture facing the second substrate 30. The bowl-shaped profile facilitates guiding the bonding pad 32 into the cavity C, allowing the bonding pad 32 to be accurately connected to the conductive layer 50 and bonding pad 12. For example, the central axis 12C of bonding pad 12 is substantially aligned with the central axis 32C of bonding pad 32, such as... Figure 1A As shown. In some embodiments, the upper surface 32U of the bonding pad 32 at the distal end of the bonding pad 12 is inserted into the cavity C and is below or substantially flush with the non-uniform interface S1 between the passivation layer 14 and the second substrate 30. In some embodiments, the width of the bonding pad 12 is greater than or substantially equal to the width of the bonding pad 32.

[0036] In some embodiments, the resistivity of bonding pad 12, conductive layer 50, bonding pad 32, conductive via 23, and conductive via 43 is each configured to improve the electrical performance of conductive structure 60. For example, the resistivity is controlled to be below 10. -3 Ωcm, but not limited to this. In some embodiments, the resistances of bonding pad 12, conductive layer 50, bonding pad 32, conductive via 23, and conductive via 43 are each configured such that the resistance of the central portion is close to the resistance of the peripheral portion to mitigate the skin effect. For example, the width or cross-sectional area of ​​conductive layer 50 can be controlled to adjust the resistance of conductive layer 50 in the central portion, thereby matching the resistance of the peripheral portion.

[0037] Figure 2A , Figure 2B , Figure 2C and Figure 2D This describes the operations used to manufacture an electronic device package 1 according to some embodiments of the present disclosure. See also... Figure 2A A first substrate 10 is provided. The first substrate 10 may be a pre-formed substrate. The first substrate 10 may include a core layer 21, one or more dielectric layers 22, and one or more circuit layers 24 stacked on top of each other. The first substrate 10 may further include bonding pads 12 and passivation layers 14 exposing the bonding pads 12. In some embodiments, the core layer 21 may be omitted.

[0038] like Figure 2BAs shown, a conductive layer 50 is formed on a bonding pad 42 exposed from the passivation layer 14. A second substrate 30 is provided. The second substrate 30 may be a pre-formed substrate. The second substrate 30 may include one or more dielectric layers 42 and an antenna 40, the antenna including one or more circuit layers 44 stacked on the dielectric layers 42. The second substrate 30 may further include a bonding pad 32 exposed from the dielectric layer 42, conductive vias 43 electrically connected to the bonding pad 32 and / or the circuit layers 44, and an insulating layer 48 above the dielectric layer 42. In some embodiments, the material of the dielectric layer 42 may comprise a thermosetting gel, which may be thermally cured and / or optically cured to provide adhesion.

[0039] like Figure 2C As shown, a second substrate 30 is laminated onto a first substrate 10, wherein bonding pad 32 faces and is aligned with the conductive layer 50 and bonding pad 12. In some embodiments, the second substrate 30 and the first substrate 10 are pre-laminated using rollers 90. In some embodiments, the thermosetting gel of the dielectric layer 42 is in stage B after pre-lamination.

[0040] like Figure 2D As shown, the second substrate 30 and the first substrate 10 are laminated by heat treatment. For example, the first substrate 10 is supported by a bottom laminating stage 10X, and the second substrate 30 is compressed by a top laminating stage 30X to provide a load L on the second substrate 30. The bottom laminating stage 10X and / or the top laminating stage 30X may be equipped with heaters to heat treat the second substrate 30 and the first substrate 10. After lamination, the thermosetting gel of the dielectric layer 42 is fully cured and converted to the C-phase, resulting in cross-reactivity between the dielectric layer 42 and the passivation layer 14 to enhance the adhesion between the first substrate 10 and the second substrate 30. In some embodiments, the first substrate 10 and the second substrate 30 may be separated after lamination to form multiple electronic device packages 1, such as... Figure 1 As explained in the text.

[0041] The electronic device packaging and manufacturing methods disclosed herein are not limited to the embodiments described above, and can be implemented according to other embodiments. To simplify this specification and to facilitate comparison between various embodiments of this disclosure, similar components in the following embodiments are labeled with the same numbers and do not require extensive description.

[0042] Figure 3 This is a cross-sectional view of an electronic device package 2 according to some embodiments of the present disclosure. For example... Figure 3As shown, the passivation layer 14 of the electronic device package 2 does not cover the bonding pad 12 and is spaced apart from the bonding pad 12. In some embodiments, the sidewall 14E of the cavity C may be, but is not limited to, substantially perpendicular to the surface 10A of the first substrate 10. In some embodiments, the sidewall 14E of the cavity C may be inclined relative to the surface 10A. In some embodiments, a conductive layer 50 is disposed between the bonding pad 12 and the bonding pad 32. The conductive layer 50 may further cover the edge 32E of the bonding pad 32 and / or the edge 12E of the bonding pad 12.

[0043] Figure 4 This is a side view of an electronic device package 3 according to some embodiments of the present disclosure. Figure 4 As shown, with Figure 1 Compared to the electronic device package 1, the first substrate 10 of the electronic device package 3 further includes an adhesive layer 16 disposed between a passivation layer 14 and a second substrate 30. The passivation layer 14 and the adhesive layer 16 may together define a cavity C. For example, the passivation layer 14 defines a first portion P1 of the cavity C, and the adhesive layer 16 defines a second portion P2 of the cavity C. The adhesive layer 16, the first substrate 10, and the second substrate 30 may all be non-uniform materials, thus the first substrate 10 and the second substrate 30 include a non-uniform interface S1, while the adhesive layer 16 and the second substrate 30 include another non-uniform interface S2. In some embodiments, the upper surface 32U of the bonding pad 32 at the distal end of the bonding pad 12 may be lower than or substantially flush with the non-uniform interface S2 between the adhesive layer 16 and the second substrate 30. In some embodiments, the width of the bonding pad 12 is greater than or substantially equal to the width of the bonding pad 32. A conductive layer 50 is disposed between the bonding pad 12 and the bonding pad 32. The conductive layer 50 may further cover the edge 32E of the bonding pad 32.

[0044] Dielectric layer 42, dielectric layer 22, and adhesive layer 16 may be non-homogeneous materials and have different properties. For example, the dielectric constant (Dk) of dielectric layer 42 is in the range of about 3.0 to about 3.4 at a frequency of about 10 GHz, and about 2.3 at a frequency of about 60 GHz. The dielectric constant (Dk) of dielectric layer 22 is in the range of about 3.4 to about 3.5 at a frequency of about 10 GHz. The dielectric constant (Dk) of adhesive layer 16 is about 3.1 at a frequency of about 10 GHz. The dissipation factor (Df) of dielectric layer 42 is in the range of about 0.0016 to about 0.0128 at a frequency of about 10 GHz, and about 0.0128 at a frequency of about 10 GHz. The dissipation factor (Df) of dielectric layer 42 is in the range of about 0.004 to about 0.005 at a frequency of about 10 GHz. The dissipation factor (Df) of adhesion layer 16 is approximately 0.0016 at a frequency of approximately 10 GHz. The CTE of dielectric layer 42 ranges from approximately 19 to approximately 110. The CTE of dielectric layer 22 ranges from approximately 11 to approximately 13. The CTE of adhesion layer 16 is approximately 70. The Young's modulus of dielectric layer 42 ranges from approximately 0.4 GPa to approximately 13 GPa. The Young's modulus of dielectric layer 22 ranges from approximately 25 GPa to approximately 26 GPa. The Young's modulus of adhesion layer 16 is approximately 0.75 GPa.

[0045] In some embodiments, the adhesive layer 16 may comprise a thermosetting tape that can be thermosetting and / or optically cured to provide adhesiveness. For example, the material of the adhesive layer 16 may be a thermosetting gel comprising monomers such as resin monomers, hardeners, catalysts, solvents, diluents, fillers, and other additives. The gel may be thermosetting or optically cured to form a polymeric material. The adhesive layer 16 may be softer than the first dielectric layer 10.

[0046] Figure 4A According to some embodiments of this disclosure Figure 4 An enlarged cross-sectional view of region "B" in the image. (See image for example.) Figure 4A As shown, the second substrate 30 may be relatively softer than the adhesive layer 16, so the side surface 30L of the second substrate 30 may extend to partially cover the side surface 16L of the adhesive layer 16. The cavity C defined by the passivation layer 14 and the adhesive layer 16 may include, but is not limited to, sidewalls 14E and 16E inclined relative to the surface 10A. For example, the cavity C may include a bowl-shaped profile with a larger aperture facing the second substrate 30. The bowl-shaped profile facilitates the guidance of the bonding pad 32 into the cavity C, allowing the bonding pad 32 to be accurately connected to the conductive layer 50 and the bonding pad 12. For example, the central axis 12C of the bonding pad 12 is substantially aligned with the central axis 32C of the bonding pad 32, such as... Figure 4A As shown.

[0047] In some embodiments, the resistivity of bonding pad 12, conductive layer 50, bonding pad 32, conductive via 23, and conductive via 43 is each configured to improve the electrical performance of conductive structure 60. For example, the resistivity is controlled to be below 10. -3 Ωcm, but not limited thereto. In some embodiments, the resistances of bonding pad 12, conductive layer 50, bonding pad 32, conductive via 23 and conductive via 43 are each configured such that the resistance of the central portion is close to the resistance of the peripheral portion to mitigate the skin effect.

[0048] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E This describes the operations used in manufacturing an electronic device package 3 according to some embodiments of the present disclosure. See also... Figure 5A A first substrate 10 is provided. The first substrate 10 may be a pre-formed substrate. The first substrate 10 may include a core layer 21, one or more dielectric layers 22, and one or more circuit layers 24 stacked on top of each other. The first substrate 10 may further include a bonding pad 12 and a passivation layer 14 defining a first portion P1 of a cavity C to expose the bonding pad 12. In some embodiments, the core layer 21 may be omitted. An adhesive layer 16 is then laminated onto the first substrate 10. In some embodiments, pre-lamination of the adhesive layer 16 and the first substrate 10 is performed by a roller 90. In some embodiments, the thermosetting tape of the adhesive layer 16 is in stage A after pre-lamination.

[0049] like Figure 5B As shown, the adhesive layer 16 is then patterned to form the second portion P2 of the cavity C, thereby exposing the bonding pad 12. In some embodiments, the adhesive layer 16 can be patterned by drilling, for example, using laser drilling. Figure 5C As shown, the conductive layer 50 is formed in a cavity C on the bonding pad 42 exposed from the passivation layer 14 and the adhesion layer 16. A second substrate 30 is provided. The second substrate 30 may be a pre-formed substrate. The second substrate 30 may include one or more dielectric layers 42 and an antenna 40, the antenna including one or more circuit layers 44 stacked on the dielectric layer 42. The second substrate 30 may further include the bonding pad 32 exposed from the dielectric layer 42, conductive vias 43 electrically connected to the bonding pad 32 and / or the circuit layers 44, and an insulating layer 48 above the dielectric layer 42.

[0050] like Figure 5D As shown, a second substrate 30 is laminated onto an adhesive layer 16, with bonding pad 32 facing and aligned with the conductive layer 50 and bonding pad 12. In some embodiments, pre-lamination is performed on the second substrate 30 and the adhesive layer 16 using rollers 90. In some embodiments, the thermosetting tape of the adhesive layer 16 is in stage B after pre-lamination.

[0051] like Figure 5E As shown, lamination of the second substrate 30 and the adhesive layer 16 is performed via heat treatment. For example, the first substrate 10 is supported by a bottom laminator 10X, and the second substrate 30 is compressed by a top laminator 30X to provide a load L on the second substrate 30. The bottom laminator 10X and / or the top laminator 30X may be equipped with heaters to heat treat the second substrate 30, the adhesive layer 16, and the first substrate 10. After lamination, the thermosetting tape of the adhesive layer 16 is fully cured and transitions to the C-phase, resulting in cross-reactivity between the adhesive layer 16 and the passivation layer 14 and the dielectric layer 42 to enhance the adhesion between the first substrate 10 and the second substrate 30. In some embodiments, the first substrate 10 and the second substrate 30 may be separated after lamination to form multiple electronic device packages 3, such as... Figure 4 As explained in the text.

[0052] Figure 6 This is a cross-sectional view of an electronic device package 4 according to some embodiments of the present disclosure. Figure 6 As shown, the passivation layer 14 of the electronic device package 4 does not cover the bonding pad 12 and is spaced apart from the bonding pad 12. In some embodiments, the sidewalls 14E of the passivation layer 14 and the sidewalls 16E of the adhesion layer 16 may be discontinuously connected. For example, the sidewalls 14E are generally perpendicular to the surface 10A, and the sidewalls 16E may be tilted relative to the surface 10A of the first substrate 10. The conductive layer 50 is disposed between the bonding pad 12 and the bonding pad 32, and may further cover the edge 32E of the bonding pad 32 and / or the edge 12E of the bonding pad 12.

[0053] Figure 7 This is a cross-sectional view of an electronic device package 5 according to some embodiments of the present disclosure. For example... Figure 7 As shown, the passivation layer 14 partially covers the bonding pad 12 and defines a first portion P1 of the cavity C. The adhesion layer 16 may have a stepped profile. For example, the second portion P2 of the cavity C defined by the adhesion layer 16 may have an upper portion P2U and a bottom portion P2B connected to the upper portion P2U. In some embodiments, the bottom portion P2B and the first portion P1 of the second portion P2 of the cavity C are filled with the conductive layer 50, while the upper portion P2U is not filled with the conductive layer 50. In some embodiments, the width or cross-sectional area of ​​the bottom portion P2B is substantially equal to the width or cross-sectional area of ​​the first portion P1. In some embodiments, the width or cross-sectional area of ​​the bottom portion P2B is narrower than that of the upper portion P2U, so the resistance of the conductive layer 50 in the central region can be reduced to near the resistance in the peripheral region, thereby mitigating the skin effect. Therefore, signal transmission loss can be reduced, especially in high-frequency applications. Furthermore, the narrower bottom portion P2B also helps guide the conductive layer 50, thus increasing alignment accuracy.

[0054] Figure 8A , Figure 8B , Figure 8C and Figure 8D This describes the operations used to manufacture an electronic device package 5 according to some embodiments of the present disclosure. See also... Figure 8A A first substrate 10 is provided. The first substrate 10 may be a pre-formed substrate. The first substrate 10 may include a core layer 21, one or more dielectric layers 22, and one or more circuit layers 24 stacked on top of each other. The first substrate 10 may further include a bonding pad 12 and a passivation layer 14 defining a first portion P1 of the cavity C to expose the bonding pad 12. In some embodiments, the core layer 21 may be omitted.

[0055] like Figure 8B As shown, the adhesive layer 16 is then laminated onto the first substrate 10. In some embodiments, pre-lamination may be performed on the adhesive layer 16 and the first substrate 10. The adhesive layer 16 may be patterned to form the upper portion P2U of the second portion P2 of the cavity C. The upper portion P2U may be formed by drilling, for example, laser drilling.

[0056] like Figure 8C As shown, the adhesive layer 16 can be repatterned to form a bottom portion P2B of the second portion P2 of the cavity C, which communicates with the first portion P1 of the cavity C. The bottom portion P2B can be formed by drilling, for example, laser drilling.

[0057] like Figure 8D As shown, a conductive layer 50 is formed in the bottom portion P2B and the first portion P1 of the cavity C on the bonding pad 42 exposed from the passivation layer 14 and the adhesion layer 16. A second substrate 30 is then laminated onto the adhesion layer 16 to form an electronic device package 5, as shown. Figure 7 As explained in the text.

[0058] Figure 9 This is a cross-sectional view of an electronic device package 6 according to some embodiments of the present disclosure. For example... Figure 9As shown, the passivation layer 14 is spaced apart from the bonding pad 12 by a gap and defines a first portion P1 of the cavity C. The adhesion layer 16 may have a stepped profile. For example, the second portion P2 of the cavity C defined by the adhesion layer 16 may have an upper portion P2U that is wider than the bottom portion P2B. In some embodiments, the bottom portion P2B of the second portion P2 of the cavity C is filled with the conductive layer 50, while the first portion P1 and the upper portion P2U are not filled with the conductive layer 50. In some embodiments, the width or cross-sectional area of ​​the bottom portion P2B is substantially equal to the width or cross-sectional area of ​​the first portion P1. In some embodiments, the width or cross-sectional area of ​​the bottom portion P2B is narrower than the width or cross-sectional area of ​​the upper portion P2U, so the resistance of the conductive layer 50 in the central region can be reduced to near the resistance in the peripheral region, thereby mitigating the skin effect. Therefore, signal transmission loss can be reduced, especially in high-frequency applications. In addition, the narrower bottom portion P2B also helps to guide the conductive layer 50, thus increasing alignment accuracy.

[0059] Figure 10 This is a cross-sectional view of an electronic device package 7 according to a comparative embodiment of the present disclosure. Figure 10 As shown, the second substrate 30 of the comparative embodiment is a glass substrate, and forming a circuit layer in a glass substrate is difficult and expensive. Therefore, the circuit layer 24 of the first substrate 10 is electrically connected to the circuit layer 44 of the antenna 40 of the second substrate 30 via a non-uniform interface S1. However, the coupling via the non-uniform interface S1 significantly increases signal transmission loss. Furthermore, the dielectric constant (Dk) of glass is approximately 5 to 10, so the thickness of the glass substrate must be increased to obtain the same gain as the electronic device package disclosed in the previous embodiments of this disclosure.

[0060] In some embodiments of this disclosure, the electronic device package comprises two or more non-uniform substrates or layers laminated together. The non-uniform substrates are selected to meet different requirements of the electronic device package. For example, high-k and rigid substrates are used to meet the requirements of RF circuitry, while low-k and soft substrates are used to meet the peak gain requirements of antennas with reduced thickness. The electronic device package includes a conductive structure passing through the non-uniform interface between the non-uniform substrates. The RF circuitry and antenna circuitry of the non-uniform substrates are directly connected through the non-uniform interface via the conductive structure, rather than electrically connected to each other, thus mitigating signal transmission losses at the non-uniform interface. The thickness of the electronic device package of this disclosure can be controlled to be substantially equal to or less than 1 mm, and the power consumption of the device package can be controlled to be less than 5 W.

[0061] Unless the context clearly specifies otherwise, as used herein, the singular terms “a / an” and “the” may include multiple indicators.

[0062] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​may be considered “substantially” the same or equal. For example, "generally parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "generally perpendicular" might refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0063] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0064] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. Those skilled in the art will understand that various changes and substitutions may be made and equivalents substituted without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, artistic representations in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to suit particular situations, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. While the methods disclosed herein are described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. An electronic device package, comprising: First substrate; A second substrate is laminated on the first substrate, wherein the first substrate and the second substrate contain a non-uniform interface; as well as A conductive structure is embedded in the first substrate and the second substrate and extends through the non-uniform interface, wherein the conductive structure includes a first bonding pad adjacent to the first substrate and a second bonding pad adjacent to the second substrate and electrically connected to the first bonding pad. The first substrate includes a passivation layer that defines a first portion of the cavity. The first substrate further includes an adhesion layer disposed between the passivation layer and the second substrate, and the adhesion layer defines a second portion of the cavity. The second portion of the cavity further includes a bottom portion communicating with the first portion and an upper portion connected to the bottom portion, wherein the bottom portion is narrower than the upper portion.

2. The electronic device package according to claim 1, wherein the first bonding pad and the second bonding pad are disposed in the cavity.

3. The electronic device package of claim 1, wherein the upper surface of the second bonding pad at the distal end of the first bonding pad is lower than the upper surface of the passivation layer facing the second substrate.

4. The electronic device package according to claim 1, further comprising a conductive layer disposed between the first bonding pad and the second bonding pad, and connecting the first bonding pad and the second bonding pad.

Images