A circuit and an electronic device

Abstract

The present invention discloses a circuit and an electronic device. In one aspect, the circuit may include a first HEMT, a second HEMT, and a variable capacitor. The drain of the first HEMT may be coupled to the source of the second HEMT. An electrode of the variable capacitor may be coupled to the source of the first HEMT, and another electrode of the variable capacitor may be coupled to the gate of the second HEMT. In another aspect, the electronic device may include a die, the die including a HEMT and a variable capacitor. An electrode of the variable capacitor may be coupled to the source or gate of the HEMT, and another electrode of the variable capacitor may be coupled to an external terminal of the die. In yet another aspect, the electronic device includes a die, wherein the die includes a variable capacitor, a first diode, and a second diode.

Description

Technical Field

[0001] The present disclosure relates to circuits and electronic devices, and more particularly to electronic devices including transistors and variable capacitors. Background Art

[0002] High electron mobility transistors can be made to operate at a variety of high voltages. However, above a certain voltage (such as 650V), the design of the transistor may become more complicated or may experience adverse effects on the GaN substrate on silicon. For example, at voltages above 650V, the buffer layer may need to be significantly thicker and cause high mechanical stresses that may cause wafer warping. Forming a GaN layer on sapphire, SiC, growing a GaN bulk substrate, or transferring a GaN layer by substrate removal may be difficult for commercial production levels. It is expected that further improvements will be made to high voltage circuits using high electron mobility transistors. Summary of the invention

[0003] The problem to be solved by the present invention is to increase the normal operating voltage of a circuit without requiring a complicated semiconductor die or a process for forming the semiconductor die.

[0004] According to one aspect of the present invention, a circuit is provided. The circuit may include: a first high electron mobility transistor; a second high electron mobility transistor, wherein the drain of the first high electron mobility transistor is coupled to the source of the second high electron mobility transistor; and a first variable capacitor, wherein a first electrode of the first variable capacitor is coupled to the source of the first high electron mobility transistor, and a second electrode of the first variable capacitor is coupled to the gate of the second high electron mobility transistor.

[0005] In one embodiment, the circuit may also include a first diode and a second diode, wherein the cathode of the first diode is coupled to the second electrode of the first variable capacitor, the anode of the first diode is coupled to the anode of the second diode and the cathode of the second diode is coupled to the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor.

[0006] In another embodiment, the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor are electrically connected to each other at an intermediate node, and the first variable capacitor has a capacitance such that when the circuit is in an off state, the intermediate node has a voltage within 10% of half the voltage difference between the source of the first high electron mobility transistor and the drain of the second high electron mobility transistor.

[0007] In yet another embodiment, the circuit may further include a third high electron mobility transistor and a second variable capacitor. A first electrode of the second variable capacitor may be coupled to the gate of the second high electron mobility transistor, a second electrode of the second variable capacitor may be coupled to the gate of the third high electron mobility transistor, and a drain of the second high electron mobility transistor may be coupled to the source of the third high electron mobility transistor.

[0008] According to another aspect, an electronic device is provided, the electronic device comprising a first die. The electronic device may include a first high electron mobility transistor and a first variable capacitor, wherein a first electrode of the first variable capacitor is coupled to a source or gate of the first high electron mobility transistor, and a second electrode of the first variable capacitor is coupled to a first external terminal of the first die.

[0009] In one embodiment, the electronic device may further include a second die including a second high electron mobility transistor. The gate electrode of the second high electron mobility transistor may be coupled to the first external terminal of the second die, and the first external terminal of the second die may be coupled to the first external terminal of the first die. The drain electrode of the first high electron mobility transistor may be coupled to the second external terminal of the first die, and the source electrode of the second high electron mobility transistor may be coupled to the second external terminal of the second die, and the second external terminal of the second die may be coupled to the second external terminal of the first die.

[0010] In a specific embodiment, the electronic device may further include a third high electron mobility transistor and a second variable capacitor. The drain of the second high electron mobility transistor may be coupled to the source of the third high electron mobility transistor, the first electrode of the second variable capacitor may be coupled to the gate of the second high electron mobility transistor, and the second electrode of the second variable capacitor may be coupled to the gate of the third high electron mobility transistor.

[0011] In yet another embodiment, the electronic device may further include a first diode, a second diode, and a second high electron mobility transistor. The first high electron mobility transistor may be an enhancement mode transistor, and the second high electron mobility transistor may be a depletion mode transistor. The first electrode of the variable capacitor may be electrically connected to the source of the first high electron mobility transistor, and the second electrode of the variable capacitor may be electrically connected to the gate of the second high electron mobility transistor and the cathode of the first diode. The drain electrode of the first high electron mobility transistor may be electrically connected to the source electrode of the second high electron mobility transistor and the cathode of the second diode. The anode of the first diode may be electrically connected to the anode of the second diode. The first high electron mobility transistor, the variable capacitor, and the first and second diodes may be on the first die, and the second high electron mobility transistor may be on the second die.

[0012] In another aspect, an electronic device is provided. The electronic device may include a first die, wherein the first die may include a variable capacitor, a first diode, and a second diode. A first electrode of the variable capacitor may be coupled to a first external terminal of the first die, and a second electrode of the variable capacitor and a cathode of the first diode may be coupled to a second external terminal of the first die. An anode of the first diode may be coupled to an anode of the second diode, and a cathode of the second diode may be coupled to a third external terminal of the first die.

[0013] In one embodiment, the electronic device may further include a first high electron mobility transistor and a second high electron mobility transistor. The gate of the first high electron mobility transistor may be coupled to the first electrode of the variable capacitor, and the drain or source of the first high electron mobility transistor is coupled to the cathode of the second diode. The gate of the second high electron mobility transistor may be coupled to the second electrode of the variable capacitor, and the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor may be coupled to the cathode of the second diode. The first high electron mobility transistor, the second high electron mobility transistor, or both transistors may be on at least one die different from the first die.

[0014] The technical effects achieved by the present invention allow modular construction of a circuit with a relatively high rated voltage by using electronic devices with a rated voltage lower than the rated voltage of the circuit, and also allow electronic devices including variable capacitors supporting such a circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments are shown by way of example in the drawings and are not limited thereto.

[0016] Figure 1 Included is a depiction of a schematic diagram of a circuit according to one embodiment.

[0017] Figure 2 Included is a graph of capacitance versus voltage across the electrodes of a variable capacitor.

[0018] Figure 3 Included are graphs of the voltage at the mid-node as a function of the circuit voltage for different capacitances.

[0019] Figure 4 Included is a depiction of a schematic diagram of a circuit according to another embodiment.

[0020] Figure 5 According to one embodiment, Figure 4 An illustration of a perspective view of the layout of electronic components in a circuit.

[0021] Figure 6 According to one embodiment, Figure 4Illustration of a top view of the layout of the die of the low-side transistor, variable capacitor, and diode in FIG.

[0022] Figure 7 include Figure 6 Illustration of a cross-sectional view of portions of the low-side transistor and variable capacitor.

[0023] Figure 8 include Figure 6 Illustration of a cross-sectional view of the various parts of a diode.

[0024] Fig. 9 An illustration including a top view of a layout of a die including a high-side transistor and a diode according to another embodiment.

[0025] Fig.10 Included is a depiction of a schematic diagram of a circuit according to yet another embodiment.

[0026] The skilled person will appreciate that the elements in the drawings are illustrated for simplicity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments of the present invention. DETAILED DESCRIPTION

[0027] The following description in conjunction with the accompanying drawings is provided to help understand the teachings disclosed herein. The following discussion will focus on the specific implementation and implementation of the teachings. This emphasis is provided to help describe the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other implementations may be adopted based on the teachings as disclosed in this application.

[0028] The group numbers correspond to the columns in the periodic table based on the 28 November 2016 edition of the IUPAC periodic table.

[0029] The term "compound semiconductor" is intended to mean a semiconductor material containing at least two different elements. Examples include SiC, SiGe, GaN, InP, Al w Ga (1-w) N (where 0≤w≤1), CdTe, etc. III-V semiconductor materials are intended to mean semiconductor materials comprising at least one trivalent metal element and at least one Group 15 element. III-N semiconductor materials are intended to mean semiconductor materials comprising at least one trivalent metal element and nitrogen. Group 13 to Group 15 semiconductor materials are intended to mean semiconductor materials comprising at least one Group 13 element and at least one Group 15 element.

[0030] The term "high voltage" when referring to a layer, structure, or device means that such layer, structure, or device can withstand at least a 200V difference across such layer, structure, or device (e.g., between the source and drain of a transistor in the off state) without exhibiting dielectric breakdown, avalanche breakdown, etc.

[0031] The terms "normal operation" and "normal operating conditions" refer to the conditions under which an electronic component or device is designed to operate. The conditions may be obtained from a data sheet or other information about voltage, current, capacitance, resistance, or other electrical parameters. Thus, normal operation does not include operating an electronic component or device outside of its design limits.

[0032] For the sake of clarity of the drawings, certain regions of the device structure, such as doped regions or dielectric regions, may be shown as having substantially straight edges and precise angle corners. However, those skilled in the art understand that due to the diffusion and activation of dopants or the formation of layers, the edges of such regions may not be straight lines and the corners may not have precise angles.

[0033] The terms "on," "overlying," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. However, "over" may also mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is above another element, but the elements are not in contact with each other and there may be another one or more elements between the two elements.

[0034] The terms "comprises," "comprising," "including," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly specified to the contrary, "or" refers to an inclusive or and not an exclusive or. For example, a condition A or B is satisfied by any of the following: A is true (or present) and B is false (or absent), A is false (or absent) and B is true (or present), and both A and B are true (or present).

[0035] In addition, "a" or "an" is used to describe the elements and components described herein. This is for convenience only and to give a general sense of the scope of the invention. The description should be considered to include one, at least one, or the singular also includes the plural, and vice versa, unless it is clearly intended to be contrary. For example, when a single item is described herein, more than one item can be used in place of the single item. Similarly, where more than one item is described herein, a single item can be used in place of the more than one item.

[0036] The use of the words "about," "approximately," or "substantially" is intended to mean that the value of a parameter is close to the specified value or position. However, slight differences may prevent the value or position from being exactly as specified. Therefore, differences of up to ten percent (10%) for values ​​(and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable differences from the ideal goal of being exactly as described.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. The materials, methods, and examples are illustrative only and are not intended to be limiting. Where not described herein, many details regarding specific materials and processing actions are conventional and can be found in textbooks and other sources in the semiconductor and electronics fields.

[0038] The circuit may be designed to operate at a higher voltage than the maximum safe operating voltage of any transistor within the circuit. The circuit is well suited for high electron mobility transistors (HEMTs) and may be implemented without the complications that may arise if a single HEMT is scaled to operate at a higher voltage. In one embodiment, a modular design may be used to allow for easier scaling to higher operating voltages of the circuit. By limiting the normal operating voltage of each HEMT within the circuit, a single HEMT with a very high breakdown voltage circuit is not required, and having to conceive of new, cumbersome, or marginal process technology or physical design for a single HEMT may be avoided.

[0039] In one embodiment, the high-side transistor may be a depletion-mode transistor, and the low-side transistor may be an enhancement-mode transistor, wherein a control signal to the gate of the low-side transistor may be used to turn the circuit on and off. A variable capacitor may be used to provide a desired voltage at a node between the source of the high-side transistor and the drain of the low-side transistor. If necessary or desired, a diode may be used to control the voltage on the gate of the high-side transistor. The variable capacitor and diode may be designed to use AlGaN technology, which may also be used for high-side transistors and low-side transistors. Variable capacitors and diodes may be implemented by modifying existing masks to combine variable capacitors and diodes, but new steps need to be added or developed or complex or cumbersome processing sequences may be used. In a specific embodiment, any individual or combination of variable capacitors and diodes may occupy no more than 20% of the die area where they are located. In another embodiment, variable capacitors and diodes may be on separate dies to allow a modular construction that is very suitable for use in a wide voltage range of the circuit.

[0040] In one aspect, the circuit may include a first HEMT, a second HEMT, and a variable capacitor. The drain of the first HEMT may be coupled to the source of the second HEMT. The first electrode of the variable capacitor may be coupled to the source of the first HEMT, and the second electrode of the variable capacitor may be coupled to the gate of the second HEMT.

[0041] In another aspect, an electronic device may include a die including a first HEMT and a variable capacitor. A first electrode of the variable capacitor may be coupled to a source or gate of the HEMT, and a second electrode of the variable capacitor may be coupled to a first external terminal of the first die.

[0042] In yet another aspect, the electronic device may include a die, wherein the die includes a variable capacitor, a first diode, and a second diode. The first electrode of the variable capacitor may be coupled to a first external terminal of the first die. The second electrode of the variable capacitor and a cathode of the first diode may be coupled to a second external terminal of the first die. The anode of the first diode may be coupled to an anode of the second diode. The cathode of the second diode may be coupled to a third external terminal of the first die.

[0043] In this specification, associations between components are described with respect to couplings. In a specific embodiment, any or all couplings may be in the form of electrical connections, i.e., connections without any intervening components (such as resistors, capacitors, transistors, etc.). Thus, electrical connections may be represented as nodes. For example, the source of a high-side transistor and the drain of a low-side transistor may be electrically connected to a node such that the source and drain are at substantially the same voltage.

[0044] Figure 1 A depiction of a schematic diagram of a circuit 100 including a high-side HEMT 122, a low-side HEMT 124, and a variable capacitor 140. The arrangement of the high-side HEMT 122 and the low-side HEMT 124 may allow a voltage difference between the drain terminal 102 and the source terminal 106 to be higher than the voltage that each of the HEMT 122 and the HEMT 124 can withstand during normal operation of the circuit 100. In one embodiment, the high-side HEMT 122 is a depletion-mode transistor and the low-side HEMT 124 is an enhancement-mode transistor. A sufficiently positive gate-source voltage (V GS ) when the circuit 100 is turned on.

[0045] A drain terminal 102 for the circuit 100 is coupled to the drain of the high-side HEMT 122, a control terminal 104 is coupled to the gate of the low-side HEMT 124, and a source terminal is coupled to the gate of the low-side HEMT 124. Each of the drain terminal, the control terminal, and the source terminal is an example of an external terminal that allows the circuit 100 to be connected to other components or circuits. For example, a high voltage power supply may be coupled to the drain terminal 102, a low voltage power supply (e.g., 0V or ground) may be coupled to the source terminal 106, and a gate controller, a gate driver, or both may be coupled to the control terminal 104. The source of the high-side HEMT 122 and the drain of the low-side HEMT 124 are coupled to each other at a node 108. An electrode of a variable capacitor 140 is coupled to the gate of the high-side HEMT 122, and another electrode of the variable capacitor 140 is coupled to the source of the low-side HEMT 124.

[0046] When the circuit 100 is off, the variable capacitor 124 helps to maintain the node 108 at a desired voltage (e.g., V GS In one embodiment, where the low-side HEMT and the high-side HEMT have substantially the same voltage capabilities, when the circuit 100 is in the off state, the voltage on the node 108 is half the voltage difference between the drain terminal 102 (or the drain of the high-side HEMT 122) and the source terminal 106 (or the source of the low-side HEMT 124), or V NODE 108 =V DS CIRCUIT / 2. To account for some manufacturing differences between HEMT 122 and HEMT 124 and variable capacitor 140, the voltage at node 108 may be DS CIRCUIT Within 10% of / 2.

[0047] The variable capacitor 140 may have a capacitance (C AK ). Figure 2 Including C AK As the voltage difference between its electrodes changes. Figure 2 As can be seen, C AK The variable capacitor 140 is significantly reduced at voltages in the range of 300 V to 320 V, and is relatively constant at voltages above 320 V. As will be addressed later in this specification, the variable capacitor 140 may be in the form of a field electrode that is capacitively coupled to a channel layer or barrier layer shared with the low-side HEMT 124. AKThe voltage that changes may be affected by the physical design (e.g., thickness of the capacitor dielectric), the composition of one or both capacitor electrodes (e.g., Al content of the barrier layer, work function of the overlying capacitor electrode, etc.), etc. Simulations may be run to determine the voltage at which C occurs for the particular capacitor structure used. AK Change position. When V DS Above 250V, the output capacitance of HEMT 122 and HEMT 124 is substantially constant.

[0048] A prototype electronic device may be used to determine capacitances that may be used for different voltages between drain terminal 102 and source terminal 106. The prototype device includes circuit 100 and also includes a diode, wherein an anode of the diode is coupled to one of the electrodes of variable capacitor 140 and a cathode of the diode is coupled to the other electrode of variable capacitor 140. Figure 3 For different capacitances of the variable capacitor 140, V NODE 108 With V DS CIRCUIT When the circuit 100 is designed for a voltage that is evenly distributed between the high-side HEMT 122 and the low-side HEMT 124, for a V DS CIRCUIT , the expected capacitance may be about 25pF; for a V of 1000V DS CIRCUIT , the capacitance can be about 22pF; and for a V of 400V DS CIRCUIT , the capacitance can be about 33pF. DS CIRCUIT is designed for at least 100V, in one embodiment, C AK may be at least 2 pF, at least 5 pF, or at least 11 pF, and in another embodiment, C AK It can be up to 200pF, up to 90pF, or up to 60pF. For V in the range of 400V to 1000V DS CIRCUIT , C AK Can be in the range of 20pF to 40pF.

[0049] Figure 4An embodiment of circuit 400 (which is similar to circuit 100) and also includes a set of back-to-back diodes, as well as a physical implementation of circuit 400. Circuit 400 includes a set of back-to-back diodes 462 and 464. Diodes 462 and 464 help regulate the voltage on the gate of high-side HEMT 122 so that the voltage difference between the gate and source of high-side HEMT 122 does not become too large. The breakdown voltage of each of diodes 462 and 464 can be at most 50V, at most 30V, or at most 20V. Diodes 462 and 464 can have different breakdown voltages. In a specific embodiment, V of high-side HEMT 122 is reduced before high-side HEMT 122 is adversely affected. GS can be in the range of -20 V to +5 V. Thus, the breakdown voltage of diode 462 can be at most 5 V, and the breakdown voltage of diode 464 can be at most 20 V. Other breakdown voltages of diodes 462 and 464 can be used. Exemplary physical designs of diodes 462 and 464 are addressed later in this specification.

[0050] Components of circuit 400 may be on multiple dies. In one embodiment, one semiconductor die 412 may include high-side HEMT 122 , and another semiconductor die 414 may include low-side HEMT 124 , variable capacitor 140 , and diodes 462 and 464 . Figure 5 A perspective view of a non-limiting exemplary embodiment of an electronic device 500 having circuit 200 is included. The electrical connections between semiconductor die 412 and 414 and other portions of electronic device 500 may be in the form of bond wires or clamps. The substrates of semiconductor die 412 and 414 are attached and electrically connected to conductive members 506 and 508. Conductive member 502 may be the drain terminal 102, conductive member 508 may be a portion of the intermediate node 108, and conductive member 506 may be the source terminal 106. One or more clamps or bond wires may connect conductive member 502 to a drain bond pad or plate of the high-side HEMT 122, and another one or more clamps or bond wires may connect conductive member 508 to a source bond pad or plate of the high-side HEMT 122. One or more clamps or bond wires may connect the conductive member 508 to the drain bond pad or plate of the low-side HEMT 124, and another one or more clamps or bond wires may connect the conductive member 506 to the source bond pad or plate of the low-side HEMT 124. The gate bond pad 504 for the low-side HEMT 124 may be the control terminal 104 for the circuit 400. The bond wires or clamps electrically connect the gate bond pad 544 for the high-side HEMT 122 to the conductive bond pad 542 on the low-side HEMT 124.

[0051] Figure 6A top view of a non-limiting exemplary layout including semiconductor die 414. Most of the area of ​​semiconductor die 414 is occupied by low-side HEMT 124, which includes a drain electrode 622 coupled to a drain bonding pad 632, a gate electrode 624 coupled to a gate bonding pad 504, and a source electrode 626 coupled to a source pad 636. In another embodiment, a drain plate, a source plate, or both may be used in place of drain bonding pad 632 and source bonding pad 636. As used herein, an external terminal is relative to a circuit or a component within a circuit. For example, terminals 102, 104, and 106 are external terminals of circuit 400, and pads 632, 504, 542, and 636 are external terminals for die 414.

[0052] The variable capacitor 140 is located at Figure 6 626 is coupled to a capacitor electrode 644 of the variable capacitor 140 through an interconnect 646. The interconnect 642 is coupled to an underlying barrier or channel layer, which is another electrode for the variable capacitor 140. The capacitor electrode 644 may be formed using the same processing sequence as the gate electrode 624, and the interconnect 642 may be formed using the same processing sequence as the drain electrode 622. The interconnect 646 may be formed during the same processing sequence as the gate electrode 624, the source electrode 626, or during a different processing sequence than each of the gate electrode 624 and the source electrode 626. The area occupied by the variable capacitor 140 may be in the range of 0.2% to 20% of the area of ​​the semiconductor die 414.

[0053] exist Figure 6 , diodes 462 and 464 are within a frame 640 that is located between drain bond pad 632 and bond pad 542 of low-side HEMT 124. The area occupied by diodes 462 and 464 is significantly less than the area occupied by variable capacitor 140. Diodes 462 and 464 may occupy at most 5% or at most 1% of the area of ​​semiconductor die 414.

[0054] Figure 7 The semiconductor die 414 is included in Figure 6 A cross-sectional view of a portion at the area indicated in . Figure 7 The right side of includes the low-side HEMT 124 , and the left side includes a portion of the variable capacitor 140 .

[0055] Semiconductor die 414 includes semiconductor substrate 702, buffer layer 704, channel layer 706, and barrier layer 708. Substrate 702 may include silicon, sapphire (single crystal Al2O-3), silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga2O3), spinel (MgAl2O4), another suitable substantially single crystalline material, etc. The selection of the specific material and crystal orientation along the major surface may be selected based on the composition of the overlying semiconductor layers.

[0056] The buffer layer 704 may include a III-N material, and in one specific embodiment, includes Al a Ga (1-a) N, where 0≤a≤1. The composition of the buffer layer 704 may depend on the composition of the semiconductor base material of the channel layer 706 and the designed operating voltage of the HEMT. The composition of the buffer layer 704 may vary with thickness, such that the closer the buffer layer 704 is to the substrate 702, the higher its aluminum content is, and the closer it is to the channel layer 706, the higher its gallium content is. In a specific embodiment, the cation (metal atom) content in the semiconductor base material of the buffer layer 704 near the substrate 702 may be 10 atomic % to 100 atomic % Al, with the remainder being Ga, and the cation content in the semiconductor base material of the buffer layer 704 near the channel layer 706 may be 0 atomic % to 50 atomic % Al, with the remainder being Ga. In another embodiment, the buffer layer 704 may include multiple films. The buffer layer 704 may have a thickness in the range of approximately 1 micron to 6 microns.

[0057] The channel layer 706 may include Al z Ga (1-z) N, where 0≤z≤0.1, and has a thickness in the range of about 10nm to 4000nm. In a specific embodiment, the channel layer 706 is a GaN layer (z=0). The channel layer 706 may be inadvertently doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. A high-density two-dimensional electron gas (2DEG) may be formed near a portion of the interface of the channel layer 706 and the barrier layer 708, and is responsible for the high mobility and low resistivity of the transistor structure when in the on state. In an enhanced HEMT, the 2DEG may not be present under the gate structure when the HEMT is in the off state. Any reduction in 2DEG electrons will increase the on-resistance of the transistor. In one embodiment, the concentration of acceptors (when the carriers are electrons) or donors (when the carriers are holes) can be reasonably kept as low as possible.

[0058] In a specific embodiment, when metal-organic chemical vapor deposition (MOCVD) is used to form the channel layer 706, the acceptor may include carbon from the source gas (e.g., Ga(CH3)3). In a specific embodiment, the lowest trap concentration is desired, but may be limited by growth or deposition conditions and precursor purity. Thus, as the channel layer 706 grows, some carbon may become incorporated, and this carbon can lead to unintentional doping. The carbon content can be controlled by controlling deposition conditions such as deposition temperature and flow rate. In one embodiment, the carrier impurity concentration of the channel layer 706 is greater than 0 atoms / cm3 and at most 5×10 17 atoms / cm3. In yet another embodiment, the carrier impurity concentration ranges from 1×10 15 atoms / cm3 to 5×10 16 atoms / cm3.

[0059] In one embodiment, the channel layer 706 has a thickness of at least 50 nm. When the thickness is less than 50 nm, it may be more difficult to generate, maintain, or both generate and maintain the 2DEG. In another embodiment, the channel layer 706 has a thickness of at most 5000 nm. In a specific embodiment, a thickness in the range of 50 nm to 300 nm can provide a thick enough channel layer 706 to allow for proper generation and maintenance of the 2DEG and still obtain a reasonable value of R DSON . Although not shown, an interlayer may be used between the channel layer 706 and the blocking layer 708 if desired.

[0060] The blocking layer 708 may include a III-V semiconductor base material, such as a III-N semiconductor base material. In a specific embodiment, the blocking layer may include Al x In y Ga (1-x-y) N, where 0 < x ≤ 1 and 0 ≤ y ≤ 0.3. The blocking layer 708 may include a single film or multiple films. When the blocking layer 708 includes multiple films, the aluminum content may remain substantially the same or increase with increasing distance from the channel layer 706. As the aluminum content in the blocking layer 708 increases, the thickness of the blocking layer 708 may be relatively thin. In one embodiment, the blocking layer 708 has a thickness of at least 5 nm, and in another embodiment, the blocking layer 708 has a thickness of at most 150 nm. In a specific embodiment, the blocking layer 708 has a thickness in the range of 20 nm to 90 nm.

[0061] Buffer layer 704, channel layer 706, and barrier layer 708 may be formed using epitaxial growth techniques, and thus at least a portion of barrier layer 708, channel layer 706, and buffer layer 704 may be single crystalline. In a specific embodiment, the metal-containing film may be formed using metal organic chemical vapor deposition.

[0062] The gate electrode 624 of the low-side HEMT 124 and the capacitor electrode 644 of the variable capacitor 140 overlie the barrier layer 708. Each of the gate electrode 624 and the capacitor electrode may include a p-type semiconductor material. In one embodiment, the p-type semiconductor material may include p-type doped Al c Ga (1-c) N, where 0≤c≤1. The p-type dopant may include Mg, Zn, Cd, etc. The p-type semiconductor material may be single crystalline or polycrystalline. The gate electrode 624 and the capacitor electrode 644 may have a thickness of at least 1×10 18 In another embodiment, the dopant concentration is at most 1×10 21 The gate electrode 624 and the capacitor electrode 644 may be formed from an electrode layer that may be formed using any of the techniques that may be used to form the channel layer 706 or the barrier layer 708. The p-type dopant may be incorporated in situ or introduced into the gate electrode layer after deposition.

[0063] The electrode layer can be patterned to achieve the shape of the gate electrode 624 and the capacitor electrode 644. The portions of the electrode layer located outside the gate electrode 624 and the capacitor electrode 644 can be removed using a technique that does not significantly etch the barrier layer 708. When the electrode layer comprises p-type GaN, the electrode layer can be dry etched using fluorine chemicals such as SF6, CHF3, NF3, etc. The use of fluorine chemicals will not significantly etch the aluminum-containing film or layer because AlF3 forms and stops further etching of the aluminum-containing film or layer. Therefore, when the gate electrode 624 and the capacitor electrode 644 are formed, the barrier layer 708 will not be significantly etched. In addition to below the electrodes 624 and 644, a 2DEG 700 is also formed along the interface between the channel layer 706 and the barrier layer 708.

[0064] In another embodiment (not shown), an access region may be formed. A sacrificial structure may be formed in the region where the gate electrode 624 and the capacitor electrode 644 will be formed, and the access region may be grown over the exposed portion of the barrier layer 708. After the sacrificial structure is removed, the gate electrode 624 and the capacitor electrode 644 may be formed in the location where the sacrificial structure was located. Thus, different processing flows may be used without departing from the concepts described herein.

[0065] An interlayer dielectric (ILD) layer 710 may be formed over the barrier layer 708 and the electrodes 624 and 644. The ILD layer 710 may include a single film or multiple films. The single film or each of these films may include an oxide, a nitride, or an oxynitride. The ILD layer 710 may have a thickness in the range of 20 nm to 500 nm.

[0066] Contact openings for drain electrode 622 and source electrode 626 and interconnect 642 may extend through ILD layer 710. In one embodiment, the contact openings fall on barrier layer 708, and in another embodiment, the contact openings may extend through a portion, but not all, of the thickness of barrier layer 708, or extend through the entire thickness of barrier layer 708 and contact channel layer 706.

[0067] The conductive layer is formed above the ILD layer 710 and in the contact opening. The conductive layer may include a single film or multiple films. In one embodiment, the conductive layer may include an adhesive film and a barrier film. Such a film may include Ta, TaSi, Ti, TiW, TiSi, TiN, etc. The conductive layer may also include a conductor film. The body film may include Al, Cu, or another material that is more conductive than other films in the conductive layer. In one embodiment, the body film may include at least 90% by weight of Al or Cu. The body film may have a thickness at least as thick as other films in the conductive layer. In one embodiment, the thickness of the body film is in the range of 20nm to 900nm, and in a more specific embodiment, in the range of 50nm to 500nm. More or less films may be used in the conductive layer. The number and composition of the films in the conductive layer may depend on the needs or expectations of a specific application. After reading this specification, the technician will be able to determine the composition of the conductive layer modulated to suit its device. The conductive layer is patterned to form a drain electrode 622 and a source electrode 626 and an interconnect 642.

[0068] The contact openings for the gate interconnect 724 and the interconnect 646 may extend through the ILD layer 710 and fall on the gate electrode 624 and the capacitor electrode 644. A conductive layer is formed over the ILD layer 710 and within the contact openings for the gate electrode 624 and the capacitor electrode 644. The conductive layer may include any composition and thickness as previously described with respect to the conductive layer for the drain electrode 622 and the source electrode 626 and the interconnect 642. The conductive layer for the interconnects 646 and 724 may have the same or different composition than the conductive layer for the drain electrode 622 and the source electrode 626 and the interconnect 642. The conductive layer for the interconnects 646 and 724 may have the same or different thickness than the conductive layer for the drain electrode 622 and the source electrode 626 and the interconnect 642. The interconnect 646 extends over the source electrode 626 to provide an electrical connection between the source electrode 626 and the capacitor electrode 644.

[0069] Figures 5 to 7 Portions of semiconductor die 414 are shown that are electrically connected to external terminals external to semiconductor die 414. Drain electrode 622 is connected to conductive member 508 via drain bonding pad 632. Gate electrode 624 is connected to control terminal 104, which is in the form of gate pad 504. Capacitor electrode 644 is electrically connected to source electrode 626 via interconnect 646, and source electrode 626 is electrically connected to conductive member 506 via source bonding pad 636. Interconnect 642 is electrically connected to bonding pad 542, which is electrically connected to bonding pad 544.

[0070] In another embodiment (not shown), the variable capacitor 140 may include a dielectric layer and a metal-based capacitor electrode. The capacitor dielectric may be formed above the barrier layer 708, or may be the lowest film (closest to the barrier layer 708) within the ILD layer 710. The opening for the interconnect 646 may stop on or within the lowest film within the ILD layer 710. The interconnect 646 may have a composition of a conductive layer as previously described, as previously described with respect to the gate interconnect 724. In another embodiment, the interconnect 646 may include a conductive film in contact with the capacitor dielectric that achieves the desired work function of the structure. In this embodiment, the transistor structure in the low-side HEMT 124 may also have a gate electrode 624 replaced by a dielectric layer, and the gate interconnect 724 may also be a gate electrode and its composition is selected to achieve the desired work function.

[0071] Figure 8 A cross-sectional view of semiconductor die 414 is included, which provides frame 640 ( Figure 6 ) in detail of a non-limiting exemplary embodiment of diodes 462 and 464. Diodes 462 and 464 may be implemented as transistor structures in which the gate electrode and source electrode of the enhancement mode transistor are short-circuited to each other. Each of the transistor structures may be designed to have a breakdown voltage of approximately 5V. In another embodiment, a different breakdown voltage may be selected.

[0072] Diodes 462 and 464 may be implemented in a process flow for forming the low-side HEMT 124. An isolation region 808 is formed that discontinuously provides a 2DEG between a gate electrode 824 and its corresponding source electrode within each of the HEMT structures. The isolation region 808 may be formed by implanting a p-type dopant. The isolation region 808 extends through the interface between the channel layer 106 and the barrier layer 108 to disrupt the 2DEG. The isolation region 808 may or may not extend completely through the channel layer 106. The dopant concentration within the isolation region 808 is higher than the n-type dopant concentration of the channel layer 106, the barrier layer 108, or both. In one embodiment, the dopant concentration within the isolation region 808 is no higher than the highest dopant concentration relative to the gate electrode 624. In an alternative embodiment, the isolation region 808 may be defined by a trench filled with an insulating material. The gate electrode 824 may be formed using the same process sequence as the gate electrode 624 for the low-side HEMT 124.

[0073] Electrode 832 is a source electrode for its transistor structure and is coupled to conductive member 508 ( Figure 5 ), electrodes 834, 836, and 838 are drains for transistor structures to the right of each electrode and sources for transistor structures to the left of each electrode. Thus, diode 464 includes four transistor structures connected in series. Electrode 840 is a source electrode for its transistor structure and is coupled to bonding pad 544. Electrodes 832, 834, 836, 838, and 840 may be formed using the same process sequence as source electrode 626 for low-side HEMT 124. Interconnect 846 electrically connects gate electrode 824 to their corresponding electrodes 832, 834, 836, 838, and 840. In one embodiment, interconnect 846 may be formed using the same process sequence as interconnect 646.

[0074] In another embodiment, diodes 462 and 464 may be implemented as Schottky diodes. In yet another embodiment, a semiconductor pn junction may be used to form either or both of diodes 462 and 464. Diode 462 may be implemented as a Zener diode. Diode 464 may be implemented as a set of Zener diodes connected in series or as a single pair of semiconductor layers or alternating p-type semiconductor layers and n-type semiconductor layers. The specific selection of the physical structure of diodes 462 and 464 may be based on the needs or desires of a particular application. In the embodiment shown in the figures, the configuration and spacing between the drain electrode 622 and the gate electrode 624 of the HEMT 124 may be substantially the same as the interconnect 642 and capacitor electrode 644 of diodes 462 and 464.

[0075] In another embodiment, one or both of diodes 462 and 464 may be located on the same semiconductor die as the high-side HEMT 122 . Fig. 9 An exemplary layout is included that includes a drain electrode 922 coupled to a drain bond pad 932, a gate electrode 924 coupled to a gate bond pad 944 (which is coupled to a source bond pad of the low-side HEMT 124), and a source electrode 926 coupled to a source bond pad 936. Block 940 includes diodes 462 and 464 and is coupled to source bond pad 936 and gate bond pad 944. Diodes 462 and 464 may have the same configuration as previously described with respect to Figure 8 Co-location of the diodes 464 and 462 with the high-side HEMT 122 may be beneficial because the diodes 462 and 464 are closer to the gate electrode 924 and the source electrode 926 of the high-side HEMT 122 .

[0076] The previously described embodiments are useful when the circuit 400 operates at a voltage higher than each of the HEMTs 122 and 124. In one specific example, the circuit 100 or 400 (V DS CIRCUIT ) can be designed to operate at 800 V, and each of the HEMTs 122 and 124 can withstand a V of 650 V. DS HEMT In another embodiment, the circuit V DS CIRCUIT It may be desirable to operate at typically 1200 V. Although in theory no further HEMTs are required, in practice node 108 may reach a transient voltage shortly after a switching operation where the V of HEMT 122 or HEMT 124 is DS HEMT 650V may be exceeded and may adversely affect such HEMTs.

[0077] Fig.10 Embodiments are included in which one or more stages may be added to circuit 100 to allow the circuit to operate at higher voltages. Each stage may include a HEMT, a variable capacitor, and a pair of diodes. Fig.101000 , HEMT 1022 may have a drain coupled to drain terminal 102, and a source coupled to the cathode of diode 1064 and the drain of the next lower HEMT (relative to the voltage within circuit 1000), such as the drain of high-side HEMT 122. The gate of HEMT 1022 may be coupled to the cathode of diode 1062 and an electrode of variable capacitor 1040. The anodes of diodes 1062 and 1064 are coupled to each other. The other electrode of variable capacitor 1040 is coupled to the gate of the next lower HEMT (relative to the voltage within circuit 1000), such as the gate of high-side HEMT 122.

[0078] In one embodiment, HEMT 1022 may be on semiconductor die 1012, and variable capacitor 1040 and diodes 1062 and 1064 may be on semiconductor die 1014. Such a configuration may allow for a modular implementation to achieve a desired operating voltage for circuit 1000. In this manner, all HEMTs except low-side HEMT 124 may have the same construction, and each die including a variable capacitor such as variable capacitor 1040 and a diode such as diodes 1062 and 1064 may have the same construction. If the operating voltage of the circuit is 1600V, another die identical to die 1012 and another die identical to die 1014 may be implemented. In a specific embodiment, die 1014 may be implemented using AlGaN or another semiconductor technology. For example, components of die 1014 may be implemented in Si, SiC, or other compound semiconductor technologies.

[0079] Embodiments may be implemented without the complications that may arise if HEMTs are scaled to operate at higher voltages. For example, HEMTs operating at such higher voltages may require significantly thicker or more complex buffer layers. Thicker buffer layers may induce more mechanical stress and cause wafer warpage. The modular design allows for easier scaling to higher operating voltages of the circuit. By limiting the operating voltage of each of the HEMTs to commonly used voltages, high voltage circuits may be designed without having to devise new complex or marginal process technologies or physical designs.

[0080] In some embodiments, variable capacitors and diodes can be implemented in AlGaN technology without adding any new steps. These changes can be achieved by modifying existing masks used to form HEMTs, where such modifications incorporate variable capacitors and diodes. In addition, variable capacitors can operate over the voltage range typically experienced by their die without taking up too much area. Thus, any individual or combination of variable capacitors and diodes can occupy no more than 20% of the area of ​​the die on which they are located. In another embodiment, variable capacitors and diodes can be on separate dies to allow for module construction that is well suited for use over the voltage range of the circuit.

[0081] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, the technician will recognize that those aspects and embodiments are only exemplary, and do not limit the scope of the invention. Embodiment can be according to any one or more of the embodiments listed below.

[0082] Embodiment 1. A circuit may include: a first high electron mobility transistor; a second high electron mobility transistor, wherein the drain of the first high electron mobility transistor is coupled to the source of the second high electron mobility transistor; and a first variable capacitor, wherein the first electrode of the first variable capacitor is coupled to the source of the first high electron mobility transistor, and the second electrode of the first variable capacitor is coupled to the gate of the second high electron mobility transistor.

[0083] Embodiment 2. The circuit of embodiment 1, wherein the first high electron mobility transistor is an enhancement mode transistor, and the second high electron mobility transistor is a depletion mode transistor.

[0084] Embodiment 3. The circuit according to embodiment 1 further includes a first diode and a second diode, wherein the cathode of the first diode is coupled to the second electrode of the first variable capacitor, the anode of the first diode is coupled to the anode of the second diode, and the cathode of the second diode is coupled to the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor.

[0085] Embodiment 4. The circuit according to Embodiment 1 further includes: a source terminal coupled to the source of the first high electron mobility transistor; a control terminal coupled to the gate of the first high electron mobility transistor; and a drain terminal coupled to the drain of the second high electron mobility transistor.

[0086] Embodiment 5. A circuit according to embodiment 1, wherein the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor are electrically connected to each other at an intermediate node, and the first variable capacitor has a capacitance such that when the circuit is in an off state, the intermediate node has a voltage within 10% of half of the voltage difference between the source of the first high electron mobility transistor and the drain of the second high electron mobility transistor.

[0087] Embodiment 6. The circuit according to embodiment 1 further includes: a third high electron mobility transistor; and a second variable capacitor, wherein the first electrode of the second variable capacitor is coupled to the gate of the second high electron mobility transistor, the second electrode of the second variable capacitor is coupled to the gate of the third high electron mobility transistor and the drain of the second high electron mobility transistor is coupled to the source of the third high electron mobility transistor.

[0088] Embodiment 7. The circuit according to embodiment 6, wherein the first high electron mobility transistor is an enhancement mode transistor, and each of the second high electron mobility transistor and the third high electron mobility transistor is a depletion mode transistor.

[0089] Embodiment 8. The circuit according to Embodiment 1 further includes a first diode and a second diode, wherein the first high electron mobility transistor is an enhancement-type transistor, the second high electron mobility transistor is a depletion-type transistor, the cathode of the first diode is electrically connected to the second electrode of the first variable capacitor, the anode of the first diode is electrically connected to the anode of the second diode, and the cathode of the second diode is electrically connected to the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor.

[0090] Embodiment 9. An electronic device may include a first tube core, which includes: a first high electron mobility transistor; and a first variable capacitor, wherein a first electrode of the first variable capacitor is coupled to a source or a gate of the first high electron mobility transistor, and a second electrode of the first variable capacitor is coupled to a first external terminal of the first tube core.

[0091] Embodiment 10. The electronic device according to Embodiment 9 further includes a second tube core, which includes a second high electron mobility transistor, wherein the gate electrode of the second high electron mobility transistor is coupled to the first external terminal of the second tube core, the first external terminal of the second tube core is coupled to the first external terminal of the first tube core, the drain electrode of the first high electron mobility transistor is coupled to the second external terminal of the first tube core, and the source electrode of the second high electron mobility transistor is coupled to the second external terminal of the second tube core, and the second external terminal of the second tube core is coupled to the second external terminal of the first tube core.

[0092] Embodiment 11. An electronic device according to Embodiment 10, wherein a first electrode of the first variable capacitor is coupled to a source electrode of the first high electron mobility transistor, and a second electrode is coupled to a gate electrode of the second high electron mobility transistor.

[0093] Embodiment 12. The electronic device according to Embodiment 10, wherein the first high electron mobility transistor is an enhancement mode transistor, and the second high electron mobility transistor is a depletion mode transistor.

[0094] Embodiment 13. The electronic device according to Embodiment 10 further includes a third high electron mobility transistor and a second variable capacitor, wherein the drain of the second high electron mobility transistor is coupled to the source of the third high electron mobility transistor, the first electrode of the second variable capacitor is coupled to the gate of the second high electron mobility transistor, and the second electrode of the second variable capacitor is coupled to the gate of the third high electron mobility transistor.

[0095] Embodiment 14. The electronic device according to Embodiment 13 further includes a first diode and a second diode, wherein the cathode of the first diode is electrically connected to the second electrode of the second variable capacitor, the anode of the first diode is electrically connected to the anode of the second diode, the cathode of the second diode is electrically connected to the drain of the second high electron mobility transistor and the source of the third high electron mobility transistor, the third high electron mobility transistor is on the third tube core, and the second variable capacitor and the first diode and the second diode are on the fourth tube core.

[0096] Embodiment 15. An electronic device according to embodiment 9, wherein the first tube core also includes a first diode and a second diode, wherein the cathode of the first diode is coupled to the second electrode of the first variable capacitor, the anode of the first diode is coupled to the anode of the second diode, and the cathode of the second diode is coupled to the drain electrode of the first high electron mobility transistor.

[0097] Embodiment 16. An electronic device according to Embodiment 9, wherein the drain of the first high electron mobility transistor and the interconnect of the first variable capacitor have substantially the same composition, the gate of the first high electron mobility transistor and the capacitor electrode of the first variable capacitor have substantially the same composition, and the spacing between the drain electrode and the gate electrode of the first high electron mobility transistor is substantially the same as the spacing between the interconnect of the first variable capacitor and the capacitor electrode of the first variable capacitor.

[0098] Embodiment 17. The electronic device according to Embodiment 9 further includes a first diode, a second diode and a second high electron mobility transistor, wherein the first high electron mobility transistor is an enhancement-type transistor, the second high electron mobility transistor is a depletion-type transistor, the first electrode of the variable capacitor is electrically connected to the source of the first high electron mobility transistor, the second electrode of the variable capacitor is electrically connected to the gate of the second high electron mobility transistor and the cathode of the first diode, the drain electrode of the first high electron mobility transistor is electrically connected to the source electrode of the second high electron mobility transistor and the cathode of the second diode, the anode of the first diode is electrically connected to the anode of the second diode, the first high electron mobility transistor, the variable capacitor, the first diode and the second diode are on a first die, and the second high electron mobility transistor is on a second die.

[0099] Embodiment 18. An electronic device may include a first tube core, wherein the first tube core includes: a variable capacitor; a first diode; and a second tube core, wherein the first electrode of the variable capacitor is coupled to the first external terminal of the first tube core, the second electrode of the variable capacitor and the cathode of the first diode are coupled to the second external terminal of the first tube core, the anode of the first diode is coupled to the anode of the second diode, and the cathode of the second diode is coupled to the third external terminal of the first tube core.

[0100] Embodiment 19. The electronic device according to Embodiment 18 further includes a first high electron mobility transistor, wherein the gate of the first high electron mobility transistor is coupled to the first electrode or the second electrode of the variable capacitor, and the drain or source of the first high electron mobility transistor is coupled to the cathode of the second diode.

[0101] Embodiment 20. The electronic device according to Embodiment 19 further includes a second high electron mobility transistor, wherein the gate of the first high electron mobility transistor is coupled to the first electrode of the variable capacitor, the gate of the second high electron mobility transistor is coupled to the second electrode of the variable capacitor, the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor are coupled to the cathode of the second diode, and the first high electron mobility transistor, the second high electron mobility transistor, or both transistors are on at least one die different from the first die.

[0102] It should be noted that not all activities described above in the general description or examples are required, that a portion of a specific activity may not be required, and that one or more additional activities may be performed in addition to those described. Also, the order in which the activities are listed is not necessarily the order in which the activities are performed.

[0103] Beneficial effects, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these beneficial effects, advantages, solutions to problems, and any features that may cause any beneficial effect, advantage, or solution to occur or become more obvious should not be construed as key, required, or essential features of any or all claims.

[0104] The description and illustration of the embodiments described herein are intended to provide a general understanding of the structures of various embodiments. The description and illustration are not intended to be used as an exhaustive and comprehensive description of all elements and features of the equipment and systems using the structures or methods described herein. A separate embodiment may also be provided in a single embodiment in combination, whereas various features described in the context of a single embodiment for the sake of simplicity may also be provided individually or in any sub-combination. In addition, reference to values ​​expressed as ranges includes all values ​​within the range. Many other embodiments are apparent only to the technician after reading this specification. Other embodiments may be used and derived from the present disclosure so that structural replacement, logical replacement or other changes may be performed without departing from the scope of the present disclosure. Therefore, the present disclosure should be considered exemplary, not restrictive.

Claims

1. A circuit, characterized in that: The circuit comprises: the first high electron mobility transistor; a second high electron mobility transistor, wherein a drain of the first high electron mobility transistor is coupled to a source of the second high electron mobility transistor; and a first variable capacitor, wherein a first electrode of the first variable capacitor is coupled to a source of the first high electron mobility transistor and a second electrode of the first variable capacitor is coupled to a gate of the second high electron mobility transistor; The circuit further comprises a first diode and a second diode, wherein: A cathode of the first diode is coupled to the second electrode of the first variable capacitor, an anode of the first diode is coupled to an anode of the second diode, and A cathode of the second diode is coupled to the drain of the first high electron mobility transistor and the source of the second high electron mobility transistor.

2. The circuit according to claim 1, wherein: The drain of the first high electron mobility transistor and the source of the second high electron mobility transistor are electrically connected to each other at an intermediate node, and The first variable capacitor has a capacitance such that when the circuit is in an off state, the intermediate node has a voltage within 10% of half a voltage difference between the source of the first high electron mobility transistor and the drain of the second high electron mobility transistor.

3. The circuit according to any one of claims 1 to 2, wherein: The circuit further comprises: The third highest electron mobility transistor; and The second variable capacitor, in: a first electrode of the second variable capacitor coupled to the gate of the second high electron mobility transistor, A second electrode of the second variable capacitor is coupled to a gate of the third high electron mobility transistor, and The drain of the second high electron mobility transistor is coupled to the source of the third high electron mobility transistor.

4. An electronic device, comprising a first tube die, characterized in that: The electronic device comprises: a first high electron mobility transistor; and a first variable capacitor, in: A first electrode of the first variable capacitor is coupled to a source or a gate of the first high electron mobility transistor, and a second electrode of the first variable capacitor is coupled to a first external terminal of the first die, The electronic device further comprises a first diode, a second diode, a second tube core and a second high electron mobility transistor. The first electrode of the first variable capacitor is electrically connected to the source of the first high electron mobility transistor, The second electrode of the first variable capacitor is electrically connected to the gate of the second high electron mobility transistor and the cathode of the first diode, The drain of the first high electron mobility transistor is electrically connected to the source of the second high electron mobility transistor and the cathode of the second diode, The anode of the first diode is electrically connected to the anode of the second diode, The first high electron mobility transistor, the first variable capacitor, and the first diode and the second diode are on a first die, and The second high electron mobility transistor is on the second die.

5. The electronic device according to claim 4, wherein: the gate of the second high electron mobility transistor is coupled to a first external terminal of the second die, the first external terminal of the second die is coupled to the first external terminal of the first die, The drain of the first high electron mobility transistor is coupled to a second external terminal of the first die, and The source of the second high electron mobility transistor is coupled to a second external terminal of the second die, and the second external terminal of the second die is coupled to the second external terminal of the first die.

6. The electronic device according to claim 5, wherein: The electronic device further comprises a third high electron mobility transistor and a second variable capacitor, wherein: The drain of the second high electron mobility transistor is coupled to the source of the third high electron mobility transistor, A first electrode of the second variable capacitor is coupled to the gate of the second high electron mobility transistor, and A second electrode of the second variable capacitor is coupled to a gate of the third high electron mobility transistor.

7. The electronic device according to any one of claims 4 to 6, wherein: The first high electron mobility transistor is an enhancement mode transistor, The second high electron mobility transistor is a depletion-mode transistor.

8. An electronic device, comprising a first tube die, characterized in that: The first tube core comprises: a first external terminal, a second external terminal and a third external terminal; a variable capacitor comprising a first electrode and a second electrode; a first diode comprising an anode and a cathode; and a second diode, the second diode comprising an anode and a cathode, in: the first electrode of the variable capacitor being coupled to the first external terminal of the first die, the second electrode of the variable capacitor being coupled to the second external terminal of the first die, The second electrode of the variable capacitor is electrically connected to the cathode of the first diode, The anode of the first diode is electrically connected to the anode of the second diode, and The cathode of the second diode is coupled to a third external terminal of the first die.

9. The electronic device according to claim 8, wherein: The electronic device further comprises a first high electron mobility transistor and a second high electron mobility transistor, wherein: The gate of the first high electron mobility transistor is coupled to the first electrode of the variable capacitor, A drain or a source of the first high electron mobility transistor is coupled to the cathode of the second diode, a gate of the second high electron mobility transistor coupled to the second electrode of the variable capacitor, The drain of the first high electron mobility transistor and the source of the second high electron mobility transistor are coupled to the cathode of the second diode, and The first high electron mobility transistor, the second high electron mobility transistor, or both transistors are on at least one die different from the first die.

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